Method for providing a silicon-filled gap for a semiconductor device
By depositing silicon precursors in the gaps and etching amorphous silicon deposits on the sidewalls, the void problem caused by uneven silicon layer growth was solved, achieving uniform silicon filling and reliable electrical contact.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ASM IP HLDG BV
- Filing Date
- 2020-11-12
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, the silicon layer grows unevenly when filling gaps, leading to the formation of voids, especially the problem of incomplete nucleation at the top and sides of the gaps.
By depositing silicon precursors in the gaps and performing epitaxial growth, followed by etching the amorphous silicon deposits on the sidewalls with an etchant, the high etching rate difference of the amorphous silicon films is utilized to achieve uniform silicon filling and avoid the formation of voids.
Uniform silicon filling was achieved, avoiding voids within the gaps and ensuring the reliability of electrical contacts and the integrity of the filling.
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Figure CN112820692B_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to methods of manufacturing semiconductor devices. More specifically, this disclosure relates to providing amorphous silicon-filled gaps. Background Technology
[0002] Semiconductor devices typically include gaps filled with silicon, which can form components of various electronic devices. Filling can include depositing silicon layers on the side and bottom surfaces of the gaps, which fill the gaps from the sides and bottom as the silicon layers grow.
[0003] However, the growth of the silicon layer may not be completely uniform, resulting in voids (such as seams) forming inside the gaps. In some cases, these voids may be caused by the deposition process in which silicon may be deposited at a higher rate at the top of the gap than at the bottom, causing the top of the gap to be sealed first, leaving voids inside the gap, or nucleation at the bottom or sides of the gap may be incomplete, thus creating voids at the bottom or sides of the gap.
[0004] Therefore, an improved process is needed to form silicon-filled gaps. Summary of the Invention
[0005] In one embodiment, a method for filling a gap is provided. The method includes providing a semiconductor substrate having a gap in a deposition chamber, the bottom of the gap comprising a crystalline semiconductor material and the sidewalls of the gap comprising an amorphous material. A silicon precursor is deposited in the gap to induce epitaxial growth of the crystalline semiconductor material on the bottom of the gap. An etchant is then provided in the gap to etch the amorphous deposition of the silicon precursor on the sidewalls of the gap.
[0006] In one embodiment, a semiconductor device is provided. The semiconductor has gaps filled according to the method described above. The silicon-filled gaps can provide electrical contact between two layers. Attached Figure Description
[0007] Figures 1a-1h A schematic series of cross-sections showing silicon-filled gaps according to a preferred embodiment of the method of the present invention are shown. Detailed Implementation
[0008] Figure 1aA schematic cross-section of a substrate 1 having a gap 2 is shown. The bottom 3 of the gap 2 comprises a crystalline semiconductor material, such as crystalline silicon, silicon-germanium, or germanium. The depth D of the gap 2 may be, for example, substantially 200 nm or greater or less, while the width W of the gap 2 may be, for example, substantially 14 nm or greater or less. The sidewalls 4 of the gap 2 may comprise an amorphous material. Such an amorphous material may comprise silicon oxide and / or silicon nitride. In this embodiment, the sidewalls 4 may comprise, for example, an outer filling layer 4a of silicon oxide and an inner insulating layer 4b of silicon nitride.
[0009] Since contact between silicon and air can cause an oxide layer to form on top of the crystalline semiconductor material, an optional step of etching the top oxide layer from the bottom 3 of the gap 2 can be performed before starting the deposition of the silicon precursor, such as... Figure 1b As shown. For example, this can be done using known methods such as HF etching.
[0010] Then, a silicon precursor can be deposited in gap 2, for example (Si3H8), silane (SiH4), or silane (Si2H6) are used to induce epitaxial growth of a crystalline semiconductor material on the bottom 3 of the gap 2. Optionally, one or more hydrogen groups in the silane can be substituted with a halogen. It has been shown that the deposition of the silicon precursor induces faster nucleation on crystalline structures than on amorphous structures. As a result, the deposition of the silicon precursor may induce epitaxial growth 5 of a crystalline semiconductor material on the bottom 3 of the gap, such as... Figure 1c As shown, the amorphous material on the sidewall temporarily inhibits nucleation on sidewall 4, or in other words, nucleation on the amorphous material on sidewall 4 may be slower than on the bottom of gap 2.
[0011] Although nucleation on the sidewalls 4 of gap 2 is slower than on the bottom 3 of gap 2, the silicon film 6 may eventually form on the sidewalls 4, as... Figure 1d As shown, the silicon film 6 can be an amorphous silicon film because it is grown on an amorphous material. After the amorphous silicon film 6 is formed on the sidewall 4, and before the amorphous film 6 can close the gap 2, an etching step, particularly a vapor phase etching step, is performed, which includes providing an etchant, such as dichloroCl2 or hydrogen chloride HCl, into the gap 2 to etch the silicon precursor, particularly the amorphous deposition of the amorphous film 6, on the sidewall 4 of the gap 2.
[0012] Furthermore, the morphological difference between the bottom 3 of the gap 2 (including the epitaxially grown crystalline semiconductor material on which silicon has been deposited) and the sidewall 4, including the amorphous material covered by the amorphous silicon film 6, causes a difference in etching rate. The etching rate of the amorphous silicon film 6 is higher than that of the crystalline epi, for example, at least five times, preferably even ten times or more. As a result, as Figure 1eAs shown, the silicon film 6 can be etched away with almost no need to etch the crystal epi, and the sidewalls 4 of the gap 2 will not be damaged.
[0013] Each as Figure 1f and 1g As shown, by alternately repeating the steps of depositing silicon precursor and providing etchant in the gap, the gap 2 can be filled with silicon from the bottom 3, especially epi-silicon, upward to the top 7, or at least up to the desired fill height, without creating any voids in the gap 2.
[0014] In one embodiment, the step of providing the silicon precursor in the gap may further include depositing a dopant in the gap 2, preferably as a co-current or alternatively in an alternating manner. The dopant may be, for example, a p-doped dopant and may include, for example, phosphine, arsine, or boron trichloride at a concentration of 1E21.
[0015] In one embodiment, the deposition of the silicon precursor and the etching can be carried out in a temperature range of about 350°C to 550°C.
[0016] In one embodiment, the gap filled according to the method described above can be a contact plug, which provides electrical contact between two layers, for example, in a semiconductor device such as a memory device.
[0017] Those skilled in the art will recognize that various omissions, additions, and modifications can be made to the above-described processes and structures without departing from the scope of the invention. It is contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments can be made while still falling within the scope of the specification. Various features and aspects of the disclosed embodiments can be combined or substituted with each other in sequence. All such modifications and changes are intended to fall within the scope of the invention as defined by the appended claims.
Claims
1. A method for filling a gap, comprising: - A semiconductor substrate with a gap is provided in a deposition chamber, wherein the gap has a bottom and sidewalls, wherein the depth of the gap is at least 200 nm and the gap has a width of 14 nm or less, wherein the bottom of the gap comprises a crystalline semiconductor material and each sidewall of the gap comprises an amorphous material. - Depositing silicon precursors in the gaps causes epitaxial growth of crystalline semiconductor material at the bottom of the gaps and amorphous deposition of silicon precursors on the sidewalls of the gaps, such that nucleation on the amorphous material on the sidewalls is slower than nucleation at the bottom of the gaps. - Provide etchant in the gap to etch the amorphous deposition of silicon precursor on the sidewalls of the gap; - Alternately repeat the steps of depositing silicon precursor and providing etchant to fill the gaps; The etchant etches the amorphous deposit of silicon precursor on each sidewall of the gap at a rate at least five times higher than the etchant etches the crystalline semiconductor material on the bottom of the gap.
2. The method according to claim 1, wherein, The crystalline semiconductor material includes silicon, silicon-germanium, or germanium.
3. The method according to claim 1, wherein, The amorphous material includes silicon oxide and / or silicon nitride.
4. The method according to claim 1, wherein, The silicon precursor includes silane, ethsilane, or propane.
5. The method according to claim 1, wherein, The etchant includes dichloride or hydrogen chloride.
6. The method according to claim 1, wherein, The etchant is provided in the gap by vapor phase etching.
7. The method according to claim 1, comprising the following steps: Before the silicon precursor is deposited, the top oxide layer is etched from the bottom of the gap using crystalline semiconductor material.
8. The method according to claim 1, wherein, The step of providing a silicon precursor in the gap includes depositing a dopant in the gap.
9. The method according to claim 8, wherein, The dopant includes phosphine, arsine, or boron trichloride.
10. The method according to claim 1, wherein, Silicon precursor deposition and etching are performed within a temperature range of 350℃-550℃.
11. The method according to claim 1, wherein, The deposition chamber is the processing chamber of the batch processing furnace.
12. The method according to claim 1, wherein, The etchant etches at a rate at which the amorphous deposition of silicon precursor on each sidewall of the gap is etched at a rate at which the etchant etches crystalline semiconductor material on the bottom of the gap at least ten times higher.
13. A semiconductor device having a gap filled by the method according to claim 1.
14. The semiconductor device according to claim 13, wherein, The filling gap is a contact plug that provides electrical contact between the two layers.
15. The semiconductor device according to claim 14, wherein, The device is a storage device.