Semiconductor device

Abstract

The present disclosure provides a semiconductor device. A semiconductor device includes: gate electrodes stacked apart from each other in a first direction on a substrate, extending in a second direction, and including pad regions curved in a third direction; a sacrificial insulating layer extending from the gate electrodes to be stacked alternately with interlayer insulating layers; partition regions penetrating the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other; and a through wiring region spaced apart from the partition regions to overlap the pad regions between the partition regions adjacent to each other, and including a contact plug penetrating the pad regions. The through wiring region includes a slit region, and each slit region is provided to penetrate the sacrificial insulating layer at one side of the corresponding pad region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically, to semiconductor devices that include multiple slit regions and pad regions in a memory cell region. Background Technology

[0002] Semiconductor devices are typically required to process large amounts of data, and their size is constantly decreasing. Therefore, it is important to increase the integration density of the semiconductor elements that constitute semiconductor devices. Consequently, as a method to improve the integration density of semiconductor devices, semiconductor devices with vertical transistor structures instead of the traditional planar transistor structures have been proposed. Summary of the Invention

[0003] An example implementation provides a semiconductor device with improved reliability.

[0004] According to one example embodiment, a semiconductor device includes: a peripheral circuit region including a first substrate, circuit elements disposed on the first substrate, and wiring structures on the circuit elements; a memory cell region including a second substrate disposed above the first substrate, and further including a gate electrode, an interlayer insulating layer stacked alternately with the gate electrode, and a channel structure, wherein the gate electrodes are stacked in a first region of the second substrate in a first direction perpendicular to the upper surface of the second substrate and spaced apart from each other, and extend in a stepped manner in a second region of the second substrate in a second direction perpendicular to the first direction, the channel structure being disposed in the first region to penetrate the gate electrode and extending in the first direction, each channel structure including a channel layer; and a through wiring region disposed in the second region and including a sacrificial insulating layer and a contact plug, the sacrificial insulating layer extending from the gate electrode to be stacked alternately with the interlayer insulating layer, the contact plug electrically connecting the gate electrode and the wiring structure to each other. The gate electrode includes a pad region configured to overlap with the through wiring region at an end of the gate electrode and be exposed relative to the interlayer insulating layer and the sacrificial insulating layer. The through-wiring area includes a slit area, which is configured to penetrate a sacrificial insulation layer on one side of the respective pad area.

[0005] According to one example embodiment, a semiconductor device includes: a peripheral circuit region including a first substrate and circuit elements disposed on the first substrate; a memory cell region including a second substrate disposed above the first substrate, and further including a gate electrode and a cell region insulating layer covering the gate electrode, the gate electrodes being stacked on the second substrate in a first direction spaced apart from each other and extending at different lengths in a second direction perpendicular to the first direction; and a through wiring region including a sacrificial insulating layer configured to extend from the gate electrode. Each gate electrode includes a pad region that is bent to extend upward in a third direction perpendicular to the first and second directions and protrudes from an end of the gate electrode in the second direction into the through wiring region, and the opposite side surfaces of the pad regions in the second direction are covered by the cell region insulating layer.

[0006] According to one example embodiment, a semiconductor device includes: gate electrodes stacked on a substrate in a first direction perpendicular to an upper surface of the substrate and spaced apart from each other, extending in a second direction perpendicular to the first direction, and including pad regions bent upward in a third direction perpendicular to the first and second directions; interlayer insulating layers stacked alternately with the gate electrodes; a channel structure penetrating the gate electrodes, extending in the first direction, and including a channel layer; partition regions penetrating the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other; and through wiring regions spaced apart from the partition regions to overlap the pad regions between adjacent partition regions, including contact plugs penetrating the pad regions, and including sacrificial insulating layers extending from the gate electrodes and stacked alternately with the interlayer insulating layers. The through wiring regions include slit regions, and each slit region is configured to penetrate the sacrificial insulating layer on one side of a corresponding pad region. Attached Figure Description

[0007] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A schematic layout of a semiconductor device according to an example embodiment is shown;

[0009] Figure 2 This is a schematic plan view of a semiconductor device according to an example embodiment;

[0010] Figures 3A to 3D This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0011] Figure 4 This is a perspective view of the elements including the gate electrode of a semiconductor device according to an example embodiment;

[0012] Figure 5 It is a plan view including a gate electrode of a semiconductor device according to an example embodiment;

[0013] Figure 6A and Figure 6B This is a plan view of a semiconductor device according to an example embodiment;

[0014] Figure 7A and Figure 7B This is a plan view of a semiconductor device according to an example embodiment;

[0015] Figures 8A to 8C This is a cross-sectional view of a semiconductor device according to an example embodiment;

[0016] Figure 9A and Figure 9B These are schematic plan views and schematic cross-sectional views of a semiconductor device according to an example embodiment;

[0017] Figure 10 This is a cross-sectional view of a semiconductor device according to an example embodiment;

[0018] Figure 11A and Figure 11B These are schematic plan views and schematic cross-sectional views of a semiconductor device according to an example embodiment; and

[0019] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Detailed Implementation

[0020] In the following description, exemplary embodiments will be described with reference to the accompanying drawings.

[0021] Figure 1 A schematic layout of a semiconductor device according to an example embodiment is shown.

[0022] Reference Figure 1 The semiconductor device 10 may include a first region R1 and a second region R2 stacked in a vertical direction. The first region R1 may include a first peripheral circuit PERI and a second peripheral circuit PERI, the first peripheral circuit PERI including a row decoder DEC and a page buffer PB. The second region R2 may include memory cell arrays MCA1 and MCA2, as well as a first through-wiring region TB1 and a second through-wiring region TB2.

[0023] In the first region R1, the row decoder DEC can decode the input address to generate and send the drive signals for the word lines. The page buffer PB can be connected to the memory cell arrays MCA1 and MCA2 via bit lines to read information (e.g., data) stored in the memory cells. The second peripheral circuit PERI can be a region including control logic circuitry and a voltage generator, and may include, for example, latch circuitry, cache circuitry, and / or sense amplifiers. The first region R1 may also include a pad area. In this case, the pad area may include electrostatic discharge (ESD) components and / or data input / output circuitry.

[0024] In the first region R1, at least a portion of the various circuit regions DEC, PB, and PERI can be disposed below the memory cell arrays MCA1 and MCA2 in the second region R2. For example, the page buffer PB can be disposed below the memory cell arrays MCA1 and MCA2 to overlap with them. However, in the example embodiment, the circuitry included in the first region R1 and its arrangement can be varied. Therefore, the circuitry configured to overlap with the memory cell arrays MCA1 and MCA2 can also be varied.

[0025] In the second region R2, the memory cell arrays MCA1 and MCA2 can be arranged to be spaced apart from each other. In the example embodiment, the number and arrangement of the memory cell arrays MCA1 and MCA2 in the second region R2 can be changed in various ways.

[0026] The first through-wire region TB1 and the second through-wire region TB2 may include wiring structures that pass through the second region R2 and connect to the first region R1. The first through-wire region TB1 may be disposed on at least one side of the memory cell arrays MCA1 and MCA2, and may include wiring structures such as contact plugs electrically connected to the row decoder DEC in the first region R1. The second through-wire regions TB2 may be disposed in the memory cell arrays MCA1 and MCA2 at predetermined intervals, and may include wiring structures such as page buffers PB electrically connected to the first region R1. The number of first through-wire regions TB1 may be greater than the number of second through-wire regions TB2, but the shape, number, arrangement, etc. of the first through-wire regions TB1 and the second through-wire regions TB2 may be varied in the example embodiments.

[0027] Figure 2 This is a schematic plan view of a semiconductor device according to an example embodiment.

[0028] Figures 3A to 3D This is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figures 3A to 3D Showing along respectively Figure 2The cross sections taken by lines I-I', II-II', III-III' and IV-IV' in the diagram.

[0029] Reference Figure 2 and Figures 3A to 3D The semiconductor device 100 may include a memory cell region (CELL), a peripheral circuit region (PERI) (here, the peripheral circuit region PERI corresponds to a first peripheral circuit PERI and a second peripheral circuit PERI), and a through wiring region (TB). In an example embodiment, the memory cell region (CELL) may be disposed above the peripheral circuit region (PERI), and the through wiring region (TB) may be configured to extend through the memory cell region (CELL) to the peripheral circuit region (PERI). In other example embodiments, the memory cell region (CELL) may be disposed below the peripheral circuit region (PERI). The peripheral circuit region (PERI) may correspond to... Figure 1 The first region R1 in the memory, the storage cell region CELL can include Figure 1 The storage cell arrays MCA1 and MCA2 are located in the memory.

[0030] The memory cell region (CELL) may include a substrate 101 having a first region A and a second region B, a gate electrode 130 stacked on the substrate 101, a first partition region MS1 ​​and a second partition region MS2 extending through the gate electrode 130 in a stacked structure, an upper partition region SS penetrating a portion of the stacked structure, and a channel structure CH configured to penetrate the stacked structure. The memory cell region (CELL) may also include: a substrate insulating layer 170 in the substrate 101; an interlayer insulating layer 120 alternately stacked on the substrate 101 with the gate electrode 130; a cell region insulating layer 190 covering the gate electrode 130; and a portion of a contact plug 180.

[0031] The first region A of the substrate 101 may be a region in which gate electrodes 130 are vertically stacked and a channel structure CH is formed. The second region B of the substrate 101 may be a region in which gate electrodes 130 extend at different lengths from each other, and may correspond to a region for electrically connecting memory cells to the peripheral circuit region PERI. The second region B may be disposed at at least one end of the first region A in at least one direction (e.g., the X direction).

[0032] Substrate 101 may have an upper surface extending in both the X and Y directions. Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a polycrystalline layer or an epitaxial layer.

[0033] A substrate insulating layer 170 may be disposed in an area where a portion of the substrate 101 is removed, and may be surrounded by the substrate 101. The substrate insulating layer 170 may have: an upper surface configured to be substantially coplanar with the upper surface of the substrate 101; and a lower surface configured to be coplanar with the lower surface of the substrate 101 or disposed at a level lower than the lower surface of the substrate 101. The substrate insulating layer 170 may comprise silicon oxide or silicon nitride. In an example embodiment, the substrate insulating layer 170 may be configured to surround the side surface of each contact plug 180.

[0034] Gate electrodes 130 may be vertically stacked and spaced apart on substrate 101 to form a stacked structure. Gate electrodes 130 may include electrodes that sequentially form a ground select transistor, a memory cell, and a string select transistor from the top of substrate 101. The number of gate electrodes 130 forming the memory cell may be determined based on the capacity of semiconductor device 100. In an example embodiment, one or more gate electrodes 130 may constitute each of the string select transistor and the ground select transistor, and may have the same or different structure as the gate electrode 130 of the memory cell. Gate electrodes 130 may also include a gate electrode 130 constituting an erase transistor and disposed above the gate electrode 130 constituting the string select transistor, which is used in an erase operation utilizing a gate-induced drain leakage (GIDL) mechanism. A portion of the gate electrode 130 (e.g., the gate electrode 130 adjacent to the gate electrode 130 constituting the string select transistor and the ground select transistor) may be a dummy gate electrode.

[0035] The gate electrodes 130 can be vertically stacked and spaced apart from each other on the first region A, and can extend from the first region A to the second region B at different lengths to form a stepped structure. For example... Figure 3B As shown, in at least a portion of the gate electrodes 130, excluding the uppermost gate electrode 130 and a portion of the lowermost gate electrode 130, a predetermined number of gate electrodes 130 (e.g., two, four, or six gate electrodes 130) can form a single gate group to form a stepped structure between the gate groups in the X direction. The gate electrodes 130 forming the single gate group can also be configured to form a stepped structure in the Y direction.

[0036] Due to this stepped structure, the gate electrode 130 can provide an end that exposes upward from the interlayer insulating layer 120 and forms a stepped shape, in which the lower gate electrode 130 extends longer than the upper gate electrode 130. At this end, the gate electrode 130 can have an upwardly increasing thickness. Figure 2As shown, the gate electrode 130 may have a pad region PAD, which is configured such that the end extending in the X direction bends in the Y direction to overlap with the through-wiring region TB. For example, the pad region PAD refers to the area of ​​the gate electrode 130 that overlaps with the through-wiring region TB. A single gate electrode 130 may have one or more pad regions PAD. The pad region PAD may extend into the through-wiring region TB and may connect to the contact plug 180 in the through-wiring region TB.

[0037] like Figure 2 As shown, the gate electrode 130 can be separated from the adjacent gate electrode 130 in the Y direction by a pair of first separating regions MS1 extending in the X direction. The gate electrodes 130 between the pair of first separating regions MS1 can form a single memory block, but the scope of the memory block is not limited thereto. A portion of the gate electrode 130 (e.g., the gate electrode constituting a memory cell) can be formed as a single layer in a single memory block.

[0038] The gate electrode 130 may include a metallic material such as tungsten (W). In an example embodiment, the gate electrode 130 may include polycrystalline silicon or a metal silicide material. In an example embodiment, the gate electrode 130 may also include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0039] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of substrate 101 and may extend in the X direction. Interlayer insulating layers 120 may include insulating materials such as silicon oxide or silicon nitride.

[0040] The first separating region MS1 ​​and the second separating region MS2 can be configured to extend through the gate electrode 130 in the X direction within the first region A and the second region B. The first separating region MS1 ​​and the second separating region MS2 can be arranged parallel to each other. The first separating region MS1 ​​and the second separating region MS2 can be connected to the substrate 101 through all the gate electrodes 130 stacked on the substrate 101. The first separating region MS1 ​​extends along the first region A and the second region B as a single region, and the second separating region MS2 extends from the first region A to only a portion of the second region B, or can be intermittently arranged within the first region A and the second region B. The first separating region MS1 ​​and the second separating region MS2 can be configured not to overlap with the through wiring region TB and can be spaced apart from the through wiring region TB. However, in the example embodiment, the arrangement order, number, etc., of the first separating region MS1 ​​and the second separating region MS2 are not limited to... Figure 2 Those shown.

[0041] like Figure 3D As shown, a separating insulating layer 160 may be disposed in the first separating region MS1 ​​and the second separating region MS2. In an example embodiment, due to the high aspect ratio, the separating insulating layer 160 may have a shape in which its width decreases in the direction toward the substrate 101. However, in an example embodiment, a conductive layer may be further disposed between the separating insulating layers 160 in the first separating region MS1 ​​and the second separating region MS2. In this case, the conductive layer may serve as a common source line of the semiconductor device 100 or a contact plug connected to a common source line.

[0042] The upper dividing region SS can extend in the X direction between the first dividing region MS1 ​​and the second dividing region MS2. The upper dividing region SS can be located in a portion of the second region B and the first region A to penetrate a portion of the gate electrode 130, including the uppermost gate electrode 130. For example... Figure 3D As shown, the upper separating region SS can separate the three gate electrodes 130 from each other in the Y direction. However, the number of gate electrodes 130 separated by the upper separating region SS can vary depending on the exemplary embodiment. The upper separating region SS may include an upper separating insulating layer 103.

[0043] Each channel structure CH can constitute a single memory cell string and can be spaced apart from each other in rows and columns on the first region A. The channel structures CH can be arranged in a grid pattern or in a zigzag pattern in one direction. The channel structures CH can have a cylindrical shape and can have sloping side surfaces depending on the aspect ratio, such that the width of the channel structures CH narrows towards the substrate 101. In an example embodiment, dummy channels that do not substantially constitute memory cell strings can be further provided at the end of the first region A adjacent to the second region B and on the second region B. For example, the dummy channels can be arranged as shown below. Figure 9A The form of the description.

[0044] A channel layer 140 may be disposed in a channel structure CH. In the channel structure CH, the channel layer 140 may be formed in an annular shape having a channel insulating layer 150 surrounding it. However, according to an example embodiment, the channel layer 140 may have a columnar shape, such as a cylinder or prism, without the channel insulating layer 150. The channel layer 140 may be connected at its lower portion to a first horizontal conductive layer 102. The channel layer 140 may comprise a semiconductor material such as polysilicon or monocrystalline silicon. The channel structure CH, which is arranged as a straight line in the Y direction between the first separating region MS1 ​​or the second separating region MS2 and the upper separating region SS, may be connected to different bit lines depending on the arrangement of the upper wiring structure connected to the channel pad 155. Although not shown, channel contact plugs may be disposed on the channel pad 155 to form an upper wiring structure.

[0045] Channel pads 155 may be disposed on the channel layer 140 in the channel structure CH. Channel pads 155 may be configured to cover the top surface of the channel insulating layer 150 and be electrically connected to the channel layer 140. Channel pads 155 may include, for example, doped polysilicon.

[0046] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer stacked sequentially from the channel layer 140. The tunneling layer allows charge to tunnel to the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), a high-k dielectric material, or combinations thereof. In an example embodiment, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130.

[0047] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be stacked on the upper surface of the substrate 101. At least a portion of the first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be used as part of the common source line of the semiconductor device 100, and can be used together with the substrate 101 as the common source line. Figure 3D As shown in the enlarged view, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 near the channel layer 140. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can include semiconductor materials, such as polysilicon. In this case, at least the first horizontal conductive layer 102 can be a doped layer, and the second horizontal conductive layer 104 can be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102.

[0048] A horizontal insulating layer 110 may be disposed in the region where the first horizontal conductive layer 102 and the second horizontal conductive layer 104 are removed in the second region B of the substrate 101. The horizontal insulating layer 110 may be formed of an insulating material and may include, for example, silicon oxide, silicon oxide nitride, or silicon nitride. In an example embodiment, the horizontal insulating layer 110 may be omitted.

[0049] The cell region insulating layer 190 can be configured to cover the substrate 101, the gate electrode 130 on the substrate 101, and the peripheral region insulating layer 290. The cell region insulating layer 190 may include a first cell region insulating layer 192 and a second cell region insulating layer 194, each of which may also include multiple insulating layers. The cell region insulating layer 190 can be formed of an insulating material.

[0050] Through-caching area TB can be with Figure 1 The first through-wiring region TB1 corresponds to the region and may include a wiring structure for electrically connecting the memory cell region CELL and the peripheral circuit region PERI (e.g., the line decoder DEC) to each other. The through-wiring region TB may include: a contact plug 180 and a through-path 185 extending from above through the substrate 101 in the Z direction; and an interlayer insulating layer 120 and a sacrificial insulating layer 118 surrounding the contact plug 180 and the through-path 185 and forming an insulating region. The through-wiring region TB may have a slit region SL configured to contact (e.g., directly adjacent to) the pad region PAD of the gate electrode 130. The through-wiring region TB may be provided in a second region B; for example, one through-wiring region TB may be provided for each of one or more memory blocks. However, Figure 2 The size, arrangement, and shape of the through-wiring area TB shown can vary according to the example implementation.

[0051] The through-wiring area TB can be spaced apart from the first dividing area MS1 and the second dividing area MS2. For example, the through-wiring area TB can be positioned at the center of a pair of adjacent first dividing areas MS1 in the Y direction. Such an arrangement allows the sacrificial insulation layer 118 to be retained within the through-wiring area TB, which will be referred to later. Figure 16A and Figure 16B For a more detailed description, the gate electrode 130 may not extend into the through-wiring area TB, except for the pad area PAD.

[0052] The sacrificial insulating layer 118 constituting the insulating region of the through-wiring region TB may be configured to have the same thickness as the gate electrode 130 at the same height level as the gate electrode 130, and may have a side surface configured to contact the gate electrode 130 at the boundary of the through-wiring region TB. The sacrificial insulating layer 118 may be alternately stacked with the interlayer insulating layer 120 to form the insulating region. The sacrificial insulating layer 118 may be formed of an insulating material different from the material of the interlayer insulating layer 120, and may include, for example, silicon oxide, silicon nitride, or silicon nitride. Figure 2 The shape of the sacrificial insulation layer 118 at the boundary of the through wiring area TB can vary according to the example implementation.

[0053] The contact plug 180 of the through-wiring region TB can extend in a direction perpendicular to the upper surface of the substrate 101, passing through the cell region insulating layer 190, the pad region PAD of the gate electrode 130, the insulating region of the through-wiring region TB, the substrate 101, and a portion of the peripheral region insulating layer 290. The contact plug 180 can be connected to the circuit wiring 280 below it. The contact plug 180 can electrically connect the gate electrode 130 and the circuit elements 220 of the peripheral circuit region PERI to each other. Specifically, each contact plug 180 can pass through the pad region PAD of the gate electrode 130 in the uppermost part of the stacked structure of the gate electrode 130 to connect to the gate electrode 130 in the pad region PAD, and can penetrate the sacrificial insulating layer 118 and the interlayer insulating layer 120 constituting the insulating region disposed therebelow, such as... Figure 3A and Figure 3C As shown. Therefore, a single contact plug 180 can be physically and electrically connected to the pad area PAD of a gate electrode 130. However, in an example embodiment, for example, when the gate electrode 130 does not have a stepped structure in the Y direction, multiple contact plugs 180 can be connected to multiple pad areas PAD of a single gate electrode 130.

[0054] In the contact plug 180, the contact plug 180 located outside the through wiring area TB can be connected to a portion of the gate electrode 130 including the uppermost gate electrode 130, and can be configured not to penetrate the gate electrode 130.

[0055] The through-path 185 extends from above through the cell region insulating layer 190, the insulating region of the through wiring region TB, the substrate 101, and a portion of the peripheral region insulating layer 290 in a direction perpendicular to the upper surface of the substrate 101, reaching the substrate 101. Unlike the contact plug 180, the through-path 185 may not be connected to the gate electrode 130 and may extend downwards only through the insulating region of the through wiring region TB. The through-path 185 may be connected to the circuit wiring 280 below it. The through-path 185 can electrically connect the overlay wiring (not shown) and the circuit elements 220 of the peripheral circuit region PERI to each other. For example, the wiring may be electrically connected to a portion of the gate electrode 130 or a portion of the channel layer 140 of the channel structure CH. The number, arrangement, and shape of the contact plugs 180 and through-paths 185 in a single through wiring region TB may vary according to exemplary embodiments. The contact plugs 180 and through-paths 185 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0056] A slit region SL can be disposed on one side of the pad region PAD of the gate electrode 130. For example, the slit region SL can be configured to contact (e.g., be directly adjacent to) the inner side surface of the opposite side surface of the pad region PAD in the X direction, closer to the first region A. The slit region SL can be used to control etching during the process of forming the pad region PAD to define the inner boundary of the pad region PAD, so that adjacent pad regions PAD can be formed to be spaced apart from each other. This will be referred to later. Figure 16A and Figure 16B To describe in more detail.

[0057] The slit region SL can be an insulating region. For example... Figure 3A As shown, the slit region SL may include a portion of the insulating region through which the wiring region TB is removed from its upper surface. For example... Figure 2 and Figure 3AAs shown, each slit region SL can be disposed on the left side of the pad region PAD, such that the pad region PAD is spaced apart from the sacrificial insulating layer 118 having the same level. The slit region SL can be configured to penetrate the sacrificial insulating layer 118 having the same level as the pad region PAD and expose the interlayer insulating layer 120 disposed thereunder. The side end of the slit region SL in the X direction (e.g., the left end in the figure) can be aligned with the right end of the adjacent left gate electrode 130 on a line in the Z direction. For example, the slit region SL can have an end disposed below and in line with the end of the gate electrode 130 extending to the same length. Since the slit region SL can prevent the pad region PAD from extending in the X direction, physical separation between pad region PADs disposed adjacent to each other in the X direction can be ensured. In an example embodiment, the slit region SL can be disposed on one side of only a portion of the pad region PAD of the gate electrode 130. For example, the slit region SL may not be disposed on one side of the uppermost pad region PAD among the pad region PADs of the gate electrode 130.

[0058] The slit region SL can be filled with the cell region insulating layer 190, and the cell region insulating layer 190 can contact the exposed interlayer insulating layer 120 in the slit region SL. Therefore, both side surfaces of the pad region PAD in the X direction can be completely covered by the cell region insulating layer 190. The cell region insulating layer 190 can include a material different from that of the sacrificial insulating layer 118, so the boundary between the cell region insulating layer 190 in the slit region SL and the sacrificial insulating layer 118 configured to contact it can be separated from each other.

[0059] like Figure 2 As shown in the enlarged view, the slot region SL has a first length L1 in the X direction and a second length L2 in the Y direction that is greater than the first length L1. Therefore, the slot region SL can have a rectangular or elliptical shape extending in the Y direction. At least a portion of the right side surface of the slot region SL can contact the pad region PAD (e.g., be directly adjacent to the pad region PAD). The pad region PAD can have a third length L3 in the X direction and a fourth length L4 in the Y direction. The fourth length L4 can be greater than the third length L3, but is not limited thereto. For example, the second length L2 of the slot region SL can be about 80% or more of the fourth length L4 of the pad region PAD. As a result, the slot region SL can allow the pad regions PAD to be stably spaced apart from each other. Furthermore, the first length L1 of the slot region SL can be, for example, in the range from about 30 nm to about 130 nm. When the first length L1 is less than this range, it may be difficult to perform the forming process. When the first length L1 is greater than this range, it may be difficult to ensure the dimensions of the pad region PAD.

[0060] In the example implementation, only one slot region SL is provided at the boundary between two pad regions PAD. Each slot region SL may perpendicularly pass through the end side of the corresponding pad in the pad region PAD and contact the edge of the corresponding pad. The slot regions SL (e.g., two adjacent slot regions SL at the same Y-direction location) may be arranged parallel to each other in the X-direction. The X-direction distance L3 between the slot regions SL may be substantially the same.

[0061] The peripheral circuit area PERI may include a substrate 201, circuit elements 220 disposed on the substrate 201, circuit contact plugs 270 and circuit wiring 280.

[0062] The substrate 201 may have an upper surface extending in both the X and Y directions. An additional device isolation layer may be formed in the substrate 201 to define an active region. Source / drain regions 205, including impurities, may be disposed within a portion of the active region. The substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0063] Circuit element 220 may include a planar transistor. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be formed in the substrate 201 on opposite sides of the circuit gate electrode 225.

[0064] A peripheral insulating layer 290 can be disposed on circuit elements 220 on a substrate 201. Circuit contact plugs 270 can pass through the peripheral insulating layer 290 and connect to the source / drain region 205. Electrical signals can be applied to the circuit elements 220 through the circuit contact plugs 270. In areas not shown, the circuit contact plugs 270 can also be connected to the circuit gate electrode 225. Circuit wiring 280 can be connected to the circuit contact plugs 270 and can be configured in multiple layers. The uppermost circuit wiring 280 can be directly connected to the contact plugs 180 and the through-path 185 within the through wiring region TB.

[0065] According to the example embodiment, the peripheral circuit region PERI can be disposed on the substrate 101 together with the memory cell region CELL and on one side of the memory cell region CELL. In this case, the gate electrode 130 of the memory cell region CELL can be bent and extended onto the circuit element 220 of the peripheral circuit region PERI, and the above description can be equally applied to other contents.

[0066] Figure 4 This is a perspective view of an element of a semiconductor device including a gate electrode according to an example embodiment.

[0067] Figure 5 It is a plan view including a gate electrode of a semiconductor device according to an example embodiment.

[0068] Reference Figure 4 This is shown in a pair of first dividing regions MS1 (see Figure 2 The stacked structure of the gate electrode 130 and the sacrificial insulating layer 118 between the gate electrodes 130. Among the gate electrodes 130, the upper gate electrode 130F can be separated by a first separating region MS1, a second separating region MS2, and an upper separating region SS, such that each upper gate electrode 130F may include four layers at the same level. The lower gate electrodes 130S may each include a single layer and may form a stepped structure in the X and Y directions. However, according to an exemplary embodiment, the lowermost gate electrode 130 may not form a stepped structure in the Y direction with the upper gate electrodes 130.

[0069] The lower gate electrode 130S may have a pad region PAD that bends along the Y direction at its end to extend inside the through wiring region TB. The pad regions PAD of the lower gate electrode 130S may be in a state where they are exposed upward in the upper part of the stacked structure, and the sacrificial insulating layer 118 constituting the insulating region of the through wiring region TB may be in a state where they are stacked below the pad regions PAD.

[0070] The slit region SL can be configured to penetrate at least the uppermost sacrificial insulating layer 118 inside the pad region PAD. The slit region SL can be configured between adjacent pad regions PAD along the X direction.

[0071] Reference Figure 5 The diagram shows a plane including a single lower gate electrode 130S. The lower gate electrode 130S can be configured to contact a sacrificial insulating layer 118 having the same level as the lower gate electrode 130S and forming a through wiring region TB, and can be spaced apart from the sacrificial insulating layer 118 inside the pad region PAD by a slit region SL. The contact plug 180 can be configured to penetrate the pad region PAD, and the through path 185 can be configured to penetrate the sacrificial insulating layer 118.

[0072] Figure 6A and Figure 6B This is a plan view of a semiconductor device according to an example implementation.

[0073] Reference Figure 6AIn semiconductor device 100a, the slit region SLa can have a shape that curves along the end of the gate electrode 130 from the inner side surface of the pad region PAD on one side. For example, the slit region SLa can be "L"-shaped. Thus, the sacrificial insulating layer 118 and the slit region SLa can be disposed between two pad regions PAD that are adjacent to each other in the X direction. However, in the example embodiment, the shape of the slit region SLa is not limited to this. For example, the slit region SLa can have various shapes such as a triangle, which contacts (e.g., is directly adjacent to) the inner side surface of the pad region PAD and the end of the gate electrode 130 in the Y direction.

[0074] Reference Figure 6B In semiconductor device 100b, the slit region SLb can extend relatively long in the Y direction within the through wiring region TB. Specifically, the corresponding slit region SLb can extend to contact (e.g., be directly adjacent to) a plurality of pad regions PAD arranged side-by-side in the Y direction. As described above, according to the example embodiment, the length of the slit region SLb in the Y direction can be greater than the length of the pad regions PAD in the Y direction.

[0075] Figure 7A and Figure 7B This is a plan view of a semiconductor device according to an example implementation.

[0076] Reference Figure 7A In semiconductor device 100c, pad regions PAD can have different lengths in the Y direction, and the lengths of the pad regions PAD protruding into the through wiring region TB (e.g., the lengths overlapping with the through wiring region TB) can be different from each other. For example, as Figure 7A As shown, the length of the pad area PAD can decrease in the direction away from the first region A. The pad area PAD closest to the first region A can have a fourth length L4 in the Y direction, and the pad area PAD furthest from the first region A can have a sixth length L6 in the Y direction that is shorter than the fourth length L4. The contact plug 180 can be spaced apart from the end of each pad area PAD by a predetermined distance in the Y direction.

[0077] Reference Figure 7B In semiconductor device 100d, the pad area PAD can have the same characteristics as... Figure 7A The same shape is described in the example implementation, but the arrangement of the contact plug 180 can be the same as in... Figure 7A The arrangement differs from that described in the example. The contact plugs 180 can be arranged in a zigzag pattern in the pad area PAD in the X direction. However, according to the example embodiment, the contact plugs 180 can be arranged in a straight line in the X direction.

[0078] Figures 8A to 8C This is a cross-sectional view of a semiconductor device according to an example embodiment. Figures 8A to 8C Each of the examples shown corresponds to Figure 3A The cross section.

[0079] Reference Figure 8A In semiconductor device 100e, one end of the slit region SL in the X direction (e.g., the left end in the figure) can be offset in the X direction from the right end of the adjacent left gate electrode 130. Therefore, the sacrificial insulating layer 118 and the slit region SL can be positioned between two pad regions PAD that are adjacent to each other in the X direction. The offset length L7 from the end of the gate electrode 130 adjacent to the slit region SL can vary within a range that ensures the width of the pad region PAD.

[0080] Reference Figure 8B In semiconductor device 100f, the depth D1 of the slit region SLf recessed in the Z direction from the upper surface of the sacrificial insulating layer 118 and the interlayer insulating layer 120 of the stacked structure can be related to... Figure 3A The examples differ from the implementation examples. Each slit region SLf can be configured to penetrate the two sacrificial insulating layers 118 and the interlayer insulating layer 120 therebetween to expose the underlying interlayer insulating layer 120. For example, each slit region SLf can be disposed between two pad regions PAD, the two pad regions PAD comprising an upper pad region and a lower pad region disposed at different levels from each other. As described above, the extension depth of the slit regions SLf can vary according to the example implementation examples. Furthermore, the extension depth of the slit regions SLf can differ from each other within the slit regions SLf.

[0081] Reference Figure 8C In the semiconductor device 100g, the slit regions SL can have different lengths in the X direction. For example, the length of the slit region SL in the X direction can increase in the direction away from the first region A. The slit region SL closest to the first region A can have an eighth length L8 in the X direction, and the slit region SL furthest from the first region A can have a ninth length L9 in the X direction that is greater than the eighth length L8. The length of the slit region SL in the X direction can vary according to an example embodiment. In the example embodiment, the length of the slit region SL can be related to the depth (e.g., in...). Figure 8B In the example implementation, the shape of the slit region SL, including its length and depth, can vary from one another to the other. As described above, in the example implementation, the shape of the slit region SL, including its length and depth, can vary from one another to the other.

[0082] Figure 9A and Figure 9B These are schematic plan views and schematic cross-sectional views of a semiconductor device according to an example embodiment. Figure 9BShow along Figure 9A The cross section intercepted by line I-I' in the middle.

[0083] Reference Figure 9A and Figure 9B The semiconductor device 100h may further include a dummy channel structure DCH disposed in the memory cell region CELL and the through wiring region TB. The dummy channel structure DCH may be regularly disposed in the second region B and the through wiring region TB of the substrate 101. The dummy channel structure DCH may have the same internal structure as the channel structure CH, and may have the same or different dimensions and shapes as the channel structure CH. The dummy channel structure DCH may be configured to penetrate at least one gate electrode 130. However, in an example embodiment, the dummy channel structure DCH may also be provided in the through wiring region TB to penetrate the sacrificial insulating layer 118 and the interlayer insulating layer 120. In an example embodiment, the dummy channel structure DCH configured to surround the contact plug 180 in four places may be omitted in the through wiring region TB. In this case, process margin during the formation of the contact plug 180 can be further ensured.

[0084] In this embodiment, the slit region SLh can have the same structure as the dummy channel structure DCH. Therefore, each slit region SLh may include a channel layer 140, a gate dielectric layer 145, a channel insulating layer 150, and a channel pad 155 provided therein. Similar to the dummy channel structure DCH, the slit region SLh can be configured to extend from the upper surface of the first cell region insulating layer 192 to the substrate 101. However, as... Figure 9A As shown, since the slit region SLh has a shape that extends along one side of the pad region PAD, when viewed from above, the slit region SLh can have a different shape than the shape of the dummy channel structure DCH.

[0085] Figure 10 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 10 Showing the corresponding Figure 3A The cross section.

[0086] Reference Figure 10 In semiconductor device 100i, similar to Figure 9B In one implementation, the slit region SLi can be configured to extend into the substrate 101. Figure 9BThe implementation differs from that of the channel structure CH and the dummy channel structure DCH. The slit region SLi does not have the same structure, and may include a columnar slit insulating layer 119. In this embodiment, similar to the slit region SLi, a support structure including the insulating layer may be further provided in the second region B, but this disclosure is not limited thereto. Additionally, in the example embodiment, the height of the upper surface of the slit insulating layer 119 may differ from the height of the upper surface of the channel structure CH.

[0087] Figure 11A and Figure 11B These are schematic plan views and schematic cross-sectional views of a semiconductor device according to an example embodiment. Figure 11B Show along Figure 11A The cross section intercepted by line IV-IV' in the middle.

[0088] Reference Figure 11A and Figure 11B In the semiconductor device 100j, the stacked structure of the gate electrode 130 may include a lower stacked structure and an upper stacked structure stacked in the vertical direction, and the channel structure CHj may include a first channel structure CH1 and a second channel structure CH2 stacked in the vertical direction. When there are a relatively large number of stacked gate electrodes 130, such a configuration of the channel structure CHj can be introduced to stably form the channel structure CHj.

[0089] The channel structure CHj can have a form in which a first channel structure CH1 provided at its lower portion and a second channel structure CH2 provided at its upper portion are connected to each other, and have a curved portion due to the width difference in the connection region. The channel layer 140, the gate dielectric layer 145, and the channel insulating layer 150 can be in a state where they are connected to each other between the first channel structure CH1 and the second channel structure CH2. The channel pad 155 can be provided only on the upper end of the upper second channel structure CH2. However, in an exemplary embodiment, each of the first channel structure CH1 and the second channel structure CH2 may include a channel pad 155. In this case, the channel pad 155 of the first channel structure CH1 can be connected to the channel layer 140 of the second channel structure CH2. An upper interlayer insulating layer 125 with a relatively large thickness can be provided on the uppermost portion of the lower stack structure. However, the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 can vary according to the exemplary embodiment.

[0090] Similar to Figure 7A and Figure 7BIn this implementation, the pad regions PAD can have different lengths in the Y direction, and the lengths of the pad regions PAD protruding to the through wiring area TB can be different from each other. For example, the length of the pad regions PAD can decrease in the direction away from the first region A. Specifically, in each of the lower and upper stack structures, the length of the pad regions PAD can decrease in the direction away from the first region A. The contact plugs 180 can be spaced apart from the ends of each pad region PAD in the Y direction by a predetermined distance, but the arrangement of the contact plugs 180 is not limited to this.

[0091] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B Showing with Figure 2 and Figure 3A The area shown corresponds to the area shown.

[0092] Reference Figure 12A and Figure 12B Circuit elements 220 and lower wiring structures can be formed on the substrate 201 to form a peripheral circuit region PERI. After the substrate 101 is formed on the peripheral circuit region PERI, a substrate insulating layer 170 can be formed, a first horizontal sacrificial layer 111 and a second horizontal sacrificial layer 112 and a second horizontal conductive layer 104 can be formed, and sacrificial insulating layers 118 and interlayer insulating layers 120 can be stacked alternately, and then an initial slit region SLp can be formed.

[0093] A gate dielectric layer 222 and a gate electrode 225 may be sequentially formed on a substrate 201. The gate dielectric layer 222 and the gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The gate dielectric layer 222 may be formed of silicon oxide, and the gate electrode 225 may be formed of at least one of polysilicon and metal silicide, but the materials are not limited thereto. A spacer layer 224 may be formed on both sidewalls of the gate dielectric layer 222 and the gate electrode 225. In an example embodiment, the spacer layer 224 may comprise multiple layers. An ion implantation process may then be performed to form source / drain regions 205. The source / drain regions 205 may be formed on both sides of the gate dielectric layer 222 and the gate electrode 225.

[0094] In the lower wiring structure, the circuit contact plug 270 can be formed by forming a portion of the peripheral region insulating layer 290, etching the portion to be removed, and filling the removed portion with conductive material. The circuit wiring 280 can be formed, for example, by depositing conductive material and patterning the deposited conductive material.

[0095] The peripheral region insulating layer 290 may include multiple insulating layers. A portion of the peripheral region insulating layer 290 may be formed in each operation forming the lower wiring structure, and another portion may be formed on the uppermost circuit wiring 280. Ultimately, the peripheral region insulating layer 290 may be formed to cover the circuit element 220 and the lower wiring structure.

[0096] Substrate 101 can be formed on peripheral region insulating layer 290. Substrate 101 can be formed of, for example, polysilicon and can be formed by chemical vapor deposition (CVD) process. The polysilicon forming substrate 101 may include impurities. Substrate 101 can be formed to have a size less than or equal to the size of substrate 201. Substrate insulating layer 170 can be formed on a portion of substrate 101 (e.g., with the through wiring region TB (see...)). Figure 2 It is formed by removing the substrate 101 in the corresponding area and filling the removed portion with insulating material.

[0097] A first horizontal sacrificial layer 111 and a second horizontal sacrificial layer 112 can be stacked on the substrate 101, such that the first horizontal sacrificial layer 111 is disposed above and below the second horizontal sacrificial layer 112. The first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 can comprise different materials from each other. The first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 can be processed using subsequent processes... Figure 3AThe first horizontal conductive layer 102 is replaced. For example, the first horizontal sacrificial layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal sacrificial layer 112 may be formed of the same material as the sacrificial insulating layer 118. The second horizontal conductive layer 104 may be formed on the first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112. The first horizontal sacrificial layer 111, the second horizontal sacrificial layer 112, and the second horizontal conductive layer 104 may be removed in the second region B, and the horizontal insulating layer 110 may be formed in the removed region.

[0098] The sacrificial insulating layer 118 may have been formed by the gate electrode 130 (see [link]) through a subsequent process. Figure 3A The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material that can be etched under specific etch conditions using etch selectivity relative to the interlayer insulating layer 120. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In example embodiments, the thickness of the interlayer insulating layer 120 may not all be the same. The thickness and number of the interlayer insulating layer 120 and the sacrificial insulating layer 118 may differ from those shown in the figures.

[0099] A portion of the stacked structure of sacrificial insulation layer 118 and interlayer insulation layer 120 can be removed from the top surface to form the initial slit region SLp. (In the corresponding...) Figure 3A The location of the slit region SL, the initial slit region SLp can penetrate the uppermost sacrificial insulation layer 118 and can extend to a portion of the lower interlayer insulation layer 120 to expose the interlayer insulation layer 120.

[0100] Reference Figure 13A and Figure 13B In the second region B, a portion of the stacked structure of the sacrificial insulation layer 118 and the interlayer insulation layer 120 can be removed, and a slit region SL can be formed.

[0101] Photolithography and etching processes can be repeatedly performed on the sacrificial insulating layer 118 using a mask layer, such that in the second region B, the upper sacrificial insulating layer 118 extends shorter than the lower sacrificial insulating layer 118. Therefore, the sacrificial insulating layer 118 can form a stepped structure in predetermined groups. During the above processes, the shape of the initial slit region SLp can be reflected in the lower part of the stacked structure to form a slit region SL adjacent to the stepped structure.

[0102] Reference Figure 14A and Figure 14BAn additional sacrificial insulation layer EA can be formed on a portion of the sacrificial insulation layer 118, such that the end of the sacrificial insulation layer 118 can be formed to have a large thickness.

[0103] An additional sacrificial insulating layer EA may be formed on the X-direction end of the sacrificial insulating layer 118 to have a predetermined width. The additional sacrificial insulating layer EA may form part of the sacrificial insulating layer 118. Figure 14A , Figure 14B , Figure 15A and Figure 15B In the diagram, the additional sacrificial insulation layer EA is shown as different from the pre-formed sacrificial insulation layer 118.

[0104] Before forming the additional sacrificial insulation layer EA, the spacer layer can be formed as a sidewall covering the stepped structure of the sacrificial insulation layer 118. Then, the additional sacrificial insulation layer EA can be formed and the spacer layer can be removed. The length of the additional sacrificial insulation layer EA in the X direction can be less than or equal to the length of the sacrificial insulation layer 118 in the X direction. Figure 14A In the diagram, the left end of the additional sacrificial insulation layer EA is shown positioned on the same line in the Y direction as the right end of the slit region SL. However, the arrangement of the additional sacrificial insulation layer EA and the slit region SL is not limited to this.

[0105] The additional sacrificial insulating layer EA may include a material having a different composition from that of the pre-formed sacrificial insulating layer 118. For example, both the additional sacrificial insulating layer EA and the sacrificial insulating layer 118 may include silicon nitrides, but may have different proportions of silicon (Si) and nitrogen (N), or the additional sacrificial insulating layer EA may include a greater amount of impurities.

[0106] The first unit region insulating layer 192 can be formed as the upper part of a stacked structure covering the sacrificial insulating layer 118 and the interlayer insulating layer 120. A portion of the first unit region insulating layer 192 can be removed and replaced with the interlayer insulating layer 120.

[0107] Reference Figure 15A and Figure 15B The channel structure CH can be formed through the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120.

[0108] A portion of the sacrificial insulation layer 118 and a portion of the interlayer insulation layer 120 can be removed to form the upper separating region SS. The upper separating region SS can be formed by: exposing the area in which the upper separating region SS will be formed using an additional mask layer, removing a predetermined number of sacrificial insulation layers 118 and interlayer insulation layers 120 to form the uppermost portion, and depositing insulating material. However, in the example embodiment, in reference... Figure 12A and Figure 12BIn the described process, the upper partition region SS can be formed before or after the formation of the initial slit region SLp.

[0109] The channel structure CH can be formed by anisotropically etching the sacrificial insulating layer 118 and the interlayer insulating layer 120, and can also be formed by forming a via and filling the via. Due to the height of the stacked structure, the sidewalls of the channel structure CH may not be perpendicular to the upper surface of the substrate 101. The channel structure CH can be formed such that a portion of the substrate 101 is recessed. At least a portion of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and the channel pad 155 can be sequentially formed in the channel structure CH.

[0110] The gate dielectric layer 145 can be formed to have a uniform thickness using an ALD or CVD process. In this operation, all or a portion of the gate dielectric layer 145 can be formed, and a portion extending along the channel structure CH in a direction perpendicular to the substrate 101 can be formed. A channel layer 140 can be formed on the gate dielectric layer 145 within the channel structure CH. A channel insulating layer 150 is formed to fill the channel structure CH and may include an insulating material. However, in an example embodiment, the space within the channel layer 140 can be filled with a conductive material instead of the channel insulating layer 150. The channel pads 155 can be formed of a conductive material (e.g., polysilicon).

[0111] Reference Figure 16A and Figure 16B The first separating region MS1 ​​and the second separating region MS2 can be formed as openings to penetrate the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120. A portion of the sacrificial insulating layer 118 can be removed through the opening to form the tunnel portion LT and the pad space PS.

[0112] Before forming the first partition region MS1 ​​and the second partition region MS2, a portion of the second cell region insulating layer 194 may be formed on the channel structure CH. After the additional sacrificial spacer layer is formed in the first partition region MS1 ​​and the second partition region MS2, the second horizontal sacrificial layer 112 may be selectively removed, and then the first horizontal sacrificial layer 111 may be removed. The first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 may be removed, for example, by a wet etching process. In the process of removing the first horizontal sacrificial layer 111, the exposed portion of the gate dielectric layer 145 may also be removed in the region where the second horizontal sacrificial layer 112 is removed. Conductive material may be deposited on the region where the first horizontal sacrificial layer 111 and the second horizontal sacrificial layer 112 are removed to form a first horizontal conductive layer 102, and then the sacrificial spacer layer may be removed in the first partition region MS1 ​​and the second partition region MS2.

[0113] Outside the through-hole routing region TB, the sacrificial insulating layer 118 can be removed. Within the through-hole routing region TB, the sacrificial insulating layer 118 can be retained and, together with the interlayer insulating layer 120, form the insulating region of the through-hole routing region TB. The sacrificial insulating layer 118 can be selectively removed relative to the interlayer insulating layer 120, for example, using wet etching. Therefore, multiple tunnel portions LT can be formed between the interlayer insulating layers 120, and pad spaces PS can be formed in the region corresponding to the pad regions PAD.

[0114] The region where the through wiring region TB is formed is spaced apart from the first separating region MS1 ​​and the second separating region MS2. Therefore, since the etchant does not reach the region, the sacrificial insulating layer 118 can remain in the region. Thus, the through wiring region TB is formed at the center of a pair of adjacent first separating regions MS1. In this case, in the sacrificial insulating layer 118, as described above... Figure 14A and Figure 14B The exposed upper region corresponding to the additional sacrificial insulating layer EA described herein can have an etch rate different from that of the other region formed below it, and can be etched relatively quickly in a wet etching process. Therefore, in the upwardly exposed sacrificial insulating layer 118, the process of removing the sacrificial insulating layer 118 can be performed relatively quickly along the Y direction in which the additional sacrificial insulating layer EA is positioned. As a result, pad spaces PS can be formed.

[0115] During the wet etching process, the internal boundaries of the pad spaces PS can be controlled by the slot region SL. Therefore, the pad spaces PS can be spaced apart in the X direction so that they do not overlap in the plane. For example, in the absence of the slot region SL, the left boundary of the pad spaces PS can be formed with a shape similar to... Figure 16A The slope of the left end of the through-wiring area TB is similar to that of the through-wiring area TB, and some areas can be formed to overlap each other perpendicularly between the vertically stacked pad spaces PS. However, in this embodiment, since the etchant does not flow into the area where the slit area SL is formed, the pad spaces PS can be completely spaced apart in the X direction and thus not overlap each other perpendicularly.

[0116] Reference Figure 17A and Figure 17B The pad space PS and tunnel portion LT, in which a portion of the sacrificial insulating layer 118 has been removed, can be filled with conductive material to form the gate electrode 130.

[0117] The conductive material forming the gate electrode 130 can fill the tunnel portion LT and the pad space PS. In the through-wiring region TB, the conductive material filling the pad space PS can form the pad region PAD of the gate electrode 130. The side surface of the gate electrode 130 can contact the side surface of the sacrificial insulating layer 118 of the through-wiring region TB. This conductive material can include metal, polysilicon, or metal silicide.

[0118] After the gate electrode 130 is formed, the conductive material deposited in the openings of the first separation region MS1 ​​and the second separation region MS2 can be removed by another process. The removed portions can then be filled with an insulating material to form a separating insulating layer 160 (see...). Figure 3C and Figure 3D ).

[0119] A second unit region insulating layer 194 can be further formed to form a unit region insulating layer 190 including a first unit region insulating layer 192 and a second unit region insulating layer 194.

[0120] Return to Figure 2 and Figures 3A to 3D This can form a contact plug 180 and a through passage 185.

[0121] Contact holes can be formed and then filled with a conductive material to form contact plugs 180 and through-paths 185. The contact holes can extend from above to penetrate the substrate 101 and can expose the circuit wiring 280 of the peripheral circuit area PERI at their lower end. Wiring can then be further formed to connect to the through-path 185.

[0122] As described above, the slit region can be formed to contact the pad region of the gate electrode. Therefore, a semiconductor device with improved reliability can be provided.

[0123] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the inventive concept as defined by the appended claims.

[0124] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0147722, filed on November 18, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The peripheral circuit area includes a first substrate, circuit elements disposed on the first substrate, and wiring structures on the circuit elements; The storage cell region includes a second substrate disposed above the first substrate, and the storage cell region further includes: Gate electrodes are stacked and spaced apart from each other in a first region of the second substrate in a first direction perpendicular to the upper surface of the second substrate, and the gate electrodes extend in a stepped manner in a second region of the second substrate in a second direction perpendicular to the first direction. Interlayer insulating layers stacked alternately with the gate electrode, and A channel structure, disposed in the first region, to penetrate the gate electrode and extend in the first direction, each channel structure including a channel layer; and A through-wiring area is provided in the second area, the through-wiring area comprising: A sacrificial insulating layer extends from the gate electrode and stacks alternately with the interlayer insulating layer, and The contact plug electrically connects the gate electrode and the wiring structure to each other. The gate electrode includes a pad region configured to overlap with the through-wiring region at the end of the gate electrode and be exposed relative to the interlayer insulating layer and the sacrificial insulating layer. The through-wiring area includes a slit area, which is configured to penetrate the sacrificial insulating layer on one side of the respective pad area.

2. The semiconductor device of claim 1, wherein each of the slit regions is configured to penetrate a corresponding sacrificial insulating layer at the same level as the corresponding pad region and expose a corresponding interlayer insulating layer disposed below the corresponding gate electrode.

3. The semiconductor device of claim 1, wherein each of the slit regions is disposed on one side of the corresponding pad region, between the corresponding pad region and the first region of the second substrate.

4. The semiconductor device of claim 1, wherein each of the slit regions is disposed between two adjacent pad regions along the second direction. The two pad regions include a first pad region and a second pad region located below the first pad region.

5. The semiconductor device of claim 1, wherein the pad region extends upward in a third direction perpendicular to the first direction and the second direction, and The first length of the slit region in the third direction is greater than the second length of the slit region in the second direction.

6. The semiconductor device of claim 5, wherein the pad region has a third length in the third direction, and The first length is eighty percent or more of the third length.

7. The semiconductor device of claim 5, wherein the second length is in the range of 30 nm to 130 nm.

8. The semiconductor device of claim 1, wherein the memory cell region further comprises a cell region insulating layer covering the gate electrode, and The unit region insulating layer fills the slit region.

9. The semiconductor device of claim 1, wherein the slit region includes a curved portion conforming to the shape of the end of the pad region and the end of the gate electrode.

10. The semiconductor device of claim 1, wherein each of the pad regions extends upward in a third direction perpendicular to the first direction and the second direction, and In the third direction, the pad regions have different lengths of overlap with the through wiring regions.

11. The semiconductor device of claim 1, wherein the contact plugs penetrate the gate electrode in the pad region and extend through the second substrate to the peripheral circuit region.

12. The semiconductor device of claim 11, wherein each of the contact plugs penetrates one of the gate electrodes and at least one of the sacrificial insulating layers beneath the one of the gate electrodes.

13. The semiconductor device of claim 1, wherein the memory cell region further includes a partition region extending through the gate electrode and in the second direction, and The through-wire area is spaced apart from the partition area.

14. A semiconductor device, comprising: The peripheral circuit area includes a first substrate and circuit elements disposed on the first substrate; The storage cell region includes a second substrate disposed above the first substrate, and the storage cell region further includes: Gate electrodes, stacked and spaced apart from each other in a first direction on the second substrate, extend at different lengths in a second direction perpendicular to the first direction. An insulating layer covering the unit region of the gate electrode; as well as The through-wiring area includes a sacrificial insulating layer configured to extend from the gate electrode. Each of the gate electrodes includes a pad region that is curved to extend upward in a third direction perpendicular to both the first and second directions and protrudes from the end of the gate electrode in the second direction into the through-wiring region. The pad area is covered by the cell area insulating layer on two opposite side surfaces in the second direction.

15. The semiconductor device of claim 14, wherein the pad region is spaced apart by the cell region insulating layer from a corresponding sacrificial insulating layer disposed at the same height as the corresponding gate electrode.

16. The semiconductor device of claim 14, wherein the gate electrode comprises a first gate electrode and a second gate electrode, the second gate electrode extending on the first gate electrode and in the second direction for a shorter length than the first gate electrode, such that a first pad region of the first gate electrode is exposed, and The cell region insulating layer extends between the first pad region of the first gate electrode and the second pad region of the second gate electrode.

17. A semiconductor device, comprising: Gate electrodes are stacked on a substrate in a first direction perpendicular to the upper surface of the substrate and spaced apart from each other. The gate electrodes extend in a second direction perpendicular to the first direction and include a pad region that bends upward in a third direction perpendicular to both the first and second directions. Interlayer insulating layers stacked alternately with the gate electrode; A channel structure that penetrates the gate electrode, extends in the first direction, and includes a channel layer; The dividing regions penetrate the gate electrode, extend in the second direction, and are spaced apart from each other to be parallel to each other; as well as A through-wiring region, spaced apart from the partition region to overlap with the pad region between adjacent partition regions, includes contact plugs penetrating the pad region, and includes sacrificial insulating layers extending from the gate electrode and stacked alternately with the interlayer insulating layers. The through-wiring area includes a slit area, and each slit area is configured to penetrate the sacrificial insulation layer on one side of the corresponding pad area.

18. The semiconductor device of claim 17, wherein each of the slit regions is disposed between a corresponding pad region and a corresponding sacrificial insulating layer, the corresponding pad region and the corresponding sacrificial insulating layer being disposed at the same level.

19. The semiconductor device of claim 17, further comprising: A virtual channel structure is provided on the outside of the channel structure and has an internal structure corresponding to the channel structure. The slit region includes a structure corresponding to the dummy channel structure.

20. The semiconductor device of claim 17, wherein the slit region forms a columnar insulating layer extending in the first direction.

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