Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, wherein the display panel includes: a substrate, a transistor array layer, a pixel defining layer, and a touch electrode, wherein the area of ​​the opening region of the first color sub-pixel is smaller than the area of ​​the opening region of the third color sub-pixel, and the area of ​​the opening region of the second color sub-pixel is smaller than the area of ​​the opening region of the third color sub-pixel; the orthographic projection of the second capacitor in the first color sub-pixel on the substrate substrate and the orthographic projection of the touch electrode on the substrate substrate have a first auxiliary overlapping area; the orthographic projection of the second capacitor in the second color sub-pixel on the substrate substrate and the orthographic projection of the touch electrode on the substrate substrate have a second auxiliary overlapping area; the orthographic projection of the second capacitor in the third color sub-pixel on the substrate substrate and the orthographic projection of the touch electrode on the substrate substrate have a third auxiliary overlapping area; at least one of the first auxiliary overlapping area and the second auxiliary overlapping area is larger than the third auxiliary overlapping area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the China Patent Office on August 17, 2020, with application number 202010822808.3 and application name “Display Panel and Display Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] Electroluminescent diodes such as organic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED) have the advantages of self-luminescence and low energy consumption, and are one of the hot topics in the current research field of electroluminescent display devices. Summary of the invention

[0005] A display panel provided by an embodiment of the present disclosure includes:

[0006] substrate substrate;

[0007] A transistor array layer, located on the substrate;

[0008] A pixel defining layer, located on a side of the transistor array layer away from the base substrate;

[0009] A touch electrode is located on a side of the pixel defining layer away from the base substrate;

[0010] The base substrate has a display area, and the display area includes a plurality of sub-pixels; the sub-pixels include a pixel circuit and a light-emitting element; the pixel circuit includes a gate line pattern, a data line pattern, and a power signal line pattern;

[0011] The transistor array layer includes a plurality of capacitor conductive parts, and the sub-pixels include corresponding capacitor conductive parts; wherein, in the same sub-pixel, the capacitor conductive part and the data line pattern corresponding to the sub-pixel and / or the power signal line pattern corresponding to the sub-pixel have an overlapping area; the capacitor conductive part at least couples the power signal line pattern corresponding to the sub-pixel or the data line pattern corresponding to the sub-pixel;

[0012] The pixel defining layer includes a plurality of opening areas, and the sub-pixel includes the corresponding opening areas;

[0013] At least part of the touch electrodes are projected as a grid on the base substrate;

[0014] The transistor array layer further comprises a first conductive layer, and the capacitor conductive part is formed on the first conductive layer;

[0015] The pixel circuit includes a plurality of transistors, and sources and drains of at least some of the transistors are formed on the first conductive layer.

[0016] In some examples, the capacitor conductive portion is arc-shaped or has an irregular shape.

[0017] In some examples, the capacitor conductive portion includes an auxiliary conductive portion, and the auxiliary conductive portion at least partially overlaps with the power signal line pattern, the data line pattern, and the touch electrode.

[0018] In some examples, the power signal line patterns of two adjacent columns of sub-pixels are electrically connected through a power input line; or the power signal line patterns corresponding to two adjacent columns of sub-pixels of the same color are electrically connected through a power input line.

[0019] In some examples, the power input line and the power signal line pattern are located in different layers.

[0020] In some examples, the width of the power signal line pattern is greater than the width of the data line pattern.

[0021] In some examples, the data line pattern and the power signal line pattern are not disposed in the same conductive layer; or, the data line pattern and the power input line are not disposed in the same conductive layer.

[0022] In some examples, the first conductive layer includes a first sub-conductive layer and a second sub-conductive layer that are stacked, and a first sub-insulating layer is disposed between the first sub-conductive layer and the second sub-conductive layer.

[0023] In some examples, an overlapping area between the capacitor conductive portion and the power signal line pattern is greater than an overlapping area between the capacitor conductive portion and the data line pattern.

[0024] In some examples, the pixel circuit includes: a seventh transistor and a second transistor; the gate of the seventh transistor is coupled to a second reset signal line pattern, and the gate of the second transistor is coupled to a first reset signal line pattern; the first reset signal line pattern and the second reset signal line pattern transmit different signals.

[0025] In some examples, the pixel circuit includes: a data writing transistor and a first transistor; the gate line pattern coupled to the gate of the data writing transistor transmits a different timing signal from the gate line pattern coupled to the gate of the first transistor.

[0026] A display device provided by an embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagrams of the structures of some display panels in the embodiments of the present disclosure;

[0028] Figure 2 for Figure 1 The partial cross-sectional structure schematic diagram of the display panel along the AA' direction shown;

[0029] Figure 3 Schematic diagram of the structure of some pixel circuits in the embodiments of the present disclosure;

[0030] Figure 4 are some signal timing diagrams in the embodiments of the present disclosure;

[0031] Figure 5a Schematic diagram of the layout structure of some display panels in the embodiments of the present disclosure;

[0032] Figure 5b Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0033] Figure 5c for Figure 5a The cross-sectional structure diagram of the display panel shown along the AA' direction;

[0034] Figure 5d for Figure 5a The cross-sectional structure diagram of the display panel shown along the BB' direction;

[0035] Figure 5e for Figure 5a The cross-sectional structure diagram of the display panel shown along the CC' direction;

[0036] Figure 5f for Figure 5a The cross-sectional structure diagram of the display panel shown along the DD' direction;

[0037] Figure 5g is a schematic diagram of the layout structure of the first color sub-pixel in an embodiment of the present disclosure;

[0038] Figure 5h is a schematic diagram of the layout structure of the second color sub-pixel in an embodiment of the present disclosure;

[0039] Figure 5i is a schematic diagram of the layout structure of the third color sub-pixel in the embodiment of the present disclosure;

[0040] Figure 6a Schematic diagram of the structure of some semiconductor layers in the embodiments of the present disclosure;

[0041] Figure 6b Schematic diagrams of structures of some third conductive layers in the embodiments of the present disclosure;

[0042] Figure 6c Schematic diagrams of the structures of some second conductive layers in the embodiments of the present disclosure;

[0043] Figure 6d Schematic diagrams of the structures of some first conductive layers in the embodiments of the present disclosure;

[0044] Figure 6e Schematic diagrams of the structures of some first electrode layers in the embodiments of the present disclosure;

[0045] Figure 6f Schematic diagram of the structure of some light-emitting functional layers in the embodiments of the present disclosure;

[0046] Figure 6g is a schematic diagram of the structure of some second touch electrodes in the embodiments of the present disclosure;

[0047] Figure 7a Schematic diagrams of structures of some other semiconductor layers in the embodiments of the present disclosure;

[0048] Figure 7b are structural schematic diagrams of some other third conductive layers in the embodiments of the present disclosure;

[0049] Figure 7c are structural schematic diagrams of some other second conductive layers in the embodiments of the present disclosure;

[0050] Figure 7d are structural schematic diagrams of some further first conductive layers in the embodiments of the present disclosure;

[0051] Figure 7e are structural schematic diagrams of some further first electrode layers in the embodiments of the present disclosure;

[0052] Figure 7f Schematic diagrams of structures of some other light-emitting functional layers in the embodiments of the present disclosure;

[0053] Figure 7g are structural schematic diagrams of some further first sub-conductive layers in the embodiments of the present disclosure;

[0054] Figure 7h are structural schematic diagrams of some other second sub-conductive layers in the embodiments of the present disclosure;

[0055] Figure 8a is a schematic diagram of the structure of some touch electrodes in the embodiments of the present disclosure;

[0056] Figure 8b Schematic diagrams of the structures of some other touch electrodes in the embodiments of the present disclosure;

[0057] Figure 8c Schematic diagrams of the structures of some other touch electrodes in the embodiments of the present disclosure;

[0058] Figure 8d for Figure 8c The cross-sectional structure diagram of the touch electrode shown along the AA' direction;

[0059] Figure 9a Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0060] Figure 9b Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0061] Fig.9c Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0062] Fig.10a Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0063] Fig.10b Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0064] Fig.11 Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0065] Fig.12 Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0066] Fig.13a Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0067] Fig.13b Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0068] Fig.14a Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0069] Fig.14b Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure;

[0070] Fig.15 Schematic diagram of the layout structure of some other display panels in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0072] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0073] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0074] The display panel provided by the embodiment of the present disclosure is as follows: Figure 1 and Figure 2 As shown, it may include: a substrate 1000, a transistor array layer ZA located on the substrate substrate 1000, a first electrode layer 500 located on the side of the transistor array layer ZA away from the substrate substrate 1000, a pixel defining layer 950 located on the side of the first electrode layer 500 away from the substrate substrate 1000, a light-emitting functional layer 600 located on the side of the pixel defining layer 950 away from the substrate substrate 1000, a second electrode 700 located on the side of the light-emitting functional layer 600 away from the substrate substrate 1000, an encapsulation layer FB located on the side of the second electrode 700 away from the substrate substrate 1000, and a touch electrode 800 located on the side of the encapsulation layer FB away from the substrate substrate 1000.

[0075] In some embodiments of the present disclosure, Figure 1As shown, the base substrate 1000 has a display area AA and a non-display area surrounding the display area. The display area has a plurality of sub-pixels spx. The non-display area has a barrier wall BK surrounding the display area AA. In addition, the non-display area may also include circuit structures such as a driving circuit, for example, a gate driver on array (GOA) and other structures, which are not described in detail here.

[0076] Exemplarily, the sub-pixel spx may include: a pixel circuit and a light-emitting element. The pixel circuit has a transistor and a capacitor for driving the light-emitting element to emit light. It should be noted that one or more embodiments described herein correspond to a display panel having a 7T2C (i.e., 7 thin-film transistors and 2 capacitors) pixel circuit. In another embodiment, the display panel may include different pixel circuits, for example, greater than or less than 7 thin-film transistors, and one or more capacitors.

[0077] like Figure 3 As shown, in the display panel provided by the embodiment of the present disclosure, the sub-pixels may include: a gate line graphic GATE (abbreviated as GA), a first reset signal line graphic RST1, a first initialization signal line graphic VINT1, a data line graphic DATA (abbreviated as DA), a light emitting control signal line graphic EM, a power signal line graphic VDD, a second reset signal line graphic RST2 and a second initialization signal line graphic VINT2.

[0078] Exemplarily, the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may transmit different signals.

[0079] Exemplarily, the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may be located in different layers. For example, the first reset signal line pattern RST1 is in the same layer as the gate line pattern GA, and the second reset signal line pattern RST2 is in the same layer as the data line pattern DA or the power signal line pattern VDD.

[0080] Exemplarily, the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may transmit the same signal.

[0081] Exemplarily, the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may also transmit different signals, for example: VINT1 is V1, and VINT2 is V1±5V.

[0082] Exemplarily, the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may be located in different layers. For example, the first initialization signal line pattern VINT1 is in the same layer as the gate line pattern GA, and the second initialization signal line pattern VINT2 is in the same layer as the data line pattern DA or the first reset signal line pattern RST1.

[0083] like Figure 3 As shown, the pixel circuit in the sub-pixel may include: a first transistor T1, a second transistor T2, a third transistor T3, a data writing transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor Cst and a second capacitor C1.

[0084] Taking a pixel circuit as an example, each transistor included in the pixel circuit is a P-type transistor. The first transistor T1 can be a dual-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern GA, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3. Of course, the first transistor T1 can be a single-gate structure or a multi-gate structure, which is not limited here.

[0085] The second transistor T2 may be a dual-gate structure, the gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1, the source S2 of the second transistor T2 is coupled to the first initialization signal line pattern VINT1, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3. Of course, the second transistor T2 may be a single-gate structure or a multi-gate structure, which is not limited here.

[0086] The gate 204g of the data writing transistor T4 is coupled to the gate line pattern GA, the source S4 of the data writing transistor T4 is coupled to the data line pattern DA, and the drain D4 of the data writing transistor T4 is coupled to the source S3 of the third transistor T3. Exemplarily, the gate line pattern GA coupled to the gate 204g of the data writing transistor T4 and the gate line pattern GA coupled to the gate 201g of the first transistor T1 can transmit different timing signals, which are not limited here.

[0087] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0088] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element L. Exemplarily, the light emitting control signal line pattern EM coupled to the gate 205g of the fifth transistor T5 and the light emitting control signal line pattern EM coupled to the gate 206g of the sixth transistor T6 can transmit different timing signals, which are not limited herein.

[0089] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light emitting element L, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line pattern VINT2.

[0090] The first plate Cst1 of the first capacitor Cst is coupled to the gate 203g of the third transistor T3, and the second plate Cst2 of the first capacitor Cst is coupled to the power signal line pattern VDD.

[0091] The first end of the second capacitor C1 (i.e., the first plate C11) is coupled to the first end of the data writing transistor (e.g., the data line pattern DA), and the second end of the second capacitor C1 (e.g., the second plate C12) is coupled to the power signal line pattern VDD. For example, the first plate C11 of the second capacitor C1 is coupled to the data line pattern DA and / or the data writing transistor T4, and the second plate C12 of the second capacitor C1 is coupled to the power signal line pattern VDD.

[0092] Optionally, the second plate C12 of the second capacitor C1 may be electrically connected to the power signal line pattern VDD, and the first plate C11 of the second capacitor C1 extends below or above the data line pattern DA, so that the first plate C12 and the data line pattern DA overlap in orthographic projection on the base substrate.

[0093] Optionally, the first end of the data writing transistor T4 may also be the source of the data writing transistor T4 (or the source region, for example: Figure 3 S4), or the drain (or drain region, for example: Figure 3 D4), or the gate (for example: Figure 3 204g). It should be noted that Figure 3 The S and D are merely reference numerals for distinguishing the two.

[0094] Optionally, the first end of the data writing transistor T4 may also be a connection structure between the source of the data writing transistor T4 and the data line pattern DA.

[0095] like Figure 4As shown, exemplarily, when the pixel circuit of the above structure is working, one working cycle includes a first reset period P1, a writing compensation period P2, a second reset period P3 and a light emitting period P4.

[0096] In the first reset period P1, the first reset signal input by the first reset signal line graph RST1 is at an effective level, the second transistor T2 is turned on, and the initialization signal transmitted by the first initialization signal line graph VINT1 is input to the gate 203g of the third transistor T3, and the gate 203g of the third transistor T3 is reset. For example, the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared.

[0097] During the write compensation period P2, the first reset signal is at a non-valid level, the second transistor T2 is turned off, and the gate scan signal input by the gate line pattern GA is at a valid level, controlling the first transistor T1 and the data write transistor T4 to be turned on, and the data line pattern DA writes the data signal, which is transmitted to the source S3 of the third transistor T3 through the data write transistor T4. At the same time, the first transistor T1 and the data write transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage compensation of the third transistor T3 is realized through the cooperation of the first transistor T1, the third transistor T3 and the data write transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to finally reach Vdata+Vth, wherein Vdata represents the data signal voltage value, and Vth represents the threshold voltage of the third transistor T3.

[0098] In the second reset period P3, the gate scan signal is at a non-valid level, the first transistor T1 and the data writing transistor T4 are both turned off, the second reset signal input by the second reset signal line RST2 is at a valid level, the seventh transistor T7 is controlled to be turned on, and the initialization signal transmitted by the second initialization signal line graph VINT2 is input to the anode of the light-emitting element L, controlling the light-emitting element L not to emit light.

[0099] During the light-emitting period P4, the light-emitting control signal written in the light-emitting control signal line graphic EM is at an effective level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line graphic VDD is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, wherein VDD is the voltage value corresponding to the power signal, and the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element L, driving the corresponding light-emitting element L to emit light.

[0100] It should be noted that when the transistor is a P-type transistor, the effective level can be a low level, and the ineffective level can be a high level. When the transistor is an N-type transistor, the effective level can be a high level, and the ineffective level can be a low level. The transistors of the pixel circuit can be both P-type transistors or N-type transistors, or can include both P-type transistors and N-type transistors. For example, transistor T3 is a P-type transistor, and transistor T1 is an N-type transistor. It can be understood that Figure 4 This is only an exemplary introduction to the working timing of the pixel circuit. The RST1, RST2, Ga, EM, Da and other signals can be adaptively adjusted according to the transistor type of the pixel circuit and the actual situation.

[0101] like Figures 5a to 5i As shown, exemplarily, when manufacturing the above transistor array layer ZA, the layout of each film layer is as follows: a semiconductor layer 400, a gate insulating layer 910, a third conductive layer 300, an interlayer dielectric layer 920, a second conductive layer 200, a first interlayer insulating layer 930, a first conductive layer 100, and a second interlayer insulating layer 940 are sequentially stacked in a direction away from the base substrate 1000. It can be understood that other metal layers or insulating layers can also be included between the base substrate 1000 and the semiconductor layer 400. For example, at least one buffer layer or organic insulating layer is also included between the base substrate 1000 and the semiconductor layer 400, for example, the buffer layer can be silicon oxide or silicon nitride, etc., and the organic insulating layer can be polyimide, etc.

[0102] like Figures 5a to 5i , Figure 6a , Figure 7aAs shown, the semiconductor layer 400 is used to form the channel region (such as: 101pg~107pg), source formation region (such as: 101ps~107ps), drain formation region (such as: 101pd~107pd) and connection formation region (such as: 101px, 102px) of each transistor in the pixel circuit; of course, other structures can also be formed as needed, for example: forming a lightly doped drain (LDD), the LDD region doped with low concentration impurities is formed between the drain formation region (such as: 101pd~107pd) of at least one transistor and the channel region (such as: 101pg~107pg) of the transistor, and between the source formation region (such as: 101ps~107ps) of the transistor and the channel region (such as: 101pg~107pg) of the transistor. The semiconductor layer 400 corresponding to the source formation region and the drain formation region has better conductivity than the semiconductor layer 400 corresponding to the channel region due to doping. Optionally, the semiconductor layer 400 may be made of amorphous silicon, polycrystalline silicon, or a combination thereof; for example, the semiconductor layer 400 is low temperature polycrystalline silicon (LTPS), the semiconductor layer 400 includes an oxide semiconductor material (for example, indium gallium zinc oxide (IGZO)), and the semiconductor layer 400 includes a low temperature polycrystalline oxide material (LTPO); for example Figure 3 As shown: the semiconductor layer 400 of T3 is low temperature polysilicon LTPS, and the semiconductor layer 400 of T1 includes an oxide semiconductor material LTPO.

[0103] It should be noted that the above-mentioned source formation region, drain formation region and connection formation region can be a conductive region of the semiconductor layer doped with n-type impurities or p-type impurities, so that the source formation region, drain formation region and connection formation region can be used as a connection structure of the semiconductor layer for electrical connection. Exemplarily, the semiconductor layer corresponding to the source formation region and the drain formation region can be directly used as the source or drain of the corresponding transistor. Alternatively, a source in contact with the source formation region can be made of a conductive material (such as a metal material), and a drain in contact with the drain formation region can be made of a conductive material (such as a metal material).

[0104] like Figures 5a to 5i , Figure 6b , Figure 7bAs shown, the third conductive layer 300 is used to form the gate of the transistor in the pixel circuit (such as: 201g ~ 207g), and at least one of the structures of the gate line pattern GA, the light-emitting control signal line pattern EM, the first reset signal line pattern RST1 and the second reset signal line pattern RST2 included in the display panel. Optionally, the gate 203g of the third transistor T3 in the pixel circuit is reused as the first plate Cst1 of the first capacitor Cst in the pixel circuit. Of course, the gate 203g of the third transistor T3 in the pixel circuit can also be reused as the second plate Cst2 of the first capacitor Cst in the pixel circuit.

[0105] like Figures 5a to 5i , Figure 6c , Figure 7c As shown, the second conductive layer 200 has a plurality of auxiliary conductive parts WD, a plurality of storage conductive parts WCst2 spaced apart from the auxiliary conductive parts WD, and a first initialization signal line pattern VINT1 and a second initialization signal line pattern VINT2 included in the display panel. Among them, the sub-pixel includes the auxiliary conductive part; in the same sub-pixel, the orthographic projection of the first end of the auxiliary conductive part WD on the substrate 1000 and the orthographic projection of the power signal line pattern on the substrate 1000 have an overlapping area, and the orthographic projection of the second end of the auxiliary conductive part WD on the substrate 1000 and the orthographic projection of the data line pattern on the substrate 1000 have an overlapping area. Optionally, the auxiliary conductive part WD at least partially overlaps with the power signal line pattern, the data line pattern, and the touch electrode.

[0106] Furthermore, the sub-pixel includes a storage conductive portion Cst2, which is used to form a second plate Cst2 of the first capacitor Cst, that is, the storage conductive portion Cst2 serves as the second plate Cst2 of the first capacitor Cst. Of course, the storage conductive portion Cst2 can also serve as the first plate Cst1 of the first capacitor Cst. The shape structure of the auxiliary conductive portion WD is not limited, and can be a regular rectangle or an irregular shape with at least one arc-shaped side. Exemplarily, one end of the auxiliary conductive portion WD extends to the other end of the auxiliary conductive portion along the row direction F4.

[0107] like Figure 3 , Figures 5a to 5i , Figure 6d , Figure 7d As shown, the first conductive layer 100 is used to form the source (such as: S1 ~ S7) and drain (such as: D1 ~ D7) of each transistor in the pixel circuit, and the data line graphics (such as DA1, DA2, DA3, DA4 and DA5) and the power signal line graphics VDD included in the display panel. Optionally, the width of the power signal line graphics VDD is greater than the width of the data line graphics (such as DA1, DA2, DA3, DA4 and DA5). It should be noted that Figure 6d and Figure 7dThe connecting lines 401, 402, 403 and 404 in the embodiment may be formed by the first conductive layer, and the specific layout is as follows: Figures 5a to 5i , Figure 6d , Figure 7d shown.

[0108] Of course, in practical applications, the data line pattern DA and the power signal line pattern VDD may not be arranged on the same conductive layer. Figure 7g and Figure 7h As shown, the first conductive layer 100 may include a first sub-conductive layer 111 and a second sub-conductive layer 112 which are stacked, and a first sub-insulating layer (not shown) is disposed between the first sub-conductive layer 111 and the second sub-conductive layer 112. Exemplarily, at least one of the connecting wires 401, 402, 403 and 404 is disposed in the same layer as the data line pattern (such as DA1, DA2) or the power signal line pattern VDD. For example, the data line pattern (such as DA1, DA2), the connecting wires 401, 402 and 403 may be disposed in the first sub-conductive layer 111, and the power signal line pattern VDD may be disposed in the second sub-conductive layer 112. That is, the data line pattern (such as DA1, DA2) and the power signal line pattern VDD are not disposed in the same conductive layer.

[0109] Exemplarily, the first sub-conductive layer 111 where the data line patterns (such as DA1 and DA2) are located is closer to the base substrate 1000 than the second sub-conductive layer where the power signal line pattern VDD is located.

[0110] Exemplarily, the connection line 404, as a connection structure between adjacent initialization signal line patterns, may be located in a sub-pixel or in a non-display area. For example, the connection line 404 connects the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2.

[0111] For more details, please refer to Figure 3 , Figures 5a to 5i ~ Figure 7d , the gate 201g of the first transistor T1 overlaps with the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.

[0112] The gate 202g of the second transistor T2 overlaps the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.

[0113] The gate 203g of the third transistor T3 overlaps the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.

[0114] The gate 204g of the data writing transistor T4 overlaps the fourth channel region 104pg, the source S4 of the data writing transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the data writing transistor T4 is located in the fourth drain formation region 104pd.

[0115] The gate 205g of the fifth transistor T5 overlaps with the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.

[0116] The gate 206g of the sixth transistor T6 overlaps the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.

[0117] The gate 207g of the seventh transistor T7 overlaps with the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.

[0118] The gate 203g of the third transistor T3 is multiplexed as a first plate Cst1 of the first capacitor Cst, and a second plate Cst2 of the first capacitor Cst is coupled to the power signal line pattern VDD.

[0119] Optionally, the capacitor conductive portion includes an auxiliary conductive portion WD, and the auxiliary conductive portion WD may include the second electrode C12 of the second capacitor C1, that is, the auxiliary conductive portion may partially or completely serve as the second electrode C12 of the second capacitor C1. For example: in the same sub-pixel, the auxiliary conductive portion WD serves as the second electrode C12 of the second capacitor C1, and the data line pattern DA serves as the first electrode C11 of the second capacitor C1; or, the data line pattern DA having an overlapping area with the second electrode C12 of the second capacitor C1 serves as the first electrode C11 of the second capacitor C1.

[0120] like Figures 5a to 5i , Figure 6e , Figure 7eAs shown, the first electrode layer 500 is used to form the first electrode (such as: 510, 520, 530, 540) of the light-emitting element L. Exemplarily, the first electrode is the anode of the light-emitting element L (such as: 510, 520, 530, 540). It should be noted that the pixel defining layer 950 includes a plurality of opening areas (such as: KK1, KK2, KK3, KK4). Among them, one first electrode corresponds to one opening area, and the orthographic projection of the opening area on the base substrate 1000 is located within the orthographic projection of the corresponding first electrode on the base substrate 1000. For example, the opening area KK1 corresponds to the first electrode 510, the opening area KK2 corresponds to the first electrode 520, the opening area KK3 corresponds to the first electrode 530, and the opening area KK4 corresponds to the first electrode 540. Exemplarily, the first electrode can be directly electrically connected to the semiconductor layer; or, the first electrode can also be electrically connected to the semiconductor layer through other conductive layers, for example: the first conductive layer 100.

[0121] like Figures 5a to 5i , Figure 6f , Figure 7f As shown, the light-emitting functional layer 600 is used to form the light-emitting layer of the light-emitting element L. For example, a first color light-emitting layer 610, a second color light-emitting layer 620, a third color light-emitting layer 630 and a fourth color light-emitting layer 640. Further, the light-emitting functional layer 600 may also include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Among them, the boundaries of the first color light-emitting layer 610, the second color light-emitting layer 620, the third color light-emitting layer 630 and the fourth color light-emitting layer 640 may overlap or not overlap. For example, at least two of the first color light-emitting layer 610, the second color light-emitting layer 620, the third color light-emitting layer 630 and the fourth color light-emitting layer 640 have overlapping areas, for example: the boundary of the first color light-emitting layer 610 extends into the second color light-emitting layer 620.

[0122] like Figure 2As shown, exemplarily, the encapsulation layer FB may include at least one or more layers of FB1, FB2, and FB3, wherein at least one layer of FB1, FB2, and FB3 is inorganic, organic, or an organic-inorganic composite material, and the inorganic material may be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), etc., and the organic material may be polyimide (PI), etc. For example, the encapsulation layer FB may include a first inorganic encapsulation layer FB1, an organic encapsulation layer FB2, and a second inorganic encapsulation layer FB3 that are stacked; wherein the organic encapsulation layer FB2 is located inside the retaining wall 110 and covers the display area AA; the first inorganic encapsulation layer FB1 and the second inorganic encapsulation layer FB3 cover the display area AA, the retaining wall 110, and the peripheral area of ​​the retaining wall 110; wherein the orthographic projection of the first inorganic encapsulation layer FB1 on the base substrate 1000 overlaps with the orthographic projection of the second inorganic encapsulation layer FB3 on the base substrate 1000. In this way, by extending the first inorganic encapsulation layer FB1 and the second inorganic encapsulation layer FB3 to the peripheral area of ​​the blocking wall 110 , the organic encapsulation layer FB and the display area can be better blocked from water and oxygen.

[0123] like Figure 2 , Figure 6g , Figure 8a , Figure 8b As shown, the touch electrode 800 may include a plurality of first touch electrodes 810 and a plurality of second touch electrodes 820 arranged crosswise, so that the orthographic projection of the touch electrode 800 on the base substrate 1000 is in a grid shape. Exemplarily, the orthographic projection of the touch electrode 800 on the base substrate 1000 does not overlap with the orthographic projection of the opening area (e.g., KK1, KK2, KK3, KK4) on the base substrate 1000. It is understandable that in the display panel, the touch electrode 800 may be at least one of the plurality of first touch electrodes 810 and the second touch electrode 820, for example: in a local display area of ​​the display panel. For example: in the sub-pixel area corresponding to at least part of the first color, the second color, the third color, and the fourth color, the touch electrode only includes a plurality of first touch electrodes 810 or a plurality of second touch electrodes 820.

[0124] Exemplarily, a plurality of first touch electrodes 810 are arranged on the same conductive film layer, and a plurality of second touch electrodes 820 are arranged on the same conductive film layer. In addition, the layer where the first touch electrode 810 is located is located on the side of the packaging layer FB away from the base substrate 1000, and the layer where the second touch electrode 820 is located is located on the side of the layer where the first touch electrode 810 is located away from the base substrate 1000. In addition, an electrode insulating layer 830 is arranged between the layer where the first touch electrode 810 is located and the layer where the second touch electrode 820 is located. Exemplarily, the electrode insulating layer 830 can be located in the display area and cover the display area. Alternatively, the electrode insulating layer 830 can not only cover the display area, but also cover the non-display area. Alternatively, the edge of the electrode insulating layer 830 is located between the two retaining walls BK. Of course, in actual applications, it can be designed according to actual applications, and is not limited here.

[0125] Exemplarily, one or more insulating layers (not shown) may be provided between the first touch electrode 810 and the encapsulation layer FB. At least one insulating layer may be inorganic, organic, or an organic-inorganic composite material. The inorganic material may be at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), etc. The organic material may be polyimide (PI), etc. For example: at least one touch electrode substrate is provided between the first touch electrode 810 and the encapsulation layer FB3, and the material is silicon nitride (SiNx), silicon oxide (SiOX), or polyimide (PI).

[0126] For example, the touch electrode substrate may be located in the display area and cover the display area. Alternatively, the electrode insulating layer 830 may not only cover the display area but also cover the non-display area. Alternatively, the edge of the touch electrode substrate is located between the two retaining walls BK. Of course, in practical applications, the design may be made according to the practical application and is not limited here.

[0127] In some examples, such as Figure 8a As shown in FIG. 1 , the orthographic projection of the first touch electrode 810 on the base substrate 1000 and the orthographic projection of the second touch electrode 820 on the base substrate 1000 may be in the shape of strips. Since the first touch electrode 810 and the second touch electrode 820 are arranged crosswise, the orthographic projection of the first touch electrode 810 on the base substrate 1000 and the orthographic projection of the second touch electrode 820 on the base substrate 1000 may form a grid shape. Alternatively, as Figure 8b As shown, the orthographic projection of the first touch electrode 810 on the base substrate 1000 and the orthographic projection of at least a part of the structure of the second touch electrode 820 on the base substrate 1000 may also be in a grid shape.

[0128] Exemplarily, the first touch electrodes 810 and the second touch electrodes 820 are arranged crosswise, and the orthographic projection of the first touch electrodes 810 on the base substrate 1000 and the orthographic projection of the second touch electrodes 820 on the base substrate 1000 form a grid. Alternatively, at least part of the first touch electrodes 810 and the second touch electrodes 820 are arranged overlappingly, and the orthographic projection of the first touch electrodes 810 on the base substrate 1000 and the orthographic projection of the second touch electrodes 820 on the base substrate 1000 overlap.

[0129] Of course, the present disclosure includes but is not limited to this. In practical applications, the design can be based on actual application requirements and is not limited here. Figure 8b The second touch electrode 820 is taken as an example for description.

[0130] In some examples, such as Figure 8c and Figure 8d As shown, the first touch electrode 810 can be electrically connected by a first bridge portion 811. The first end of the first bridge portion 811 can be electrically connected to one first touch electrode 810 through a via hole 831 penetrating the electrode insulating layer 830, and the second end of the first bridge portion 811 can be electrically connected to another first touch electrode 810 through a via hole 832 penetrating the electrode insulating layer 830. Similarly, Figure 8c and Figure 8d As shown, the second touch electrodes 820 may be electrically connected using the second bridge portion 821. The first end of the second bridge portion 821 may be electrically connected to one second touch electrode 820 through a via hole penetrating the electrode insulating layer 830, and the second end of the second bridge portion 821 may be electrically connected to another second touch electrode 820 through a via hole penetrating the electrode insulating layer 830.

[0131] It should be noted that the light-emitting element can be set as an electroluminescent diode, such as at least one of an organic light-emitting diode (OLED) and a quantum dot light-emitting diode (QLED). Among them, the light-emitting element may include a first electrode 500 (for example, an anode of the light-emitting element), a light-emitting functional layer 600, and a second electrode 700 (for example, a cathode of the light-emitting element) arranged in a stacked manner. Of course, the present disclosure includes but is not limited to this. In practical applications, it can be designed according to the actual application requirements, which is not limited here.

[0132] In practical applications, the materials of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 may be the same or different. At least one of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 includes a metal material or an alloy material or other conductive material, for example, at least one of metal aluminum (Al), titanium (Ti), molybdenum (Mo), molybdenum-niobium alloy, aluminum-neodymium alloy, graphene, etc.

[0133] Optionally, at least one of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 may form a single-layer structure, or a stacked-layer structure formed by using molybdenum / aluminum / molybdenum or titanium / aluminum / titanium sublayers.

[0134] Optionally, at least one of the third conductive layer 300 , the second conductive layer 200 , the first conductive layer 100 , the second touch electrode 820 , and the first touch electrode 810 has a thickness ranging from 100 nm to 500 nm.

[0135] Exemplarily: the third conductive layer 300, the second conductive layer 200, and the first conductive layer 100 can be selected from at least one of metal aluminum (AL), titanium (Ti), molybdenum (Mo), etc.; or, at least one of the second touch electrode 820 and the first touch electrode 810 is a stacked junction obtained by forming sublayers of titanium / aluminum / titanium; or, at least one of the second touch electrode 820 and the first touch electrode 810 includes graphene. Due to the high reflectivity of the surface of the conductive layer, for example: the surface reflectivity of the molybdenum metal material is high, it is easy to cause the second capacitor C1 to reflect the external ambient light or the light emitted by the light-emitting functional layer 600 into the adjacent opening area, thereby causing the problem of poor light crosstalk or light mixing effect.

[0136] In view of this, the embodiments of the present disclosure provide some display panels, such as Figures 5a to 5i to Figure 7f As shown, the display panel includes a plurality of repeating units; the repeating unit may include a plurality of sub-pixels, for example, the plurality of sub-pixels may include a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. In other words, the repeating unit may include a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. In this way, the display panel may use the first color sub-pixel, the second color sub-pixel and the third color sub-pixel for light mixing to achieve color display. In some examples, the first color, the second color and the third color may be selected from red, green and blue. For example, the second color is red, the first color is green, and the third color is blue. Of course, the embodiments of the present disclosure include but are not limited to this. The above-mentioned first color, second color and third color may also be other colors.

[0137] Optionally, the repeating unit may further include a fourth color sub-pixel. In this way, the display panel may use the first color sub-pixel, the second color sub-pixel, the third color sub-pixel, and the fourth color sub-pixel to mix light to achieve color display. In some examples, the fourth color sub-pixel may be a green sub-pixel, or a white sub-pixel, or a yellow sub-pixel, or other colors, which are not limited here.

[0138] The following description is made by taking an example where the repeating unit includes a first color sub-pixel, a second color sub-pixel, a third color sub-pixel and a fourth color sub-pixel, and the first color and the fourth color are green, the second color is red, and the third color is blue.

[0139] In some examples, such as Figures 5a to 5i to Figure 7f As shown, the first color sub-pixel has the pixel circuit of any of the above embodiments, the first electrode 510, the first color light-emitting layer 610 and the opening area KK1. The orthographic projection of the first color light-emitting layer 610 on the base substrate 1000 covers the orthographic projection of the opening area KK1 in the first color sub-pixel on the base substrate 1000, and the light-emitting area of ​​the first color sub-pixel includes the opening area KK1. Exemplarily, the opening area KK1 can be used as the light-emitting area of ​​the first color sub-pixel.

[0140] Furthermore, the second color sub-pixel has the pixel circuit of any of the above embodiments, the first electrode 520, the second color light-emitting layer 620, and the opening area KK2. The orthographic projection of the second color light-emitting layer 620 on the base substrate 1000 covers the orthographic projection of the opening area KK2 in the second color sub-pixel on the base substrate 1000, and the light-emitting area of ​​the second color sub-pixel includes the opening area KK2. Exemplarily, the opening area KK2 can serve as the light-emitting area of ​​the second color sub-pixel.

[0141] Furthermore, the third color sub-pixel has the pixel circuit of any of the above embodiments, the first electrode 530, the third color light-emitting layer 630, and the opening area KK3. The orthographic projection of the third color light-emitting layer 630 on the base substrate 1000 covers the orthographic projection of the opening area KK3 in the third color sub-pixel on the base substrate 1000, and the light-emitting area of ​​the third color sub-pixel includes the opening area KK3. Exemplarily, the opening area KK3 can serve as the light-emitting area of ​​the third color sub-pixel.

[0142] Furthermore, the fourth color sub-pixel has the pixel circuit of any of the above embodiments, the first electrode 540, the fourth color light-emitting layer 640, and the opening area KK4. The orthographic projection of the fourth color light-emitting layer 640 on the base substrate 1000 covers the orthographic projection of the opening area KK4 in the fourth color sub-pixel on the base substrate 1000, and the light-emitting area of ​​the fourth color sub-pixel includes the opening area KK4. Exemplarily, the opening area KK4 can serve as the light-emitting area of ​​the fourth color sub-pixel.

[0143] The area of ​​the opening region KK1 in the first color sub-pixel is smaller than the area of ​​the opening region KK3 in the third color sub-pixel. The area of ​​the opening region KK2 in the second color sub-pixel is smaller than the area of ​​the opening region KK3 in the third color sub-pixel. The area of ​​the opening region KK4 in the fourth color sub-pixel is smaller than the area of ​​the opening region KK3 in the third color sub-pixel.

[0144] For example, when the luminous efficiency of the green light-emitting element and the red light-emitting element is higher than that of the blue light-emitting element, the adjacent sub-pixels are greatly affected, so the area of ​​the opening region of the green sub-pixel can be made smaller than that of the blue sub-pixel, and the area of ​​the opening region of the red sub-pixel can be made smaller than that of the blue sub-pixel, thereby improving the emission of blue light. In addition, this will also cause a larger portion of the second capacitor C1 of the green sub-pixel and the red sub-pixel that is not blocked by the opening region, resulting in a larger portion of the second capacitor C1 being exposed, which in turn leads to the problem of luminous interference and poor light mixing effect.

[0145] In the specific implementation, in the embodiment of the present disclosure, if Figures 3 to 6g As shown, the transistor array layer includes a plurality of capacitor conductive parts R, and at least a portion of the sub-pixels include the capacitor conductive part R; wherein, in the same sub-pixel, the capacitor conductive part R has an overlapping area with the power signal line graph VDD and / or the data line graph. For example, in the same sub-pixel, the capacitor conductive part R has an overlapping area with the power signal line graph VDD and the data line graph. Alternatively, in the same sub-pixel, the capacitor conductive part R has an overlapping area with the power signal line graph VDD. Alternatively, in the same sub-pixel, the capacitor conductive part R has an overlapping area with the data line graph. Optionally, the overlapping area between the capacitor conductive part R and the power signal line graph VDD is greater than the overlapping area between the capacitor conductive part R and the data line graph DA.

[0146] In the specific implementation, in the embodiment of the present disclosure, if Figures 3 to 6gAs shown, the orthographic projection of the capacitor conductive portion R in the first color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000 have a first auxiliary overlapping area S1. The orthographic projection of the capacitor conductive portion R in the second color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000 have a second auxiliary overlapping area S2. The orthographic projection of the capacitor conductive portion R in the third color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000 have a third auxiliary overlapping area S3. The orthographic projection of the capacitor conductive portion R in the fourth color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000 have a fourth auxiliary overlapping area S4. Among them, at least one of the first auxiliary overlap area S1, the second auxiliary overlap area S2 and the fourth auxiliary overlap area S4 is larger than the third auxiliary overlap area S3. For example: the first auxiliary overlap area S1 is larger than the second auxiliary overlap area S2, and the second auxiliary overlap area S2 is larger than the third auxiliary overlap area S3; or, the first auxiliary overlap area S1 is larger than the second auxiliary overlap area S2, and the second auxiliary overlap area S2 is equal to the third auxiliary overlap area S3; or the first auxiliary overlap area S1 is substantially equal to the second auxiliary overlap area S2, and the second auxiliary overlap area S2 is larger than the third auxiliary overlap area S3. In this way, the second capacitor C1 can be shielded by the touch electrode 800, thereby improving the problem of light interference and poor light mixing effect caused by the second capacitor C1.

[0147] For example, Figures 3 to 6g As shown, the transistor array layer ZA includes a plurality of data line patterns (e.g., DA1, DA2) and a plurality of power signal line patterns (e.g., VDD), and the transistor array layer ZA includes a plurality of capacitor conductive parts R, and the sub-pixel includes the capacitor conductive part R, and the capacitor conductive part R has an overlapping area with the power signal line pattern VDD and / or the data line pattern DA; for example, the plurality of capacitor conductive parts R are formed in the second conductive layer 200. Of course, they can also be formed in other conductive layers, such as the first conductive layer.

[0148] Optionally, at least a portion of the capacitor conductive portion R forms a capacitor with the power signal line pattern VDD or the data line pattern DA, that is, there is at least one insulating layer between the capacitor conductive portion R and the power signal line pattern VDD or the data line pattern DA. For example, the capacitor conductive portion R forms a capacitor plate of the second capacitor C1. Specifically, part or all of the capacitor conductive portion forms the first plate C11 or the second plate C12 of the second capacitor.

[0149] Optionally, the capacitor conductive portion R may be an arc-shaped or irregular shape.

[0150] Optionally, the capacitor conductive portion R includes an auxiliary conductive portion WD, which is formed in the second conductive layer 200, the auxiliary conductive portion WD is located below the data line pattern (for example, DA1, DA2), and the first end of the auxiliary conductive portion WD is connected to the power signal line pattern VDD, for example: the first end of the auxiliary conductive portion WD is connected to the power signal line pattern VDD through a via of the first interlayer insulating layer 930; the second end of the auxiliary conductive portion WD extends below the data line pattern, and the auxiliary conductive portion WD has an overlapping area with the power signal line pattern and / or the data line pattern, that is, at this time, the second plate C12 of the second capacitor C1 is formed in the auxiliary conductive portion WD, and the first plate of the second capacitor C1 is formed in the corresponding sub-pixel data line pattern DA (for example, DA1, DA2); or the first plate of the second capacitor C1 is formed in the corresponding sub-pixel data line pattern DA (for example, DA1, DA2) that has an overlapping area with the auxiliary conductive portion WD.

[0151] Optionally, the capacitor conductive part R may also include a second auxiliary conductive part WN2 (not shown), the second auxiliary conductive part WN2 is formed in the second conductive layer 200, the second auxiliary conductive part WN2 is located below the data line pattern of the corresponding sub-pixel (for example, DA1, DA2), and the first end of the second auxiliary conductive part WD2 is connected to the data line pattern corresponding to each sub-pixel (for example, data line pattern DA1), for example, the first end of the second auxiliary conductive part WD2 is connected to the data line pattern corresponding to each sub-pixel (for example, data line pattern DA1) through a via hole in the first interlayer insulating layer 930; the second end of the second auxiliary conductive part WN2 extends below the power signal line pattern, and the second auxiliary conductive part WN2 has an overlapping area with the power signal line pattern and / or the data line pattern, that is, at this time, the first plate of the second capacitor C1 is formed in the second auxiliary conductive part WD2, and the second plate of the second capacitor C1 is the power signal line pattern VDD; or the second plate of the second capacitor C1 is formed in the corresponding sub-pixel power signal line pattern VDD that has an overlapping area with the second auxiliary conductive part WD2.

[0152] For ease of understanding, at least some of the following embodiments are described using the capacitor conductive part R as the auxiliary conductive part WD as an example. For example, since the area of ​​the opening area KK1 in the first color sub-pixel is smaller than the area of ​​the opening area KK3 in the third color sub-pixel, the capacitor conductive part R in the first color sub-pixel is less blocked by the opening area, while the capacitor conductive part R in the third color sub-pixel is more blocked by the opening area, which results in a stronger effect of the capacitor conductive part R in the first color sub-pixel emitting light. By making the first auxiliary overlapping area S1 larger than the third auxiliary overlapping area S3, the disclosed embodiment can make the capacitor conductive part R in the first color sub-pixel blocked by the touch electrode 800 more, thereby reducing the problems of luminous interference and poor light mixing effect caused by the capacitor conductive part R in the first color sub-pixel.

[0153] For example, since the area of ​​the opening area KK2 in the second color sub-pixel is smaller than the area of ​​the opening area KK3 in the third color sub-pixel, the portion of the capacitor conductive part R in the second color sub-pixel blocked by the opening area is smaller, while the portion of the capacitor conductive part R in the third color sub-pixel blocked by the opening area is larger, which results in a stronger effect of the capacitor conductive part R in the second color sub-pixel emitting light. In the embodiment of the present disclosure, by making the second auxiliary overlapping area S2 larger than the third auxiliary overlapping area S3, the portion of the capacitor conductive part R in the second color sub-pixel blocked by the touch electrode 800 is larger, thereby reducing the problem of light emission interference and poor light mixing effect caused by the capacitor conductive part R in the second color sub-pixel.

[0154] For example, since the area of ​​the opening area KK4 in the fourth color sub-pixel is smaller than the area of ​​the opening area KK3 in the third color sub-pixel, the portion of the capacitor conductive part R in the fourth color sub-pixel blocked by the opening area is smaller, while the portion of the capacitor conductive part R in the third color sub-pixel blocked by the opening area is larger, which results in a stronger effect of the capacitor conductive part R in the fourth color sub-pixel emitting light. In the embodiment of the present disclosure, by making the fourth auxiliary overlapping area S4 larger than the third auxiliary overlapping area S3, the portion of the capacitor conductive part R in the fourth color sub-pixel blocked by the touch electrode 800 is larger, thereby reducing the problem of light emission interference and poor light mixing effect caused by the capacitor conductive part R in the fourth color sub-pixel.

[0155] In the specific implementation, in the embodiment of the present disclosure, if Figure 6e As shown, the area of ​​the opening area KK1 in the first color sub-pixel can be made smaller than the area of ​​the opening area KK2 in the second color sub-pixel. For example, the area of ​​the opening area of ​​the green sub-pixel can be made smaller than the area of ​​the opening area of ​​the red sub-pixel. In this way, the portion of the capacitor conductive part R blocked by the opening area in the first color sub-pixel is smaller than that in the second color sub-pixel. In the embodiment of the present disclosure, by making the first auxiliary overlapping area S1 approximately equal to the second auxiliary overlapping area S2; or, the first auxiliary overlapping area S1 is larger than the second auxiliary overlapping area S2, the portion of the capacitor conductive part R blocked by the touch electrode 800 in the first color sub-pixel is larger than that in the second color sub-pixel, thereby further reducing the luminous interference and poor light mixing effect caused by the capacitor conductive part R in the first color sub-pixel.

[0156] In a specific implementation, in the embodiment of the present disclosure, the area of ​​the opening region KK1 of the first color sub-pixel may be 100 μm 2 ~130μm 2The shape of the opening area KK1 is not limited, for example, it can be a polygon, rectangle, square, rhombus, ellipse, circle, etc. Of course, it can also be other irregular shapes, such as a closed shape composed of at least 2 arc segments and 1 straight line segment. For example, the opening area KK1 of the first color sub-pixel is a rectangle, the first side length is 12μm-13μm, and the second side length of the opening area KK1 of the first color sub-pixel is 9μm-10μm.

[0157] Optionally, the opening area of ​​the opening region KK1 of the first color sub-pixel is 10*10 μm 2 ~12*10μm 2 Or 11*10μm 2 ~12*10μm 2 Optionally, the opening area of ​​the opening region KK1 of the first color sub-pixel is 13*9 μm 2 ~12*10μm 2 For example, the area of ​​the opening region KK1 of the first color sub-pixel may be 13*9 μm. 2 (length*width), or the area of ​​the opening region KK1 of the first color sub-pixel may be 12*10 μm 2 (length*width). Of course, in practical applications, the design can be determined according to the needs of the actual application environment, and is not limited here.

[0158] In specific implementation, in the embodiment of the present disclosure, the area of ​​the opening region KK2 of the second color sub-pixel may be 120 μm 2 ~200μm 2 The shape of the opening area KK2 is not limited, for example, it can be: rectangle, square, rhombus, ellipse, circle, etc.; of course, it can also be other irregular shapes, such as: a closed shape composed of at least 2 arc segments and 1 straight line segment. For example: the opening area KK2 of the second color sub-pixel is a square with a side length of 13μm-15μm. Optionally, the opening area of ​​the opening area KK2 of the second color sub-pixel is 13*10μm 2 ~19*10μm 2 Or 13*15μm 2 ~18*11μm 2 Optionally, the opening area of ​​the opening region KK1 of the first color sub-pixel may be 13*13 μm. 2 ~14*14μm 2 For example, the area of ​​the opening region KK2 of the second color sub-pixel may be 13*13 μm. 2 Alternatively, the area of ​​the opening region KK2 of the second color sub-pixel may be 14*14 μm 2Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0159] In the specific implementation, in the embodiment of the present disclosure, the area of ​​the opening region KK3 of the third color sub-pixel is 180 μm 2 ~230μm 2 The shape of the opening area KK3 is not limited, for example, it can be: rectangle, square, rhombus, ellipse, circle, etc.; of course, it can also be other irregular shapes, such as: a closed shape composed of at least 2 arc segments and 1 straight line segment. For example: the opening area KK3 of the third color sub-pixel is a rectangle, the first side length is 15μm-16μm, and the second side length of the opening area KK1 of the first color sub-pixel is 13μm-14μm. Optionally, the opening area of ​​the opening area KK3 of the third color sub-pixel is 18*10μm 2 ~23*10μm 2 Or 20*10μm 2 ~22*10μm 2 Optionally, the opening area of ​​the opening region KK1 of the first color sub-pixel may be 15*13 μm. 2 ~16*14μm 2 (length*width). For example, the area of ​​the opening region KK3 of the third color sub-pixel may be 15*13 μm. 2 (length*width). Alternatively, the area of ​​the opening region KK3 of the third color sub-pixel may be 16*13 μm. 2 (length*width). Alternatively, the area of ​​the opening region KK3 of the third color sub-pixel may be 16*14 μm. 2 (length*width). Of course, in practical applications, the design can be determined according to the needs of the actual application environment, and is not limited here.

[0160] In a specific implementation, in the embodiment of the present disclosure, the area of ​​the opening region KK4 of the fourth color sub-pixel may be 100 μm 2 ~230μm 2 The shape of the opening area KK4 is not limited, for example, it can be: rectangle, square, diamond, ellipse, circle, etc.; of course, it can also be other irregular shapes, such as: a closed shape composed of at least 2 arc segments and 1 straight line segment. For example: the opening area of ​​the fourth color sub-pixel is an ellipse, and the area can be 100μm 2 ~130μm 2; Alternatively, the opening area KK4 of the fourth color sub-pixel is a rectangle, the first side length is 12μm-13μm, and the second side length of the opening area KK4 of the fourth color sub-pixel is 9μm-10μm. Optionally, the opening area of ​​the opening area KK1 of the first color sub-pixel is 13*9μm 2 ~12*10μm 2 For example, the area of ​​the opening region KK4 of the fourth color sub-pixel may be 13*9 μm. 2 (length*width), or the area of ​​the opening region KK4 of the fourth color sub-pixel may be 12*10 μm 2 (length*width). Of course, in practical applications, the design can be determined according to the needs of the actual application environment, and is not limited here.

[0161] In the specific implementation, in the embodiment of the present disclosure, the first auxiliary overlapping area S1 may be 3 μm. 2 ~40μm 2 Optionally, the first auxiliary overlapping area S1 may be 6 μm 2 ~20μm 2 For example, the first auxiliary overlapping area S1 may be 3 μm 2 Alternatively, the first auxiliary overlapping area S1 may be 6 μm 2 Alternatively, the first auxiliary overlapping area S1 may be 10 μm 2 Alternatively, the first auxiliary overlapping area S1 may be 20 μm 2 Alternatively, the first auxiliary overlapping area S1 may be 30 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0162] In the specific implementation, in the embodiment of the present disclosure, the second auxiliary overlapping area S2 may be 0-10 μm. 2 Optionally, the second auxiliary overlapping area S2 may be 0-5 μm 2 For example, the second auxiliary overlapping area S2 may be 0 μm 2 Alternatively, the second auxiliary overlapping area S2 may be 5 μm 2 Alternatively, the second auxiliary overlapping area S2 may be 10 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0163] In the specific implementation, in the embodiment of the present disclosure, the third auxiliary overlapping area S3 can be 0-6 μm. 2 Optionally, the third auxiliary overlapping area S3 may be 0-3 μm 2 For example, the third auxiliary overlapping area S3 may be 0 μm2 Alternatively, the third auxiliary overlapping area S3 may be 3 μm 2 Alternatively, the third auxiliary overlapping area S3 may be 6 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0164] In the specific implementation, in the embodiment of the present disclosure, the fourth auxiliary overlapping area S4 may be 0-40 μm. 2 Optionally, the fourth auxiliary overlapping area S4 may be 0-15 μm 2 For example, the fourth auxiliary overlapping area S4 may be 0 μm 2 Alternatively, the fourth auxiliary overlapping area S4 may be 5 μm 2 Alternatively, the fourth auxiliary overlapping area S4 may be 15 μm 2 Alternatively, the fourth auxiliary overlap area S4 is substantially equal to at least one of the first auxiliary overlap area S3, the second auxiliary overlap area S2, and the third auxiliary overlap area S3; or, the fourth auxiliary overlap area S4 is greater than at least one of the first auxiliary overlap area S3, the second auxiliary overlap area S2, and the third auxiliary overlap area S3. Of course, in actual applications, the design can be determined according to the needs of the actual application environment, and is not limited here.

[0165] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6g As shown, the area of ​​the opening region KK1 in the first color sub-pixel can be made larger than the area of ​​the opening region KK4 in the fourth color sub-pixel. The area of ​​the opening region KK1 in the first color sub-pixel can also be made substantially equal to the area of ​​the opening region KK4 in the fourth color sub-pixel. These can be designed and determined according to the needs of actual applications and are not limited here.

[0166] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6gAs shown, the second conductive layer 200 may include a capacitor conductive portion R (WD) (the auxiliary conductive portion WD is taken as the capacitor conductive portion R for example), and the first auxiliary overlapping area S1 may include an overlapping area between the orthographic projection of the auxiliary conductive portion in the first color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000. The second auxiliary overlapping area S2 may include an overlapping area between the orthographic projection of the auxiliary conductive portion in the second color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000. The third auxiliary overlapping area S3 includes an overlapping area between the orthographic projection of the auxiliary conductive portion in the third color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000. The fourth auxiliary overlapping area S4 includes an overlapping area between the orthographic projection of the auxiliary conductive part in the fourth color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the base substrate 1000. In this way, the auxiliary conductive part can be shielded by the touch electrode (for example, the second touch electrode 820), thereby reducing the problem of light interference and poor light mixing effect caused by the auxiliary conductive part reflecting light.

[0167] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Fig.9c As shown, the auxiliary conductive portion WD in the first color sub-pixel includes a first auxiliary exposed portion WD1, and the orthographic projection of the first auxiliary exposed portion WD1 on the substrate 1000 does not overlap with the orthographic projections of the data line pattern DA2 and the power signal line pattern VDD on the substrate 1000. The first auxiliary overlapping area S1 includes a first auxiliary sub-overlapping area S11, and the first auxiliary exposed portion WD1 has the first auxiliary sub-overlapping area S11 between the orthographic projection of the substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate 1000.

[0168] Exemplarily, in the first color sub-pixel, the orthographic projection of the first auxiliary exposed portion WD1 on the base substrate 1000 is located between the orthographic projections of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000 .

[0169] Optionally, the orthogonal projection of the first auxiliary exposed portion WD1 on the substrate 1000 may be located on the side where the orthogonal projection of the data line pattern DA2 on the substrate 1000 is away from the orthogonal projection of the power signal line pattern VDD on the substrate 1000. Alternatively, the orthogonal projection of the first auxiliary exposed portion WD1 on the substrate 1000 may be located on the side where the orthogonal projection of the power signal line pattern VDD on the substrate 1000 is away from the orthogonal projection of the data line pattern DA2 on the substrate 1000.

[0170] It can be understood that the first auxiliary exposure portion WD1 may include at least one of the first auxiliary exposure portion first area WD11 (not shown), the first auxiliary exposure portion second area WD12 (not shown), and the first auxiliary exposure portion third area WD13 (not shown); wherein, the first auxiliary exposure portion first area WD11 is a first area where the orthogonal projection of the auxiliary conductive portion WD on the substrate substrate 1000 is located between the orthogonal projection of the data line pattern DA2 and the orthogonal projection of the power signal line pattern VDD on the substrate substrate 1000, the first auxiliary exposure portion second area WD12 is a second area where the orthogonal projection of the auxiliary conductive portion WD on the substrate substrate 1000 is located on the side of the orthogonal projection of the data line pattern DA2 on the substrate substrate 1000 away from the orthogonal projection of the power signal line pattern VDD on the substrate substrate 1000, and the first auxiliary exposure portion third area WD13 is a third area where the orthogonal projection of the auxiliary conductive portion WD on the substrate substrate 1000 is located on the side of the orthogonal projection of the power signal line pattern VDD on the substrate substrate 1000 away from the orthogonal projection of the data line pattern DA2 on the substrate substrate 1000.

[0171] In specific implementation, in the embodiment of the present disclosure, the first auxiliary sub-overlapping area S11 may be 2 μm 2 ~10μm 2 Optionally, the first auxiliary sub-overlapping area S11 may be 3 μm 2 ~6μm 2 For example, the first auxiliary sub-overlapping area S11 may be 2 μm 2 Alternatively, the first auxiliary sub-overlapping area S11 may be 3 μm 2 Alternatively, the first auxiliary sub-overlapping area S11 may be 5 μm 2 Alternatively, the first auxiliary sub-overlapping area S11 may be 6 μm 2 Alternatively, the first auxiliary sub-overlapping area S11 may be 10 μm 2 Of course, in practical applications, the design can be determined according to the needs of the actual application environment, and is not limited here.

[0172] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6dAs shown, in the same sub-pixel, the orthographic projection of the auxiliary conductive part WD on the base substrate 1000 has a total area Sm. The ratio range between the first auxiliary overlapping area S1 and the total area Sm can be 1 / 6 to 3 / 4. Optionally, the ratio range between the first auxiliary overlapping area S1 and the total area Sm can be: 1 / 3 to 2 / 3, that is, 1 / 3≤S1 / Sm≤2 / 3. For example, S1 / Sm=1 / 3, S1 / Sm=2 / 3, or S1 / Sm=1 / 2. Of course, in actual applications, the specific value of S1 / Sm can be set according to the needs of the actual application, and is not limited here.

[0173] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, in the same sub-pixel, the orthographic projection of the auxiliary conductive part WD on the base substrate 1000 has a total area Sm. Among them, the ratio range between the first auxiliary sub-overlapping area S11 and the total area Sm can be: 1 / 8~2 / 3. Optionally, the ratio range between the first auxiliary sub-overlapping area S11 and the total area Sm can be: 1 / 6~1 / 3, that is, 1 / 6≤S11 / Sm≤1 / 3. For example, S11 / Sm=1 / 6, S11 / Sm=1 / 4, or S11 / Sm=1 / 3. Of course, in actual applications, the specific value of S11 / Sm can be set according to the needs of the actual application, and is not limited here.

[0174] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 9c As shown, in the first color sub-pixel, the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the base substrate 1000 can also cover the orthographic projection of the first auxiliary exposed portion WD1 on the base substrate 1000. In this way, the first auxiliary exposed portion WD1 that may reflect light can be covered as much as possible.

[0175] In the specific implementation, in the embodiment of the present disclosure, if Figure 9b and Fig.9c As shown, the auxiliary conductive portion WD in the first color sub-pixel may further include a first auxiliary shielding portion WZ1, and the orthographic projection of the first auxiliary shielding portion WZ1 on the base substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000. The first auxiliary shielding portion WZ1 and the first auxiliary exposed portion WD1 of the same auxiliary conductive portion are integrally arranged to form an auxiliary conductive portion. For example, as Figure 9b As shown, the width of the first auxiliary exposed portion WD1 in the column direction F3 can be made substantially equal to the width of the first auxiliary shielding portion WZ1 in the column direction F3. This can reduce the difficulty of preparing the auxiliary conductive portion in the first color sub-pixel. Fig.9cAs shown, the width of the first auxiliary exposed portion WD1 in the column direction F3 may also be made smaller than the width of at least a portion of the first auxiliary shielding portion WZ1 in the column direction F3. In this way, the first auxiliary exposed portion WD1 can be further shielded. Exemplarily, the width of the first auxiliary exposed portion WD1 in the row direction F4 may also be made smaller than the width of at least a portion of the first auxiliary shielding portion WZ1 in the row direction F4, so that the area of ​​the exposed auxiliary conductive portion WD can be made smaller, which is beneficial to reducing the reflected light generated by the auxiliary conductive portion WD.

[0176] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Fig.9c As shown, the auxiliary conductive portion WD in the second color sub-pixel includes a second auxiliary exposed portion WD2, and the orthographic projection of the second auxiliary exposed portion WD2 on the substrate substrate 1000 does not overlap with the orthographic projections of the data line pattern DA3 and the power signal line pattern VDD on the substrate substrate 1000 respectively; and the second auxiliary overlapping area S2 includes a second auxiliary sub-overlapping area S12, and there is a second auxiliary sub-overlapping area S12 between the orthographic projection of the second auxiliary exposed portion WD2 on the substrate substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate substrate 1000. Exemplarily, in the second color sub-pixel, the orthographic projection of the second auxiliary exposed portion WD2 on the substrate substrate 1000 is located between the orthographic projections of the data line pattern DA3 and the power signal line pattern VDD on the substrate substrate 1000. Alternatively, the orthographic projection of the second auxiliary exposed portion WD2 on the substrate substrate 1000 is located on the side of the orthographic projection of the data line pattern DA3 on the substrate substrate 1000 away from the orthographic projection of the power signal line pattern VDD on the substrate substrate 1000. Alternatively, the orthographic projection of the second auxiliary exposed portion WD2 on the base substrate 1000 is located on a side of the orthographic projection of the power signal line pattern VDD on the base substrate 1000 away from the orthographic projection of the data line pattern DA3 on the base substrate 1000 .

[0177] In the specific implementation, in the embodiment of the present disclosure, the second auxiliary sub-overlapping area S12 may be 0-4.5 μm. 2 Optionally, the second auxiliary sub-overlapping area S12 may be 0-2.2 μm 2 For example, the second auxiliary sub-overlapping area S12 may be 0 μm 2 Alternatively, the second auxiliary sub-overlapping area S12 may be 1.5 μm 2 Alternatively, the second auxiliary sub-overlapping area S12 may be 2.2 μm 2 Alternatively, the second auxiliary sub-overlapping area S12 may be 3.5 μm 2 Alternatively, the second auxiliary sub-overlapping area S12 may be 4.5 μm 2Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0178] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, in the same sub-pixel, for example, the second color sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Among them, in the same sub-pixel, the ratio range between the second auxiliary overlapping area S2 and the total area Sm (second color sub-pixel) can be: 1 / 20 to 3 / 4. Optionally, the ratio range between the second auxiliary overlapping area S2 and the total area Sm (second color sub-pixel) can be: 1 / 10 to 7 / 20, that is, 1 / 10≤S2 / Sm≤7 / 20. For example, S2 / Sm=1 / 10, S2 / Sm=1 / 5, or S2 / Sm=7 / 20. Of course, in actual applications, the specific value of S2 / Sm can be set according to the needs of the actual application, and is not limited here.

[0179] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, in the same sub-pixel, for example, the second color sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Among them, the ratio range between the second auxiliary sub-overlapping area S12 and the total area Sm can be: 1 / 10 to 1 / 2. The ratio range between the second auxiliary sub-overlapping area S12 and the total area Sm can be: 1 / 5 to 1 / 4, that is, 1 / 5≤S12 / Sm≤1 / 4. For example, S12 / Sm=1 / 4, S12 / Sm=1 / 5, or S12 / Sm=9 / 40. Of course, in actual applications, the specific value of S12 / Sm can be set according to the needs of the actual application, and is not limited here.

[0180] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 9c As shown, in the second color sub-pixel, the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the base substrate 1000 can also cover the orthographic projection of the second auxiliary exposed portion WD2 on the base substrate 1000. In this way, the second auxiliary exposed portion WD2 that may reflect light can be covered as much as possible.

[0181] In the specific implementation, in the embodiment of the present disclosure, if Figure 9b and Fig.9cAs shown, the auxiliary conductive portion WD in the second color sub-pixel may further include a second auxiliary shielding portion WZ2. And the orthographic projection of the second auxiliary shielding portion WZ2 on the substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern and the power signal line pattern VDD on the substrate 1000. The second auxiliary shielding portion WZ2 and the second auxiliary exposed portion WD2 of the same auxiliary conductive portion are integrally arranged to form an auxiliary conductive portion. For example, as Figure 9b As shown, the width of the second auxiliary exposed portion WD2 in the column direction F3 can be made substantially equal to the width of the second auxiliary shielding portion WZ2 in the column direction F3. This can reduce the difficulty of preparing the auxiliary conductive portion in the second color sub-pixel. Fig.9c As shown, the width of the second auxiliary exposure portion WD2 in the column direction F3 can also be made smaller than the width of at least a portion of the second auxiliary shielding portion WZ2 in the column direction F3. In this way, the second auxiliary exposure portion WD2 can be further shielded. Exemplarily, the width of the second auxiliary exposure portion WD2 in the row direction F4 is smaller than the width of at least a portion of the second auxiliary shielding portion WZ2 in the row direction F4.

[0182] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6g As shown, the auxiliary conductive portion WD in the third color sub-pixel includes a third auxiliary exposed portion WD3, and the orthographic projection of the third auxiliary exposed portion WD3 on the substrate substrate 1000 does not overlap with the orthographic projections of the data line pattern DA1 and the power signal line pattern VDD on the substrate substrate 1000; and the third auxiliary overlapping area S3 includes a third auxiliary sub-overlapping area S13, and there is a third auxiliary sub-overlapping area S13 between the orthographic projection of the third auxiliary exposed portion WD3 on the substrate substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate substrate 1000. Exemplarily, in the third color sub-pixel, the orthographic projection of the third auxiliary exposed portion WD3 on the substrate substrate 1000 is located between the orthographic projections of the data line pattern DA1 and the power signal line pattern VDD on the substrate substrate 1000.

[0183] In specific implementation, in the embodiment of the present disclosure, the third auxiliary sub-overlapping area S13 may be 0-2.5 μm. 2 Optionally, the third auxiliary sub-overlapping area S13 may be 0-1.2 μm 2 For example, the third auxiliary sub-overlapping area S13 may be 0 μm 2 Alternatively, the third auxiliary sub-overlapping area S13 may be 0.5 μm 2 Alternatively, the third auxiliary sub-overlapping area S13 may be 1.0 μm 2 Alternatively, the third auxiliary sub-overlapping area S13 may be 1.2 μm 2Alternatively, the third auxiliary sub-overlapping area S13 may be 2.5 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and no specific limitation is made here.

[0184] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, in the same sub-pixel, for example, the third color sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. The ratio range between the third auxiliary overlapping area S3 and the total area Sm can be: 0 to 1 / 2; optionally, the ratio range between the third auxiliary overlapping area S3 and the total area Sm can be: 0 to 1 / 4, that is, 0≤S3 / Sm≤1 / 4. For example, S3 / Sm=0, S3 / Sm=1 / 16, or S3 / Sm=1 / 4. Of course, in actual applications, the specific value of S3 / Sm can be set according to the needs of the actual application, and is not limited here.

[0185] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, in the same sub-pixel, for example, the third color sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. The ratio range between the third auxiliary sub-overlapping area S13 and the total area Sm can be: 0 to 1 / 8; optionally, the ratio range between the third auxiliary sub-overlapping area S13 and the total area Sm can be: 0 to 1 / 16, that is, 0≤S13 / Sm≤1 / 16. For example, S13 / Sm=0, S13 / Sm=1 / 16, or S13 / Sm=1 / 32. Of course, in actual applications, the specific value of S13 / Sm can be set according to the needs of the actual application, and is not limited here.

[0186] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 9c As shown, in the third color sub-pixel, the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the base substrate 1000 can also cover the orthographic projection of the third auxiliary exposure portion WD3 on the base substrate 1000. In this way, the third auxiliary exposure portion WD3 that may reflect light can be covered as much as possible.

[0187] In the specific implementation, in the embodiment of the present disclosure, if Figure 9b and Fig.9cAs shown, the auxiliary conductive portion WD in the third color sub-pixel may further include a third auxiliary shielding portion WZ3. And the orthographic projection of the third auxiliary shielding portion WZ3 on the substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern and the power signal line pattern VDD on the substrate 1000. The third auxiliary shielding portion WZ3 and the third auxiliary exposed portion WD3 of the same auxiliary conductive portion are integrally arranged to form an auxiliary conductive portion. For example, as Figure 9b As shown, the width of the third auxiliary exposed portion WD3 in the column direction F3 can be made substantially equal to the width of the third auxiliary shielding portion WZ3 in the column direction F3. This can reduce the difficulty of preparing the auxiliary conductive portion in the third color sub-pixel. Fig.9c As shown, the width of the third auxiliary exposure portion WD3 in the column direction F3 can also be made smaller than the width of at least a portion of the third auxiliary shielding portion WZ3 in the column direction F3. In this way, the third auxiliary exposure portion WD3 can be further shielded. Exemplarily, the width of the third auxiliary exposure portion WD3 in the row direction F4 is smaller than the width of at least a portion of the third auxiliary shielding portion WZ3 in the row direction F4.

[0188] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6g As shown, the auxiliary conductive portion WD in the fourth color sub-pixel includes a fourth auxiliary exposure portion WD4, and the orthographic projection of the fourth auxiliary exposure portion WD4 on the substrate substrate 1000 does not overlap with the orthographic projections of the data line pattern DA4 and the power signal line pattern VDD on the substrate substrate 1000. And the fourth auxiliary overlapping area S4 includes a fourth auxiliary sub-overlapping area S14, and there is a fourth auxiliary sub-overlapping area S14 between the orthographic projection of the fourth auxiliary exposure portion WD4 on the substrate substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the substrate substrate 1000. Exemplarily, in the fourth color sub-pixel, the orthographic projection of the fourth auxiliary exposure portion WD4 on the substrate substrate 1000 is located between the orthographic projections of the data line pattern DA4 and the power signal line pattern VDD on the substrate substrate 1000.

[0189] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, in the same sub-pixel, for example, the fourth color sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. The ratio between the fourth auxiliary overlapping area S4 and the total area Sm can range from 1 / 6 to 5 / 6, that is, 1 / 6≤S4 / Sm≤5 / 6. For example, S4 / Sm=1 / 6, S4 / Sm=2 / 3, or S4 / Sm=5 / 6. Of course, in actual applications, the specific value of S4 / Sm can be set according to the needs of the actual application, and is not limited here.

[0190] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, in the same sub-pixel, for example, the fourth color sub-pixel, the orthographic projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Among them, the ratio between the fourth auxiliary sub-overlapping area S14 and the total area Sm can range from 1 / 3 to 2 / 3, that is, 1 / 3≤S14 / Sm≤2 / 3. For example, S14 / Sm=1 / 3, S14 / Sm=2 / 3, or S14 / Sm=1 / 2. Of course, in actual applications, the specific value of S14 / Sm can be set according to the needs of the actual application, and is not limited here.

[0191] In specific implementation, in the embodiment of the present disclosure, the fourth auxiliary sub-overlapping area S14 may be 2 μm 2 ~10μm 2 Optionally, the fourth auxiliary sub-overlapping area S14 may be 3 μm 2 ~6μm 2 For example, the fourth auxiliary sub-overlapping area S14 may be 2 μm 2 Alternatively, the fourth auxiliary sub-overlapping area S14 may be 3 μm 2 Alternatively, the fourth auxiliary sub-overlapping area S14 may be 5 μm 2 Alternatively, the fourth auxiliary sub-overlapping area S14 may be 6 μm 2 Alternatively, the fourth auxiliary sub-overlapping area S14 may be 10 μm 2 Of course, in practical applications, the design can be determined according to the needs of the actual application environment, and is not limited here.

[0192] In the specific implementation, in the embodiment of the present disclosure, if Figures 9a to 9c As shown, in the fourth color sub-pixel, the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the base substrate 1000 can also cover the orthographic projection of the fourth auxiliary exposure portion WD4 on the base substrate 1000. In this way, the fourth auxiliary exposure portion WD4 that may reflect light can be covered as much as possible.

[0193] In the specific implementation, in the embodiment of the present disclosure, if Figure 9b and Fig.9c As shown, the auxiliary conductive portion in the fourth color sub-pixel may further include a fourth auxiliary shielding portion WZ4. And the orthographic projection of the fourth auxiliary shielding portion WZ4 on the substrate 1000 overlaps with the orthographic projection of at least one of the data line pattern and the power signal line pattern VDD on the substrate 1000. The fourth auxiliary shielding portion WZ4 and the fourth auxiliary exposed portion WD4 of the same auxiliary conductive portion are integrally arranged to form an auxiliary conductive portion. For example, as Figure 9bAs shown, the width of the fourth auxiliary exposure portion WD4 in the column direction F3 can be made substantially equal to the width of the fourth auxiliary shielding portion WZ4 in the column direction F3. This can reduce the difficulty of preparing the auxiliary conductive portion in the fourth color sub-pixel. Fig.9c As shown, the width of the fourth auxiliary exposure portion WD4 in the column direction F3 can also be made smaller than the width of at least a portion of the fourth auxiliary shielding portion WZ4 in the column direction F3. In this way, the fourth auxiliary exposure portion WD4 can be further shielded. Exemplarily, the width of the fourth auxiliary exposure portion WD4 in the row direction F4 is smaller than the width of at least a portion of the fourth auxiliary shielding portion WZ4 in the row direction F4.

[0194] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, the first auxiliary sub-overlapping area S11 can be made larger than the second auxiliary sub-overlapping area S12. In this way, the first color sub-pixel can have more auxiliary conductive parts in the first color sub-pixel shielded by the touch electrode (for example, the second touch electrode 820) than the second color sub-pixel, thereby reducing the problem of luminous interference and poor light mixing effect caused by the reflection of light from the first auxiliary exposed part WD1.

[0195] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, the first auxiliary sub-overlapping area S11 can be made larger than the third auxiliary sub-overlapping area S13. In this way, the first color sub-pixel can have more auxiliary conductive parts in the first color sub-pixel shielded by the touch electrode (for example, the second touch electrode 820) than the third color sub-pixel, thereby reducing the problem of luminous interference and poor light mixing effect caused by the reflection of light from the first auxiliary exposed part WD1.

[0196] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, the fourth auxiliary sub-overlapping area S14 can be made larger than the second auxiliary sub-overlapping area S12. In this way, the fourth color sub-pixel can have more auxiliary conductive parts in the fourth color sub-pixel shielded by the touch electrode (for example, the second touch electrode 820) than the second color sub-pixel, thereby reducing the problem of luminous interference and poor light mixing effect caused by the reflection of light from the fourth auxiliary exposed part WD4.

[0197] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6dAs shown, the fourth auxiliary sub-overlapping area S14 can be made larger than the third auxiliary sub-overlapping area S13. In this way, the fourth color sub-pixel can have more auxiliary conductive parts in the fourth color sub-pixel shielded by the touch electrode (for example, the second touch electrode 820) than the third color sub-pixel, thereby reducing the problem of luminous interference and poor light mixing effect caused by the reflection of light from the fourth auxiliary exposed part WD4.

[0198] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, the second auxiliary sub-overlapping area S12 can be made larger than the third auxiliary sub-overlapping area S13, so that the first auxiliary sub-overlapping area S11 is larger than the second auxiliary sub-overlapping area S12, and the second auxiliary sub-overlapping area S12 is larger than the third auxiliary sub-overlapping area S13. In this way, the areas of the first auxiliary exposure portion WD1, the second auxiliary exposure portion WD2, and the third auxiliary exposure portion WD3 shielded by the touch electrode (for example, the second touch electrode 820) can be increased in sequence, thereby further reducing the problem of luminous interference and poor light mixing effect caused by the reflection of light from the first auxiliary exposure portion WD1, the second auxiliary exposure portion WD2, and the third auxiliary exposure portion WD3. Of course, the second auxiliary sub-overlapping area S12 may be approximately equal to the third auxiliary sub-overlapping area S13, for example: the second auxiliary sub-overlapping area S12 is equal to the third auxiliary sub-overlapping area S13, and both are equal to 0; or, the fourth auxiliary sub-overlapping area S14 is equal to at least one of the first auxiliary sub-overlapping area S11, the second auxiliary sub-overlapping area S12, and the third auxiliary sub-overlapping area S13; or, the fourth auxiliary sub-overlapping area S14 is greater than at least one of the first auxiliary sub-overlapping area S11, the second auxiliary sub-overlapping area S12, and the third auxiliary sub-overlapping area S13.

[0199] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 6d As shown, the fourth auxiliary sub-overlapping area S14 can be made larger than the first auxiliary sub-overlapping area S11. In this way, the fourth auxiliary exposure portion WD4 shielded by the touch electrode (for example, the second touch electrode 820) can be larger than the first auxiliary exposure portion WD1, thereby further reducing the problem of luminous interference and poor light mixing effect caused by the reflection of light from the fourth auxiliary exposure portion WD4. Of course, the fourth auxiliary sub-overlapping area S14 can also be substantially equal to the first auxiliary sub-overlapping area S11.

[0200] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10bAs shown, the orthographic projection of the first capacitor (for example, taking the second plate Cst2 of the first capacitor as an example) in the first color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the base substrate 1000 have a first storage overlapping area SC1. Exemplarily, the first storage overlapping area SC1 includes the overlapping area between the orthographic projection of the storage conductive portion Cst2 in the first color sub-pixel on the base substrate 1000 and the orthographic projection of the touch electrode (for example, the second touch electrode 820) on the base substrate 1000.

[0201] For example, Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10b As shown, the grid structure formed by the touch electrodes in at least one sub-pixel includes at least 5 internal angles, of which at least 2 are obtuse angles and 2 are acute angles. For example, 5 to 10 internal angles, of which at least 2 are obtuse angles and 2 are acute angles.

[0202] Optionally, the grid structure formed by the touch electrodes in at least one sub-pixel has at least four unequal internal angles. For example, in the first color sub-pixel, the second touch electrodes 820 form internal angles A1 to A5, where A1 is equal to 90°, A2 and A5 are acute angles, with angles of 30°-80°, and A3 and A4 are continuous obtuse angles, with angles of 95° to 150°.

[0203] Of course, the above situation is not limited. For example, optionally, A2 and A5 are equal acute angles, and A3 and A4 are equal obtuse angles. Alternatively, the internal angles of the grid are equal, for example, forming a regular pentagon or a hexagon.

[0204] For example, Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10b As shown, the grid structure formed by the touch electrodes in at least one sub-pixel includes at least 5 edges, of which at least 2 edges are of unequal length. For example, in the first color sub-pixel, the second touch electrodes 820 form 5 edges of A1 to A5 inner angles. For example, the lengths of a1 to a5 are all unequal.

[0205] For example, Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10bAs shown, the structure formed by the touch electrode in at least one sub-pixel includes at least 4 edges, of which at least 2 edges have unequal widths. Optionally, among the multiple edges of the touch electrode in at least one corresponding sub-pixel, the width of at least one edge gradually decreases. For example: the width of the a4 edge decreases from the starting end of the A4 angle to the end of the A5 angle. Optionally, among the multiple edges of the touch electrode in the corresponding sub-pixel, at least one edge includes three parts with unequal widths. For example: Figure 9b As shown, one side of the touch electrode includes at least three parts with unequal widths, DC1 is greater than DC2, and DC1 is greater than DC4. Among them, DC4 has a smaller width, which can reduce the overlap with the power signal line and reduce the impact on the touch signal.

[0206] Of course, the present invention is not limited to the above-mentioned cases. For example, the touch electrodes may be formed into a polygonal structure with equal sides or equal widths, such as a regular pentagon or a regular hexagon.

[0207] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10b As shown, the orthographic projection of the first capacitor in the second color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a second storage overlapping area SC2. Exemplarily, the second storage overlapping area SC2 includes an overlapping area between the orthographic projection of the storage conductive portion Cst2 in the second color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000.

[0208] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10b As shown, the orthographic projection of the first capacitor in the third color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a third storage overlapping area SC3. Exemplarily, the third storage overlapping area SC3 includes an overlapping area between the orthographic projection of the storage conductive portion Cst2 in the third color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000.

[0209] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10bAs shown, the orthographic projection of the first capacitor in the fourth color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000 have a fourth storage overlapping area SC4. Exemplarily, the fourth storage overlapping area SC4 includes an overlapping area between the orthographic projection of the storage conductive portion Cst2 in the fourth color sub-pixel on the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000.

[0210] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10b As shown, at least one of the first storage overlap area SC1, the second storage overlap area SC2 and the fourth storage overlap area SC4 can be made larger than the third storage overlap area SC3. For example, the first storage overlap area SC1, the second storage overlap area SC2 and the fourth storage overlap area SC4 can all be made larger than the third storage overlap area SC3; or at least one of the first storage overlap area SC1 or the fourth storage overlap area SC4 is larger than the second storage overlap area SC2, and the second storage overlap area SC2 is equal to the third storage overlap area SC3.

[0211] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 7f as well as Fig.10a , Fig.10b As shown, the first storage overlap area SC1 can be made larger than the second storage overlap area SC2, so that the first capacitor in the first color sub-pixel can be shielded by the touch electrode (eg, the second touch electrode 820) as much as possible.

[0212] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i to Figure 9b As shown, the touch electrode (for example, the second touch electrode 820) includes a first electrode portion DC1 and a second electrode portion DC2; wherein the orthographic projection of the first electrode portion DC1 on the base substrate 1000 and the orthographic projection of the auxiliary conductive portion on the base substrate 1000 have an overlapping area, and the orthographic projection of the second electrode portion DC2 on the base substrate 1000 and the orthographic projection of the auxiliary conductive portion on the base substrate 1000 do not overlap. The width of the first electrode portion DC1 can be made greater than the width of the second electrode portion DC2. In this way, the touch electrode can better shield the auxiliary conductive portion.

[0213] Alternatively, if Figures 5a to 5i to Figure 9bAs shown, the touch electrode (for example, the second touch electrode 820) includes at least three parts with different widths, and the touch electrode includes a first electrode part DC1, a second electrode part DC2, and a third electrode part DC3 (not shown); for example: the orthographic projection of the first electrode part DC1 on the substrate 1000 and the orthographic projection of the auxiliary conductive part on the substrate 1000 have an overlapping area, the orthographic projection of the second electrode part DC2 on the substrate 1000 and the orthographic projection of the auxiliary conductive part on the substrate 1000 do not overlap, and the orthographic projection of the third electrode part DC3 on the substrate 1000 and the orthographic projection of the storage conductive part on the substrate 1000 have an overlapping area. Optionally, the width of the first electrode part DC1 is smaller than the width of the second electrode part DC2, and the width of the second electrode part DC2 is smaller than the width of the third electrode part DC3.

[0214] Alternatively, if Figures 5a to 5i to Figure 9b As shown, the touch electrode has a protrusion in at least one corresponding sub-pixel region; for example, DC1. The touch electrode has protrusions in at least two corresponding sub-pixel regions, and the protrusions have different protrusion directions or different widths.

[0215] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f as well as Figure 6g As shown, the orthographic projection of the touch electrode (e.g., the second touch electrode 820) located between adjacent opening regions on the base substrate 1000 overlaps with the orthographic projection of at least two different color light-emitting layers on the base substrate 1000. Optionally, the orthographic projection of the touch electrode (e.g., the second touch electrode 820) located between adjacent opening regions on the base substrate 1000 is covered by the orthographic projection of at least two different color light-emitting layers on the base substrate 1000.

[0216] For example, the orthographic projection of the touch electrode (for example, the second touch electrode 820) between adjacent opening regions on the base substrate 1000 may be covered by the orthographic projections of the light-emitting layers of two different colors on the base substrate 1000. The orthographic projection of the touch electrode (for example, the second touch electrode 820) between adjacent opening regions on the base substrate 1000 may also be covered by the orthographic projections of the light-emitting layers of three different colors on the base substrate 1000.

[0217] Exemplarily, in the same sub-pixel, there is an overlapping area (e.g., SC1) between the touch electrode (e.g., 820) and the storage conductive portion WCst2, and the touch electrode (e.g., 820) is overlapped by the orthographic projections of at least three different colors of light-emitting layers on the base substrate 1000, and the area of ​​the orthographic projection of the storage conductive portion WCst2 on the base substrate 1000 is Sn, wherein SC1 / Sn is approximately 1 / 5 to 4 / 5.

[0218] Optionally, in the same sub-pixel, the ratio of the area of ​​the touch electrode covered by the orthographic projection of the light-emitting layer of at least three different colors on the substrate 1000 to the area of ​​the orthographic projection of the corresponding storage conductive portion WCst2 on the substrate 1000 is approximately 3 / 10 to 2 / 5. For example, the ratio of the area of ​​the touch electrode covered by the orthographic projection of the light-emitting layer of at least three different colors on the substrate 1000 to the area of ​​the orthographic projection of the corresponding storage conductive portion WCst2 on the substrate 1000 is approximately 1 / 5. Alternatively, the ratio of the area of ​​the touch electrode covered by the orthographic projection of the light-emitting layer of at least three different colors on the substrate 1000 to the area of ​​the orthographic projection of the corresponding storage conductive portion WCst2 on the substrate 1000 is approximately 3 / 10. Alternatively, the ratio of the area of ​​the touch electrode covered by the orthographic projection of the light-emitting layer of at least three different colors on the substrate 1000 to the area of ​​the orthographic projection of the corresponding storage conductive portion WCst2 on the substrate 1000 is approximately 2 / 5. Alternatively, the ratio of the area of ​​the touch electrode covered by the orthographic projection of the light-emitting layer of at least three different colors on the base substrate 1000 to the orthographic projection area of ​​the corresponding storage conductive part WCst2 on the base substrate 1000 is approximately 1 / 2. Of course, in practical applications, the design can be made according to the requirements of the actual application environment, and is not limited here.

[0219] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f , Figure 6g as well as Fig.11 As shown, the orthographic projection of the touch electrode (for example, the second touch electrode 820) surrounding the opening area KK1 in the first color sub-pixel on the base substrate 1000 can be located within the orthographic projection of the first color light-emitting layer 610 on the base substrate 1000. In this way, the area of ​​the first color light-emitting layer 610 can be increased to ensure the light-emitting effect.

[0220] Optionally, the auxiliary conductive portion is further shielded by making at least a portion of the boundary ES1 of the first color light emitting layer 610 cover the auxiliary conductive portion.

[0221] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f , Figure 6g as well as Fig.11 As shown, the orthographic projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening area KK2 in the second color sub-pixel on the base substrate 1000 can be located within the orthographic projection of the second color light-emitting layer 620 on the base substrate 1000. In this way, the area of ​​the second color light-emitting layer 620 can be increased to ensure the light-emitting effect.

[0222] Optionally, the auxiliary conductive portion is further shielded by making at least a portion of the boundary ES2 of the second color light emitting layer 620 cover the auxiliary conductive portion.

[0223] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f , Figure 6g as well as Fig.11 As shown, the orthographic projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening area KK3 in the third color sub-pixel on the base substrate 1000 can be located within the orthographic projection of the third color light-emitting layer 630 on the base substrate 1000. In this way, the area of ​​the third color light-emitting layer 630 can be increased to ensure the light-emitting effect.

[0224] Optionally, the auxiliary conductive portion is further shielded by making at least a portion of the boundary ES3 of the third color light emitting layer 630 cover the auxiliary conductive portion.

[0225] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f , Figure 6g as well as Fig.11 As shown, the orthographic projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening area KK4 in the fourth color sub-pixel on the base substrate 1000 can be located within the orthographic projection of the fourth color light-emitting layer 640 on the base substrate 1000. In this way, the area of ​​the fourth color light-emitting layer 640 can be increased to ensure the light-emitting effect.

[0226] Optionally, the auxiliary conductive portion is further shielded by making at least a portion of the boundary ES4 of the fourth color light emitting layer 640 cover the auxiliary conductive portion.

[0227] It is understandable that in the region where at least two color light-emitting layers overlap, the stacking position of the light-emitting layers is not limited to the cases listed in this embodiment, and can be adjusted according to actual conditions or process conditions, for example: different color light-emitting layers are made in the same step or in different steps. Figure 5e In the figure, the order from the pixel defining layer 950 upwards is 610, 620, 630. Of course, the order from the pixel defining layer 950 upwards may be 630, 620, 610 or 610, 630, 620 or 630, 610, 620 and so on.

[0228] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f , Figure 6g as well as Fig.11As shown, for the adjacent third color light-emitting layer 630 and the second color light-emitting layer 620, there is a first minimum distance W0S1 between the boundary ES3 of the orthographic projection of the third color light-emitting layer 630 on the substrate 1000 and the boundary CK3 of the orthographic projection of the touch electrode (for example, the second touch electrode 820) surrounding the third color sub-pixel on the substrate 1000, and there is a second minimum distance W0S2 between the boundary ES2 of the orthographic projection of the second color light-emitting layer 620 on the substrate 1000 and the boundary CK1 of the orthographic projection of the touch electrode (for example, the second touch electrode 820) surrounding the second color sub-pixel on the substrate 1000. Among them, the first minimum distance W0S1 is greater than the second minimum distance W0S2. In this way, on the one hand, the area of ​​the third color light-emitting layer 630 can be further increased to ensure the light-emitting effect. On the other hand, by making at least part of the boundary ES3 of the third color light-emitting layer 630 cover the auxiliary conductive part, the auxiliary conductive part is further shielded. Furthermore, since the light emitting area of ​​the second color sub-pixel is relatively small, when the third color light emitting layer 630 extends into the second color light emitting layer 620 , the light emitting effect of the second color sub-pixel is less affected.

[0229] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f , Figure 6g as well as Fig.11 As shown, the area enclosed by the orthographic projection of the touch electrode (for example, the second touch electrode 820) surrounding the opening area KK1 in the first color sub-pixel on the substrate 1000 is the first grid area WG1. The area enclosed by the orthographic projection of the touch electrode (for example, the second touch electrode 820) surrounding the opening area KK2 in the second color sub-pixel on the substrate 1000 is the second grid area WG2. The area enclosed by the orthographic projection of the touch electrode (for example, the second touch electrode 820) surrounding the opening area KK3 in the third color sub-pixel on the substrate 1000 is the third grid area WG3. Among them, the third grid area WG3 is greater than the second grid area WG2 and greater than the first grid area WG1. In this way, the third grid area WG3, the second grid area WG2 and the first grid area WG1 can be proportional to the opening area KK3 in the third color sub-pixel, the opening area KK2 in the second color sub-pixel and the opening area KK1 in the first color sub-pixel, respectively, so as to improve the light transmittance.

[0230] It is understandable that the first touch electrodes 810 and / or the second touch electrodes in the embodiment of the present disclosure are not required to be all in a closed grid shape, and the touch electrodes corresponding to local areas or individual sub-pixels may have gaps or be disconnected. Figure 1-Figure 2 ,as well as Figures 5a to 5i , Figure 6f , Figure 6g-Figure 11As shown: at the edge of the display area AA close to the non-display area, or in the non-display area, or the touch electrodes corresponding to individual sub-pixels have gaps or are disconnected.

[0231] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 6f , Figure 6g as well as Fig.11 As shown, the area enclosed by the orthographic projection of the touch electrode (e.g., the second touch electrode 820) surrounding the opening area KK4 in the fourth color sub-pixel on the base substrate 1000 is the fourth grid area WG4. The first grid area WG1 corresponding to the first color sub-pixel can be made larger than the fourth grid area WG4 corresponding to the fourth color sub-pixel. Alternatively, the first grid area WG1 corresponding to the first color sub-pixel can be made substantially equal to the fourth grid area WG4 corresponding to the fourth color sub-pixel, which is not limited here.

[0232] In specific implementation, in the embodiment of the present disclosure, the first grid area WG1 may be 850-920 μm 2 Optionally, the first grid area WG1 may be 860 μm 2 ~910μm 2 For example, the first grid area WG1 may be 850 μm 2 Alternatively, the first grid area WG1 may be 860 μm 2 Alternatively, the first grid area WG1 may be 900 μm 2 Alternatively, the first grid area WG1 may be 910 μm 2 Alternatively, the first grid area WG1 may be 920 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0233] Alternatively, in a specific implementation, in the embodiment of the present disclosure, the first grid area WG1 may also be 30.5*28.5 μm 2 ~35.5*30.5μm 2 Optionally, the first grid area WG1 may be 30.5*28.5 μm 2 For example, the first grid area WG1 may be 31.5*29.5 μm 2 Alternatively, the first grid area WG1 may be 32.5*29.1 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0234] In specific implementation, in the embodiment of the present disclosure, the second grid area WG2 may be 950-1050 μm 2Optionally, the second grid area WG2 may be 960-1040 μm 2 For example, the second grid area WG2 may be 950 μm 2 Alternatively, the second grid area WG2 may be 960 μm 2 Alternatively, the second grid area WG2 may be 980 μm 2 Alternatively, the second grid area WG2 may be 1000 μm 2 Alternatively, the second grid area WG2 may be 1040 μm 2 Alternatively, the second grid area WG2 may be 1050 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0235] Alternatively, in a specific implementation, in the embodiment of the present disclosure, the second grid area WG2 may be 30.1*30.1 μm. 2 ~32.1*32.1μm 2 Optionally, the second grid area WG2 may be 30.5*30.5 μm 2 ~32.0*32.0μm 2 For example, the second grid area WG2 may be 30.1*30.1 μm 2 Alternatively, the second grid area WG2 may be 30.5*30.5 μm 2 Alternatively, the second grid area WG2 may be 31.6*31.6 μm 2 Alternatively, the second grid area WG2 may be 32.0*32.0 μm 2 Alternatively, the second grid area WG2 may be 32.1*32.1 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0236] In specific implementation, in the embodiment of the present disclosure, the third grid area WG3 may be 1100 μm 2 ~1300μm 2 Optionally, the third grid area WG3 may be 1150 μm 2 ~1250μm 2 For example, the third grid area WG3 may be 1100 μm 2 Alternatively, the third grid area WG3 may be 1150 μm 2 Alternatively, the third grid area WG3 may be 1200 μm 2 Alternatively, the third grid area WG3 may be 1225 μm 2Alternatively, the third grid area WG3 may be 1300 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0237] Alternatively, in a specific implementation, in the embodiment of the present disclosure, the third grid area WG3 may be 32*32 μm 2 ~37*37μm 2 Optionally, the third grid area WG3 may be 33*33 μm 2 ~36*36μm 2 For example, the third grid area WG3 may be 32*32 μm 2 Alternatively, the third grid area WG3 may be 33*33 μm 2 Alternatively, the third grid area WG3 may be 34*34 μm 2. Alternatively, the third grid area WG3 may be 35*35 μm 2 Alternatively, the third grid area WG3 may be 36*36 μm 2 Alternatively, the third grid area WG3 may be 37*37 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0238] In specific implementation, in the embodiment of the present disclosure, the fourth grid area WG4 may be 850-920 μm 2 Optionally, the fourth grid area WG4 may be 860 μm 2 ~910μm 2 For example, the fourth grid area WG4 may be 850 μm 2 Alternatively, the fourth grid area WG4 may be 860 μm 2 Alternatively, the fourth grid area WG4 may be 900 μm 2 Alternatively, the fourth grid area WG4 may be 910 μm 2 Alternatively, the fourth grid area WG4 may be 920 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0239] Alternatively, in a specific implementation, in the embodiment of the present disclosure, the fourth grid area WG4 may also be 30.5*28.5 μm 2 ~35.5*30.5μm 2 Optionally, the fourth grid area WG4 may be 30.5*28.5 μm 2 For example, the fourth grid area WG4 may be 31.5*29.5 μm2 Alternatively, the fourth grid area WG4 may be 32.5*29.1 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the actual application environment, and is not limited here.

[0240] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i and Fig.11 As shown, in the same repeating unit, the opening area KK3 in the third color sub-pixel and the opening area KK1 in the first color sub-pixel can be arranged along the first direction F1. The opening area KK2 in the second color sub-pixel and the opening area KK4 in the fourth color sub-pixel can also be arranged along the first direction F1. Among them, the area surrounded by the inner boundary NS3 of the touch electrode (for example, the second touch electrode 820) surrounding the opening area KK3 in the third color sub-pixel has a first width WK1 in a direction perpendicular to the first direction F1. The area surrounded by the inner boundary NS1 of the touch electrode (for example, the second touch electrode 820) surrounding the opening area KK1 in the first color sub-pixel has a second width WK2 in a direction perpendicular to the first direction F1. The area surrounded by the inner boundary NS2 of the touch electrode (for example, the second touch electrode 820) surrounding the opening area KK2 in the second color sub-pixel has a third width WK3 in a direction perpendicular to the first direction F1. The area enclosed by the inner boundary NS4 of the touch electrode (eg, the second touch electrode 820 ) surrounding the opening area KK4 in the fourth color sub-pixel has a fourth width WK4 in a direction perpendicular to the first direction F1 .

[0241] Optionally, the first direction F1 and the row direction F3 may form a certain angle, for example, the angle may be greater than 0 degrees and less than 90 degrees. Optionally, the first direction F1 and the row direction F3 may form 25 to 75 degrees. Optionally, the first direction F1 and the row direction F3 may form 30 to 60 degrees. For example, the first direction F1 and the row direction F3 may form 25 degrees. Alternatively, the first direction F1 and the row direction F3 may form 30 degrees. Alternatively, the first direction F1 and the row direction F3 may form 45 degrees. Alternatively, the first direction F1 and the row direction F3 may form 60 degrees. Alternatively, the first direction F1 and the row direction F3 may form 75 degrees. Of course, in actual applications, the design can be determined according to the needs of the actual application environment, and is not limited here.

[0242] In a specific implementation, in the embodiment of the present disclosure, the first width WK1 may be 34.0 μm to 35.0 μm. Optionally, the first width WK1 may be 34.1 μm to 34.9 μm. For example, the first width WK1 may be 34.0 μm. Alternatively, the first width WK1 may be 34.1 μm. Alternatively, the first width WK1 may be 34.4 μm. Alternatively, the first width WK1 may be 34.8 μm. Alternatively, the first width WK1 may be 34.9 μm. Alternatively, the first width WK1 may be 35.0 μm. Of course, in actual applications, the design may be determined according to the requirements of the actual application environment, and is not limited here.

[0243] In a specific implementation, in the embodiment of the present disclosure, the second width WK2 may be 30.5 μm to 31.5 μm. Optionally, the second width WK2 may be 30.7 μm to 31.4 μm. For example, the second width WK2 may be 30.5 μm. Alternatively, the second width WK2 may be 30.7 μm. Alternatively, the second width WK2 may be 31.2 μm. Alternatively, the second width WK2 may be 31.4 μm. Alternatively, the second width WK2 may be 31.5 μm. Of course, in actual applications, the design may be determined according to the requirements of the actual application environment, and is not limited here.

[0244] In a specific implementation, in the embodiment of the present disclosure, the third width WK3 may be 30.8 μm to 32.5 μm. Optionally, the third width WK3 may be 31.0 μm to 32.0 μm. For example, the third width WK3 may be 30.8 μm. Alternatively, the third width WK3 may be 31.0 μm. Alternatively, the third width WK3 may be 31.6 μm. The third width WK3 may be 31.8 μm. Alternatively, the third width WK3 may be 32.0 μm. Alternatively, the third width WK3 may be 32.5 μm. Of course, in actual applications, the design may be determined according to the requirements of the actual application environment, and is not limited here.

[0245] In a specific implementation, in the embodiment of the present disclosure, the fourth width WK4 may be 28.8 to 31.5 μm. Optionally, the fourth width WK4 may be 29.2 to 30.5 μm. For example, the fourth width WK4 may be 28.8 μm. Alternatively, the fourth width WK4 may be 29.2 μm. Alternatively, the fourth width WK4 may be 29.9 μm. Alternatively, the fourth width WK4 may be 30.5 μm. Alternatively, the fourth width WK4 may be 31.5 μm. Of course, in actual applications, the design may be determined according to the requirements of the actual application environment, and is not limited here.

[0246] For example, Fig.11As shown, the first width WK1 can be made greater than the second width WK2. In this way, the opening area KK3 in the third color sub-pixel and the opening area KK1 in the first color sub-pixel can be ensured, and the light transmittance can be improved. Exemplarily, the difference between the first width WK1 and the second width WK2 can be 3.0μm to 4.0μm. Optionally, the difference between the first width WK1 and the second width WK2 can be 3.1μm to 3.9μm. For example, the difference between the first width WK1 and the second width WK2 can be 3.0μm. Alternatively, the difference between the first width WK1 and the second width WK2 can be 3.3μm. Alternatively, the difference between the first width WK1 and the second width WK2 can be 3.6μm. Alternatively, the difference between the first width WK1 and the second width WK2 can be 3.8μm. Alternatively, the difference between the first width WK1 and the second width WK2 can be 3.9μm. Alternatively, the difference between the first width WK1 and the second width WK2 can be 4.0μm. Of course, in practical applications, the design can be determined according to the requirements of the actual application environment and is not limited here.

[0247] For example, Fig.11 As shown, the third width WK3 can be made greater than the fourth width WK4. In this way, the opening area KK2 in the second color sub-pixel and the opening area KK4 in the fourth color sub-pixel can be guaranteed, and the light transmittance can be improved. Exemplarily, the difference between the third width WK3 and the fourth width WK4 can be 1.0μm to 2.0μm. Optionally, the difference between the third width WK3 and the fourth width WK4 can be 1.2μm to 1.8μm. For example, the difference between the third width WK3 and the fourth width WK4 can be 1.0μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 can be 1.2μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 can be 1.5μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 can be 1.7μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 can be 1.8μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 can be 2.0μm. Of course, in practical applications, the design can be determined according to the requirements of the actual application environment and is not limited here.

[0248] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i and Fig.12As shown, the extension direction F0 of the grid line of the touch electrode (for example, the second touch electrode 820) having an overlapping area with the orthographic projection of the auxiliary conductive part has an angle β with the third direction; and 15°≤β≤60°; optionally, the angle β is 20°≤β≤50°. The third direction is substantially perpendicular to the extension direction of the data line pattern, for example, the third direction may be the row direction F4. Exemplarily, tanβ=A1 / A2 can be made; wherein A1 represents the width of the auxiliary conductive part in the direction perpendicular to the third direction, and A2 represents the width of the auxiliary conductive part in the third direction. For example, β=15°, β=25°, β=35°, β=45°, β=50°, or β=60°. Of course, in practical applications, the specific value of β can be determined according to the needs of the practical application, and is not limited here.

[0249] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i and Fig.12 As shown, the extending direction of the grid lines of the touch electrode (e.g., the second touch electrode 820) having an overlapping area with the orthographic projection of the auxiliary conductive portion in the first color sub-pixel has a first angle β1 with the third direction. The extending direction of the grid lines of the touch electrode (e.g., the second touch electrode 820) having an overlapping area with the orthographic projection of the auxiliary conductive portion in the second color sub-pixel has a second angle β2 with the third direction. The extending direction of the grid lines of the touch electrode (e.g., the second touch electrode 820) having an overlapping area with the orthographic projection of the auxiliary conductive portion in the third color sub-pixel has a third angle β3 with the third direction. The first angle can be made smaller than the second angle and smaller than the third angle, so that the touch electrode (e.g., the second touch electrode 820) can cover the auxiliary conductive layer as much as possible. Of course, according to actual conditions, at least two of the angles β1, β2, and β3 can be the same.

[0250] In the specific implementation, in the embodiment of the present disclosure, if Figures 5a to 5i , Figure 9a , Fig.10a As shown, the opening areas of four adjacent sub-pixels are an opening group, and the orthographic projections of the grid intersections of the touch electrodes (for example, the second touch electrodes 820) on the base substrate 1000 are located in the area surrounded by the orthographic projections of the opening group on the base substrate 1000. Further, the orthographic projections of the grid intersections of the touch electrodes (for example, the second touch electrodes 820) on the base substrate 1000 are approximately located at the center of the area surrounded by the orthographic projections of the opening group on the base substrate 1000. In this way, the grid intersections can be evenly dispersed in the display area, further improving the display uniformity.

[0251] In the specific implementation, in the embodiment of the present disclosure, if Fig.13a and Fig.13bAs shown, the first electrode 510 (e.g., anode) in the first color sub-pixel has a first anode overlapping area BS1 in the overlapping area between the orthographic projection of the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000; the first electrode 520 in the second color sub-pixel has a second anode overlapping area BS2 in the overlapping area between the orthographic projection of the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000; the first electrode 530 in the third color sub-pixel has a third anode overlapping area BS3 in the overlapping area between the orthographic projection of the substrate 1000 and the touch electrode (e.g., the second touch electrode 820) on the substrate 1000; the first electrode 540 in the fourth color sub-pixel has a fourth anode overlapping area BS4 in the overlapping area between the orthographic projection of the substrate 1000 and the orthographic projection of the touch electrode (e.g., the second touch electrode 820) on the substrate 1000. Wherein, at least one of the first anode overlap area BS1, the second anode overlap area BS2 and the fourth anode overlap area BS4 is greater than the third anode overlap area BS3.

[0252] For example, the first anode overlap area BS1 may be larger than the third anode overlap area BS3, the second anode overlap area BS2 may be larger than the third anode overlap area BS3, and the fourth anode overlap area BS4 may be larger than the third anode overlap area BS3.

[0253] In the specific implementation, in the embodiment of the present disclosure, if Fig.13a and Fig.13b As shown, the first anode overlap area BS1 can be made larger than the second anode overlap area BS2. Alternatively, the first anode overlap area BS1 can be made substantially equal to the second anode overlap area BS2.

[0254] In the specific implementation, in the embodiment of the present disclosure, if Fig.13a and Fig.13b As shown, the first anode overlap area BS1 is larger than the fourth anode overlap area BS4. Alternatively, the first anode overlap area BS1 may be substantially equal to the fourth anode overlap area BS4.

[0255] In the specific implementation, in the embodiment of the present disclosure, if Fig.13a and Fig.13b As shown, the fourth anode overlap area BS4 is larger than the second anode overlap area BS2. Alternatively, the fourth anode overlap area BS4 may be substantially equal to the second anode overlap area BS2.

[0256] Optionally, the first anode overlap area BS1 is 2.5 μm 2 -35μm 2Optionally, the first anode overlap area BS1 is 3 μm 2 -25μm 2 Alternatively, the first anode overlap area BS1 may be set to 6 μm 2 -20μm 2 .

[0257] Optionally, the second anode overlap area BS2 is 0 μm 2 -30μm 2 Optionally, the second anode overlap area BS2 is 1.5 μm 2 -25μm 2 Alternatively, the second anode overlap area BS2 may be set to 6 μm. 2 -20μm 2 .

[0258] Optionally, the third anode overlap area BS3 is 0 μm 2 -25μm 2 Optionally, the third anode overlap area BS3 is 1.5 μm 2 -25μm 2 Alternatively, the third anode overlap area BS3 may be set to 5 μm 2 -20μm 2 .

[0259] Optionally, the fourth anode overlap area BS4 is 0 μm 2 -30μm 2 Optionally, the fourth anode overlap area BS4 is 1.5 μm 2 -25μm 2 Alternatively, the first anode overlap area BS4 may be set to 6 μm 2 -20μm 2 .

[0260] In the specific implementation, in the embodiment of the present disclosure, if Fig.14a and Fig.14b As shown, combined Figure 8a-8d An auxiliary insulating layer may be further provided on the side of the second touch electrode 820 away from the base substrate 1000. An auxiliary electrode 840 may also be provided on the side of the auxiliary insulating layer away from the base substrate 1000. Exemplarily, the auxiliary electrode 840 is in a floating state and does not transmit a signal. Of course, the auxiliary electrode 840 may be made in the same layer and / or formed of the same material as the first touch electrode 810.

[0261] It is understandable that if Fig.14a and Fig.14b Shown and combined Figure 8a-8dAn insulating layer 830 is disposed on the side of the first touch electrode 810 away from the base substrate 1000. An auxiliary electrode 840 may also be disposed on the side of the first touch electrode 810 away from the base substrate 1000. The auxiliary electrode 840 is in a floating state and does not transmit signals. The auxiliary electrode 840 may be made in the same layer and / or made of the same material as the second touch electrode 820 (or 811).

[0262] In the specific implementation, in the embodiment of the present disclosure, if Fig.15 As shown, the display panel also includes a power input line VDDIN located in the non-display area. The power signal line pattern VDD in the display area is electrically connected to the power input line VDDIN. Exemplarily, the power signal line patterns VDD of two adjacent columns of sub-pixels are electrically connected through the power input line VDDIN; or, the power signal line patterns VDD corresponding to two adjacent columns of sub-pixels of the same color are electrically connected through the power input line VDDIN. Exemplarily, the power input line VDDIN can be set on the same layer as the power signal line pattern VDD. Alternatively, the power input line VDDIN can also be set on a different layer from the power signal line pattern VDD, so it is also necessary to electrically connect the power signal line pattern VDD and the power input line VDDIN through a via. In addition, the data line pattern DA and the power input line VDDIN may not be set on the same conductive layer.

[0263] It can be understood that the above disclosed embodiments can be adaptively combined as needed, and the numerical ranges can be adjusted accordingly.

[0264] The present disclosure also provides a display device, including the display panel provided in the present disclosure, for example, an organic light emitting diode (OLED). The principle of the display device to solve the problem is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.

[0265] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a watch, a bracelet, etc. Other essential components of the display device are components that should be understood by a person of ordinary skill in the art, and are not described in detail here, nor should they be used as a limitation to the present disclosure.

[0266] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0267] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: substrate substrate; A transistor array layer, located on the substrate; A pixel defining layer, located on a side of the transistor array layer away from the base substrate; A touch electrode is located on a side of the pixel defining layer away from the base substrate; The base substrate has a display area, and the display area includes a plurality of sub-pixels; the sub-pixels include a pixel circuit and a light-emitting element; the pixel circuit includes a gate line pattern, a data line pattern, and a power signal line pattern; The transistor array layer includes a plurality of capacitor conductive parts, and the sub-pixels include corresponding capacitor conductive parts; wherein, in the same sub-pixel, the capacitor conductive part and the data line pattern corresponding to the sub-pixel and / or the power signal line pattern corresponding to the sub-pixel have an overlapping area; the capacitor conductive part at least couples the power signal line pattern corresponding to the sub-pixel or the data line pattern corresponding to the sub-pixel; The pixel defining layer includes a plurality of opening areas, and the sub-pixel includes the corresponding opening areas; At least part of the touch electrodes are projected as a grid on the base substrate; The transistor array layer further comprises a first conductive layer, and the capacitor conductive part is formed on the first conductive layer; The pixel circuit includes a plurality of transistors, and sources and drains of at least some of the transistors are formed on the first conductive layer.

2. The display panel according to claim 1, wherein: The capacitor conductive part is in an arc shape or an irregular shape.

3. The display panel according to claim 1, wherein: The capacitor conductive part includes an auxiliary conductive part, and the auxiliary conductive part at least partially overlaps with the power signal line pattern, the data line pattern, and the touch electrode.

4. The display panel according to claim 1, wherein: The power signal line patterns of two adjacent columns of sub-pixels are electrically connected via a power input line; or the power signal line patterns corresponding to two adjacent columns of sub-pixels of the same color are electrically connected via a power input line.

5. The display panel according to claim 4, wherein: The power input line and the power signal line pattern are located in different layers.

6. The display panel according to claim 1, wherein: The width of the power signal line pattern is greater than the width of the data line pattern.

7. The display panel according to claim 4, wherein: The data line pattern and the power signal line pattern are not arranged on the same conductive layer; or, the data line pattern and the power input line are not arranged on the same conductive layer.

8. The display panel according to claim 1, wherein: The first conductive layer includes a first sub-conductive layer and a second sub-conductive layer which are stacked, and a first sub-insulating layer is disposed between the first sub-conductive layer and the second sub-conductive layer.

9. The display panel according to claim 1, wherein: An overlapping area between the capacitor conductive portion and the power signal line pattern is greater than an overlapping area between the capacitor conductive portion and the data line pattern.

10. The display panel according to claim 1, wherein: The pixel circuit includes: a seventh transistor and a second transistor; the gate of the seventh transistor is coupled to the second reset signal line pattern, and the gate of the second transistor is coupled to the first reset signal line pattern; the first reset signal line pattern and the second reset signal line pattern transmit different signals.

11. The display panel according to claim 1, wherein: The pixel circuit includes: a data writing transistor and a first transistor; the gate line pattern coupled to the gate of the data writing transistor and the gate line pattern coupled to the gate of the first transistor transmit different timing signals.

12. A display device, wherein: Comprising a display panel as described in any one of claims 1-11.

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