Display device

Abstract

A display device according to an embodiment of the present inventive concept includes a substrate including a main display portion and a first side portion connected to the main display portion; a plurality of scan lines and a plurality of data lines disposed on the substrate; a pixel connected to the plurality of scan lines and the plurality of data lines; a data voltage transmission line connected to the plurality of data lines, respectively; a connection wiring connected to the data voltage transmission line; a sub-connection wiring connected to the connection wiring; and a driver connected to the sub-connection wiring, wherein an arrangement order of the data lines from a leftmost side to a rightmost side at the first side portion and an arrangement order of connection of the data lines to the driver through the sub-connection wiring are the same.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0148746, filed on November 19, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The technical field relates to a display device. Background Technology

[0003] Mobile electronic devices, such as mobile phones, navigation systems, digital cameras, e-readers, portable game consoles, and various terminals, are widely used. These mobile electronic devices can include liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays.

[0004] Such display devices are usually rectangular, but recently rounded (or circular) corners have been adopted.

[0005] Signal lines are placed in the rounded corners, side surfaces, and other areas of the display device to transmit image signals, thereby increasing the non-display area and decreasing the light-emitting area. When signal lines are placed to prevent the light-emitting area from decreasing, the arrangement order of the drivers and the arrangement order of the signal lines become different from each other, and a specific arrangement of the drivers is required.

[0006] The information disclosed above in this background section is only intended to enhance the understanding of the background of the inventive concept, and therefore may contain information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] Efforts have been made to provide a display device that can prevent a reduction in the light-emitting area while preventing an increase in manufacturing costs.

[0008] A display device according to an embodiment of the present invention includes: a substrate including a main display portion and a first side portion connected to the main display portion; scan lines and data lines disposed on the substrate; pixels connected to the scan lines and data lines; data voltage transmission lines respectively connected to the data lines; connection wiring connected to the data voltage transmission lines; sub-connection wiring connected to the connection wiring; and a driver connected to the sub-connection wiring, wherein the arrangement order of the data lines from the leftmost to the rightmost side portion and the connection order of the data lines to the driver via the sub-connection wiring are the same arrangement order.

[0009] The display device may have: a connection wire in the connection wire that is connected to the nth data line (n is a positive integer) in the data line, and a sub-connection wire in the sub-connection wire that is connected to the driver.

[0010] The display device may have a second side portion that curves from the main display portion, wherein a driver is connected to the second side portion.

[0011] The display device may have: a main display portion, the main display portion including a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer that are insulated from each other, and a connection wiring including at least one of a first connection wiring disposed in the same layer as the first conductive layer, a second connection wiring disposed in the same layer as the second conductive layer, a third connection wiring disposed in the same layer as the third conductive layer and a fourth connection wiring disposed in the same layer as the fourth conductive layer.

[0012] The display device may have the following configuration: a data line and a data voltage transmission line are connected to each other at one edge of a first side portion.

[0013] The display device may have an edge portion disposed between a main display portion and a first side portion, wherein when n data lines are disposed between the first side portion and the edge portion, an edge of each of the data voltage transmission lines connected to the n data lines in the first side portion and the edge portion is respectively located between the n data lines in the main display portion adjacent to the edge portion.

[0014] The display device may have: wherein a data line is connected to a driver via a first connection wiring, and wherein a data voltage transmission line is connected to the driver via a first sub-connection wiring and a fourth connection wiring.

[0015] The display device may have contact holes formed in a plurality of insulating layers, wherein the plurality of insulating layers are disposed between a first sub-connection wiring and a fourth connection wiring, and wherein the first sub-connection wiring and the fourth connection wiring are connected through contact holes.

[0016] The display device may have the following features: wherein the first connecting wires are positioned alternately in sequence.

[0017] The display device may have a shielding layer disposed between the first sub-connection wiring and the fourth connection wiring and disposed in the same layer as the third conductive layer.

[0018] The display device may have: wherein the driver includes a curved portion and a driving circuit portion, wherein the curved portion is disposed between at least one of the second side portions and the driving circuit portion, and wherein a fourth connecting wire is disposed between the curved portion and the driving circuit portion.

[0019] The display device may have: wherein the driver includes a curved portion and a driving circuit portion, wherein the curved portion is disposed between the second side portion and the driving circuit portion, and wherein a fourth connecting wire is disposed between the second side portion and the curved portion.

[0020] The display device according to an embodiment includes: a substrate including a main display portion and a first side portion connected to the main display portion; scan lines and data lines disposed on the substrate; pixels connected to the scan lines and data lines; data voltage transmission lines connected to the data lines respectively; connection wiring connected to the data voltage transmission lines; and a driver connected to the connection wiring.

[0021] The display device may have: wherein the connection wiring includes a third connection wiring and a fourth connection wiring, wherein n data lines (n is a positive integer) in the main display section are connected to the driver through the third connection wiring, and wherein the data voltage transmission line is connected to the driver through the third connection wiring and the fourth connection wiring.

[0022] The display device may have: wherein an insulating layer is disposed between a third connecting wire and a fourth connecting wire, wherein the insulating layer includes a contact hole, and wherein the third connecting wire and the fourth connecting wire are in contact with each other through the contact hole.

[0023] The display device may have: wherein the driver includes a curved portion and a driving circuit portion, wherein the curved portion is disposed between the second side portion and the driving circuit portion, and wherein a fourth connecting wire is disposed in the curved portion.

[0024] The display device may have: wherein the connection wiring includes a third connection wiring and a fifth connection wiring, wherein n data lines (n is a positive integer) in the main display part are connected to the driver through the third connection wiring, wherein the data voltage transmission line is connected to the driver through the third connection wiring and the fifth connection wiring, and wherein the display device further includes a shielding layer, the shielding layer and the fourth conductive layer are disposed in the same layer, and are disposed between the third connection wiring and the fifth connection wiring.

[0025] The display device may have: a second side portion that bends from the main display portion, wherein the driver includes the bent portion and the driving circuit portion, wherein the bent portion is disposed between the second side portion and the driving circuit portion, and wherein a fifth connection wiring is disposed in the bent portion.

[0026] The display device may have: wherein the connection wiring includes a first connection wiring, a second connection wiring and a fourth connection wiring, wherein n data lines in the main display section are connected to the driver through the first connection wiring or the second connection wiring, and wherein the data voltage transmission line is connected to the driver through the fourth connection wiring.

[0027] The display device may have the following features: at least one of the first connecting wire, the second connecting wire, and the fourth connecting wire intersects with another of the first connecting wire, the second connecting wire, and the fourth connecting wire, and an insulating layer is disposed between them.

[0028] The display device may have: a shielding layer disposed in the same layer as the third conductive layer and located between at least two of the first connecting wire, the second connecting wire and the fourth connecting wire.

[0029] The display device may have: wherein the driver includes a curved portion and a driving circuit portion, wherein the curved portion is disposed between the second side portion and the driving circuit portion, and wherein a fourth connecting wire is disposed between the second side portion and the curved portion.

[0030] The display device may have a second side portion that bends from the main display portion, wherein the driver includes a bent portion and a driving circuit portion, wherein the bent portion is disposed between the second side portion and the driving circuit portion, and wherein a fourth connection wiring is disposed between the bent portion and the driving circuit portion.

[0031] The display device may have: wherein the connection wiring includes a first connection wiring, a second connection wiring and a fourth connection wiring, wherein the driver includes a chip on film, wherein n data lines in the main display portion are connected to the chip on film through the first connection wiring or the second connection wiring, and wherein the data voltage transmission line is connected to the chip on film through the fourth connection wiring.

[0032] The display device according to an embodiment includes: a substrate including a main display portion and a first side portion connected to the main display portion; scan lines and data lines disposed on the substrate; pixels connected to the scan lines and data lines; data voltage transmission lines connected to the data lines; connection wiring connected to the data voltage transmission lines; sub-connection wiring connected to the connection wiring; and a driver connected to the sub-connection wiring, wherein the data lines and data voltage transmission lines are connected to each other at one edge of the first side portion.

[0033] The display device may have the following arrangement: the data lines in the first side portion are arranged in the same order from left to right as the data lines are connected to the driver via sub-connection wiring.

[0034] The display device may have: a connection wire connected to the nth data line (n is a positive integer) and a sub-connection wire connected to the driver.

[0035] The display device may have: wherein the main display portion includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer that are insulated from each other, and wherein the connecting wiring includes one or more of a first connecting wiring disposed in the same layer as the first conductive layer, a second connecting wiring disposed in the same layer as the second conductive layer, a third connecting wiring disposed in the same layer as the third conductive layer and a fourth connecting wiring disposed in the same layer as the fourth conductive layer.

[0036] The display device may have a second side portion that curves from the main display portion, wherein a driver is connected to the second side portion.

[0037] The display device may have: wherein the driver includes a curved portion and a driving circuit portion, and wherein the curved portion is disposed between the second side portion and the driving circuit portion.

[0038] According to the embodiment, the arrangement order of the data lines is the same as the connection order of the driver, which prevents the reduction of the light-emitting area and prevents the increase of the driver manufacturing cost. Attached Figure Description

[0039] Figure 1 This is a perspective view of a display device according to an embodiment.

[0040] Figure 2 yes Figure 1 The plan view of the display device shown.

[0041] Figure 3 The connection between the wiring and the drive circuitry in the first side portion and edge portion of the substrate is shown.

[0042] Figure 4 yes Figure 3 An enlarged view of region A in the image.

[0043] Figure 5 It is intercepted along line V-V'. Figure 4 A sectional view.

[0044] Figure 6 A display device according to an embodiment is shown.

[0045] Figure 7 A display device according to an embodiment is shown.

[0046] Figure 8 yes Figure 7 A magnified view of region B in the image.

[0047] Figure 9 It is a cut along line IX-IX'. Figure 8 A sectional view.

[0048] Figure 10The embodiments shown are related to Figure 8 The same parts.

[0049] Figure 11 It is a cut along line IX-IX'. Figure 10 A sectional view.

[0050] Figure 12 A display device according to an embodiment is shown.

[0051] Figure 13 It is intercepted along line XIII-XIII'. Figure 12 A sectional view.

[0052] Figure 14 The embodiments are shown with respect to Figure 12 The same area shown.

[0053] Figure 15 The embodiments are shown with respect to Figure 12 The same area shown.

[0054] Figure 16 This is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0055] Figure 17 This is a timing diagram of the drive signals of the display device according to an embodiment.

[0056] Figure 18 This is a top plan view of a plurality of adjacent pixels in a display device according to an embodiment.

[0057] Figure 19 It is shown Figure 18 A top-down plan view of one pixel out of a set of pixels.

[0058] Figure 20 It is intercepted along line VIII-VIII'. Figure 19 A sectional view.

[0059] Figure 21 This is a top plan view of the pixels of the display device according to an embodiment.

[0060] Figure 22 It is intercepted along line X-X'. Figure 21 A sectional view. Detailed Implementation

[0061] The inventive concept will be described more fully below with reference to the accompanying drawings, which illustrate embodiments of the inventive concept. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the inventive concept.

[0062] The accompanying drawings and descriptions should be considered illustrative rather than restrictive in nature. The same reference numerals may indicate the same elements throughout the specification.

[0063] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. When an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on said other element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly on" another element, there are no intermediate elements present. The terms "on" or "above" indicate positioning on or below a portion of an object and do not necessarily indicate positioning on the upper side of the object portion based on the direction of gravity.

[0064] Furthermore, unless explicitly stated otherwise, the word "including" and its variations shall be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0065] In the following description, a display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0066] When the term "comprising" and / or variations thereof are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0067] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” may also include the plural forms.

[0068] Although the terms "first," "second," etc., may be used to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. A first element may be named a second element without departing from the teachings of one or more embodiments. Describing an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first," "second," etc., may be used to distinguish elements of different categories or groups. For brevity, the terms "first," "second," etc., may respectively represent "first class (or first group)," "second class (or second group)," etc.

[0069] First, refer to Figures 1 to 3 The following describes a display device according to an embodiment. Figure 1 This is a perspective view of a display device according to an embodiment. Figure 2 yes Figure 1 The diagram shows an unfolded view of the display device.

[0070] like Figure 1 and Figure 2As shown, the display device according to an embodiment includes a substrate 110, which includes a main display portion 111, an edge portion 112 located at the edge of the main display portion 111, a first side portion 115 curved from the edge portion 112, and a second side portion 116 curved from the main display portion 111. The main display portion 111, the edge portion 112, the first side portion 115, and the second side portion 116 may be included in a display area DA.

[0071] The main display portion 111 is located at the center of the base 110 and can be formed in a polygonal shape. The main display portion 111 can also be formed in a quadrilateral shape. Alternatively, the main display portion 111 can be formed in a rectangular shape including two sides extending along a first direction W1 and two sides extending along a second direction W2. The length of the two sides extending along the first direction W1 can be longer than the length of the two sides extending along the second direction W2.

[0072] Edge portion 112 is located at the opposite edge of the main display portion 111. Edge portion 112 may be located at the left and right edges of the main display portion 111. Edge portion 112 extends along a first direction W1. Edge portion 112 may include corner portion 113. Figure 1 In the middle, the corner portion 113 is rounded, but the corner portion 113 can be formed as a right angle (not a rounded) angle of a quadrilateral.

[0073] The first side portion 115 curves from the edge portion 112. In this case, the first side portion 115 extends from a portion of the edge portion 112 (excluding the corner portion 113). Therefore, the side surface is not formed in the portion where the corner portion 113 is located. The first side portion 115 extends along the first direction W1.

[0074] According to an embodiment, the edge portion 112 can be omitted. In this case, the first side portion 115 can be bent from the main display portion 111.

[0075] The second side portion 116 bends from the main display portion 111. The second side portion 116 may bend from the upper and lower edges of the main display portion 111. In an embodiment, the edge portion 112 may be located at the upper and lower edges of the main display portion 111. In this case, the second side portion 116 may bend from the left and right edges of the main display portion 111. The second side portion 116 extends along a second direction W2.

[0076] The second side portion 116 is connected to the driver 420 and can be directly connected to the driver 420. The driver 420 includes a drive circuit portion 400 and a bent portion 410. That is, the driver 420 can be hardware including circuitry. The bent portion 410 is disposed between the second side portion 116 and the drive circuit portion 400. The driver 420 is bent in the bent portion 410, and the drive circuit portion 400 can be located on the rear side of the main display portion 111. According to an embodiment, the bent portion 410 can be omitted.

[0077] exist Figure 1 and Figure 2 In this context, the driver 420 can be provided as a chip-on-film (COF).

[0078] Figure 3 The connection between the wiring in the first side portion 115 and the edge portion 112 of the substrate 110 and the drive circuit portion 400 is shown. Hereinafter, the edge portion 112 and the first side portion 115 may be referred to as the auxiliary display portion AA.

[0079] Multiple data lines 171 are located in the auxiliary display section AA of the substrate 110. The data lines 171 are connected to the drive circuit section 400 via data voltage transmission lines 510. In the accompanying drawings, portions of the wiring that come into contact with each other (such as the contact area between data lines 171 and data voltage transmission lines 510) are indicated by black circles. A bend 410 is provided between the drive circuit section 400 and the substrate 110.

[0080] exist Figure 3 In this context, each data line 171 is numbered. (Refer to...) Figure 3 Multiple data lines 171 are shown in the base 110 of the auxiliary display section AA in the order of 1, 2, ..., n, ... and 2n. That is, the data lines are arranged in the order of 1 at the far left of the auxiliary display section AA and 2n at the far right of the auxiliary display section AA. However, the order in which the data voltage transmission line 510 connects to the curved section 410 is different from the order in which the data lines 171 are arranged in the display area. The order is shown near the wiring.

[0081] To connect the data lines 171 located in the first side portion 115 and the edge portion 112 to the drive circuit portion 400, a data voltage transmission line 510 is required. In the comparative example, to ensure that the arrangement order of the data lines 171 is the same as the order of the data voltage transmission lines 510 connected to the drive circuit portion 400, the contact areas of the data lines 171 and the data voltage transmission lines 510 are largely overlapped with the first side portion 115 and the edge portion 112.

[0082] In other words, in the comparative example, when the first data line in data line 171 contacts the data voltage transmission line 510 at one edge, the second data line in data line 171 needs to contact the data voltage transmission line 510 in a region higher than that contact region (i.e., a region closer to the interior of the display area DA than the contact region of the first data line). When n data lines 171 sequentially contact their respective data voltage transmission lines 510, n contact regions are required, and such contact regions overlap with the display area DA. When the data lines 171 and data voltage transmission lines 510 contact each other in the display area DA, the contact regions are considered as diagonal spots of the display area DA when the display device is driven.

[0083] However, refer to Figure 3 The data line 171 and the data voltage transmission line 510 located in the first side portion 115 and the edge portion 112 are in contact with each other at the edge of the display area DA. That is, the data line 171 and the data voltage transmission line 510 are in contact with each other at the edge of the first side portion 115 and the edge portion 112 without overlapping with the interior of the display area DA, thereby preventing the occurrence of diagonal spots.

[0084] like Figure 3 and Figure 4 As shown, when the data line 171 and the data voltage transmission line 510 contact each other at the edge of the substrate 110, the initial arrangement order of the data line 171 and the order in which it is connected to the bent portion 410 become different from each other. This is because the data voltage transmission line 510 is connected to the data line 171 alternately in sequence. That is, the data voltage transmission line 510 is connected to the first data line 171 to the nth data line 171 in sequence, and the (n+1)th data line 171 to the 2nth data line 171 and the data voltage transmission line 510 connected to the first data line 171 to the nth data line 171 are connected to the connecting wirings 144 and 145 alternately in sequence.

[0085] Because the arrangement order of the data lines 171 and the order in which the data voltage transmission lines 510 are connected to the bend 410 are different from each other, the drive circuit section 400 will also need to change the signal order of each wire, which will increase the manufacturing cost of the display device.

[0086] However, refer to Figure 3 and Figure 4In the display device according to this embodiment, the data voltage transmission line 510 and the bent portion 410 are connected to each other via a first connection wiring 144 and a second connection wiring 145. Then, the bent portion 410 and the drive circuit portion 400 can be connected to each other via a first sub-connection wiring 144S, a second sub-connection wiring 145S, and a fourth connection wiring 511. The data line 171 is connected to the drive circuit portion 400 in the same order as their arrangement. That is, the first data line in the data line 171 (as shown in the example) Figure 3 The leftmost data line 171 of the auxiliary display section AA shown is also the leftmost of all the wiring connected to the drive circuit section 400. Therefore, it is not necessary to change the signal order of the drive circuit section 400, thereby preventing increased manufacturing costs and preventing diagonal spotting.

[0087] The connection wiring can be located in various layers. For example, the connection wiring can be located in the same layer as one of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, which is referred to as the display area DA. In the following text, the wiring located in the same layer as the first conductive layer of the display area DA will be referred to as the first connection wiring 144, the wiring located in the same layer as the second conductive layer will be referred to as the second connection wiring 145, the wiring located in the same layer as the third conductive layer will be referred to as the third connection wiring 178, and the wiring located in the same layer as the fourth conductive layer will be referred to as the fourth connection wiring 511.

[0088] The first, second, third, and fourth conductive layers of the display area DA will be described in detail later.

[0089] Return to reference Figure 3 and Figure 4 The connection wiring of the display device according to this embodiment includes a first connection wiring 144, a second connection wiring 145, and a fourth connection wiring 511. Additionally, sub-connection wiring may include a first sub-connection wiring 144S and a second sub-connection wiring 145S.

[0090] The first connecting wiring 144 and the first sub-connecting wiring 144S can be on the same layer as the first conductive layer of the display area DA (i.e., at the same level as the first conductive layer of the display area DA), and the second connecting wiring 145 can be on the same layer as the second conductive layer of the display area DA. In addition, the fourth connecting wiring 511 can be on the same layer as the data voltage transmission line 510, and can also be on the same layer as the fourth conductive layer of the display area DA.

[0091] Figure 4 Shown separately Figure 3 The region marked A in the middle. Figure 5 It is intercepted along line V-V'. Figure 4A sectional view. (Refer to...) Figure 4 The first sub-connection wiring 144S, which is on the same layer as the first conductive layer, and the second sub-connection wiring 145S, which is on the same layer as the second conductive layer, are arranged alternately. (Refer to...) Figure 4 When n data lines are located in the first side portion 115 and the edge portion 112, each of the n data lines is connected to the first sub-connection line 144S and the second sub-connection line 145S via the fourth connection line 511. That is, the first data line in data line 171 is connected to the first sub-connection line 144S via the fourth connection line 511, and the second data line in data line 171 is connected to the second sub-connection line 145S via the fourth connection line 511. The n lines located in the first side portion 115 and the edge portion 112 are connected to the first sub-connection line 144S and the second sub-connection line 145S via the fourth connection line 511, and lines from the (n+1)th line to the 2nth line are directly connected to the first sub-connection line 144S and the second sub-connection line 145S without going through the fourth connection line 511. Therefore, the arrangement order of the data lines 171 and the signal order of the drive circuit portion 400 become equivalent to each other in the display area DA.

[0092] Because the first sub-connection wiring 144S and the second sub-connection wiring 145S are arranged alternately, the gap between the wirings can be narrowed. In an embodiment of the present invention, only one of the first sub-connection wiring 144S and the second sub-connection wiring 145S may be used.

[0093] Figure 5 It is intercepted along line V-V'. Figure 4 A sectional view. (Refer to...) Figure 5 The buffer layer 120 is located on the substrate 110. The first insulating layer 141 is located in the buffer layer 120. The first sub-connection wiring 144S is located on the first insulating layer 141. The first sub-connection wiring 144S is located in the first conductive layer of the display area DA.

[0094] Next, the second insulating layer 142 is located on the first sub-connection wiring 144S. Then, the second sub-connection wiring 145S is positioned, and the second sub-connection wiring 145S is located on the same layer as the second conductive layer of the display area DA.

[0095] Shielding layer 177 is located on the third insulating layer 160. Shielding layer 177 is on the same layer as the third conductive layer of display area DA. Shielding layer 177 prevents capacitance between connection wires. Fourth insulating layer 162 is located on shielding layer 177.

[0096] The fourth connection wiring 511 is located on the fourth insulating layer 162. The fourth connection wiring 511 is located on the same layer as the fourth conductive layer of the display area DA. The fourth connection wiring 511 can be electrically connected to the first sub-connection wiring 144S and the second sub-connection wiring 145S through contact holes provided in the second insulating layer 142, the third insulating layer 160, the shielding layer 177, and the fourth insulating layer 162. In an embodiment, the shielding layer 177 can be omitted.

[0097] exist Figure 3 In one embodiment, the first sub-connection wiring 144S, the second sub-connection wiring 145S, and the fourth connection wiring 511 are disposed between the bent portion 410 and the drive circuit portion 400.

[0098] Figure 6 A display device according to an embodiment is shown. In such a way... Figure 6 In the display device shown, the first sub-connection wiring 144S, the second sub-connection wiring 145S and the fourth connection wiring 511 are disposed between the display area DA and the curved portion 410.

[0099] Figure 7 A display device according to an embodiment is shown. Figure 7 A data voltage transmission line 510 connected to the first connection wiring 144 is shown. Figure 8 yes Figure 7 A magnified view of region B in the middle.

[0100] Reference Figure 8 The display device according to this embodiment includes a third connection wiring 178 on the same layer as the third conductive layer of the display area DA.

[0101] When the n data lines are located in the first side portion 115 and the edge portion 112, each of the n data lines is connected to the third connection line 178 via the fourth connection line 511. That is, the first data line in the data line 171 is connected to the first and third connection lines 178 in the third connection line 178 via the fourth connection line 511, and the second data line in the data line 171 is connected to the second and third connection lines 178 in the third connection line 178 via the fourth connection line 511. The (n+1)th to the 2nth wirings are directly connected to the third connection line 178 without the fourth connection line 511. Therefore, the arrangement order of the data lines 171 and the signal order of the drive circuit portion 400 can be set to be equivalent to each other in the display area DA.

[0102] Figure 9 It is a cut along line IX-IX'. Figure 8 A sectional view. (Refer to...) Figure 9The buffer layer 120, the first insulating layer 141, the second insulating layer 142 and the third insulating layer 160 are sequentially located on the substrate 110.

[0103] The third connecting wire 178 is located on the third insulating layer 160.

[0104] The fourth insulating layer 162 is located on the third connecting wiring 178. The fourth connecting wiring 511 is located on the fourth insulating layer 162.

[0105] The fourth connecting wire 511 and the third connecting wire 178 are connected to each other through the contact hole of the fourth insulating layer 162.

[0106] Figure 10 It is shown Figure 7 An example of region B in the example. Figure 11 It is a cut along line IX-IX'. Figure 10 A sectional view.

[0107] Reference Figure 10 and Figure 11 The display device includes a shielding layer 515 located on the same layer as the fourth conductive layer.

[0108] The protective layer 180 is located on the shielding layer 515.

[0109] The fifth connection wiring 517 is located on the protective layer 180. The fifth connection wiring 517 is connected to the third connection wiring 178 through contact holes, which are all located in the fourth insulating layer 162, the shielding layer 515, and the protective layer 180. With the shielding layer 515 located in this position, capacitance between the fifth connection wiring 517 and the third connection wiring 178 can be prevented.

[0110] Figure 12 A display device according to an embodiment is shown. Figure 13 It is intercepted along line XIII-XIII'. Figure 12 A cross-sectional view. The display device according to the embodiment arranges the second connecting wire 145 and the fourth connecting wire 511 to cross each other so that the order of the data lines 171 and the connection order of the connecting wires 145 and 511 with the bent portion 410 are the same. Detailed descriptions of identical constituent elements are omitted.

[0111] Reference Figure 12 and Figure 13 In the display device according to this embodiment, the data voltage transmission line 510 is connected to the fourth connection wiring 511, and the data line 171 not connected to the data voltage transmission line 510 is connected to the second connection wiring 145.

[0112] A shielding layer 177, on the same layer as the third conductive layer, is disposed between the fourth connecting wire 511 and the second connecting wire 145. A second insulating layer 142, a third insulating layer 160, and a fourth insulating layer 162 are disposed between the fourth connecting wire 511 and the second connecting wire 145. Figure 12 and Figure 13 As shown, the second connection wiring 145 and the fourth connection wiring 511 align the connection sequence of the data line 171 and the drive circuit section 400, while crossing each other at different layers.

[0113] Figure 14 It shows the relationship with Figure 12 The example shown is of the same region. Figure 14 In the middle, the second connecting wire 145 and the fourth connecting wire 511 are located between the bent portion 410 and the drive circuit portion 400.

[0114] Figure 15 It shows the relationship with Figure 12 The example shown is of the same region. Figure 15 The portion includes a chip-on-film (COF) pad (or "soldering pad") 470 but excludes the bent portion 410 and the drive circuit portion 400.

[0115] The pixels disposed in the base 110 of the display device will be described below.

[0116] In the following text, refer to Figure 16 This will describe a pixel of the display device according to an embodiment. Figure 16 This is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0117] like Figure 16 As shown, the display device according to an embodiment includes a plurality of pixels PX capable of displaying images based on image signals, and a plurality of signal lines 151, 152, 153, 154, 171, and 172. Each pixel PX may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to the plurality of signal lines 151, 152, 153, 154, 171, and 172, a capacitor Cst, and at least one light-emitting diode ED. One pixel PX includes one light-emitting diode ED.

[0118] Signal lines 151, 152, 153, 154, 171, and 172 may include multiple scan lines 151, 152, and 154, multiple control lines 153, multiple data lines 171, and multiple drive voltage lines 172.

[0119] Multiple scan lines 151, 152, and 154 can transmit scan signals GWn, GIn, and GI(n+1). Scan signals GWn, GIn, and GI(n+1) can transmit the gate on-state voltage and gate off-state voltage that enable / disable the transistors T2, T3, T4, and T7 included in pixel PX.

[0120] Scan lines 151, 152, and 154 connected to a pixel PX may include a first scan line 151 transmitting a scan signal GWn, a second scan line 152 transmitting a scan signal GIn with a gate on-state voltage at a timing different from that of the first scan line 151, and a third scan line 154 transmitting a scan signal GI(n+1). The following description will primarily focus on the case where the second scan line 152 transmits the gate on-state voltage at an earlier timing than the first scan line 151. For example, when the scan signal GWn is the nth scan signal Sn (n is a natural number greater than 1), the scan signal GIn may be a previous scan signal such as the (n-1)th scan signal S(n-1), and the scan signal GI(n+1) may be the nth scan signal Sn. In an embodiment, the scan signal GI(n+1) may be a scan signal other than the nth scan signal Sn.

[0121] Control line 153 can transmit a control signal, which can be a light emission control signal EM that controls the light emission of a light-emitting diode ED included in pixel PX. The control signal transmitted by control line 153 can transmit a gate on-state voltage or a gate off-state voltage, and can have a waveform different from the waveform of the scan signal transmitted by scan lines 151, 152 and 154.

[0122] Data line 171 transmits the data signal Dm, and drive voltage line 172 can transmit the drive voltage ELVDD. The data signal Dm can have different voltage levels depending on the input image signal, and the drive voltage ELVDD can have a substantially constant level.

[0123] Transistors T1, T2, T3, T4, T5, T6, and T7 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0124] The first scan line 151 can transmit the scan signal GWn to the second transistor T2 and the third transistor T3, the second scan line 152 can transmit the scan signal GIn to the fourth transistor T4, the third scan line 154 can transmit the scan signal GI(n+1) to the seventh transistor T7, and the control line 153 can transmit the light emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0125] The gate electrode G1 of the first transistor T1 is connected to the first terminal Cst1 of the capacitor Cst through the driving gate node GN. The source electrode S1 of the first transistor T1 is connected to the driving voltage line 172 through the fifth transistor T5, and the drain electrode D1 of the first transistor T1 is electrically connected to the anode of the light-emitting diode ED through the sixth transistor T6. The first transistor T1 can receive the data signal Dm transmitted by the data line 171 according to the switching operation of the second transistor T2, and supply the driving current Id to the light-emitting diode ED.

[0126] The gate electrode G2 of the second transistor T2 is connected to the first scan line 151, the source electrode S2 of the second transistor T2 is connected to the data line 171, and the drain electrode D2 of the second transistor T2 is connected to the drive voltage line 172 via the fifth transistor T5, and is also connected to the source electrode S1 of the first transistor T1. The second transistor T2 is turned on according to the scan signal GWn transmitted through the first scan line 151, thus the data signal Dm transmitted from the data line 171 can be transmitted to the source electrode S1 of the first transistor T1.

[0127] The gate electrode G3 of the third transistor T3 is connected to the first scan line 151. The source electrode S3 of the third transistor T3 is connected to the anode of the light-emitting diode ED via the sixth transistor T6, and is also connected to the drain electrode D1 of the first transistor T1. The drain electrode D3 of the third transistor T3 is connected to the drain electrode D4 of the fourth transistor T4, the first terminal Cst1 of the capacitor Cst, and the gate electrode G1 of the first transistor T1. The third transistor T3 is turned on according to the scan signal GWn transmitted through the first scan line 151. In this way, the third transistor T3 can connect the gate electrode G1 and the drain electrode D1 of the first transistor T1 by connecting the gate electrode G1 and the drain electrode D1 to each other, thus making the first transistor T1 diode connected.

[0128] The gate electrode G4 of the fourth transistor T4 is connected to the second scan line 152, the source electrode S4 of the fourth transistor T4 is connected to the terminal of the initialization voltage Vint, and the drain electrode D4 of the fourth transistor T4 is connected to the first terminal Cst1 of the capacitor Cst and the gate electrode G1 of the first transistor T1 through the drain electrode D3 of the third transistor T3. The fourth transistor T4 is turned on according to the scan signal GIn transmitted through the second scan line 152 and transmits the initialization voltage Vint to the gate electrode G1 of the first transistor T1, so that an initialization operation for initializing the voltage of the gate electrode G1 of the first transistor T1 can be performed.

[0129] The gate electrode G5 of the fifth transistor T5 is connected to the control line 153, the source electrode S5 of the fifth transistor T5 is connected to the drive voltage line 172, and the drain electrode D5 of the fifth transistor T5 is connected to the source electrode S1 of the first transistor T1 and the drain electrode D2 of the second transistor T2.

[0130] The gate electrode G6 of the sixth transistor T6 is connected to control line 153. The source electrode S6 of the sixth transistor T6 is connected to the drain electrode D1 of the first transistor T1 and the source electrode S3 of the third transistor T3. The drain electrode D6 of the sixth transistor T6 is electrically connected to the light-emitting diode ED. The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light-emitting control signal EM transmitted through control line 153. The driving voltage ELVDD can therefore be compensated through the first transistor T1 connected to the diode and transmitted to the light-emitting diode ED.

[0131] The gate electrode G7 of the seventh transistor T7 is connected to the third scan line 154, the source electrode S7 of the seventh transistor T7 is connected to the anode of the light-emitting diode ED, and the drain electrode D7 of the seventh transistor T7 is connected to the terminal of the initialization voltage Vint and the source electrode S4 of the fourth transistor T4. Optionally, the gate electrode G7 of the seventh transistor T7 can be connected to a separate control line (not shown).

[0132] Each of transistors T1, T2, T3, T4, T5, T6, and T7 can be a P-type channel transistor such as PMOS, or an N-type channel transistor.

[0133] As previously described, the first terminal Cst1 of capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the second terminal Cst2 is connected to the drive voltage line 172. The cathode of the light-emitting diode ED can be connected to the terminal of the common voltage ELVSS that transmits the common voltage ELVSS and can therefore receive the common voltage ELVSS.

[0134] The structure of pixel PX according to the embodiments is not limited to Figure 16 The structure shown can be modified in various ways, including the number of transistors and capacitors included in a pixel PX, as well as the connection relationships.

[0135] Reference Figure 17 , with the above Figure 16 Together, the operation of the display device according to the embodiment will be described. Transistors T1, T2, T3, T4, T5, T6, and T7 are shown as P-channel transistors, and their operation during one frame will be described.

[0136] Figure 17 This is a timing diagram of the drive signals of the display device according to an embodiment.

[0137] like Figure 17 As shown, low-level scan signals (..., S(n-2), S(n-1), Sn, ...) can be sequentially applied to multiple first scan lines 151 connected to multiple pixels PX.

[0138] During the initialization period, a low-level scan signal GIn is supplied through the second scan line 152. The scan signal GIn can be, for example, the (n-1)th scan signal S(n-1). Then, the fourth transistor T4 is turned on in response to the low-level scan signal GIn, and the initialization voltage Vint is applied to the gate electrode G1 of the first transistor T1 through the fourth transistor T4, such that the gate electrode G1 of the first transistor T1 is initialized by the initialization voltage Vint.

[0139] Next, during the data programming and compensation period, a low-level scan signal GWn is provided through the first scan line 151, and then the second transistor T2 and the third transistor T3 are turned on in response to the low-level scan signal GWn. The scan signal GWn can be, for example, the nth scan signal Sn. In this case, the first transistor T1 is connected to a diode and forward biased through the turned-on third transistor T3. Then, a compensation voltage Dm+Vth (Vth is negative) is applied to the gate electrode G1 of the first transistor T1. This compensation voltage Dm+Vth (Vth is negative) is the voltage by which the data signal Dm supplied from the data line 171 is reduced by the threshold voltage Vth of the first transistor T1. That is, the gate voltage applied to the gate electrode G1 of the first transistor T1 can be changed to the compensation voltage (Dm+Vth).

[0140] The driving voltage ELVDD and the compensation voltage (Dm+Vth) are applied to the opposite terminals of capacitor Cst, and the charge corresponding to the voltage difference at the opposite terminals of capacitor Cst can be stored in capacitor Cst.

[0141] Next, during the light-emitting period, the light-emitting control signal EM supplied from control line 153 changes from high to low. The light-emitting control signal EM can be changed within a frame after the scan signal GWn is applied to all first scan lines 151. Then, during the light-emitting period, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level light-emitting control signal EM. Subsequently, a drive current Id is generated based on the voltage difference between the gate voltage of the gate electrode G1 of the first transistor T1 and the drive voltage ELVDD, and the drive current Id is supplied to the light-emitting diode ED through the sixth transistor T6, causing the drive current Id to flow to the light-emitting diode ED. During the light-emitting period, the gate-source voltage Vgs of the first transistor T1 is maintained at (Dm+Vth)-ELVDD through capacitor Cst, and according to the current-voltage relationship of the first transistor T1, the drive current Id can be the square of the value obtained by subtracting the threshold voltage from the drive gate-source voltage (i.e., (Dm-ELVDD)). 2 This is proportional to the threshold voltage Vth of the first transistor T1. Therefore, the drive current Id can be determined without considering the threshold voltage Vth of the first transistor T1.

[0142] Simultaneously, during the initialization period, the seventh transistor T7 receives a low-level scan signal GI(n+1) through the third scan line 154 and is thus turned on. The scan signal GI(n+1) can be the nth scan signal Sn. In this case, the seventh transistor T7 can be turned on simultaneously with the second transistor T2 and the third transistor T3. A portion of the drive current Id can pass through the turned-on seventh transistor T7 as a bypass current Ibp, and the remaining portion of the drive current Id can flow through the light-emitting diode ED as a current Ied.

[0143] Reference Figures 18 to 20 , with the above Figure 16 and Figure 17 Together, the structure of a portion of the display device according to the embodiment will be described in detail.

[0144] Figure 18 This is a top plan view of a plurality of adjacent pixels in a display device according to an embodiment. Figure 19 It is shown Figure 18 A top-view plan view of one pixel out of a set of pixels. Figure 20 It is intercepted along line VIII-VIII'. Figure 19 A sectional view. Figures 18 to 20 The first side portion of the base 110 is shown. Figure 1 115) and edge parts ( Figure 1 The pixels in 112).

[0145] The plurality of pixels PX included in the display device according to the embodiment can display a specific color. For example, the plurality of pixels PX may include a red pixel R that displays red, a green pixel G that displays green, and a blue pixel B that displays blue. Figure 18 The diagram shows a red pixel R, a green pixel G, and a blue pixel B that are adjacent to each other. In an embodiment, at least one of the red pixel R, green pixel G, and blue pixel B can be a different color. Additionally, pixels that can be colored other than red, green, and blue may be included.

[0146] The display device according to an embodiment may include a first conductive layer, which includes a first scan line 151 for transmitting a scan signal GWn, a second scan line 152 for transmitting a scan signal GIn, a third scan line 154 for transmitting a scan signal GI(n+1), and a control line 153 for transmitting a light emission control signal EM. Additionally, the first conductive layer may include, for example, Figure 3 The first connection wiring 144 is shown. The first conductive layer may be disposed on one side of the substrate 110 in cross-section.

[0147] The substrate 110 may include inorganic or organic insulating materials such as glass or plastic, and may have varying degrees of flexibility.

[0148] Multiple scan lines 151, 152, and 154, along with a control line 153, can extend primarily along the second direction W2 in the plane. The first scan line 151 can be positioned in the plane between the second scan line 152 and the control line 153. When the display device is viewed as a whole, the third scan line 154 is substantially identical to the second scan line 152, and the third scan line 154 can transmit a scan signal GI(n+1) (as the next scan signal following the scan signal GIn transmitted by the second scan line 152). As previously described, when the first scan line 151 transmits the nth scan signal Sn, the third scan line 154 can also transmit the nth scan signal Sn.

[0149] The display device according to an embodiment may further include a second conductive layer, the second conductive layer including a storage line 156 and an initialization voltage line 159. Additionally, the second conductive layer may include, for example, Figure 3 The second connection wiring 145 is shown. The second conductive layer is located on a different layer than the first conductive layer. For example, in a cross-sectional view, the second conductive layer may be located directly on the first conductive layer.

[0150] The storage line 156 and the initialization voltage line 159 may extend primarily along the second direction W2 in the plane. The storage line 156 may be located in the plane between the first scan line 151 and the control line 153, and may include an extension portion 157 located in each of pixels R, G, and B. The extension portion 157 is connected to the drive voltage line 172 via a contact hole 68, and thus can receive the drive voltage ELVDD. A storage opening 51 is formed in the extension portion 157.

[0151] The initialization voltage line 159 transmits the initialization voltage Vint, and can be positioned on the plane between the third scan line 154 and the control line 153.

[0152] The display device according to the embodiment may further include a third conductive layer, which includes a data line 171 for transmitting data signal Dm, a drive voltage line 172 for transmitting drive voltage ELVDD, etc. The third conductive layer may also include, Figure 5 The shielding layer 177 shown and / or as Figure 9 or Figure 11 The third connection wiring 178 is shown. The third conductive layer is disposed on a different layer than the first and second conductive layers in cross-section. For example, in the cross-sectional view, the third conductive layer may be located on the second conductive layer.

[0153] The data line 171 and the drive voltage line 172 can extend primarily along the first direction W1 in the plane and can intersect with multiple scan lines 151, 152 and 154, control line 153, initialization voltage line 159 and storage line 156.

[0154] Each of pixels R, G, and B may include multiple transistors T1, T2, T3, T4, T5, T6, and T7 connected to scan lines 151, 152, and 154, control line 153, data line 171, and drive voltage line 172, capacitor Cst, and light-emitting diode ED.

[0155] For each of pixels R, G, and B, the channel of each of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 can be formed within an active pattern 130, and the active pattern 130 can be bent in various shapes. The active pattern 130 may include semiconductor materials such as polysilicon, oxide semiconductors, etc.

[0156] In the cross-sectional view, the active pattern 130 may be located between the substrate 110 and the first conductive layer.

[0157] The active pattern 130 may include channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g, respectively forming the channels of each transistor T1, T2, T3, T4, T5, T6, and T7, as well as conductive regions. Specifically, the third transistor T3 and the fourth transistor T4 may have a dual-gate structure. The third transistor T3 may include two channel regions 131c_1 and 131c_2, and the fourth transistor T4 may include two channel regions 131d_1 and 131d_2.

[0158] The conductive regions of the active pattern 130 are disposed on opposite sides of each of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g, and have a higher carrier concentration than each of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g. The majority of the active pattern 130 may be conductive regions, except for the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g. A pair of conductive regions located on opposite sides of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g of each of transistors T1, T2, T3, T4, T5, T6, and T7 are the source and drain regions of the corresponding transistors T1, T2, T3, T4, T5, T6, and T7, and can be used as the source electrode and drain electrode, respectively.

[0159] The first transistor T1 includes a channel region 131a and a driving gate electrode 155a superimposed on the channel region 131a on a plane. The first transistor T1 also includes a source region 136a and a drain region 137a located on the opposite side of the channel region 131a as conductive regions of an active pattern 130.

[0160] The channel region 131a of the first transistor T1 can be bent at least once. For example, the channel region 131a can have a tortuous shape or a zigzag shape.

[0161] Source region 136a and drain region 137a can be connected to the opposite side of channel region 131a in the plane.

[0162] The driving gate electrode 155a may be included in the first conductive layer and may be connected to the connection member 174 via the contact hole 61 and the storage opening 51. The storage opening 51 surrounds the contact hole 61. The connection member 174 may be included in the third conductive layer. The connection member 174 may extend in a direction parallel to the extension direction of the data line 171. The connection member 174, together with the driving gate electrode 155a, corresponds to... Figure 16 The driving gate node GN is shown in the circuit diagram.

[0163] The second transistor T2 includes a channel region 131b and a gate electrode 155b superimposed on the channel region 131b in a plane. The second transistor T2 also includes a source region 136b and a drain region 137b located on opposite sides of the channel region 131b as conductive regions of an active pattern 130. The gate electrode 155b is part of a first scan line 151. Referring to the first scan line 151, the source region 136b is disposed in the upper part of the plane and connected to the channel region 131b, and is connected to a data line 171 through a contact hole 62. Referring to the first scan line 151, the drain region 137b is disposed in the lower part of the plane and connected to the channel region 131b, and is connected to the source region 136a of the first transistor T1.

[0164] The third transistor T3 can be formed by two parts to prevent leakage current. That is, the third transistor T3 can include an upper third transistor T3_1 and a lower third transistor T3_2 that are adjacent to and in contact with each other.

[0165] The upper third transistor T3_1 includes a channel region 131c_1 superimposed on the first scan line 151 on a plane, a source region 136c_1 and a drain region 137c_1 located on the opposite side of the channel region 131c_1 as conductive regions of the active pattern 130, and a gate electrode 155c_1 superimposed on the channel region 131c_1. The gate electrode 155c_1 may be part of a protrusion of the first scan line 151. Referring to the first scan line 151, the drain region 137c_1 is located in the upper part and is connected to the connecting member 174 through the contact hole 63.

[0166] The lower third transistor T3_2 includes a channel region 131c_2 superimposed on the first scan line 151 on a plane and a gate electrode 155c_2 superimposed on the channel region 131c_2. The lower third transistor T3_2 also includes a channel region 131c_2 superimposed on the first scan line 151 on a plane, a source region 136c_2 and a drain region 137c_2 located on the opposite side of the channel region 131c_2 as conductive regions of the active pattern 130. The gate electrode 155c_2 is part of the first scan line 151. The source region 136c_2 of the lower third transistor T3_2 is connected to the drain region 137a of the first transistor T1, and the drain region 137c_2 is connected to the source region 136c_1 of the upper third transistor T3_1.

[0167] The fourth transistor T4 can also be formed by two parts to prevent leakage current. That is, the fourth transistor T4 can include a left fourth transistor T4_1 and a right fourth transistor T4_2 that are adjacent to and in contact with each other.

[0168] The left-side fourth transistor T4_1 includes a channel region 131d_1 superimposed on the second scan line 152 on a plane, and a gate electrode 155d_1 superimposed on the channel region 131d_1. The left-side fourth transistor T4_1 also includes a source region 136d_1 and a drain region 137d_1 located on the opposite side of the channel region 131d_1, forming a conductive region of the active pattern 130. The gate electrode 155d_1 is part of the second scan line 152. Referring to the second scan line 152, the drain region 137d_1 is located in the lower part and is connected to the connection member 174 through a contact hole 63.

[0169] The right-side fourth transistor T4_2 includes a channel region 131d_2 superimposed on the second scan line 152 on a plane, and a gate electrode 155d_2 superimposed on the channel region 131d_2. The right-side fourth transistor T4_2 also includes a source region 136d_2 and a drain region 137d_2 located on the opposite side of the channel region 131d_2, forming a conductive region of the active pattern 130. The gate electrode 155d_2 is part of the second scan line 152. The drain region 137d_2 is connected to the source region 136d_1 of the left-side fourth transistor T4_1, and the source region 136d_2 is connected to the connecting member 175 through a contact hole 65.

[0170] In the cross-sectional view, the connecting member 175 may be included in the third conductive layer. The connecting member 175 may be electrically connected to the initialization voltage line 159 through the contact hole 64.

[0171] The fifth transistor T5 includes a channel region 131e and a gate electrode 155e superimposed on the channel region 131e. The fifth transistor T5 also includes a source region 136e and a drain region 137e located on opposite sides of the channel region 131e as conductive regions of an active pattern 130. The gate electrode 155e is part of a control line 153. Referring to the control line 153, the source region 136e is located in the lower part of the plane and connected to the channel region 131e, and is connected to the drive voltage line 172 through a contact hole 67. Referring to the control line 153, the drain region 137e is located in the upper part of the plane and connected to the channel region 131e, and is connected to the source region 136a of the first transistor T1.

[0172] The sixth transistor T6 includes a channel region 131f and a gate electrode 155f superimposed on the channel region 131f. The sixth transistor T6 also includes a source region 136f and a drain region 137f located on opposite sides of the channel region 131f as conductive regions of an active pattern 130. The gate electrode 155f is part of a control line 153. Referring to the control line 153, the source region 136f is disposed in the upper portion of a plane and connected to the channel region 131f, and connected to the drain region 137a of the first transistor T1. Referring to the control line 153, the drain region 137f is disposed in the lower portion of a plane and connected to the channel region 131f, and connected to a connection member 179 via a contact hole 69. The connection member 179 may be included in a third conductive layer in cross-section.

[0173] The seventh transistor T7 includes a channel region 131g and a gate electrode 155g superimposed on the channel region 131g. The seventh transistor T7 also includes a source region 136g and a drain region 137g located on the opposite side of the channel region 131g as conductive regions of an active pattern 130. The gate electrode 155g is part of a third scan line 154. Referring to the third scan line 154, the source region 136g is disposed in the upper part of the plane and connected to the channel region 131g, and connected to the drain region 137f of the sixth transistor T6. Referring to the third scan line 154, the drain region 137g is disposed in the lower part of the plane and can receive the initialization voltage Vint by connecting to the connection member 175 via a contact hole 65.

[0174] The capacitor Cst may include a drive gate electrode 155a and an extension 157 of the storage line 156 stacked on a plane as two terminals. The capacitor Cst can maintain a voltage corresponding to the voltage difference between the extension 157 of the storage line 156 and the drive gate electrode 155a receiving the drive voltage ELVDD. The extension 157 of the storage line 156 may have a wider area on the plane than the drive gate electrode 155a and may cover the entire area of ​​the corresponding drive gate electrode 155a.

[0175] The second conductive layer may further include a shielding pattern 158 superimposed on the data line 171. The shielding pattern 158 is connected to the drive voltage line 172 via contact holes 66 and can therefore receive the drive voltage ELVDD. The shielding pattern 158 shields the drive gate node GN and the data line 171 to prevent voltage variations in the drive gate node GN due to changes in the data signal Dm. The shielding pattern 158 may be omitted.

[0176] The display device according to an embodiment may further include a fourth conductive layer, which includes a data voltage transmission line 510 for transmitting a data signal Dm. The fourth conductive layer is located on a different layer than the first, second, and third conductive layers. For example, the fourth conductive layer may be located on the third conductive layer. The fourth conductive layer may include a fourth connection wiring 511 (see...). Figure 4 ).

[0177] At least a portion of the data voltage transmission line 510 located in the first side portion 115 and the edge portion 112 of the substrate 110 may extend in the plane along the second direction W2.

[0178] The end of the data voltage transmission line 510 can be stacked with the data line 171. The data voltage transmission line 510 can transmit the data signal Dm by connecting to the data line 171 via the contact hole 610. The data voltage transmission line 510 is disposed on a different layer than the data line 171.

[0179] The data line 171 located in the first side portion 115 and the edge portion 112 of the substrate 110 is not directly connected to the drive circuit portion 400. Since the data voltage transmission line 510 connects the data line 171 located in the first side portion 115 and the edge portion 112 of the substrate 110 to the drive circuit portion 400, the data voltage transmission line 510 can transmit the data signal Dm.

[0180] The display device according to an embodiment may further include a fifth conductive layer, which includes a plurality of pixel electrodes 191a, 191b, and 191c and a pixel conductive pattern 192. The fifth conductive layer is disposed on a layer different from the first, second, third, and fourth conductive layers in cross-section. For example, the fifth conductive layer may be located on the fourth conductive layer in cross-section.

[0181] Multiple pixel electrodes 191a, 191b, and 191c can be arranged in a PenTile matrix. For example, pixel electrodes 191a of red pixel R and pixel electrodes 191c of blue pixel B can be arranged alternately in the horizontal direction, pixel electrodes 191a of red pixel R and pixel electrodes 191b of green pixel G can be arranged alternately in the diagonal direction, and pixel electrodes 191c of blue pixel B and pixel electrodes 191b of green pixel G can be arranged alternately in another diagonal direction.

[0182] Each of the pixel electrodes 191a, 191b and 191c can be connected to the connection member 179 through the contact hole 89 and can therefore receive voltage.

[0183] The pixel conductive pattern 192 may be curved along the edges of adjacent pixel electrodes 191a, 191b, and 191c, and may include alternately arranged straight portions 192a, 192b, and 192c and diagonal portions 193. The straight portions 192a, 192b, and 192c may extend primarily parallel to scan lines 151, 152, and 154, and the diagonal portion 193 may extend obliquely relative to the extension direction of the straight portions 192a, 192b, and 192c. The straight portion 192a is adjacent to pixel electrode 191a at the top of pixel electrode 191a of the red pixel R, the straight portion 192b is adjacent to pixel electrode 191b at the top of pixel electrode 191b of the green pixel G, and the straight portion 192c is adjacent to pixel electrode 191c at the top of pixel electrode 191c of the blue pixel B.

[0184] The pixel conductive pattern 192 can transmit the initialization voltage Vint.

[0185] The cross-sectional structure of the display device according to the embodiment will be described in further detail below.

[0186] Buffer layer 120 may be located on substrate 110. Buffer layer 120 prevents impurities from migrating from substrate 110 to layers above buffer layer 120 (specifically, active pattern 130), thereby improving the characteristics of active pattern 130 and relieving stress. Buffer layer 120 may include materials such as silicon nitride (SiN). x ) or silicon dioxide (SiO) x Inorganic insulating materials and / or organic insulating materials. At least a portion of the buffer layer 120 may be omitted.

[0187] The active pattern 130 is located on the buffer layer 120, and the first insulating layer 141 is located on the active pattern 130.

[0188] The first conductive layer may be located on the first insulating layer 141. The first conductive layer may include metals such as copper (Cu), aluminum (Al), molybdenum (Mo), and alloys thereof.

[0189] The second insulating layer 142 may be located on the first conductive layer and the first insulating layer 141.

[0190] The second conductive layer may be located on the second insulating layer 142. The second conductive layer may include metals such as copper (Cu), aluminum (Al), molybdenum (Mo), and alloys thereof.

[0191] The third insulating layer 160 may be located on the second conductive layer and the second insulating layer 142.

[0192] At least one of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may include materials such as silicon nitride (SiN).x ), silicon dioxide (SiO) x Inorganic insulating materials and / or organic insulating materials, etc.

[0193] Contact holes 61 located on the drive gate electrode 155a can be formed in the second insulating layer 142 and the third insulating layer 160. Contact holes 62 located on the source electrode 136b of the second transistor T2, contact holes 63 located on the drain region 137c_1 of the upper third transistor T3_1 or the drain region 137d_1 of the left fourth transistor T4_1, contact holes 64 located on the initialization voltage line 159, contact holes 65 located on the source region 136d_2 of the right fourth transistor T4_2 or the drain region 137g of the seventh transistor T7, contact holes 66 located on the shielding pattern 158, contact holes 67 located on the source region 136e of the fifth transistor T5, contact holes 68 located on the extension portion 157 of the storage line 156, and contact holes 69 located on the drain region 137f of the sixth transistor T6.

[0194] The third conductive layer may be located on the third insulating layer 160. The third conductive layer may include metals such as copper (Cu), aluminum (Al), molybdenum (Mo), and alloys thereof.

[0195] While the second insulating layer 142 is disposed between the extension portion 157 of the storage line 156 and the drive gate electrode 155a, the extension portion 157 of the storage line 156 can form a capacitor Cst by being stacked with the drive gate electrode 155a.

[0196] The fourth insulating layer 162 may be located on the third conductive layer and the third insulating layer 160.

[0197] The fourth insulating layer 162 may include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x Inorganic insulating materials and / or organic insulating materials, etc.

[0198] The contact hole 610 located on the data line 171 can be formed in the fourth insulating layer 162.

[0199] The fourth conductive layer may be located on the fourth insulating layer 162. The fourth conductive layer may include metals such as copper (Cu), aluminum (Al), molybdenum (Mo), and alloys thereof.

[0200] The protective layer 180 is located on the fourth conductive layer and the fourth insulating layer 162. That is, a portion of the protective layer 180 is on the fourth conductive layer including the data voltage transmission line 510, and a portion of the protective layer 180 is flush with a portion of the drive voltage transmission line 520 (i.e., on the same layer as a portion of the drive voltage transmission line 520). The protective layer 180 may include an organic insulating material such as polyacrylic acid resin, polyimide resin, etc., and the protective layer 180 may have a substantially flat top surface. The protective layer 180 may include contact holes 89 provided on the connecting member 179.

[0201] The aforementioned fifth conductive layer may be located on the protective layer 180.

[0202] A pixel defining layer (PDL) 350 may be disposed on the protective layer 180 and the fifth conductive layer. The pixel defining layer 350 includes openings 351 located on pixel electrodes 191a, 191b and 191c.

[0203] The emitting layer 370 is located on pixel electrodes 191a, 191b, and 191c. The emitting layer 370 may be disposed inside the opening 351. The emitting layer 370 may include organic or inorganic light-emitting materials.

[0204] The common electrode 270 is located on the emitter layer 370. The common electrode 270 is also formed on the pixel defining layer 350, allowing it to extend across multiple pixel PXs.

[0205] Pixel electrodes 191a, 191b and 191c, an emitter layer 370 and a common electrode 270 form a light-emitting diode ED.

[0206] An encapsulation layer (not shown) protecting the light-emitting diode ED may be further disposed on the common electrode 270. The encapsulation layer may include alternately stacked inorganic and organic layers.

[0207] and Figure 16 and Figure 17 Refer to together Figure 21 and Figure 22 The structure of another area of ​​the display device according to the embodiment will be described in further detail.

[0208] Figure 21 This is a top plan view of the pixels of the display device according to an embodiment, and Figure 22 It is intercepted along line X-X'. Figure 21 A sectional view. Figure 21 and Figure 22 The main display portion located on the substrate 110 is shown. Figure 1 The pixels in 111).

[0209] The display device according to the embodiment includes a plurality of signal lines 151, 152, 153, 154, 171 and 172 disposed on a substrate 110, and transistors T1, T2, T3, T4, T5, T6 and T7.

[0210] The display device according to this embodiment may further include a drive voltage transmission line 520 for transmitting the drive voltage ELVDD. The drive voltage transmission line 520 may be located in the main display portion of the substrate 110. Figure 1 On (111). The driving voltage transmission line 520 may be located in the fourth conductive layer. The driving voltage transmission line 520 may be located on the same layer as the data voltage transmission line 510.

[0211] The drive voltage transmission line 520 may extend primarily along the first direction W1 in the plane. The drive voltage transmission line 520 may extend parallel to the drive voltage line 172.

[0212] The drive voltage transmission line 520 can be stacked with the drive voltage line 172. The drive voltage transmission line 520 is located in a different layer than the drive voltage line 172. The drive voltage transmission line 520 can be located on the fourth insulating layer 162. A contact hole 620 located on the drive voltage line 172 can be formed in the fourth insulating layer 162. The drive voltage transmission line 520 is connected to the drive voltage line 172 through the contact hole 620, and thus transmits the drive voltage ELVDD. The drive voltage transmission line 520 can reduce the resistance of the drive voltage line 172 by connecting to the drive voltage line 172.

[0213] Although the inventive concept has been described in conjunction with embodiments now considered practical, it will be understood that the inventive concept is not limited to the disclosed embodiments. Rather, the inventive concept is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device comprising: a substrate including a main display portion and a first side portion connected to the main display portion; scan lines and data lines provided on the substrate, the data lines extending in a first direction and including 1st to nth data lines arranged in a second direction in order, where n is a positive integer; pixels connected to the scan lines and the data lines; data voltage transmission lines including 1st to nth data voltage transmission lines connected to the 1st to nth data lines, respectively, in order; a connection wiring; a sub-connection wiring connected to the connection wiring; and a driver connected to the sub-connection wiring, wherein the data lines and the data voltage transmission lines are connected to each other at one edge of the first side portion, wherein the 1st to nth data voltage transmission lines extend from the one edge in the second direction to the main display portion in order, wherein the nth+1 to 2nth data lines are connected to the connection wiring in order, alternately with the nth to 1st data voltage transmission lines connected to the nth to 1st data lines, respectively, and wherein the arrangement order of the data lines connected to the connection wiring is the same as the arrangement order of the sub-connection wirings connected to the connection wiring.

2. The display device according to claim 1, wherein The connection wiring connected to the nth data line among the data lines is connected to the nth sub-connection wiring among the sub-connection wirings connected to the driver. 3.The display device according to claim 1, the display device comprising a second side portion bent from the main display portion, wherein the driver being connected to the second side portion.

4. The display device according to claim 1, wherein The main display portion includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer insulated from each other, wherein the connection wiring includes at least one of a first connection wiring provided in the same layer as the first conductive layer, a second connection wiring provided in the same layer as the second conductive layer, a third connection wiring provided in the same layer as the third conductive layer, and a fourth connection wiring provided in the same layer as the fourth conductive layer. 5.The display device according to claim 4, the display device further comprising an edge portion provided between the main display portion and the first side portion, wherein when n data lines are provided between the first side portion and the edge portion, one edge of each of the data voltage transmission lines connected to the n data lines in the first side portion and the edge portion is located between n data lines in the main display portion adjacent to the edge portion, respectively.

6. The display device of claim 5, wherein, The data lines are connected to a driver through a first connection wiring, and wherein the data voltage transmission lines are connected to the driver through a first sub-connection wiring and a fourth connection wiring. 7.The display device according to claim 6, the display device further comprising contact holes formed in a plurality of insulating layers, wherein the plurality of insulating layers are provided between the first sub-connection wiring and the fourth connection wiring, and The first sub-connection wiring and the fourth connection wiring are connected through the contact hole.

8. The display device of claim 6, wherein, The first connection wiring is positioned alternately in sequence. 9.The display device according to claim 6, further comprising a shield layer disposed between the first sub-connection wiring and the fourth connection wiring, and disposed in the same layer as the third conductive layer.

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