Display panel and organic light emitting diode display device including the same

Abstract

A display panel and an organic light emitting diode (OLED) display device including the display panel are provided. The organic light emitting diode display device includes a first power supply circuit, a display panel, and a scan driver, wherein the first power supply circuit is configured to generate a pixel driving voltage, the display panel is configured to receive the pixel driving voltage from the first power supply circuit and includes a plurality of pixels each configured to emit light based on the pixel driving voltage, and the scan driver is configured to receive the pixel driving voltage from the display panel and provide a scan signal to the plurality of pixels based on the pixel driving voltage.

Description

Technical Field

[0001] The present disclosure relates generally to display devices, and more particularly, to organic light emitting diode (OLED) display devices. Background Art

[0002] The scan driver of the OLED display device may receive a gate-on voltage from a power supply circuit through a single gate-on voltage line, and may output the gate-on voltage as a scan signal. However, due to a voltage drop (e.g., IR drop) at the single gate-on voltage line, the gate-on voltage may decrease as the distance from the power supply circuit increases. Accordingly, the scan signal output from the scan driver may not have a consistent voltage level, and therefore, the display quality of the OLED display device may be reduced. In addition, as the size of the display panel of the OLED display device increases, the voltage level difference between the scan signal at a position close to the power supply circuit and the scan signal at a position far from the power supply circuit may increase, and therefore, the display quality of the OLED display device may be further reduced. Summary of the invention

[0003] Exemplary embodiments of the present disclosure provide an organic light emitting diode (OLED) display device capable of maintaining a substantially uniform scan signal voltage.

[0004] According to an exemplary embodiment, an OLED display device is provided, which includes a first power supply circuit, a display panel and a scan driver, wherein the first power supply circuit is configured to generate a pixel driving voltage, the display panel is configured to receive the pixel driving voltage from the first power supply circuit and includes a plurality of pixels each configured to emit light based on the pixel driving voltage, and the scan driver is configured to receive the pixel driving voltage from the display panel and is configured to provide a scan signal to the plurality of pixels based on the pixel driving voltage.

[0005] In an exemplary embodiment, the display panel may further include a power line for transmitting a pixel driving voltage to the plurality of pixels. The scan driver may receive the pixel driving voltage from the first power supply circuit through the power line of the display panel.

[0006] In an exemplary embodiment, the power lines of the display panel may have a grid or mesh structure.

[0007] In an exemplary embodiment, each of the plurality of pixels may include a switching transistor, a storage capacitor, a driving transistor, and an OLED, wherein the switching transistor is configured to transmit a data voltage in response to a pixel driving voltage provided from a scan driver, the storage capacitor is configured to store the data voltage transmitted through the switching transistor, the driving transistor is coupled to a power line and configured to generate a driving current corresponding to the data voltage stored in the storage capacitor based on the pixel driving voltage provided through the power line, and the OLED is configured to emit light based on the driving current.

[0008] In an exemplary embodiment, the OLED display device may further include a second power supply circuit configured to generate a gate-off voltage. The scan driver may also receive the gate-off voltage from the second power supply circuit, may output the pixel driving voltage as a scan signal having an on-level, and may output the gate-off voltage as a scan signal having an off-level.

[0009] In an exemplary embodiment, the OLED display device may further include a controller configured to control the scan driver by providing a scan start signal and a scan clock signal to the scan driver.

[0010] In an exemplary embodiment, the scan driver may include a shift register and an output buffer circuit, wherein the shift register is configured to sequentially generate an internal scan signal by shifting a scan start signal in response to a scan clock signal, and the output buffer circuit is configured to receive a pixel drive voltage from a first power supply circuit and also receive a gate turn-off voltage from a second power supply circuit, output the pixel drive voltage as a scan signal with an on-level in response to the internal scan signal, and output the gate turn-off voltage as a scan signal with an off-level.

[0011] In an exemplary embodiment, the second power supply circuit may further generate a digital high level power supply voltage and a digital low level power supply voltage. The shift register may operate based on the digital high level power supply voltage and the digital low level power supply voltage received from the second power supply circuit.

[0012] In an exemplary embodiment, the scan driver may further include a level shift circuit, wherein the level shift circuit is configured to receive a pixel driving voltage from the first power supply circuit to increase a voltage level of an internal scan signal output from the shift register based on the pixel driving voltage, and provide the internal scan signal with the increased voltage level to the output buffer circuit.

[0013] In an exemplary embodiment, the display panel may further include a power line for transmitting a pixel driving voltage to a plurality of pixels. The first power supply circuit may apply the pixel driving voltage to the power line of the display panel through the first power supply line. The scan driver may receive the pixel driving voltage from the first power supply circuit through the first power supply line and the power line of the display panel.

[0014] In an exemplary embodiment, the OLED display device may further include a source driver, a first source film, a first source plate, a first flexible film, a control board, a second flexible film, and a power board, wherein the source driver is configured to provide a data voltage to a plurality of pixels, the first source film is coupled to the display panel, the source driver is arranged on the first source film, the first source plate is coupled to the first source film, the first flexible film is coupled to the first source plate, the control board is coupled to the first flexible film, the second flexible film is coupled to the control board, and the power board is coupled to the second flexible film, and the first power circuit is arranged on the power board. The first power line may be formed on the power board, the second flexible film, the control board, the first flexible film, the first source plate, and the first source film.

[0015] In an exemplary embodiment, the first source film may be coupled to a first side of the display panel. The first power circuit may apply a pixel driving voltage to a power line at the first side of the display panel through a first power line, and may also apply a pixel driving voltage to the power line at a second side of the display panel opposite to the first side through a second power line.

[0016] In an exemplary embodiment, the OLED display device may further include a second source film, a second source plate, and a third flexible film, wherein the second source film is coupled to the second side of the display panel, the source driver is not disposed on the second source film, the second source plate is coupled to the second source film, and the third flexible film is coupled to the second source plate and the control board. The second power line may be coupled to the first power line on the control board and may be formed on the third flexible film, the second source plate, and the second source film.

[0017] According to an exemplary embodiment, an OLED display device is provided, the OLED display device including a display panel, a source driver, a source film, a source plate, a first flexible film, a control board, a second flexible film, a first power supply circuit, a power board, a power line, and a scan driver, wherein the display panel includes a plurality of pixels and a power line for transmitting a pixel driving voltage to the plurality of pixels, the source driver is configured to provide a data voltage to the plurality of pixels, the source film is coupled to the display panel, the source driver is arranged on the source film, the source plate is coupled to the source film, the first flexible film is coupled to the source plate, the control board is coupled to the first flexible film, the second flexible film is coupled to the control board, the first power supply circuit is configured to generate a pixel driving voltage, the power board is coupled to the second flexible film, the first power supply circuit is arranged on the power board, the power line is formed on the power board, the second flexible film, the control board, the first flexible film, the source plate, and the source film and configured to apply the pixel driving voltage generated by the first power supply circuit to the power line of the display panel, and the scan driver is configured to receive the pixel driving voltage from the first power supply circuit through the power line and the power line of the display panel and provide the pixel driving voltage as a scan signal to the plurality of pixels.

[0018] In an exemplary embodiment, the OLED display device may further include a scanning film coupled to the display panel. The scanning driver may be implemented as a scanning integrated circuit disposed on the scanning film.

[0019] In an exemplary embodiment, the scan driver may be integrated in a peripheral portion of the display panel.

[0020] In an exemplary embodiment, the OLED display device may further include a second power supply circuit disposed on the control board and configured to generate a gate-off voltage. The scan driver may also receive the gate-off voltage from the second power supply circuit, may output the pixel driving voltage as a scan signal having an on-level, and may output the gate-off voltage as a scan signal having an off-level.

[0021] According to an exemplary embodiment, an OLED display device is provided, the OLED display device including a display panel, a source driver, a first source film, a first source plate, a first flexible film, a second flexible film, a control board, a first power circuit, a power board, a first power line, a second source film, a second source plate, a third flexible film, a second power line, and a scan driver, wherein the display panel includes a plurality of pixels and a power line for transmitting a pixel driving voltage to the plurality of pixels, the source driver is configured to provide a data voltage to the plurality of pixels, the first source film is coupled to a first side of the display panel, the source driver is arranged on the first source film, the first source plate is coupled to the first source film, the first flexible film is coupled to the first source plate, the control board is coupled to the first flexible film, the second flexible film is coupled to the control board, the first power circuit is configured to generate a pixel driving voltage, the power board is coupled to the second flexible film, the first power circuit is arranged on the power board, the first power line A display panel is formed on the power board, the second flexible film, the control board, the first flexible film, the first source plate and the first source film and is configured to apply a pixel driving voltage to the power line at a first side of the display panel, the second source film is connected to a second side of the display panel opposite to the first side, the source driver is not arranged on the second source film, the second source plate is connected to the second source film, the third flexible film connects the second source plate and the control board, the second power line is connected to the first power line on the control board, the second power line is formed on the third flexible film, the second source plate and the second source film and is configured to apply a pixel driving voltage to the power line at the second side of the display panel, and the scan driver is configured to receive the pixel driving voltage from the first power circuit through the first power line and the power line of the display panel, and also receive the pixel driving voltage from the first power circuit through the second power line and the power line of the display panel, and provide the pixel driving voltage as a scan signal to multiple pixels.

[0022] In an exemplary embodiment, the OLED display device may further include a scanning film coupled to the display panel. The scanning driver may be implemented as a scanning integrated circuit disposed on the scanning film.

[0023] In an exemplary embodiment, the scan driver may be integrated in a peripheral portion of the display panel.

[0024] As described above, in the OLED display device, for example, the scan driver may receive a pixel driving voltage provided to a plurality of pixels, and may provide the pixel driving voltage as a scan signal to the plurality of pixels. Accordingly, a pixel driving voltage having a relatively small voltage drop may be used to replace a gate turn-on voltage having a relatively large voltage drop in the scan driver, and the number of lines (or wires) and the border width of the OLED display device may be reduced.

[0025] According to an exemplary embodiment, a display panel is provided, which includes a power line, a plurality of pixels, and at least one scanning power line, wherein the power line has at least one power supply terminal and a plurality of output terminals, the plurality of pixels are connected to the plurality of output terminals, and the at least one scanning power line is connected to at least one of the plurality of output terminals.

[0026] In an exemplary embodiment, the display panel may be configured such that the plurality of pixels are arranged in a multi-dimensional matrix, and the power line includes a plurality of conductive lines, each of the plurality of conductive lines extending along an orthogonal dimension of the matrix and interconnected at vertices of the matrix.

[0027] In an exemplary embodiment, the display panel may further include a plurality of scan signal lines, wherein each of the plurality of scan signal lines is connected to a multivariate single-dimensional subset of the plurality of pixels, wherein each of the plurality of scan signal lines is switchably connected to at least one scan power line.

[0028] In an exemplary embodiment, the display panel may further include another scan power line and an additional plurality of scan signal lines, the other scan power line being connected to at least one of the plurality of output terminals, the additional plurality of scan signal lines being each connected to another multivariate single-dimensional subset of the plurality of pixels, wherein each of the additional plurality of scan signal lines is switchably connected to the other scan power line.

[0029] In an exemplary embodiment, the display panel may further include a plurality of power terminals, wherein each of the plurality of power terminals is connected to a power line, wherein the plurality of power terminals are configured in at least one of a column configuration and a first row and a last row configuration.

[0030] In an exemplary embodiment, the display panel may further include a plurality of scan power lines, wherein each of the plurality of scan power lines is connected to at least one of the plurality of output terminals, wherein the plurality of scan power lines are configured in at least one of a row configuration and a first column and a last column configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a partial schematic block diagram showing an organic light emitting diode (OLED) display device according to an exemplary embodiment;

[0033] Figure 2 is a schematic circuit diagram showing an example of a pixel included in an OLED display device according to an exemplary embodiment;

[0034] Figure 3is a schematic block diagram showing an example of a scan driver included in an OLED display device according to an exemplary embodiment;

[0035] Figure 4 is a partial schematic block diagram showing an OLED display device according to an exemplary embodiment;

[0036] Figure 5 is a diagram showing the non-preferred gate-on voltage applied to the scan driver through the gate-on voltage line and the gate-on voltage applied to the Figure 4 A graphical diagram comparing a pixel driving voltage of a scan driver in an OLED display device;

[0037] Figure 6 is a partial schematic block diagram showing an OLED display device according to an exemplary embodiment;

[0038] Figure 7 is a partial schematic block diagram showing an OLED display device according to an exemplary embodiment;

[0039] Figure 8 is a diagram showing the non-preferred gate-on voltage applied to the scan driver through the gate-on voltage line and the gate-on voltage applied to the Figure 7 A graphical diagram comparing a pixel driving voltage of a scan driver in an OLED display device;

[0040] Fig. 9 is a partial schematic block diagram showing an OLED display device according to an exemplary embodiment; and

[0041] Fig.10 is a schematic block diagram illustrating an example of an electronic device including an OLED display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0042] Hereinafter, exemplary embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.As used herein, like reference numerals may refer to like elements.

[0043] Figure 1 An organic light emitting diode (OLED) display device 100 according to an exemplary embodiment is shown. Figure 2 An example of a pixel PX included in the OLED display device 100 according to an exemplary embodiment is shown, and Figure 3 An example of the scan driver 130 included in the OLED display device 100 according to an exemplary embodiment is shown.

[0044] Reference Figure 1According to an exemplary embodiment, the OLED display device 100 may include a first power supply circuit 140 generating a pixel driving voltage ELVDD, a display panel 110 including a plurality of pixels PX emitting light based on the pixel driving voltage ELVDD, and a scan driver 130 receiving the pixel driving voltage ELVDD from the first power supply circuit 140 and providing the pixel driving voltage ELVDD as a scan signal SS to the plurality of pixels PX. In an exemplary embodiment, the OLED display device 100 may further include a source driver 120, a second power supply circuit 150, and a controller 160.

[0045] The display panel 110 may include a plurality of data lines, a plurality of scan lines, and a plurality of pixels PX coupled to the plurality of data lines and the plurality of scan lines. In an exemplary embodiment, each pixel PX may include at least one capacitor, at least two transistors, and an OLED, and the display panel 110 may be an OLED display panel.

[0046] Although a two-dimensional (2-D) display device 100 and display panel 110 have been shown and described using rows and columns for illustrative purposes, the present disclosure is not limited thereto. For example, alternative embodiments may be configured as a three-dimensional (3-D) device and / or panel using rows, columns, and height. In such 3-D embodiments, the grid or meshed power line structure of the device and / or panel may similarly extend in all three dimensions, but is not limited thereto.

[0047] like Figure 2 As shown in , each pixel PX may include a switching transistor TSW, a storage capacitor CST, a driving transistor TDR, and an OLED EL. The switching transistor TSW may transmit a data voltage DV in response to a scan signal SS having an on level. In an exemplary embodiment, the scan signal SS having an on level may be a pixel driving voltage ELVDD (e.g., a high-level power supply voltage ELVDD for the OLED EL). For example, the switching transistor TSW may include a gate receiving the scan signal SS having an on level or the pixel driving voltage ELVDD through a scan line, a first terminal receiving the data voltage DV, and a second terminal coupled to the storage capacitor CST.

[0048] The storage capacitor CST may store the data voltage DV transmitted through the switching transistor TSW. For example, the storage capacitor CST may include a first electrode coupled to the power line PL to which the pixel driving voltage ELVDD is applied and a second electrode coupled to the second terminal of the switching transistor TSW.

[0049] The driving transistor TDR may be coupled to a power line PL to which a pixel driving voltage ELVDD is applied, and may generate a driving current corresponding to a data voltage DV stored in the storage capacitor CST based on the pixel driving voltage ELVDD provided through the power line PL. For example, the driving transistor TDR may include a gate coupled to a second electrode of the storage capacitor CST, a first terminal coupled to the power line PL, and a second terminal coupled to the OLED EL.

[0050] The OLED EL may emit light in response to a driving current generated by the driving transistor TDR based on the pixel driving voltage ELVDD. For example, the OLED EL may include an anode coupled to the second terminal of the driving transistor TDR and a cathode coupled to a line of a low-level power supply voltage ELVSS for the OLED EL.

[0051] In an exemplary embodiment, if Figure 2 As shown in FIG. 1 , the switch transistor TSW and the drive transistor TDR may be NMOS transistors, but are not limited thereto. Figure 2 An example in which each pixel PX has a 2T1C structure including two transistors TSW and TDR and one capacitor CST is shown, but the pixel PX according to alternative embodiments may have any suitable pixel structure.

[0052] Refer again Figure 1 In an exemplary embodiment, the display panel 110 may further include a power line PL for transmitting the pixel driving voltage ELVDD to the plurality of pixels PX. Figure 1 As shown in , the power line PL may have a grid or mesh circuit configuration, layout or structure.

[0053] In an exemplary embodiment, the power line PL may receive the pixel driving voltage ELVDD at a first side (e.g., top side) of the display panel 110 through the first power line PSL1 from the first power circuit 140. For example, the OLED display device 100 may further include a first source film on which the source driver 120 is arranged, a first source plate coupled to the first source film, a first flexible film coupled to the first source plate, a control board coupled to the first flexible film, a second flexible film coupled to the control board, and a power board on which the first power circuit 140 is arranged and coupled to the second flexible film, and the first power line PSL1 may be formed on the power board, the second flexible film, the control board, the first flexible film, the first source plate, and the first source film.

[0054] In an alternative embodiment, the first source film may be coupled to a first side (e.g., top side) of the display panel 110, and the power line PL may receive the pixel driving voltage ELVDD at the first side of the display panel 110 from the first power circuit 140 through the first power line PSL1, and may receive the pixel driving voltage ELVDD at a second side (e.g., bottom side) opposite to the first side of the display panel 110 from the first power circuit 140 through the second power line PSL2. For example, the OLED display device 100 may further include a second source film on which the source driver 120 is not disposed and coupled to the second side of the display panel 110, a second source plate coupled to the second source film, and a third flexible film coupling the second source plate and the control board, and the second power line PSL2 may be coupled to the first power line PSL1 on the control board, and may be formed on the third flexible film, the second source plate, and the second source film.

[0055] The source driver 120 may provide a data voltage DV to a plurality of pixels PX through a plurality of data lines based on the output image data ODAT and the data control signal DCTRL received from the controller 160. In an exemplary embodiment, the data control signal DCTRL may include an output data enable signal, a horizontal start signal, and a load signal, but is not limited thereto. In an exemplary embodiment, the source driver 120 may be implemented in the form of an integrated circuit (IC). For example, the source driver 120 implemented in the form of an IC may be referred to as a source IC or a data IC. In addition, in an exemplary embodiment, the source driver 120 may be implemented as one or more source ICs.

[0056] The scan driver 130 may provide a scan signal SS to a plurality of pixels PX through a plurality of scan lines in response to a scan control signal received from the controller 160. In an exemplary embodiment, the scan control signal may include a scan start signal SSP and a scan clock signal SCLK, but is not limited thereto. In an exemplary embodiment, the scan driver 130 may be implemented as one or more scan ICs. In an alternative embodiment, the scan driver 130 may be integrated or formed in a peripheral portion of the display panel 110. For example, the scan driver 130 may be implemented as one or more oxide silicon gate (OSG) blocks integrated in a peripheral portion of the display panel 110.

[0057] The first power circuit 140 may generate a pixel driving voltage ELVDD based on a first power control signal PCTRL1 received from the controller 160. In an exemplary embodiment, the first power circuit 140 may apply the pixel driving voltage ELVDD to the power line PL at a first side (e.g., top side) of the display panel 110 through a first power line PSL1. In an alternative embodiment, the first power circuit 140 may apply the pixel driving voltage ELVDD to the power line PL at a first side of the display panel 110 through the first power line PSL1, and may also apply the pixel driving voltage ELVDD to the power line PL at a second side (e.g., bottom side) of the display panel 110 opposite to the first side through a second power line PSL2. In an exemplary embodiment, the pixel driving voltage ELVDD may be a high-level power voltage ELVDD for the OLED EL, and the first power circuit 140 may also generate a low-level power voltage ELVSS for the OLED EL. In addition, in an exemplary embodiment, the first power circuit 140 may be a switch mode power supply (SMPS), but is not limited thereto.

[0058] The second power supply circuit 150 may generate a gate-off voltage VOFF based on a second power control signal PCTRL2 received from the controller 160. In an exemplary embodiment, the second power supply circuit 150 may also generate a digital high-level power supply voltage VDD (e.g., a high-level power supply voltage for a digital circuit) and a digital low-level power supply voltage VSS (e.g., a low-level power supply voltage for a digital circuit). The second power supply circuit 150 may provide the digital high-level power supply voltage VDD, the digital low-level power supply voltage VSS, and the gate-off voltage VOFF to the scan driver 130. In an exemplary embodiment, the second power supply circuit 150 may be implemented as an IC, but is not limited thereto. The IC of the second power supply circuit 150 may be referred to as a power management integrated circuit (PMIC). In an exemplary embodiment, the first power supply circuit 140 and the second power supply circuit 150 may be implemented as separate ICs. In an alternative embodiment, the first power supply circuit 140 and the second power supply circuit 150 may be implemented as a single IC.

[0059] The controller 160 (e.g., a timing controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host (e.g., a graphic processing unit (GPU) or a graphic card). In an exemplary embodiment, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, or the like, but is not limited thereto. The controller 160 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, a first power control signal PCTRL1, and a second power control signal PCTRL2 based on the input image data IDAT and the control signal CTRL. The controller 160 can control the operation of the source driver 120 by providing the output image data ODAT and the data control signal DCTRL to the source driver 120, can control the operation of the scan driver 130 by providing the scan control signal to the scan driver 130, can control the operation of the first power circuit 140 by providing the first power control signal PCTRL1 to the first power circuit 140, and can control the operation of the second power circuit 150 by providing the second power control signal PCTRL2 to the second power circuit 150.

[0060] In the OLED display device 100 according to an exemplary embodiment, the scan driver 130 may receive a pixel driving voltage ELVDD from the first power circuit 140. In an exemplary embodiment, the scan driver 130 may receive the pixel driving voltage ELVDD from the first power circuit 140 through the power line PL of the display panel 110. In an example, the scan driver 130 may receive the pixel driving voltage ELVDD from the first power circuit 140 through the first power line PSL1 and the power line PL of the display panel 110. In another example, the scan driver 130 may receive the pixel driving voltage ELVDD from the first power circuit 140 through the first power line PSL1 and the power line PL of the display panel 110, and may also receive the pixel driving voltage ELVDD from the first power circuit 140 through the second power line PSL2 and the power line PL of the display panel 110. In addition, the scan driver 130 may provide the pixel driving voltage ELVDD as a scan signal SS to a plurality of pixels PX. In an exemplary embodiment, the scan driver 130 may also receive a gate-off voltage VOFF from the second power circuit 150 , may output the pixel driving voltage ELVDD as a scan signal SS having an on level, and may output the gate-off voltage VOFF as a scan signal SS having an off level.

[0061] In an exemplary embodiment, if Figure 3As shown in , the scan driver 130 may include a shift register 132 and an output buffer circuit 136. The shift register 132 may receive a scan start signal SSP and a scan clock signal SCLK from the controller 160. The shift register 132 may sequentially generate an internal scan signal ISS by shifting the scan start signal SSP in response to the scan clock signal SCLK. In an exemplary embodiment, the shift register 132 may receive a digital high-level power supply voltage VDD and a digital low-level power supply voltage VSS from the second power supply circuit 150 as power supply voltages, and may operate based on the digital high-level power supply voltage VDD and the digital low-level power supply voltage VSS. For example, the digital high-level power supply voltage VDD may be about 3.3V, but is not limited thereto, and the digital low-level power supply voltage VSS may be about 0V, but is not limited thereto. In this case, the internal scan signal ISS having an on level may be about 3.3V, but is not limited thereto, and the internal scan signal ISS having an off level may be about 0V, but is not limited thereto.

[0062] The output buffer circuit 136 may receive a pixel driving voltage ELVDD from the first power supply circuit 140. For example, the power line PL of the display panel 110 may receive the pixel driving voltage ELVDD from the first power supply circuit 140 through the first power line PSL1 and / or the second power line PSL2, and the output buffer circuit 136 receives the pixel driving voltage ELVDD from the power line PL of the display panel 110. The output buffer circuit 136 may also receive a gate turn-off voltage VOFF from the second power supply circuit 150. In response to the sequentially activated internal scan signals ISS or ISS', the output buffer circuit 136 may output the sequentially activated scan signals SS to a plurality of scan lines of the display panel 110. In addition, the output buffer circuit 136 may output the pixel driving voltage ELVDD as the scan signal SS having an on-level, and may output the gate turn-off voltage VOFF as the scan signal SS having an off-level. In an example, as Figure 3 As shown in , the pixel driving voltage ELVDD may be about 25V, but not limited thereto, and the gate off voltage VOFF may be about -7V, but not limited thereto. In this case, the scan signal SS having an on level may be about 25V, but not limited thereto, and the scan signal SS having an off level may be about -7V, but not limited thereto. For example, the pixel driving voltage ELVDD and the scan signal SS having an on level may be in the range of about 22V to about 25V, and the gate off voltage VOFF and the scan signal SS having an off level may be in the range of about -7V to about -5V.

[0063] In an exemplary embodiment, the scan driver 130 may further include a level shift circuit 134. The level shift circuit 134 may receive a pixel driving voltage ELVDD from the first power supply circuit 140 through a power line PL of the display panel 110, and may receive a digital low-level power supply voltage VSS from the second power supply circuit 150. The level shift circuit 134 may increase a voltage level of an internal scan signal ISS output from the shift register 132 based on the pixel driving voltage ELVDD, and may provide the internal scan signal ISS' having the increased voltage level to the output buffer circuit 136. For example, the internal scan signal ISS' having an on-level output from the level shift circuit 134 may be about 25V, but is not limited thereto, and the internal scan signal ISS' having an off-level output from the level shift circuit 134 may be about 0V, but is not limited thereto.

[0064] The scan driver of the non-preferred OLED display device may receive a gate-on voltage from a power supply circuit through a single gate-on voltage line, and may output the gate-on voltage as a scan signal. However, due to a voltage drop (e.g., IR drop) at a single gate-on voltage line, the gate-on voltage may decrease as the distance from the power supply circuit increases. However, in the OLED display device 100 according to the exemplary embodiment, the scan driver 130 may receive a pixel driving voltage ELVDD from the first power supply circuit 140 through a power line PL of the display panel 110, and may provide the pixel driving voltage ELVDD as a scan signal SS to a plurality of pixels PX. Since the pixel driving voltage ELVDD may be transmitted through a power line PL having a mesh or mesh structure, the pixel driving voltage ELVDD may be more consistent than a non-preferred gate-on voltage transmitted through a single gate-on voltage line. That is, instead of a non-preferred gate-on voltage having a relatively large voltage drop, the pixel driving voltage ELVDD transmitted through the power line PL may be used as a scan signal SS having a turn-on level of the scan driver 130. Furthermore, since a gate-on voltage line may not be required in the OLED display device 100 according to the exemplary embodiment, the number of lines (or conductive lines) of the OLED display device 100 may be reduced, and the bezel width of the OLED display device 100 may be reduced.

[0065] Figure 4 An OLED display device 200 according to an exemplary embodiment is shown, and Figure 5 The non-preferred gate-on voltage VON applied to the scan driver through the gate-on voltage line VONL is shown in FIG. Figure 4 1 and 2. A comparison of the pixel driving voltage ELVDD of the scan driver 230 in the OLED display device 200 is shown in FIG.

[0066] Reference Figure 4, the OLED display device 200 according to the exemplary embodiment may include a display panel 210, a source driver 220, a source film 222, a source plate 225, a first flexible film FFC1, a control board 265, a second flexible film FFC2, a first power circuit 240, a power board 245, a power line PSL1, and a scan driver 230. In an exemplary embodiment, the OLED display device 200 may further include a scan film 232, a second power circuit 250, and a controller 260.

[0067] The display panel 210 may include a plurality of pixels and a power line PL for transmitting a pixel driving voltage ELVDD to the plurality of pixels. Figure 4 As shown in , the power line PL may have a grid or mesh structure.

[0068] The source driver 220 may provide data voltages to a plurality of pixels. In an exemplary embodiment, the source driver 220 may be implemented as a plurality of integrated circuits DIC. For example, the integrated circuit DIC of the source driver 220 may be referred to as a source integrated circuit or a data integrated circuit. The source driver 220 may be arranged on a source film 222 coupled to the display panel 210. For example, the source film 222 may be a flexible film, and the source driver 220 may be mounted on the source film 222 in a chip on film (COF) manner. In an exemplary embodiment, as shown in FIG. Figure 4 As shown in FIG. 2 , a plurality of source integrated circuits DIC may be arranged on the plurality of source films 222 .

[0069] A plurality of source films 222 may be coupled to a source plate 225. For example, the source plate 225 may be a source printed circuit board (PCB) or a source printed board assembly (PBA), but is not limited thereto. The source plate 225 may be coupled to a control board 265 via a first flexible film FFC1. For example, the first flexible film FFC1 may be a flexible flat cable (FFC) or a flexible printed circuit (FPC), but is not limited thereto. In addition, for example, the control board 265 may be a control PCB or a control PBA, but is not limited thereto. The second power supply circuit 250 and the controller 260 may be arranged on the control board 265. In an exemplary embodiment, the second power supply circuit 250 may generate a gate-off voltage, and the scan driver 230 may receive the gate-off voltage from the second power supply circuit 250, and may output the gate-off voltage as a scan signal having an off level.

[0070] The control board 265 may be coupled to the power board 245 through the second flexible film FFC2. For example, the second flexible film FFC2 may be FFC or FPC, but is not limited thereto. In addition, the power board 245 may be a power supply PCB or a power supply PBA, but is not limited thereto. Figure 4 An example is shown where the control board 265 and the power board 245 are separate boards, but in an exemplary embodiment, the control board 265 and the power board 245 may be implemented with a single board. The first power supply circuit 240 generating the pixel driving voltage ELVDD may be disposed on the power board 245 .

[0071] The scan driver 230 may provide a scan signal to a plurality of pixels. Figure 4 As shown in , the scan driver 230 may be implemented as a plurality of integrated circuits SIC. For example, the integrated circuit SIC of the scan driver 230 may be referred to as a scan integrated circuit or a gate integrated circuit. The scan driver 230 may be arranged on a scan film 232 coupled to the display panel 210. For example, the scan film 232 may be a flexible film, and the scan driver 230 may be mounted on the scan film 232 in a COF manner. In an exemplary embodiment, as shown in FIG. Figure 4 As shown in FIG. 2 , a plurality of scanning integrated circuits SIC may be arranged on the plurality of scanning films 232 .

[0072] In a non-preferred OLED display device, a plurality of scan integrated circuits SIC may receive a gate-on voltage through a single gate-on voltage line VONL from the second power supply circuit 250. The single gate-on voltage line VONL may be formed such that the single gate-on voltage line VONL may bypass (or detour) the source integrated circuit DIC on the source film 222, and may pass outside the plurality of scan integrated circuits SIC on the plurality of scan films 232. In a non-preferred OLED display device, the gate-on voltage may be applied in a multi-drop manner through the single gate-on voltage line VONL.

[0073] However, in the OLED display device 200 according to the exemplary embodiment, the power line PSL1 may be formed on the power board 245, the second flexible film FFC2, the control board 265, the first flexible film FFC1, the source board 225, and the source film 222. The pixel driving voltage ELVDD generated by the first power circuit 240 may be applied to the power line PL through the power line PSL1. Figure 4As shown in , the power line PSL1 may be formed on a plurality of source films 222, and a pixel driving voltage ELVDD may be applied to the power line PL at a plurality of locations. The scan driver 230 or a plurality of scan integrated circuits SIC may receive the pixel driving voltage ELVDD from the first power circuit 240 through the power line PSL1 and the power line PL of the display panel 210, and may provide the pixel driving voltage ELVDD as a scan signal to a plurality of pixels. That is, the scan driver 230 of the OLED display device 200 according to the exemplary embodiment may use the pixel driving voltage ELVDD received through the power line PL having a grid or mesh structure instead of the gate-on voltage received through the single gate-on voltage line VONL. For example, as Figure 5 As indicated by 310 in FIG. 2 , as the distance from one side (e.g., the top side) of the display panel 210 increases, the gate-on voltage VON received through the single gate-on voltage line VONL may decrease relatively sharply due to the voltage drop (e.g., IR drop) of the single gate-on voltage line VONL. Figure 5 As indicated by 330 in FIG. 2 , as the distance from one side (e.g., the top side) of the display panel 210 increases, the pixel driving voltage ELVDD received through the power line PL having a grid or mesh structure may drop relatively slowly. Accordingly, in the OLED display device 200 according to the exemplary embodiment, a substantially uniform pixel driving voltage ELVDD may be applied to the scan driver 230 or a plurality of scan integrated circuits SIC through the power line PL having a grid or mesh structure, and the scan driver 230 may output the substantially uniform pixel driving voltage ELVDD as a scan signal. In addition, since the OLED display device 200 may not have the gate turn-on voltage line VONL, the number of lines (or conductive lines) of the OLED display device 200 may be reduced, and the border width of the OLED display device 200 may be reduced.

[0074] Figure 6 An OLED display device 400 according to an exemplary embodiment is shown.

[0075] Reference Figure 6 , the OLED display device 400 according to the exemplary embodiment may include a display panel 410, a source driver 420, a source film 422, a source plate 425, a scan driver 430, a first flexible film FFC1, a first power circuit 440, a power plate 445, a second flexible film FFC2, a second power circuit 450, a controller 460, a control board 465, and a power line PSL1. In addition to the scan driver 430 being implemented as a plurality of OSG blocks integrated in the peripheral portion 412 of the display panel 410, Figure 6 The OLED display device 400 may have Figure 4The OLED display device 200 has substantially the same structure.

[0076] The scan driver 430 may be integrated or formed in the peripheral portion 412 of the display panel 410. In an exemplary embodiment, the scan driver 430 may be implemented as a plurality of OSG blocks integrated in the peripheral portion 412 of the display panel 410. For example, the plurality of OSG blocks may be a plurality of silicon oxide gate blocks, but is not limited thereto.

[0077] like Figure 6 As shown in, in the OLED display device 400 according to the exemplary embodiment, the scan driver 430 or the plurality of silicon oxide gate (OSG) blocks may receive the pixel driving voltage ELVDD from the first power circuit 440 through the power line PSL1 and the power line PL of the display panel 410, and may provide the pixel driving voltage ELVDD as a scan signal to the plurality of pixels. Accordingly, in the OLED display device 400 according to the exemplary embodiment, a substantially uniform pixel driving voltage ELVDD may be applied to the scan driver 430 or the plurality of silicon oxide gate (OSG) blocks through the power line PL having a grid or mesh structure, and the scan driver 430 may output the substantially uniform pixel driving voltage ELVDD as a scan signal. In addition, since the OLED display device 400 may not have a gate turn-on voltage line, the number of lines (or wires) of the OLED display device 400 may be reduced, and the border width of the OLED display device 400 may be reduced.

[0078] Figure 7 An OLED display device 500 according to an exemplary embodiment is shown, and Figure 8 The non-preferred gate-on voltage VON applied to the scan driver through the gate-on voltage line VONL is shown in FIG. Figure 7 1 and 2. FIG. 1 is a comparison of the pixel driving voltage ELVDD of the scan driver 530 in the OLED display device 500. FIG.

[0079] Reference Figure 7 According to an exemplary embodiment, the OLED display device 500 may include a display panel 510, a source driver 520, a first source film 522, a first source plate 525, a first flexible film FFC1, a control board 565, a second flexible film FFC2, a first power circuit 540, a power board 545, a first power line PSL1, a second source film 572, a second source plate 575, a third flexible film FFC3, a second power line PSL2, and a scan driver 530. In an exemplary embodiment, the OLED display device 500 may further include a scan film 532, a second power circuit 550, and a controller 560. Figure 4 Compared with the OLED display device 200, Figure 7The OLED display device 500 may further include a third flexible film FFC3 , a second source plate 575 , a second source film 572 , and a second power line PSL2 formed on the third flexible film FFC3 , the second source plate 575 , and the second source film 572 .

[0080] The first source film 522 where the source driver 520 is arranged may be coupled to a first side (e.g., top side) of the display panel 510. In addition, a first power line PSL1 may be formed on the power board 545, the second flexible film FFC2, the control board 565, the first flexible film FFC1, the first source board 525, and the first source film 522, and may apply a pixel driving voltage ELVDD to the power line PL at the first side of the display panel 510.

[0081] The second source film 572 may be coupled to a second side (e.g., bottom side) of the display panel 510 opposite to the first side. For example, the second source film 572 may be a flexible film. In an exemplary embodiment, the source driver 520 may not be arranged on the second source film 572. The second source plate 575 may be coupled to the second source film 572, and may be coupled to the control board 565 through the third flexible film FFC3. For example, the second source plate 575 may be a source PCB or a source PBA, but is not limited thereto. In addition, the third flexible film FFC3 may be an FFC or an FPC, but is not limited thereto. The second power line PSL2 may be coupled to the first power line PSL1 on the control board 565, and may be formed on the third flexible film FFC3, the second source plate 575, and the second source film 572. Therefore, the second power line PSL2 may apply the pixel driving voltage ELVDD to the power line PL at the second side of the display panel 510 opposite to the first side.

[0082] Accordingly, the scan driver 530 or the plurality of scan integrated circuits SIC may receive the pixel driving voltage ELVDD from the first power circuit 540 through the first power line PSL1 and the power line PL of the display panel 510, may also receive the pixel driving voltage ELVDD from the first power circuit 540 through the second power line PSL2 and the power line PL of the display panel 510, and may provide the pixel driving voltage ELVDD as a scan signal to the plurality of pixels of the display panel 510. That is, the scan driver 530 of the OLED display device 500 according to the exemplary embodiment may use the pixel driving voltage ELVDD received through the power line PL having a mesh or mesh structure instead of the gate-on voltage received through the single gate-on voltage line VONL. For example, as Figure 8As indicated by 610 in FIG. 5 , as the distance from one side (e.g., the top side) of the display panel 510 increases, the gate-on voltage VON received through the single gate-on voltage line VONL may decrease relatively sharply due to the voltage drop (e.g., IR drop) of the single gate-on voltage line VONL. Figure 8 As indicated by 630 in FIG. 5 , as the distance from one side (e.g., the top side) of the display panel 510 increases, the pixel driving voltage ELVDD received at both sides of the display panel 510 through the power line PL having a grid or mesh structure to which the pixel driving voltage ELVDD is applied may drop relatively slowly, and then may increase relatively slowly. Accordingly, in the OLED display device 500 according to the exemplary embodiment, a substantially uniform pixel driving voltage ELVDD may be applied to the scan driver 530 or a plurality of scan integrated circuits SIC through the power line PL having a grid or mesh structure, and the scan driver 530 may output the substantially uniform pixel driving voltage ELVDD as a scan signal. In addition, since the OLED display device 500 may not have the gate turn-on voltage line VONL, the number of lines (or wires) of the OLED display device 500 may be reduced, and the border width of the OLED display device 500 may be reduced.

[0083] Fig. 9 An OLED display device 700 according to an exemplary embodiment is shown.

[0084] Reference Fig. 9 , the OLED display device 700 according to the exemplary embodiment may include a display panel 710, a source driver 720, a first source film 722, a first source plate 725, a first flexible film FFC1, a scan driver 730, a first power circuit 740, a power plate 745, a second flexible film FFC2, a second power circuit 750, a controller 760, a control board 765, a first power line PSL1, a second source film 772, a second source plate 775, a third flexible film FFC3, and a second power line PSL2. In addition to the scan driver 730 being implemented as a plurality of OSG blocks integrated in the peripheral portion 712 of the display panel 710, Fig. 9 The OLED display device 700 may have Figure 7 The OLED display device 500 has substantially the same structure.

[0085] The scan driver 730 may be integrated or formed in the peripheral portion 712 of the display panel 710. In an exemplary embodiment, the scan driver 730 may be implemented as a plurality of OSG blocks integrated in the peripheral portion 712 of the display panel 710. For example, the plurality of OSG blocks may be a plurality of silicon oxide gate blocks, but is not limited thereto.

[0086] like Fig. 9As shown in FIG. 1 , in the OLED display device 700 according to the exemplary embodiment, the scan driver 730 or the plurality of silicon oxide gate (OSG) blocks may receive the pixel driving voltage ELVDD from the first power circuit 740 through the first power line PSL1 and the power line PL of the display panel 710, and may also receive the pixel driving voltage ELVDD from the first power circuit 740 through the second power line PSL2 and the power line PL of the display panel 710, and may provide the pixel driving voltage ELVDD as a scan signal to the plurality of pixels of the display panel 710. Accordingly, in the OLED display device 700 according to the exemplary embodiment, a substantially uniform pixel driving voltage ELVDD may be applied to the scan driver 730 or the plurality of silicon oxide gate (OSG) blocks through the power line PL having a mesh or mesh structure, and the scan driver 730 may output the substantially uniform pixel driving voltage ELVDD as a scan signal. In addition, since the OLED display device 700 may not have a gate turn-on voltage line, the number of lines (or wires) of the OLED display device 700 may be reduced, and the border width of the OLED display device 700 may be reduced.

[0087] Fig.10 An example of an electronic device 1100 including an OLED display device according to an exemplary embodiment is shown.

[0088] Reference Fig.10 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and an OLED display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electrical devices, or the like.

[0089] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), or the like. The processor 1110 may be connected to other components via an address bus, a control bus, a data bus, or the like. In addition, in an exemplary embodiment, the processor 1110 may also be connected to an expansion bus such as a peripheral component interconnection (PCI) bus.

[0090] The memory device 1120 may store data used for the operation of the electronic device 1100 . For example, the memory device 1120 may include at least one nonvolatile memory device and / or at least one volatile memory device, wherein the at least one nonvolatile memory device is such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device, or the like, and the at least one volatile memory device is such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or the like. memory, SRAM) device or mobile dynamic random access memory (mobile DRAM) device or the like.

[0091] The storage device 1130 may be a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, or the like, and an output device such as a printer, a speaker, or the like. The power supply 1150 may supply power for the operation of the electronic device 1100.

[0092] In the OLED display device 1160, the scan driver may receive a pixel driving voltage provided to a plurality of pixels, and may provide the pixel driving voltage as a scan signal to the plurality of pixels. Accordingly, a pixel driving voltage having a relatively small voltage drop may be used instead of a gate turn-on voltage having a relatively large voltage drop in the scan driver, and the number of lines (or conductive lines) and the border width of the OLED display device 1160 may be reduced.

[0093] According to an exemplary embodiment, the electronic device 1100 may be any electronic device including the OLED display device 1160, such as a cellular phone, a smart phone, a tablet computer, a wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a digital television, a 3D television, a personal computer (PC), a home appliance, a laptop computer, or the like.

[0094] The foregoing is illustrative of the present disclosure and will not be construed as limiting it. Although exemplary embodiments have been shown and described, it will be readily appreciated by those of ordinary skill in the art that modifications may be made without materially departing from the novel teachings of the present disclosure. All such modifications are intended to be included within the scope of the inventive concept as defined in the appended claims. It will be understood that the foregoing is illustrative of the inventive concept but will not be construed as limited to the specific embodiments disclosed, and it will be understood that modifications to the disclosed embodiments and alternative embodiments are intended to be included within the scope and spirit of the appended claims and their equivalents.

Claims

1. An organic light emitting diode display device, comprising: a first power supply circuit configured to generate a pixel driving voltage; a display panel configured to receive the pixel driving voltage from the first power supply circuit and including a plurality of pixels each configured to emit light based on the pixel driving voltage; as well as a scan driver configured to receive the pixel driving voltage from the display panel and provide a scan signal to the plurality of pixels based on the pixel driving voltage, The display panel further comprises a power circuit, and the power circuit is used to transmit the pixel driving voltage to the plurality of pixels. wherein the first power circuit applies the pixel driving voltage to the power line of the display panel through a first power line, wherein the scan driver receives the pixel driving voltage from the first power circuit through the first power line and the power line of the display panel, Wherein, the organic light emitting diode display device further comprises: a source driver configured to provide data voltages to the plurality of pixels; A source film connected to the display panel, the source driver being arranged on the source film; a source plate connected to the source film; a first flexible membrane coupled to the source plate; a control board coupled to the first flexible membrane; a second flexible membrane coupled to the control board; and A power board is coupled to the second flexible film, and the first power circuit is arranged on the power board.

2. The organic light emitting diode display device according to claim 1, wherein: The power lines of the display panel have a grid structure.

3. The organic light emitting diode display device according to claim 1, wherein: Each of the plurality of pixels comprises: a switching transistor configured to transmit a data voltage in response to the scan signal from the scan driver; a storage capacitor configured to store the data voltage transmitted through the switching transistor; a driving transistor coupled to the power line and configured to generate a driving current corresponding to the data voltage stored in the storage capacitor based on the pixel driving voltage provided through the power line; and An organic light emitting diode is configured to emit light based on the driving current.

4. The organic light emitting diode display device according to claim 1, further comprising: a second power supply circuit configured to generate a gate-off voltage, The scan driver further receives the gate turn-off voltage from the second power supply circuit, outputs the pixel driving voltage as the scan signal with an on-level, and outputs the gate turn-off voltage as the scan signal with an off-level.

5. The organic light emitting diode display device according to claim 4, further comprising: A controller is configured to control the scan driver by providing a scan start signal and a scan clock signal to the scan driver.

6. The organic light emitting diode display device according to claim 5, wherein: The scanning driver comprises: a shift register configured to sequentially generate internal scan signals by shifting the scan start signal in response to the scan clock signal; and An output buffer circuit is configured to receive the pixel driving voltage from the first power supply circuit and the gate turn-off voltage from the second power supply circuit, output the pixel driving voltage as the scanning signal with the on-level in response to the internal scanning signal, and output the gate turn-off voltage as the scanning signal with the off-level.

7. The organic light emitting diode display device according to claim 6, wherein: The second power supply circuit also generates a digital high level power supply voltage and a digital low level power supply voltage, and The shift register operates based on the digital high-level power supply voltage and the digital low-level power supply voltage received from the second power supply circuit.

8. An organic light emitting diode display device, comprising: a display panel comprising a plurality of pixels and a power line for transmitting a pixel driving voltage to the plurality of pixels; a source driver configured to provide a data voltage to the plurality of pixels; a source film, the source film being coupled to the display panel, the source driver being arranged on the source film; a source plate coupled to the source film; a first flexible membrane coupled to the source plate; a control board coupled to the first flexible membrane; a second flexible membrane coupled to the control board; a first power supply circuit configured to generate the pixel driving voltage; a power board coupled to the second flexible film, the first power circuit being disposed on the power board; a power line formed on the power board, the second flexible film, the control board, the first flexible film, the source board, and the source film, and configured to apply the pixel driving voltage generated by the first power circuit to the power line of the display panel; as well as A scan driver is configured to receive the pixel driving voltage from the first power supply circuit through the power supply line and the power line of the display panel, and provide the pixel driving voltage as a scan signal to the plurality of pixels.

9. A display device, comprising: a display panel comprising a plurality of pixels and a power line for transmitting a pixel driving voltage to the plurality of pixels; a source driver configured to provide a data voltage to the plurality of pixels; a first source film, the first source film being coupled to a first side of the display panel, and the source driver being arranged on the first source film; a first source plate coupled to the first source film; a first flexible membrane coupled to the first source plate; a control board coupled to the first flexible membrane; a second flexible membrane coupled to the control board; a first power supply circuit configured to generate the pixel driving voltage; a power board coupled to the second flexible film, the first power circuit being disposed on the power board; a first power line formed on the power board, the second flexible film, the control board, the first flexible film, the first source board, and the first source film, and configured to apply the pixel driving voltage to the power line at the first side of the display panel; a second source film, the second source film being coupled to a second side of the display panel opposite to the first side, and the source driver being not disposed on the second source film; a second source plate coupled to the second source film; a third flexible film coupled to the second source plate and the control plate; a second power line coupled to the first power line on the control board, formed on the third flexible film, the second source plate, and the second source film, and configured to apply the pixel driving voltage to the power line at the second side of the display panel; as well as A scan driver configured to receive the pixel driving voltage from the first power supply circuit through the first power supply line and the power line of the display panel, also receive the pixel driving voltage from the first power supply circuit through the second power supply line and the power line of the display panel, and provide the pixel driving voltage as a scan signal to the plurality of pixels.

Images