Non-volatile memory and methods of operating the same

Abstract

A non-volatile memory device includes: a resistive switching layer; a gate on the resistive switching layer; a gate oxide layer between the resistive switching layer and the gate; and a source and a drain on the resistive switching layer and spaced apart from each other. The resistance value of the resistive switching layer changes based on the illuminance of light illuminating the resistive switching layer and remains at the changed resistance value.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application 62 / 937,850, filed November 20, 2019, with the U.S. Patent and Trademark Office, and Korean Patent Application 10-2020-0010030, filed January 28, 2020, with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to non-volatile storage devices and methods of operating thereof. Background Technology

[0004] Non-volatile memory devices, as semiconductor memory devices, retain the information stored on them even when the power is off, so the stored information can be accessed and / or used again when power is supplied. Non-volatile memory devices can be used in mobile phones, digital cameras, personal digital assistants (PDAs), mobile computers, fixed computers, and other devices.

[0005] Recently, research has been conducted on the use of non-volatile memory devices in chips included in next-generation neuromorphic computing platforms or neural networks.

[0006] In particular, non-volatile storage devices with photoconductivity (PC) are required. Summary of the Invention

[0007] A non-volatile storage device and a method of operating it are provided. A computer-readable recording medium on which a program for executing the method on a computer is recorded is also provided. The technical problem to be solved is not limited to the above-mentioned technical problem, and therefore other technical problems can be solved.

[0008] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0009] According to a first aspect of some example embodiments, a non-volatile memory device includes: a resistor switching layer having a resistance value, the resistor switching layer being configured to change the resistance value based on the illuminance of light illuminating it and the resistor switching layer being configured to maintain the changed resistance value; a gate on the resistor switching layer; a gate oxide layer between the resistor switching layer and the gate; and a source and a drain on the resistor switching layer and spaced apart from each other.

[0010] The gate may include a transparent conductive electrode (TCE) gate above the resistance switching layer and configured to transmit the illuminated light.

[0011] The resistive switching layer may include a two-dimensional (2D) material, which may include at least one of transition metal dichalcogenide (TMD), silicene, phosphorus (black phosphorus) or graphene.

[0012] The resistor switching layer can be formed as a single layer or multiple layers.

[0013] The resistive switching layer may include a three-dimensional (3D) material, which may include at least one of germane, silicon, III-V semiconductors or IGZO.

[0014] The gate oxide layer can be formed as a multilayer, wherein the multilayer may include a charge trapping layer.

[0015] The change in the resistance value of the resistive switching layer can include decreasing the resistance value of the resistive switching layer as the illuminance of the light illuminating the resistive switching layer increases while a cutoff voltage is applied to the gate.

[0016] When an on-state voltage is applied to the gate, the resistor switching layer can be configured to reset the resistor value.

[0017] According to a second aspect of another example embodiment, a method of performing operation using a cross array comprising a plurality of nonvolatile memory devices, the method comprising: applying a cutoff voltage to the gate of each of the plurality of nonvolatile memory devices; changing the resistance value of a resistance switching layer of each of the plurality of nonvolatile memory devices by irradiating the plurality of nonvolatile memory devices with light having an illuminance corresponding to the plurality of elements; and applying a gate cutoff voltage to at least one row of the cross array and obtaining source power from each column of the cross array.

[0018] The irradiated light may correspond to multiple pixels included in the image; and the operation may include obtaining the image by applying a gate cutoff voltage to each row of the cross array and obtaining source current from each column of the cross array.

[0019] The irradiated light may correspond to multiple pixels included in the image, and the irradiation may include: sequentially arranging multiple color filters on the non-volatile memory devices, and irradiating each of the multiple non-volatile memory devices with the light. The operation includes: obtaining intermediate images corresponding to the multiple color filters respectively by applying a gate cutoff voltage to each row of the cross array and obtaining source current from each column of the cross array; and obtaining a color image by synthesizing the intermediate images.

[0020] Illumination may include: illuminating the plurality of nonvolatile memory devices with light having an illuminance corresponding to one of the plurality of weights included in a particular layer of the neural network, and the operation may include performing a vector matrix operation of the particular layer by applying a gate cutoff voltage to at least one row of the raster array and obtaining a source current from each column of the raster array.

[0021] Illumination may include moving the window one step across the image and illuminating each column of the cross array with light having an illuminance corresponding to the plurality of elements included in the window.

[0022] According to a third aspect of another example embodiment, a method for recognizing an image using a cross array comprising a plurality of nonvolatile memory devices, the method comprising: applying a cutoff voltage to the gate of each of the plurality of nonvolatile memory devices; moving a window one step over the image and illuminating each column of the cross array with light having an illuminance corresponding to the image included in the window; performing a pooling operation by applying a gate cutoff voltage to at least one row of the cross array and obtaining a first source current from each column of the cross array; and further performing a pooling operation by applying an on-state voltage to the plurality of nonvolatile memory devices. The method involves: resetting a plurality of non-volatile memory devices by applying a cutoff voltage to the gate of each of the reset plurality of non-volatile memory devices; illuminating the plurality of non-volatile memory devices with light having an illuminance corresponding to a plurality of weights included in a particular layer of a neural network; performing a fully connected convolution operation by applying a voltage corresponding to a first source current as a drain voltage to at least one row of the cross array and obtaining a second source current from each column of the cross array; and identifying an image based on the second source current.

[0023] According to a fourth aspect of another example embodiment, a non-transitory computer-readable recording medium has been recorded thereon with a program for causing a computer to perform the method of the second aspect when run on a computer. The computer-readable recording medium has thereon recorded with a program for performing the method of the second aspect on a computer. Attached Figure Description

[0024] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1A and Figure 1B This is a diagram used to describe a method of operation of a cross array including multiple non-volatile storage devices according to some example embodiments;

[0026] Figure 2 This is a diagram illustrating the architecture of a neural network according to some example embodiments;

[0027] Figure 3 It is a diagram illustrating the relationship between input feature maps and output feature maps in a neural network according to some example embodiments;

[0028] Figure 4A and Figure 4B This is a diagram illustrating, based on some example embodiments, an attempt to compare operations performed in a crossbar array with vector-matrix multiplication;

[0029] Figure 5 This is a diagram used to illustrate examples of performing convolution operations in a cross array according to some example embodiments;

[0030] Figure 6 This is a diagram used to illustrate examples of matching between crossbar arrays and sub-feature maps according to some example embodiments;

[0031] Figure 7A and Figure 7B This is a side view illustrating a non-volatile memory device with phototransistor and storage characteristics according to some example embodiments.

[0032] Figure 8 This is a diagram used to illustrate the phenomenon of the change in the resistance value of a non-volatile memory device before and after it is exposed to light.

[0033] Figure 9A and Figure 9B It is a diagram used to describe the process of storing and obtaining an image using a cross array comprising multiple non-volatile storage devices according to some example embodiments;

[0034] Figure 10 This is a diagram used to describe the process of performing pooling operations of a neural network using a crossbar array comprising multiple non-volatile memory devices, according to some example embodiments.

[0035] Figure 11 This is a diagram used to describe the process of performing a convolution operation of a neural network using a crossbar array comprising multiple non-volatile memory devices, according to some example embodiments.

[0036] Figure 12 This is a flowchart of a method for performing operations using a transverse array according to some example embodiments.

[0037] Figure 13 This is a block diagram illustrating a storage system according to some example embodiments. Detailed Implementation

[0038] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When an expression such as “at least one” precedes a list of elements, it modifies the entire list of elements and does not modify the individual elements of the list.

[0039] The terms “in some example embodiments” and “in one example embodiment” as used herein do not necessarily refer to the same embodiment.

[0040] Some exemplary embodiments of this disclosure can be represented by functional blocks and various processing operations. Some or all of these functional blocks can be implemented as various numbers of hardware and / or software components for performing a specific function. For example, the functional blocks of this disclosure can be implemented using one or more microprocessors, or using circuitry for a predetermined function. Furthermore, for example, the functional blocks of this disclosure can be implemented using various programming or scripting languages. Functional blocks can be implemented as algorithms to be executed by one or more processors. Furthermore, this disclosure can employ typical techniques for electronic environment setup, signal processing, and / or data processing. Terms such as “mechanism,” “element,” “device,” “configuration,” etc., are used extensively herein and are not limited to mechanical and physical configurations.

[0041] Although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions are not limited by these provisions. These terms are used only to distinguish one element, component, region, layer, and / or portion from another. Therefore, without departing from the scope of this disclosure, the first element, component, region, layer, and / or portion discussed below may be referred to as the second element, component, region, layer, and / or portion.

[0042] When an element is referred to as being "on" another element, the element may be directly on the other element, and / or one or more other intermediary elements may be present. Conversely, when an element is referred to as being "directly on another element," no intermediary element is present. Additionally, when an element is referred to as being between two elements, the element may be the only element between the two elements, or one or more other intermediary elements may be present.

[0043] Furthermore, the connecting lines or assemblies between the components shown in the accompanying drawings are merely examples of functional connections and / or physical or circuit connections. In practical applications, they can be replaced or embodied as various additional functional connections, physical connections, or circuit connections.

[0044] Generally speaking, computer-accessible media can include any tangible and / or non-transitory storage media and / or storage media. As used herein, the term "non-transitory" refers to a limitation on the medium itself (e.g., as tangible rather than signaling), rather than a limitation on the persistence of data storage (e.g., RAM vs. ROM).

[0045] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1A and Figure 1B This is a diagram illustrating a method of operating a cross array of multiple non-volatile storage devices according to some example embodiments.

[0047] refer to Figure 1A The transverse array may include a plurality of presynaptic neurons 10, a plurality of postsynaptic neurons 20, and synapses 30 providing connections between the plurality of presynaptic neurons 10 and the plurality of postsynaptic neurons 20. Synapses 30 may represent, for example, nonvolatile storage devices.

[0048] In one example embodiment, the transverse array may include four presynaptic neurons 10, four postsynaptic neurons 20, and 16 synapses 30, but the number of the aforementioned elements can vary. When the number of presynaptic neurons 10 is N (where N is a natural number greater than or equal to 2) and the number of postsynaptic neurons 20 is M (where M is a natural number greater than or equal to 2, and M may be equal to or different from N), they can be arranged in a matrix form. 30 synapses.

[0049] In detail, line 12 can connect to each of the plurality of presynaptic neurons 10 and can extend in a first direction (e.g., horizontal direction), and line 22 can connect to each of the plurality of postsynaptic neurons 20 and can extend in a second direction (e.g., vertical direction) intersecting the first direction. Hereinafter, for convenience, line 12 extending in the first direction is referred to as a row line, and line 22 extending in the second direction is referred to as a column line. A plurality of synapses 30 can be arranged at each intersection of row line 12 and column line 22 to connect corresponding row lines 12 and corresponding column lines 22 to each other.

[0050] Presynaptic neuron 10 can be configured to generate and send signals, such as signals corresponding to specific data, to row line 12, and postsynaptic neuron 20 can be configured to receive synaptic signals that have passed through synapse 30 via column line 22 and can process synaptic signals. Presynaptic neuron 10 may correspond to an axon, while postsynaptic neuron 20 may correspond to a neuron. However, a neuron can be determined as either presynaptic neuron 10 or postsynaptic neuron 20 based on its relative relationship to another neuron. For example, when presynaptic neuron 10 receives a synaptic signal from another neuron, presynaptic neuron 10 can function as postsynaptic neuron 20. Similarly, when postsynaptic neuron 20 sends a signal to another neuron, postsynaptic neuron 20 can function as presynaptic neuron 10. Presynaptic neuron 10 and postsynaptic neuron 20 can be implemented as various circuits such as metal-oxide-semiconductor (CMOS).

[0051] A connection between the presynaptic neuron 10 and the postsynaptic neuron 20 can be established via synapse 30. Synapse 30 can be a device configured to change weight or conductance by applying electrical impulses (e.g., voltage and / or current) to both ends of synapse 30.

[0052] Synapse 30 may include, for example, a variable resistor. The variable resistor can switch between different resistance states depending on the voltage or current applied across its terminals. The variable resistor can have a single-layer or multi-layer structure and includes various materials that can have multiple resistance states, such as metal oxides (e.g., transition metal oxides); perovskite-based materials; phase change materials (e.g., chalcogenide-based materials); and / or ferroelectric or ferromagnetic materials. The operation of the variable resistor element and / or the synthesizer 30 changing from a high resistance state (e.g., high resistance state) to a low resistance state (e.g., low configuration state) can be referred to as a setting operation, and the operation of the variable resistor element and / or the synthesizer 30 changing from a low resistance state to a high resistance state can be referred to as a reset operation.

[0053] However, the synapse 30 can be implemented with various characteristics different from those of a variable resistive device in memory. For example, unlike the variable resistive devices used in memory devices such as resistive random access memory (RRAM), parametric RAM (PRAM), ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), etc., the synapse 30 can exhibit analog behavior in which the resistance does not change abruptly and the conductance changes gradually depending on the number of electrical pulses input during set and reset operations.

[0054] The following reference Figure 1BDescribe the operation of the column array. For convenience, the row lines 12 can be referred to as first row line 12A, second row line 12B, third row line 12C and fourth row line 12D from top to bottom, and the column lines 22 can be referred to as first column line 22A, second column line 22B, third column line 22C and fourth column line 22D from left to right.

[0055] Reference Figure 1B In the initial state, all synapses 30 can be in a state with relatively low conductance, such as a high resistance state. When at least a portion of the plurality of synapses 30 is in a low resistance state, an initialization operation can switch a portion of the plurality of synapses 30 to a high resistance state. Each of the plurality of synapses 30 can have a threshold for changing its resistance and / or conductance. For example, a synapse 30 can have a desired (or alternatively, predetermined) threshold for changing its resistance and / or conductance. A synapse 30 can be configured to: for example, not change its conductance when a voltage and / or current less than the threshold is applied across the synapse 30; and change its conductance when a voltage and / or current greater than the threshold is applied across the synapse 30.

[0056] In this state, an input signal corresponding to specific data can be input to row line 12 to execute an operation that outputs specific data as a result of a specific column line 22. Here, the input signal can be indicated by applying an electrical pulse to row line 12. For example, when an input signal corresponding to the data "0011" is input to row line 12, an electrical pulse may not be applied to row line 12 corresponding to the digit "0" (e.g., first and second row lines 12A and 12B), but an electrical pulse may be applied to row line 12 corresponding to the digit "1" (e.g., third and fourth row lines 12C and 12D). Column line 22 can be driven with appropriate voltage and / or current to execute the output.

[0057] For example, when column line 22 for outputting specific data is determined, it can be driven such that the contact 30 at the intersection of column line 22 and row line 12, corresponding to the digit "1", can receive a voltage equal to or higher than the voltage required for the setting operation (hereinafter referred to as the setting voltage Vset). The remaining column lines 22 can also be driven such that the remaining contacts 30 can receive voltages lower than the setting voltage Vset. For example, when the setting voltage is Vset, and the column line 22 for outputting the data "0011" is determined to be the third column line 22C, the amplitude of the electrical pulses applied to the third row line 12C and the fourth row line 12D can be at least Vset, and the voltage applied to the third column line 22C can be 0V, such that the first contact 30A and the second contact 30B at the intersection of the third column line 22C and the third row line 12C and the fourth row line 12D can receive a voltage of at least Vset. Therefore, the first contact 30A and the second contact 30B can be in a low-resistance state. As the number of electrical pulses increases, the conductance of the first and second synthesizers 30A and 30B, which are in a low-resistance state, can gradually increase. The amplitude and width of the applied electrical pulses can be substantially constant. The voltage applied to the remaining lines (i.e., the first, second, and fourth lines 22A, 22B, and 22D) can have a value between 0V and Vset, for example, 1 / 2 Vset, so that the synthesizers 30 other than the first and second synthesizers 30A and 30B can receive a relative voltage lower than Vset. Therefore, the impedance state of the synthesizers 30 other than the first and second synthesizers 30A and 30B may not change. In this case, the flow of current and / or electrons is... Figure 1B The dashed arrow in the middle indicates this.

[0058] In another example, the column line 22 used to output specific data may not yet be determined. In this case, the current flowing through each column line 22 can be measured while an electrical pulse corresponding to the specific data is applied to the row line 12, and the column line 22 whose current reaches the threshold current earliest can be determined, for example, the third column line 22C outputting specific data.

[0059] In this way, different data can be output to different column lines 22.

[0060] Figure 2 This is a diagram illustrating the architecture of a neural network according to some example embodiments.

[0061] Reference Figure 2Neural network 2 can have an architecture of deep neural networks (DNNs) and / or n-layer neural networks. DNNs and / or n-layer neural networks can correspond to convolutional neural networks (CNNs), recurrent neural networks (RNNs), deep belief networks, restricted Boltzmann machines, etc. For example, neural network 2 can be implemented as a CNN, an artificial neural network (ANN) system, a deep learning system, a deconvolutional neural network (DCNN), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network (GAN), and / or a restricted Boltzmann machine (RBM), but is not limited thereto. Alternatively and / or additionally, such a machine learning system can include other forms of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including, for example, ensembles of random forests. Although Figure 2 The diagram illustrates some convolutional layers of a convolutional neural network as an example of neural network 2. However, in addition to the convolutional layers shown, convolutional neural networks can also include pooling layers, fully connected layers, etc.

[0062] Neural Network 2 can be implemented using an architecture with multiple layers, including an input image, a feature map, and an output. In Neural Network 2, a convolution operation is performed between the input image and filters called weights, and the feature map is output as the result of the convolution operation. A convolution operation is then performed between the output feature map (which serves as the input feature map) and the weights, outputting a new feature map. As a result of repeatedly performing this convolution operation, a result can be outputting the features of the input image recognized by Neural Network 2.

[0063] For example, when an image with a size of 24×24 pixels is input into Figure 2 In Neural Network 2, the input image is output as a 4-channel feature map of size 20×20 through convolution operations between the input image and weights. Subsequently, the size of the 20×20 feature map can be reduced by repeating convolution operations between the feature map and weights, ultimately outputting features of size 1×1. Neural Network 2 can filter and output robust features that represent the entire image from the input image by repeatedly performing convolution operations and subsampling (e.g., pooling) operations in multiple layers, from which the result of recognizing the input image can be derived by outputting the final features.

[0064] Figure 3 This is a diagram illustrating the relationship between input feature maps and output feature maps in a neural network according to some example embodiments.

[0065] Reference Figure 3In layer 3 of the neural network, the first feature map FM1 can correspond to the input feature map, and the second feature map FM2 can correspond to the output feature map. The feature maps can represent a dataset containing various features representing the input data. Feature maps FM1 and FM2 can have elements of a two-dimensional matrix or elements of a three-dimensional matrix, where a pixel value can be defined in each element. Feature maps FM1 and FM2 have a width W (e.g., column), a height H (e.g., row), and a depth D. The depth D can correspond to, for example, the number of channels.

[0066] A convolution operation can be performed on a first feature map FM1 and weights, and a second feature map FM2 can be generated as the result of the convolution operation. The features of the first feature map FM1 are weighted and filtered through a convolution operation between the weights and the first feature map FM1. While shifting the first feature map FM1 in a sliding window manner, the weights are convolved with a window (and / or tile) of the first feature map FM1. During each shift, the weights can be multiplied by each pixel value of the overlapping window in the first feature map FM1, and the weights can be summed. Since the first feature map FM1 and the weights are convolved, one channel of the second feature map FM2 can be generated. Although in Figure 3 The figure shows a single weight. In reality, multiple weights can be convolved with the first feature map FM1 to generate a second feature map FM2 with multiple channels.

[0067] The second feature map FM2 can correspond to the input feature map of the next layer. For example, the second feature map FM2 can be the input feature map of a pooling (or subsampling) layer.

[0068] For convenience, Figure 2 and Figure 3 A schematic architecture of neural network 2 is shown. However, neural network 2 may include more or fewer layers, feature maps, and weights, and those skilled in the art will understand that various modifications can be made to the dimensions of the layers, feature maps, and weights.

[0069] Figure 4A and Figure 4B This is a diagram illustrating, according to some example embodiments, an operation performed in a crossbar array and a vector-matrix multiplication.

[0070] Reference Figure 4A Vector-matrix multiplication can be used to perform convolution operations between the input feature map and the weights. For example, the pixel data of the input feature map can be represented as matrix X 410, and the weight values ​​can be represented as matrix W 411. The pixel data of the output feature map can be represented as matrix Y 412, which can be the result of the product between matrix X 410 and matrix W 411.

[0071] Reference Figure 4BVector matrix multiplication operations can be performed using non-volatile memory devices in a transverse array. Figure 4A For comparison, pixel data of the input feature map can be received as input values ​​for the non-volatile storage device, where the input value can be voltage 420. Furthermore, weight values ​​can be stored in the synapses of the non-volatile storage device (e.g., memory cells), and the weight values ​​stored in the memory cells can be the conductance 421 of the synapses. Therefore, the output value of the non-volatile storage device can be represented as current 422, which is the result of the interaction between voltage 420 and conductance 421.

[0072] Figure 5 This is a diagram used to illustrate examples of performing convolution operations in a cross array according to some example embodiments.

[0073] The transverse array 500 can receive pixel data from the input feature map 510. The transverse array 500 may include multiple non-volatile storage devices.

[0074] In some example embodiments, when the transverse array 500 is an N×M matrix (where N and M are natural numbers equal to or greater than 2), the number of pixel data in the input feature map 510 can be equal to or less than the number of columns M of the transverse array 500. The pixel data of the input feature map 510 can represent parameters in floating-point and / or fixed-point formats. In another example embodiment, the number of pixel data in the input feature map 510 can be greater than the number of columns M of the transverse array 500, and reference will be made to... Figure 6 Provide a detailed description.

[0075] The digital-to-analog converter (DAC) 520 can be configured to receive pixel data of digital signal type and convert the pixel data into voltage of analog signal type. The pixel data input to feature map 510 can have various bit resolution values, such as 1-bit, 4-bit, or 8-bit resolution. In some example embodiments, after the pixel data is converted into voltage using DAC 520, the transverse array 500 can be configured to receive voltage 501 as the input value of transverse array 500.

[0076] Furthermore, the trained weight values ​​can be stored separately in multiple non-volatile storage devices included in the transverse array 500. The weight values ​​can be stored in the storage cells of the non-volatile storage devices, where the weight value stored in the storage cell can be a conductance 502. Here, the transverse array 500 can calculate the output value by performing a multiplication between voltage 501 and conductance 502, and the output value can be represented as current 503. For example, the transverse array 500 can output the same result value as the result of performing a convolution operation between the input feature map and the weights using multiple non-volatile storage devices.

[0077] Since the current 503 output from the cross array 500 is an analog signal, an analog-to-digital converter (ADC) 530 can be used to convert the current 503 into input data for another cross array 550. The current 503 output from the cross array 500 can be converted into a digital signal by the ADC 530. In some example embodiments, the current 503 can be converted into a digital signal using the ADC 530 to have the same bit resolution as the pixel data of the input feature map 510. For example, when the pixel data of the input feature map 510 has a 1-bit resolution, the current 503 can be converted into a 1-bit resolution digital signal by the ADC 530.

[0078] Activator 540 can apply an activation function to the digital signal obtained by conversion through ADC 530. The activation function may include a sigmoid function, a tanh function, and / or a rectified linear unit (ReLU) function, but the activation functions that can be applied to digital signals are not limited to these.

[0079] A digital signal with an applied activation function can be used as an input value for another transverse array 550. When a digital signal with an applied activation function is used as an input value for another transverse array 550, the same process described above can be applied to that other transverse array 550.

[0080] Figure 6 This is a diagram used to describe an example of matching between a crossbar array and a sub-feature map according to some example embodiments.

[0081] The input feature map 610 used for training and inference can have various sizes. Here, since the size of the transverse array 600 is limited, the number of pixel data in a single input feature map 610 can be greater than the number of input values ​​that the transverse array 600 can receive.

[0082] Reference Figure 6 The input feature map 610 has a size of 8×8, and the matrix array 600 has a size of 16×16. In this case, the number of pixel data in the 8×8 input feature map 610 is 64 (= 8×8), and is therefore greater than 16, which is the number of input values ​​that the matrix array 600 can receive.

[0083] When the number of pixel data in the input feature map 610 is greater than the number of input values ​​in the matrix array 600 (e.g., the number of rows m), the input feature map 610 can be divided into sub-feature maps 611. The input feature map 610 can be divided into sub-feature maps 611 based on the size information of the matrix array 600.

[0084] Specifically, when the size of the input feature map 610 is 8×8 and the size of the matrix array 600 is 16×16, the input feature map 610 can be divided into four sub-feature maps, such that the number of pixel data in each sub-feature map can be 16. Each sub-feature map can be matched with the matrix array 600.

[0085] For example, the cross array 600 can be configured to receive pixel data as input values, such as receiving “aa” of sub-feature map 610 as a first input value “V1”, receiving “ab” of sub-feature map 610 as a second input value “V2”, and receiving “dd” of sub-feature map 610 as a 16th input value “V16”.

[0086] As referenced above Figure 5 As described, the pixel data of the sub-feature map 610 can be a digital signal (e.g., a 1-bit signal, a 4-bit signal, etc.) and can be converted into analog voltage signals V1 to V2 via a DAC. 16 It is then input into the 600-axis horizontal and vertical array.

[0087] In addition, the current I1 to I output from the crossbar array 600 16 It can be an analog signal, and can be converted into a digital signal by an ADC.

[0088] Figure 7A and 7B This is a side view illustrating a non-volatile memory device with phototransistor and storage characteristics according to some example embodiments.

[0089] Non-volatile memory devices 710 and 720 may include resistive switching layers 715 and 725. Gates 713 and 723 may be on (e.g., above and / or below) resistive switching layers 715 and 725. Gate oxide layers 714 and 724 may be between resistive switching layers 715 and 725 and gates 713 and 723. Furthermore, sources 711 and 721 and drains 712 and 722 may be on resistive switching layers 715 and 725 and may be spaced apart from each other. Non-volatile memory devices 710 and 720 may include synapses 30 as described above, wherein gates 713 and 723 and drains 712 and 722 are respectively connected to presynaptic neuron 10 and postsynaptic neuron 20.

[0090] In some example embodiments, when light is shone onto the resistive switching layers 715 and 725, a cutoff voltage is applied to the gates 713 and 723, and a reference voltage is applied. Figure 8 Provide a detailed description.

[0091] The resistance values ​​of the resistance switching layers 715 and 725 can be changed based on the illuminance of the light illuminating the resistance switching layers 715 and 725, and can be maintained at the changed resistance values.

[0092] For example, as light shines on the resistance switching layers 715 and 725, charges (e.g., electrons and / or holes) may be trapped in internal defects of the resistance switching layers 715 and 725. Charges may be generated in the resistance switching layers 715 and 725, for example, through photoelectric response to light between the resistance switching layers 715 and 725. Since the charges are trapped in the internal defects of the resistance switching layers 715 and 725, the resistance values ​​of the resistance switching layers 715 and 725 can be changed, and then the resistance values ​​of the resistance switching layers 715 and 725 can be maintained at the changed resistance values ​​even when light is not shining on the resistance switching layers 715 and 725.

[0093] As the illuminance of light illuminating the resistance switching layers 715 and 725 increases, the rate of decrease in the resistance value of the resistance switching layers 715 and 725 can increase. Specifically, as the illuminance of light illuminating the resistance switching layers 715 and 725 increases, the charge trapped in the internal defects of the resistance switching layers 715 and 725 can increase. When the charge trapped in the resistance switching layers 715 and 725 increases, the resistance value of the resistance switching layers 715 and 725 may decrease.

[0094] In some example embodiments, the light illuminating the resistance switching layers 715 and 725 can be light in the visible light region. The resistance switching layers 715 and 725 can include the materials described below, such that the resistance values ​​of the resistance switching layers 715 and 725 can be changed even when light in the visible light region, rather than high-energy light such as ultraviolet (UV) light, irradiates the resistance switching layers 715 and 725.

[0095] In some example embodiments, the resistance switching layers 715 and 725 may comprise two-dimensional (2D) materials. The resistance switching layers 715 and 725 may comprise a single-layer 2D material or a multi-layer 2D material. For example, the resistance switching layers 715 and 725 may comprise at least one of transition metal dichalcogenides (TMD), phosphorus (black phosphorus), silicene, and / or graphene. For example, the TMD may comprise at least one and / or a combination of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, TaS2, TaSe2, TiS2, TiSe2, ZrS2, ZrSe2, HfS2, HfSe2, SnS2, SnSe2, GeS2, GeSe2, GaS2, GaSe2, GaSe, GaTe, InSe, In2Se3, Bi2S3, Bi2Se3, and Bi2Te3.

[0096] In another example embodiment, resistor switching layers 715 and 725 may comprise a three-dimensional (3D) material. For example, resistor switching layers 715 and 725 may comprise at least one and / or a combination of germane, silicon, group III-V semiconductors, indium-based semiconductors such as indium gallium zinc oxide (IGZO).

[0097] In some example embodiments, gate oxide layers 714 and 724 may be formed as a single layer. For example, gate oxide layers 714 and 724 may be formed as a single layer of aluminum oxide.

[0098] In another example embodiment, gate oxide layers 714 and 724 may be formed as a multilayer. Gate oxide layers 714 and 724 may include charge trapping layers. For example, gate oxide layers 714 and 724 may have a structure in which the charge trapping layer is located between two aluminum oxide layers. The charge trapping layer may include, but is not limited to, at least one of hafnium oxide and / or silicon nitride.

[0099] Figure 7A A non-volatile memory device 710 using a back gate 713 is shown. The back gate 713 may be located below the resistor switching layer 715. For example, the back gate 713 may be implemented using suitable techniques, such as silicon-on-insulator (SOI) substrate technology.

[0100] The gate oxide layer 714 can be disposed below the resistor switching layer 715 and between the resistor switching layer 715 and the back gate 713.

[0101] Figure 7B A non-volatile memory device 720 using a transparent conductive electrode (TCE) gate 723 is shown. The TCE gate 723 can be disposed above a resistive switching layer 725. Figure 7A and 7B In this context, "above" and "below" can refer to the position of the gate relative to the potential light source.

[0102] Since the light shines onto the resistor switching layer 725 from above, it reaches the TCE gate 723 before reaching the resistor switching layer 725. Because the non-volatile memory device 720 uses a light-transmitting TCE gate 723, light can reach the resistor switching layer 725 from above.

[0103] The gate oxide layer 724 can be disposed above the resistor switching layer 725 and between the resistor switching layer 725 and the TCE gate 723.

[0104] Figure 8 It is a graph used to describe the change in the resistance of a non-volatile memory device before and after light is irradiated onto it.

[0105] Non-volatile memory devices may include a resistive switching layer. A gate may be disposed above and / or below the resistive switching layer. A gate oxide layer may be located between the resistive switching layer and the gate. Furthermore, a source and a drain may be formed on the resistive switching layer and may be spaced apart from each other.

[0106] When a cutoff voltage is applied to the gate of a non-volatile memory device, the non-volatile memory device can be used as a device with phototransistor and storage characteristics. In the following text, it is assumed that the non-volatile memory device is an N-type metal-oxide-semiconductor (NMOS) device; however, it will be apparent to those skilled in the art that a non-volatile memory device can be implemented as various types of field-effect transistors (FETs), such as variable-resistance FETs.

[0107] The first curve 810 indicates the time before light shines on the non-volatile memory device, based on the gate voltage V. G Current I detected from the source of a non-volatile memory device S .

[0108] The second curve 820 indicates the effect of light irradiating the non-volatile memory device, based on the gate voltage V. G Current I detected from the source of a non-volatile memory device S .

[0109] Regarding the first curve 810 and the second curve 820, the voltage V D It is applied to the drain of a non-volatile memory device.

[0110] Because the charge is trapped in internal defects in the resistive switching layer of the non-volatile memory device, even if the gate voltage V of the non-volatile memory device... G Even at the cutoff voltage, a constant current I can be detected from the source. S .

[0111] The resistance of the resistive switching layer can be reduced because more charge is trapped in defects when light shines on the resistive switching layer of a non-volatile memory device. Subsequently, even without light shining on the resistive switching layer, its resistance can be maintained at the reduced value.

[0112] Referring to the first curve 810, when a cutoff voltage is applied to the gate of a non-volatile memory device, the current detected from the source is I1.

[0113] Referring to the second curve 820, which indicates the current detected from the source of the non-volatile memory device after light is irradiated onto the non-volatile memory device, the current detected from the source can increase from I1 to I2 when a cutoff voltage is applied to the gate of the non-volatile memory device. Since light is irradiated onto the resistive switching layer of the non-volatile memory device, the resistance value of the resistive switching layer decreases, and therefore, the current detected from the source of the non-volatile memory device increases. Thereafter, even if light is not irradiated onto the resistive switching layer of the non-volatile memory device, the resistance value of the resistive switching layer can be maintained at a variable value, and the current detected from the source can remain at I2 when a cutoff voltage is applied to the gate of the non-volatile memory device.

[0114] In some example embodiments, as the illuminance of light illuminating the resistive switching layer of the non-volatile memory device increases, the charge trapped in the resistive switching layer can increase, and therefore the resistance value of the resistive switching layer can decrease. As a result, the current detected from the source of the non-volatile memory device can increase to more than I2.

[0115] Furthermore, when a turn-on voltage equal to or greater than a threshold is applied to the gate of the non-volatile memory device, the resistance value of the resistance switching layer of the non-volatile memory device can be reset. For example, a 7 V voltage can be applied to the gate for 10 seconds to reset the resistance value of the resistance switching layer.

[0116] As light is irradiated onto the resistive switching layer of the non-volatile memory device, when the source current increases from I1 to I2 at the gate cutoff voltage, the source current can decrease from I2 back to I1 when an on-state voltage equal to or greater than the threshold is applied to the gate of the non-volatile memory device.

[0117] Figure 9A and Figure 9B This is a diagram used to describe the process of storing and obtaining an image using a cross array comprising multiple non-volatile storage devices, according to some example embodiments.

[0118] although Figure 9A and 9B The image 910 is shown to have a size of 4×4, and the transverse array 900 has a size of 4×4. Those skilled in the art will understand that the size of the image 910 and the size of the transverse array 900 can be modified differently.

[0119] The transverse array 900 can include multiple non-volatile memory devices. Figure 9A and 9B In the diagram, non-volatile storage devices are represented as the positions (a, b) where the rows and columns of the 900 grid intersect.

[0120] Reference Figure 9AImages can be stored using a cross array 900 that includes multiple non-volatile storage devices.

[0121] A cutoff voltage can be applied to the gate of multiple non-volatile memory devices, and the drain voltage V can be applied to the gate of the device. D An image is stored using a transverse array 900 by applying a drain to multiple non-volatile memory devices.

[0122] Light with an illuminance corresponding to the image can be irradiated onto each of the plurality of nonvolatile memory devices to change the resistance value of the resistance switching layer of each of the plurality of nonvolatile memory devices.

[0123] Having multiple pixels P included in image 910 11 To P 14 P 21 To P 24 P 31 To P 34 and P 41 To P 44 Light corresponding to each pixel in the image can be illuminated to multiple non-volatile storage devices. For example, pixel P in image 910... 11 Light of corresponding illuminance can be irradiated onto the non-volatile storage device (1, 1), having the same pixel P as image 910. 21 Light with corresponding illuminance can be irradiated onto the non-volatile storage device (2, 1), which can then display pixels P with the same illuminance as image 910. 32 Light with corresponding illuminance is irradiated onto the non-volatile storage device (3, 2), and / or pixels P with the same illuminance as image 910 can be used. 44 Light of corresponding illuminance is irradiated onto the non-volatile storage device (4, 4).

[0124] The brightness of each pixel in the plurality of pixels included in image 910 can be different from each other; therefore, the illuminance of light illuminating each of the plurality of non-volatile memory devices can be different from each other. As a result, the change in resistance value of the resistance switching layer of each of the plurality of non-volatile memory devices may be different from each other. Even if no light is illuminating the plurality of non-volatile memory devices, the resistance value of the resistance switching layer can be maintained at a changing value.

[0125] For example, even after the resistance value of each of the plurality of non-volatile memory devices is changed according to the brightness of each of the plurality of pixels included in the image 910, and the light is no longer emitted, the resistance value of each of the plurality of non-volatile memory devices is maintained at the changed value, so the image 910 can be stored in the cross array 900.

[0126] Furthermore, R shown on the cross-array 900 11 To R14 R 21 To R 24 R 31 To R 34 and R 41 To R 44 This represents the resistance value of each of a plurality of non-volatile storage devices.

[0127] Reference Figure 9B The stored image can be obtained using a cross array 900 that includes multiple non-volatile storage devices.

[0128] A gate cutoff voltage can be applied to each row of the transverse array 900 to obtain an image stored in the transverse array 900. Figure 9B In the illustrated cross array 900, non-volatile memory devices to which gate cutoff voltages are applied are marked with circles.

[0129] For example, a gate cutoff voltage can be applied to the first row 901a of the cross array 900 to obtain a pixel P included in the first row of the image 910. 11 To P 14 The gate on-state voltage can be sequentially applied to rows 901b through 901d from the second to the fourth row.

[0130] The resistance values ​​R of the non-volatile storage devices (1,1) to (1,4) can be used as a reference. 11 To R 14 Determine the source current IS obtained from each column of the 900-column array. 11 To IS 14 According to the pixel P included in the first row of image 910. 11 To P 14 The resistance value R of the non-volatile memory device is determined by the corresponding illuminance of light. 11 To R 14 Therefore, pixel P is included in the first row of image 910. 11 To P 14 The source current IS obtained from each column of the 900-column array can be used. 11 To IS 14 To obtain.

[0131] Similarly, the pixels included in the second to fourth rows of the image 910 can be obtained sequentially by applying a gate cut-off voltage to each of the second to fourth rows 901b to 901d of the cross array 900 and applying a gate turn-on voltage to the remaining rows.

[0132] In some example embodiments, color filters may be arranged sequentially on the transverse array 900 to obtain a color image from the transverse array 900.

[0133] For example, a color image can be obtained from the transverse array 900 using three color filters, including red, green, and / or blue filters.

[0134] For example, after arranging a red color filter on the transverse array 900, light with an illuminance corresponding to each of the plurality of pixels included in the color image can be irradiated onto each of the plurality of non-volatile memory devices. A red image can be obtained by applying a gate cutoff voltage to each row of the transverse array 900 and obtaining a source current from each column of the transverse array 900.

[0135] After resetting the transverse array 900 by applying a gate on-state voltage, the above operation is repeated using a green color filter and a blue color filter to obtain a green image and a blue image. After obtaining the red, green, and blue images, a color image can be finally obtained by synthesizing the three images.

[0136] The transverse array 900, which includes a plurality of non-volatile storage devices according to the present disclosure, may have photoconductive (PC) characteristics, and due to these characteristics, the transverse array 900 may be used in imaging mode (image storage / acquisition).

[0137] Figure 10 This is a diagram used to describe the process of performing pooling operations of a neural network using a crossbar array comprising multiple non-volatile memory devices, according to some example embodiments.

[0138] although Figure 10 The image 1010 is shown to have a size of 8×8, and the matrix array 1000 has a size of 16×16. However, those skilled in the art will understand that the size of the image 1010 and the size of the matrix array 1000 can be modified in various ways. For example, the image 1010 may be an image representing the number "1" or "9", but is not limited thereto.

[0139] In some example embodiments, window 1011 may move one step on image 1010. The size of window 1011 may be determined based on the size of the landscape array 1000. In some example embodiments, the size of window 1011 may be determined based on the number of rows in the landscape array 1000. For example, if the number of rows in the landscape array 1000 is 16, the size of window 1011 may be 4×4.

[0140] In the following text, window 1011 is shifted by "1 step", and the size of window 1011 is 4×4. However, those skilled in the art will understand that various modifications can be made to the shift and size of window 1011.

[0141] A window 1011 at each location on image 1010 may include multiple pixels. For example, at a first location, window 1011 may include pixel P. 11 To P 14 P 21 To P 24 P 31 To P 34 and P 41 To P 44 Furthermore, window 1011 may include pixel P at a position shifted by one step from the first position. 12 To P 15 P 22 To P 25 P 32 To P 35 and P 42 To P 45 .

[0142] Light with illuminance corresponding to the plurality of pixels included in window 1011 can illuminate each column of the columnar array 1000. For example, light with illuminance corresponding to the plurality of pixels P included in window 1011 at a first position. 11 To P 14 P 21 To P 24 P 31 Light with the corresponding illuminance can illuminate the first column 1002a of the cross array 1000. That is, light with an illuminance corresponding to each of the 16 pixels included in the window 1011 at the first position can illuminate the 16 non-volatile memory devices included in the first column 1002a.

[0143] Similarly, light with an illuminance corresponding to the plurality of pixels included in window 1011 at position n can illuminate the nth column of the cross array 1000.

[0144] The gate cutoff voltage can be applied to the first to sixteenth rows 1001a to 1001p of the transverse array 1000. Additionally, the drain voltages V0 to V... 15 It can be applied to the first to sixteenth rows 1001a to 1001p of the transverse array 1000. Drain voltage V0 to V 15 It can be set as a mask for pooling operations.

[0145] Pooling operations can be performed by obtaining source currents from each column of the cross array 1000. For example, the first-to-first source current I obtained from the first column 1002a. S11 It can be a plurality of pixels P included in window 1011 at the first position. 11 To P 14 P 21To P 24 P 31 To P 34 and P 41 To P 44 The result of execution pooling.

[0146] Similarly, the first-second source current to the first-fifth source current I obtained from columns 1002b to 1002e in columns 2 to 5. S12 to I S15 This could be the result of pooling performed on window 1011 at positions 2 through 5.

[0147] Furthermore, since window 1011 can be located at 25 positions on image 1010, the pooling operation of the neural network can be completed by obtaining the pooling results performed on multiple pixels included in window 1011 at the first to twenty-fifth positions using the method described above.

[0148] The raster array 1000 according to this disclosure, which includes multiple non-volatile storage devices, can perform vector matrix operations (e.g., pooling operations), and the raster array 1000 can be used for in-memory computation by using this feature.

[0149] Figure 11 This is a diagram used to describe the process of performing convolution operations on a neural network using a crossbar array comprising multiple non-volatile memory devices, according to some example embodiments.

[0150] The crossbar array 1000 can store multiple weights included in a specific layer of a neural network. Multiple weights can be stored in the crossbar array 1000 by illuminating each of the multiple non-volatile memory devices of the crossbar array 1000 with light having an illuminance corresponding to each of the multiple weights included in the specific layer. (See above reference.) Figure 9A The specific method for this operation is described, and therefore omitted here.

[0151] In some example embodiments, a fully connected convolution operation can be performed using a transverse array 1000. Figure 11 In the middle, used for identification Figure 10 A fully connected convolution operation is performed on image 1010. For example, a fully connected convolution operation can be performed using a grid array 1000 to determine which number from 1 to 9 corresponds to image 1010.

[0152] The transverse array 1000 can be reset to perform fully connected convolution operations.

[0153] The drain voltage of the cross array 1000 can correspond to the input value of the fully connected layer. The first to fifth source currents IS, obtained from the cross array 1000 and corresponding to windows 1011 at the first to fifth positions, are the first to fifth source currents. 11 To IS 15 This can correspond to the input values ​​used for fully connected layers.

[0154] For example, the first-first source current to the first-fifth source current I can be... S11 to I S15 Converted to the first to fifth drain voltage V D11 To V D15 In addition, the first drain voltage V can be... D11 to the fifth drain voltage V D15 Apply to rows 1001a through 1001e respectively.

[0155] Image 1010 can be identified by obtaining the source current from each column of the cross array 1000. For example, the second-first source current I can be obtained from the first column 1002a. 11 Second - First source current I 11 This represents the probability that image 1010 will correspond to the digit "1". Furthermore, the second to ninth source currents I can be obtained from columns 1002b to 1002i, respectively. 12 to I 19 The second-to-second source current to the second-to-ninth source current I 12 to I 19 This indicates the probability that image 1010 will correspond to the numbers “2” through “9”.

[0156] Window 1011 can be located at 25 positions on image 1010, and the second to ninth source currents I obtained from the cross array 1000 are also available. 11 to I 19 This is merely the result of the full join operations performed on window 1011 at the first to fifth positions. That is, image 1010 can be ultimately identified by obtaining the result of the full join operations performed on window 1011 at the remaining positions on image 1010.

[0157] The above process can be repeated to obtain the second-first source current to the second-ninth source current I of the first to ninth columns 1002a to 1002i from the cross array 1000 based on the 25 source currents corresponding to the windows 1011 at the first to 25 positions. 11 to I 19 .

[0158] The second to ninth source currents I obtained from the first to ninth columns 1002a to 1002i of the cross array 1000 11 to I 19 It can indicate the probability that image 1010 will correspond to the digits "1" through "9". Image 1010 can ultimately be identified as the digit with the highest probability value among the digits "1" through "9". For example, when the second-first source current I... 11 When the value is at its maximum, image 1010 can ultimately be recognized as the number "1".

[0159] As the neural network is trained, multiple weights stored in a specific layer of the neural network can be updated. When a weight is updated, the updated weights can be stored in the transverse array 1000 by illuminating each of the multiple non-volatile memory devices with light having an illuminance corresponding to each updated weight after resetting the transverse array 1000. The transverse array 1000 can be widely used in the training and inference processes of neural networks.

[0160] The transverse array 1000, which includes a plurality of non-volatile storage devices according to the present disclosure, can perform vector matrix operations, and the transverse array 1000 can be used for training and inference processes for image recognition by using this feature.

[0161] In some example embodiments, the transverse array used in imaging mode (image storage / acquisition) can be used in recognition mode (neural network training / inference) after a reset. Therefore, a single transverse array can be used in both imaging and recognition modes.

[0162] Figure 12 This is a flowchart describing a method for performing a predetermined operation using a crossbar array according to some example embodiments. Figure 12 The method for performing the predetermined operation shown is related to the embodiments described above with reference to the accompanying drawings. Therefore, although omitted below, the description provided above with reference to the accompanying drawings can be applied to... Figure 12 The method.

[0163] The cross array described below may include multiple non-volatile memory devices. Each non-volatile memory device may include a resistor-switching layer. A gate may be disposed above or below the resistor-switching layer. A gate oxide layer may be formed between the resistor-switching layer and the gate. Furthermore, source and drain electrodes may be formed on the resistor-switching layer and may be spaced apart from each other.

[0164] Reference Figure 12 In operation 1210, a cutoff voltage can be applied to the gate of each of the plurality of non-volatile memory devices.

[0165] When a cutoff voltage is applied to the gate of a non-volatile memory device, the non-volatile memory device can be used as a device with phototransistor and storage characteristics. The gate cutoff voltage can be -6V, but is not limited to this.

[0166] Furthermore, the non-volatile memory device can be reset when an on-state voltage is applied to its gate.

[0167] In operation 1220, light having an illuminance corresponding to each of the plurality of elements can be irradiated onto each of the plurality of nonvolatile memory devices to change the resistance value of the resistance switching layer of each of the plurality of nonvolatile memory devices.

[0168] The resistance value of the resistance switching layer can be changed based on the illuminance of the light illuminating the resistance switching layer, and can be maintained at the changed resistance value. Specifically, since the charge is trapped in the internal defects of the resistance switching layer when light is illuminating it, the resistance value of the resistance switching layer can be changed, and then the resistance value of the resistance switching layer can be maintained at the changed resistance value even when no light is illuminating it.

[0169] As the illuminance of light illuminating the resistive switching layer increases, the rate of decrease in the resistance of the resistive switching layer can increase. As the illuminance of light illuminating the resistive switching layer increases, the charge trapped in the internal defects of the resistive switching layer can increase. When the charge trapped in the resistive switching layer increases, the resistance of the resistive switching layer can decrease.

[0170] As described above, in some example embodiments, the resistance switching layer may include a 2D material. For example, the resistance switching layer may include at least one selected from the group consisting of transition metal dichalcogenides (TMD), silicene, phosphorus (black phosphorus), and graphene.

[0171] Furthermore, the resistance switching layer may comprise a 3D material. For example, the resistance switching layer may comprise at least one material selected from the group consisting of germane, silicon, III-V semiconductors, and / or IGZO.

[0172] In operation 1230, a gate cutoff voltage can be applied to at least one row of the cross array and a source current can be obtained from each column of the cross array.

[0173] In some example embodiments, processor 1310 may be configured to operate and / or control the method described above for performing predetermined operations using a cross array. Processor 1310 may also be configured to acquire an image using a cross array. In this case, the plurality of elements may be a plurality of pixels included in the image.

[0174] Light with an illuminance corresponding to each of the plurality of pixels included in the image can be irradiated onto each of the plurality of non-volatile memory devices. The processor 1310 can acquire the image by applying a gate cutoff voltage to each row of the transverse array and obtaining a source current from each column of the transverse array.

[0175] Furthermore, color filters can be arranged sequentially on a cross array to obtain a color image from the cross array.

[0176] In some example embodiments, processor 1310 may use a crossbar array to perform neural network operations. In this case, the multiple elements may be multiple weights included in a specific layer of the neural network.

[0177] Light with an illuminance corresponding to each of a plurality of weights included in a specific layer of the neural network can be irradiated onto each of a plurality of non-volatile memory devices. Processor 1310 can perform neural network operations by applying a gate cutoff voltage to at least one row of a raster array and obtaining source current from each column of the raster array. For example, neural network operations may include, but are not limited to, pooling operations, convolution operations, and fully connected convolution operations.

[0178] In this disclosure, images can be stored using a matrix array, or stored images can be obtained from a matrix array. Furthermore, in this disclosure, images can be recognized by performing neural network operations using a matrix array.

[0179] Figure 13 This is a block diagram illustrating a storage system according to some example embodiments.

[0180] Reference Figure 13 The memory system 1300 may include a processor 1310 and at least one transpose array 1320. The processor 1310 may perform control operations on the transpose array 1320, and may, for example, provide the transpose array 1320 with an address (ADD) and a command (CMD) to perform data storage, retrieval, and erasure operations on the transpose array 1320. Furthermore, data to be stored or retrieved may be sent / received between the processor 1310 and the transpose array 1320.

[0181] The row and column array 1321 may include multiple non-volatile memory devices arranged in regions where multiple rows and multiple columns intersect. In some example embodiments, the non-volatile memory devices may include a resistor-switching layer. A gate may be above and / or below the resistor-switching layer. A gate oxide layer may be between the resistor-switching layer and the gate. Furthermore, the source and drain may be on the resistor-switching layer and may be spaced apart from each other.

[0182] Processor 1310 may include a storage / read controller 1311, a voltage controller 1312, and a data discriminator 1313. However, the above-described elements included in processor 1310 are merely examples, and those skilled in the art may exclude some elements or further include others.

[0183] The storage / read controller 1311 can be configured to generate address ADD and command CMD for performing data storage, read, and erase operations on the transpose array 1321. The voltage controller 1312 can be configured to generate voltage control signals for controlling at least one voltage used in the transpose array 1321. For example, the voltage controller 1312 can generate voltage control signals to control the level of voltage applied to the rows of the transpose array 1321 to read data from or store data in the transpose array 1321.

[0184] Data discriminator 1313 can be configured to discriminate data read from the row array 1320. For example, data discriminator 1313 can discriminate data read from the row array 1321 to determine whether each of the plurality of non-volatile memory devices included in the row array 1321 is in an on or off state. For example, once data is stored in the row array 1321, data discriminator 1313 can use a read voltage to discriminate the data status of the plurality of non-volatile memory devices included in the row array 1321 to determine whether the data has been properly stored in the non-volatile memory devices.

[0185] The processor 1310 and / or the included memory / read controller 1311, voltage controller 1312, and data discriminator 1313 may include: for example, processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), and programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0186] This embodiment can be implemented as a recording medium containing computer-executable instructions, such as program modules executed by a computer. Computer-readable media can include any available medium accessible to a computer, and can include all volatile and non-volatile media, as well as removable and non-removable media. Furthermore, computer-readable media can include all computer storage media and communication media. Computer storage media includes all volatile and non-volatile media, as well as removable and non-removable media that can be implemented by any method or technique for storing information such as computer-readable instructions, data structures, program modules, and / or other data. Communication media typically include other data modulated data signals, such as computer-readable instructions, data structures and program modules, or other transmission mechanisms, and includes any information transmission medium.

[0187] The above description is merely illustrative, and it will be readily understood that those skilled in the art can easily make modifications without departing from the technical concept of this disclosure or changing its essential features. Therefore, the above embodiments should be considered illustrative and not construed as restrictive. For example, each component described as a single type can be distributed, and similarly, the components described as being distributed can be implemented in a composite form.

[0188] According to this disclosure, a cross array comprising multiple non-volatile storage devices can have photoconductive properties and, due to these properties, can be used to store / acquire images.

[0189] Furthermore, according to this disclosure, the raster array can perform vector matrix operations, and the raster array can be used for the training and inference processes of neural networks by using this feature.

[0190] Furthermore, according to this disclosure, the crossbar array used in the imaging mode (image storage / acquisition) can be used in the recognition mode (neural network training / inference) after reset. Therefore, a single crossbar array can be used to perform both the imaging mode and the recognition mode.

[0191] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A transverse array adapted to store an image based on the illuminance of light incident upon it, the transverse array comprising a plurality of non-volatile storage devices, each of the plurality of non-volatile storage devices comprising: A resistance switching layer having a resistance value is configured to change the resistance value based on the illuminance of light illuminating it, and the resistance switching layer is configured to maintain the changed resistance value even if the light is not illuminating it. Gate on the resistor switching layer; Gate oxide layer between the resistor switching layer and the gate; and The source and drain electrodes are spaced apart from each other on the resistor switching layer. The gate includes a transparent conductive electrode gate above the resistance switching layer and configured to transmit the illuminated light, or The gate includes a back gate beneath the resistor switching layer. The cross array is adapted to store the image based on the illuminance of the light illuminating it, wherein the illuminating light corresponds to a plurality of pixels included in the image, by means of the change in the resistance value of the resistance switching layer of each of the plurality of non-volatile memory devices when light with illuminance corresponding to a plurality of elements illuminates the plurality of non-volatile memory devices.

2. The crosspoint array of claim 1, wherein, The resistance switching layer comprises a two-dimensional 2D material, which includes at least one of transition metal dichalcogenide (TMD), silicene, phosphorus, or graphene.

3. The crosspoint array of claim 2, wherein, The resistor switching layer is a single layer.

4. The crosspoint array of claim 2, wherein, The resistor switching layer is multi-layered.

5. The cross-array according to claim 1, wherein, The resistor switching layer comprises a three-dimensional 3D material, which includes at least one of germane, silicon, III-V semiconductor, or IGZO.

6. The cross-array according to claim 1, wherein, The gate oxide layer is a multilayer structure including a charge trapping layer.

7. The cross-array according to claim 1, wherein, The change in the resistance value of the resistor switching layer includes a decrease in the resistance value of the resistor switching layer as the illuminance of the light illuminating the resistor switching layer increases when a cutoff voltage is applied to the gate.

8. The cross-array according to claim 1, wherein, The resistor switching layer is configured to reset the resistance value when an on-state voltage is applied to the gate.

9. A method for performing operations using a crossbar array as described in claim 1, the method comprising: Apply a cutoff voltage to the gate of each of the multiple non-volatile memory devices; By illuminating the plurality of non-volatile memory devices with light having an illuminance corresponding to a plurality of elements, the resistance value of the resistance switching layer of each of the plurality of non-volatile memory devices is changed, and the changed resistance value of the resistance switching layer is maintained even when the light is not illuminating, wherein the illuminating light corresponds to a plurality of pixels included in an image; and A gate cutoff voltage is applied to at least one row of the cross array, and source current is obtained from each column of the cross array. The operation includes obtaining the image by applying a gate cutoff voltage to each row of the transverse array and obtaining source current from each column of the transverse array.

10. The method according to claim 9, wherein, The irradiation includes: sequentially arranging a plurality of color filters on the non-volatile storage devices, and irradiating each of the plurality of non-volatile storage devices with the light, and The operation includes: By applying a gate cutoff voltage to each row of the transverse array and obtaining a source current from each column of the transverse array, intermediate images corresponding to multiple color filters are obtained; and A color image is obtained by synthesizing intermediate images.

11. The method according to claim 9, wherein, The illumination includes: illuminating the plurality of non-volatile memory devices with light having an illuminance corresponding to multiple weights included in a specific layer of the neural network, and The operation includes performing a specific layer vector matrix operation by applying a gate cutoff voltage to at least one row of the transverse array and obtaining source current from each column of the transverse array.

12. The method according to claim 9, wherein, The illumination involves moving the window one step across the image and illuminating each column of the cross array with light having an illuminance corresponding to the plurality of elements included in the window.

13. A method for recognizing images using the transverse array as described in claim 1, the method comprising: Apply a cutoff voltage to the gate of each of the multiple non-volatile memory devices; Move the window one step over the image and illuminate each column of the cross array with light having an illuminance corresponding to the image included in the window; Pooling is performed by applying a gate cutoff voltage to at least one row of the cross array and obtaining a first source current from each column of the cross array. Multiple non-volatile memory devices are reset by applying an on-state voltage to the gate of each of the multiple non-volatile memory devices. A cutoff voltage is applied to the gate of each of the reset non-volatile memory devices. Light with illuminance corresponding to multiple weights included in a specific layer of a neural network is irradiated onto multiple non-volatile storage devices; The resistance value of the resistance switching layer of each of the plurality of nonvolatile memory devices is changed by irradiating the light, and the changed resistance value is maintained even when the light is not irradiated. A fully connected convolution operation is performed by applying a voltage corresponding to the first source current as a drain voltage to at least one row of the cross array and obtaining a second source current from each column of the cross array. and Image recognition based on the second source current.

14. A non-transitory computer-readable recording medium having a program recorded thereon for causing a computer to perform the method of any one of claims 9-13 when run on a computer.

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