Apparatus and method for notifying time and frequency resource allocation for multi-slot transmission

Abstract

The present disclosure provides an apparatus and method for notifying time and frequency resource allocation for multi-slot transmission. An apparatus for a UE includes a processor circuit, which is used to: generate a first index a based on the number n of additional time slots after a first time slot, the number S of available subchannels in each additional time slot, and the number m of allocated subchannels in each additional time slot, wherein the first time slot and the additional time slot are used to carry the same TB; based on n, S, m, and the index k of the starting subchannel for each additional time slot j to generate a second index b; to generate a third index I based on the sum of the first index a and the second index b; and to encode the third index I in the SCI of the PSCCH for transmission to a receiving UE. Other embodiments are also disclosed and claimed.

Description

[0001] Priority declaration

[0002] This application is based on and claims priority to U.S. Provisional Application Serial No. 62 / 938,093 filed on November 20, 2019. The entire contents of the application are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to the field of wireless communications, and in particular, to an apparatus and method for notifying time and frequency resource allocation for multi-slot transmission. Background Art

[0004] With the development of wireless communication, New Radio (NR) vehicle-to-everything (V2X) services can be implemented through various types of V2X applications, such as vehicle-to-vehicle (V2V), vehicle-to-pedestrian (V2P), vehicle-to-infrastructure (V2I), vehicle-to-network (V2N), etc. The present disclosure will provide a solution for notifying time and frequency resource allocation for multi-slot transmission in NR V2X. Summary of the invention

[0005] An aspect of the present disclosure provides an apparatus for a user equipment (UE), the apparatus comprising: a radio frequency (RF) interface; and a processor circuit, the processor circuit being coupled to the RF interface, wherein the processor circuit is used to: generate a first index a based on the number n of additional time slots after a first time slot, the number S of available subchannels in each of the additional time slots, and the number m of allocated subchannels in each of the additional time slots, wherein the first time slot and the additional time slot are used to carry the same transport block (TB); and generate an index k for a starting subchannel of each of the additional time slots based on the number n of additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and the index k for a starting subchannel of each of the additional time slots. j , to generate a second index b, where j∈{0,…,n-1}; generating a third index I based on the sum of the first index a and the second index b, where the third index I is used to notify the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots j Both; and encoding the third index I in the sidelink control information (SCI) of the physical sidelink control channel (PSCCH) for transmission to the receiving UE via the RF interface.

[0006] One aspect of the present disclosure provides an apparatus for a user equipment (UE), the apparatus comprising: a radio frequency (RF) interface; and a processor circuit, the processor circuit being coupled to the RF interface, wherein the processor circuit is used to: decode sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting UE via the RF interface to obtain a single index I; decode time resource signaling received from the transmitting UE via the RF interface to obtain the number n of additional time slots after a first time slot; obtain the number S of available subchannels in each of the additional time slots according to a resource pool configuration; and determine the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots based on the index I, the number n of additional time slots, and the number S of available subchannels in each of the additional time slots. j , where j∈{0,…,n-1}.

[0007] An aspect of the present disclosure provides a computer-readable medium having instructions stored thereon, which, when executed by a processor circuit, causes the processor circuit to: generate a first index a based on the number n of additional time slots following a first time slot, the number S of available subchannels in each of the additional time slots, and the number m of allocated subchannels in each of the additional time slots, wherein the first time slot and the additional time slot are used to carry the same transport block (TB); generate a first index a based on the number n of additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and the index k of the starting subchannel for each of the additional time slots; j , to generate a second index b, where j∈{0,…,n-1}; generating a third index I based on the sum of the first index a and the second index b, where the third index I is used to notify the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots j Both; and encoding the third index I in sidelink control information (SCI) of a physical sidelink control channel (PSCCH) for transmission to a receiving user equipment (UE), wherein n=1 or n=2.

[0008] The present disclosure provides a computer-readable medium having instructions stored thereon, which, when executed by a processor circuit, causes the processor circuit to: decode sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting user equipment (UE) to obtain a single index I; decode time resource signaling received from the transmitting UE to obtain the number n of additional time slots after a first time slot; obtain the number S of available subchannels in each of the additional time slots according to a resource pool configuration; and determine the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots based on the index I, the number n of additional time slots, and the number S of available subchannels in each of the additional time slots. j , where j∈{0,…,n-1}, where n=1 or n=2. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure will be illustrated by way of example and not limitation in the accompanying drawings in which like reference numerals refer to similar elements.

[0010] Figure 1 An example architecture of a system according to some embodiments of the present disclosure is shown.

[0011] Figure 2 A flow chart of a method for notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown.

[0012] Figure 3 An example of notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown.

[0013] Figure 4 A flow chart of a method for notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown.

[0014] Figure 5 An example of notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown.

[0015] Figure 6 Example components of a device according to some embodiments of the present disclosure are shown.

[0016] Figure 7 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium and performing any one or more of the methodologies discussed herein, according to some example embodiments.

[0017] Figure 8Examples of infrastructure equipment according to various embodiments are shown. DETAILED DESCRIPTION

[0018] The various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of the present disclosure to other persons skilled in the art. However, it will be readily understood by those skilled in the art that many alternative embodiments may be practiced using portions of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the illustrative embodiments. However, it will be readily understood by those skilled in the art that alternative embodiments may be practiced without these specific details. In other cases, well-known features may be omitted or simplified to avoid blurring the illustrative embodiments.

[0019] Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0020] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. The phrase generally does not refer to the same embodiment; however, it may. The terms "comprising," "having," and "including" are synonymous unless the context dictates otherwise. The phrases "A or B" and "A / B" mean "(A), (B), or (A and B)."

[0021] The 3rd Generation Partnership Project (3GPP) Radio Access Network (RAN) has completed a study item (SI) on NR-V2X, which is defined in 3GPP TR 38.885 V2.0.0 (2019-03) ("NR; Research for Vehicle-to-Everything (Release 16)", March 2019). In addition, 3GPP RAN approved a new work item (WI) to develop the corresponding fifth generation (5G) V2X specifications (3GPP RP-190766: "New WID for 5G V2X with NR Sidelink", LG Electronics, Huawei, March 2019), in particular, the NR-based sidelink (SL) part. The present disclosure will provide a solution for notifying time and frequency resource allocation for multi-slot transmission in NR V2X, in particular, the NR-based SL part.

[0022] In the case of resource sensing for resource selection, it is beneficial for the sidelink control information (SCI) of the physical sidelink control channel (PSCCH) to notify the physical sidelink shared channel (PSSCH) resources allocated for transmitting the same transport block (TB) in multiple time slots or transmission time intervals (TTIs). Since the SCI needs to be sent in the most robust physical layer format, each additional bit in the SCI affects the overall coverage. Therefore, the present disclosure will provide solutions for effectively notifying time and frequency resource allocation for multi-slot transmissions in NR V2X. Both mode 1 and mode 2 sidelink operations are applicable. In mode 1, the signaling includes reserving resources (allocated by the network) for future transmissions. In mode 2, resources are not allocated by the network. In both cases, the reservation for future transmissions is included in the SCI.

[0023] Figure 1 An example architecture of a system 100 according to some embodiments of the present disclosure is shown. The following description is provided for an example system 100 operating in conjunction with the Long Term Evolution (LTE) system standard and the 5G or New Radio (NR) system standard provided by the 3GPP Technical Specification (TS). However, the example embodiments are not limited in this regard, and the described embodiments may be applied to other networks that benefit from the principles described herein, such as future 3GPP systems (e.g., sixth generation (6G)) systems, Institute of Electrical and Electronics Engineers (IEEE) 802.16 protocols (e.g., wireless metropolitan area networks (MANs), Worldwide Interoperability for Microwave Access (WiMAX)), etc.), etc.

[0024] like Figure 1As shown, system 100 may include UE 101a and UE 101b (collectively referred to as "(one or more) UE 101"). As used herein, the term "user equipment" or "UE" may refer to a device with radio communication capabilities and may describe a remote user of network resources in a communication network. The terms "user equipment" or "UE" may be considered synonymous and may be referred to as a client, mobile phone, mobile device, mobile terminal, user terminal, mobile unit, mobile station, mobile user, subscriber, user, remote station, access agent, user agent, receiver, radio device, reconfigurable radio device, reconfigurable mobile device, etc. In addition, the term "user equipment" or "UE" may include any type of wireless / wired device or any computing device that includes a wireless communication interface. In this example, UE 101 is shown as a smart phone (e.g., a handheld touch screen mobile computing device that can connect to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as a consumer electronic device, a cellular phone, a smart phone, a feature phone, a tablet computer, a wearable computer device, a personal digital assistant (PDA), a pager, a wireless handheld device, a desktop computer, a laptop computer, an in-vehicle infotainment system (IVI), an in-vehicle entertainment (ICE) device, an instrument cluster (IC), a head-up display (HUD) device, an on-board diagnostic (OBD) device, a dashboard mobile equipment (DME), a mobile data terminal (MDT), an electronic engine management system (EEMS), an electronic / engine control unit (ECU), an electronic / engine control module (ECM), an embedded system, a microcontroller, a control module, an engine management system (EMS), a networked or "smart" device, a machine type communication (MTC) device, a machine to machine (M2M), an Internet of Things (IoT) device, and / or the like.

[0025] In some embodiments, any of the UEs 101 may include an IoT UE, which may include a network access layer designed for low-power IoT applications that utilize short-term UE connections. The IoT UE may utilize technologies such as M2M or MTC to exchange data with an MTC server or device via a PLMN, proximity-based services (ProSe) or device-to-device (D2D) communications, a sensor network, or an IoT network. The data exchange of M2M or MTC may be a machine-initiated data exchange. The IoT network describes interconnected IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure) with short-term connections. The IoT UE may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate connectivity to the IoT network.

[0026] UE 101 may be configured to connect (e.g., be communicatively coupled) to RAN 110. In an embodiment, RAN 110 may be a next generation (NG) RAN or 5G RAN, an evolved universal mobile telecommunications system (UMTS) terrestrial radio access network (E-UTRAN), or a traditional RAN, such as UTRAN (UMTS terrestrial radio access network) or GERAN (GSM (Global System for Mobile Communications or Groupe Spécial Mobile) EDGE (GSM Evolution) Radio Access Network). As used herein, the term "NGRAN" or the like may refer to RAN 110 operating in NR or 5G system 100, and the term "E-UTRAN" or the like may refer to RAN 110 operating in LTE or 4G system 100. UE 101 utilizes connections (or channels) 103 and 104, respectively, each connection comprising a physical communication interface or layer (discussed in further detail below). As used herein, the term "channel" may refer to any tangible or intangible transmission medium for transmitting data or data streams. The term "channel" may be synonymous and / or equivalent to "communication channel", "data communication channel", "transmission channel", "data transmission channel", "access channel", "data access channel", "link", "data link", "carrier", "radio frequency carrier" and / or any other similar terms representing a path or medium through which data is transmitted. In addition, the term "link" may refer to a connection between two devices over a radio access technology (RAT) for the purpose of sending and receiving information.

[0027] In this example, connections 103 and 104 are shown as air interfaces to achieve communication coupling, and may be consistent with a cellular communication protocol, such as a Global System for Mobile Communications (GSM) protocol, a Code Division Multiple Access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a Cellular PTT (POC) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a Fifth Generation (5G) protocol, a New Radio (NR) protocol, and / or any other communication protocol discussed herein. In an embodiment, the UE 101 may directly exchange communication data via a ProSe interface 105. The ProSe interface 105 may alternatively be referred to as a sidelink (SL) interface 105 and may include one or more logical channels, including but not limited to a physical sidelink control channel (PSCCH), a physical sidelink shared channel (PSSCH), a physical sidelink discovery channel (PSDCH), and a physical sidelink broadcast channel (PSBCH).

[0028] UE 101b is shown as being configured to access an access point (AP) 106 (also referred to as "WLAN node 106", "WLAN 106", "WLAN terminal 106", or "WT 106", etc.) via a connection 107. Connection 107 may include a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, where AP 106 would include a Wireless Fidelity (WiFi) router. In this example, AP 106 is shown as being connected to the Internet without being connected to a core network of a wireless system (described in further detail below). In various embodiments, UE 101b, RAN 110, and AP 106 may be configured to utilize LTE-WLAN aggregation (LWA) operation and / or WLAN LTE / WLAN radio level integration (LWIP) operation with IPsec tunneling. LWA operation may involve UE 101b in RRC_CONNECTED being configured by RAN node 111 to utilize radio resources of LTE and WLAN. LWIP operation may involve UE 101b using WLAN radio resources (e.g., connection 107) via an Internet Protocol security (IPsec) protocol tunnel to authenticate and encrypt packets (e.g., Internet Protocol (IP) packets) sent over connection 107. The IPsec tunnel may include encapsulating the entire original IP packet and adding a new packet header, thereby protecting the original header of the IP packet.

[0029] The RAN 110 may include one or more RAN nodes 111a and 111b (collectively referred to as “RAN node(s) 111”) that enable connections 103 and 104. As used herein, the terms “access node (AN)”, “access point”, “RAN node”, etc. may describe a device that provides radio baseband functionality for data and / or voice connections between a network and one or more users. These access nodes may be referred to as base stations (BS), next generation Node Bs (gNBs), RAN nodes, evolved NodeBs (eNBs), NodeBs, road side units (RSUs), transmission reception points (TRxPs or TRPs), etc., and may include ground stations (e.g., terrestrial access points) or satellite stations that provide coverage within a geographic area (e.g., a cell). As used herein, the terms “NGRAN nodes”, etc. may refer to RAN nodes 111 (e.g., gNBs) operating in NR or 5G systems 100, and the terms “E-UTRAN nodes”, etc. may refer to RAN nodes 111 (e.g., eNBs) operating in LTE or 4G systems 100. According to various embodiments, the RAN node 111 may be implemented as one or more dedicated physical devices such as a macro cell base station and / or a low power (LP) base station for providing a femto cell, a pico cell or other similar cells having a smaller coverage area, a smaller user capacity or a higher bandwidth than a macro cell.

[0030] In some embodiments, all or part of the RAN node 111 may be implemented as part of a virtual network as one or more software entities running on a server computer, which may be referred to as a cloud radio access network (CRAN) and / or a virtual baseband unit pool (vBBUP). In these embodiments, the CRAN or vBBUP may implement RAN functional splitting, such as: PDCP splitting, where the RRC and PDCP layers are operated by the CRAN / vBBUP, while other Layer 2 (L2) protocol entities are operated by individual RAN nodes 111; MAC / PHY splitting, where the RRC, PDCP, RLC, and MAC layers are operated by the CRAN / vBBUP, and the PHY layer is operated by an individual RAN node 111; or a "lower PHY" splitting, where the RRC, PDCP, RLC, MAC layer, and upper part of the PHY layer are operated by the CRAN / vBBUP, and the lower part of the PHY layer is operated by an individual RAN node 111. This virtualization framework allows the processor cores of the RAN node 111 to be freed up to execute other virtualized applications. In some implementations, an individual RAN node 111 may represent a RAN node 111 via an individual F1 interface ( Figure 1 The RAN 110 may include an individual gNB-DU (not shown) connected to the gNB-CU. In these implementations, the gNB-DU may include one or more remote radio heads or radio front end modules (RFEMs), and the gNB-CU may be operated by a server (not shown) located in the RAN 110 or by a server pool in a manner similar to CRAN / vBBUP. Additionally or alternatively, one or more RAN nodes 111 may be a next generation eNB (ng-eNB), which is a RAN node that provides E-UTRA user plane and control plane protocol terminations to the UE 101 and is connected to the 5GC via an NG interface.

[0031] In a V2X scenario, one or more RAN nodes 111 may be or act as an RSU. The term "roadside unit" or "RSU" may refer to any transportation infrastructure entity used for V2X communications. The RSU may be implemented in or by a suitable RAN node or a fixed (or relatively stationary) UE, wherein an RSU implemented in or by a UE may be referred to as a "UE-type RSU", an RSU implemented in or by an eNB may be referred to as an "eNB-type RSU", an RSU implemented in or by a gNB may be referred to as a "gNB-type RSU", and the like. In one example, the RSU is a computing device coupled to a radio frequency circuit located on the roadside that provides connectivity support for a passing vehicle UE 101 (vUE 101). The RSU may also include internal data storage circuitry for storing intersection map geometry, traffic statistics, media, and applications / software for sensing and controlling ongoing vehicle and pedestrian traffic. The RSU can operate on the 5.9 GHz direct short-range communication (DSRC) band to provide very low latency communications required for high-speed events, such as collision avoidance, traffic warnings, etc. Additionally or alternatively, the RSU can operate on the cellular V2X band to provide the above-mentioned low-latency communications as well as other cellular communication services. Additionally or alternatively, the RSU can operate as a WiFi hotspot (2.4 GHz band) and / or provide connection to one or more cellular networks to provide uplink and downlink communications. The computing device(s) and some or all of the RF circuits of the RSU can be packaged in a weatherproof enclosure suitable for outdoor installation, and can include a network interface controller to provide a wired (e.g., Ethernet) connection to a traffic signal controller and / or a backhaul network.

[0032] Any RAN node 111 may terminate the air interface protocol and may be the first point of contact for the UE 101. In some embodiments, any RAN node 111 may fulfill various logical functions of the RAN 110, including but not limited to Radio Network Controller (RNC) functions, such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0033] In an embodiment, UE 101 may be configured to communicate with each other or any RAN node 111 over a multi-carrier communication channel using orthogonal frequency division multiplexing (OFDM) communication signals according to various communication techniques, such as, but not limited to, orthogonal frequency division multiple access (OFDMA) communication techniques (e.g., for downlink communications) or single carrier frequency division multiple access (SC-FDMA) communication techniques (e.g., for uplink and ProSe or sidelink communications), although the scope of the embodiments is not limited in this respect. OFDM signals may include multiple orthogonal subcarriers.

[0034] In some embodiments, a downlink resource grid may be used for downlink transmissions from any RAN node 111 to UE 101, while uplink transmissions may use similar techniques. The grid may be a time-frequency grid, referred to as a resource grid or a time-frequency resource grid, which is the physical resource for each time slot in the downlink. This time-frequency plane representation is a common practice for OFDM systems, which makes radio resource allocation intuitive. Each column and row of the resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one time slot in a radio frame. The smallest time-frequency unit in the resource grid is represented as a resource element. Each resource grid includes a plurality of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block includes a set of resource elements; in the frequency domain, this may represent the minimum amount of resources that can currently be allocated. There are several different physical downlink channels that are transmitted using such resource blocks.

[0035] According to various embodiments, the UE 101 and the RAN node 111 communicate (e.g., send and receive) data over a licensed medium (also referred to as a "licensed spectrum" and / or a "licensed band") and an unlicensed shared medium (also referred to as an "unlicensed spectrum" and / or an "unlicensed band"). The licensed spectrum may include channels operating in a frequency range of approximately 400 MHz to approximately 3.8 GHz, and the unlicensed spectrum may include a 5 GHz band.

[0036] To operate in the unlicensed spectrum, the UE 101 and the RAN node 111 may operate using license assisted access (LAA), enhanced LAA (eLAA), and / or other eLAA (feLAA) mechanisms. In these implementations, the UE 101 and the RAN node 111 may perform one or more known medium sensing operations and / or carrier sensing operations to determine whether one or more channels in the unlicensed spectrum are unavailable or otherwise occupied before transmitting in the unlicensed spectrum. The medium / carrier sensing operations may be performed according to a listen-before-talk (LBT) protocol.

[0037] LBT is a mechanism in which a device (e.g., UE 101, RAN nodes 111, 112, etc.) senses the medium (e.g., a channel or carrier frequency) and transmits when the medium is sensed to be idle (or when a particular channel in the medium is sensed to be unoccupied). The medium sensing operation may include a clear channel assessment (CCA), which utilizes at least energy detection (ED) to determine whether other signals are present on the channel in order to determine whether the channel is occupied or idle. The LBT mechanism allows cellular / LAA networks to coexist with incumbent systems in unlicensed spectrum and with other LAA networks. ED may include sensing radio frequency (RF) energy over an expected transmission band for a period of time and comparing the sensed RF energy to a predetermined or configured threshold.

[0038] Typically, the incumbent system in the 5 GHz band is a WLAN based on IEEE 802.11 technology. WLAN adopts a contention-based channel access mechanism called carrier sense multiple access with collision avoidance (CSMA / CA). Here, when a WLAN node (e.g., a mobile station (MS) such as UE 101, AP 106) intends to transmit, the WLAN node may first perform CCA before transmitting. In addition, a backoff mechanism is used to avoid conflicts in the case where more than one WLAN node senses the channel as idle and transmits at the same time. The backoff mechanism may be a counter randomly drawn within the contention window size (CWS), which increases exponentially when a conflict occurs and is reset to a minimum value when the transmission is successful. The LBT mechanism designed for LAA is somewhat similar to CSMA / CA for WLAN. In some implementations, the LBT process for a DL or UL transmission burst including a PDSCH or PUSCH transmission, respectively, may have a LAA contention window of variable length between X and Y extended CCA (ECCA) slots, where X and Y are the minimum and maximum values ​​of the CWS for LAA. In one example, the minimum CWS for LAA transmissions may be 9 microseconds (μs); however, the size of the CWS and the maximum channel occupancy time (MCOT) (eg, transmission burst) may be based on government regulatory requirements.

[0039] The LAA mechanism is based on the carrier aggregation (CA) technology of the LTE Advanced (LTE-Advanced) system. In CA, each aggregated carrier is called a component carrier (CC). A CC can have a bandwidth of 1.4, 3, 5, 10, 15, or 20 MHz, and up to five CCs can be aggregated, so the maximum aggregate bandwidth is 100 MHz. In a frequency division duplex (FDD) system, the number of aggregated carriers can be different for DL ​​and UL, where the number of UL CCs is equal to or lower than the number of DL component carriers. In some cases, an individual CC may have a different bandwidth from other CCs. In a time division duplex (TDD) system, the number of CCs and the bandwidth of each CC are typically the same for DL ​​and UL.

[0040] CA also includes separate serving cells to provide separate CCs. The coverage of the serving cells may be different, for example, because CCs on different frequency bands will experience different path losses. The primary serving cell or primary cell (PCell) can provide a primary CC (PCC) for both UL and DL, and can handle radio resource control (RRC) and non-access stratum (NAS) related activities. Other serving cells are called secondary cells (SCells), and each SCell can provide a separate secondary CC (SCC) for both UL and DL. SCCs can be added and removed as needed, and changing PCCs may require UE 101 to undergo switching. In LAA, eLAA, and feLAA, some or all SCells can operate in an unlicensed spectrum (referred to as "LAA SCells"), and the LAA SCells are assisted by PCells operating in licensed spectrum. When a UE is configured with more than one LAA SCell, the UE can receive an UL grant on the configured LAA SCell, which indicates different physical uplink shared channel (PUSCH) starting positions within the same subframe.

[0041] The physical downlink shared channel (PDSCH) may carry user data and higher layer signaling to the UE 101. The physical downlink control channel (PDCCH) may carry information about the transport format and resource allocation related to the PDSCH channel, among other things. It may also inform the UE 101 of the transport format, resource allocation, and H-ARQ (Hybrid Automatic Repeat Request) information related to the uplink shared channel. Typically, downlink scheduling (allocation of control and shared channel resource blocks to UE 101b within a cell) may be performed at any RAN node 111 based on channel quality information fed back from any UE 101. Downlink resource allocation information may be sent on the PDCCH for (e.g., allocated to) each UE 101.

[0042] PDCCH can use control channel elements (CCE) to convey control information. Before mapping to resource elements, PDCCH complex symbols can first be organized into four tuples, which can then be permuted using a sub-block interleaver for rate matching. Each PDCCH can be sent using one or more of these CCEs, where each CCE can correspond to nine groups of four physical resource elements called resource element groups (REGs). Four quadrature phase shift keying (QPSK) symbols can be mapped to each REG. PDCCH can be sent using one or more CCEs, depending on the size of the downlink control information (DCI) and channel conditions. Four or more different PDCCH formats (e.g., aggregation levels, L=1, 2, 4, or 8) with different numbers of CCEs can be defined in LTE.

[0043] Some embodiments may use the concept of resource allocation for control channel information, which is an extension of the above concept. For example, some embodiments may use an enhanced physical downlink control channel (EPDCCH), which uses PDSCH resources for control information transmission. One or more enhanced control channel elements (ECCEs) may be used to send EPDCCH. Similar to the above, each ECCE may correspond to nine groups of four physical resource elements referred to as enhanced resource element groups (EREGs). In some cases, ECCEs may have other numbers of EREGs.

[0044] The RAN nodes 111 may be configured to communicate with each other via an interface 112. In an embodiment where the system 100 is an LTE system, the interface 112 may be an X2 interface 112. The X2 interface may be defined between two or more RAN nodes 111 (e.g., two or more eNBs, etc.) connected to the EPC 120 and / or between two eNBs connected to the EPC 120. In some implementations, the X2 interface may include an X2 user plane interface (X2-U) and an X2 control plane interface (X2-C). The X2-U may provide a flow control mechanism for user data packets transmitted over the X2 interface, and may be used to transmit information about user data transfer between eNBs. For example, the X2-U may provide specific sequence number information for user data transmitted from a master eNB (MeNB) to a secondary eNB (SeNB); information about successfully transmitting PDCP PDUs in sequence from the SeNB to the UE 101 for user data; information about PDCP PDUs that are not delivered to the UE 101; information about the current minimum required buffer size at the SeNB for sending user data to the UE; and the like. X2-C can provide intra-LTE access mobility functions, including context transfer from the source eNB to the target eNB, user plane transmission control, etc.; load management functions; and inter-cell interference coordination functions.

[0045] In an embodiment where the system 100 is a 5G or NR system, the interface 112 may be an Xn interface 112. The Xn interface is defined between two or more RAN nodes 111 (e.g., two or more gNBs, etc.) connected to the 5GC 120, between a RAN node 111 (e.g., a gNB) and an eNB connected to the 5GC 120, and / or between two eNBs connected to the 5GC 120. In some implementations, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. The Xn-U may provide unguaranteed delivery of user plane PDUs and support / provide data forwarding and flow control functions. The Xn-C may provide: management and error handling functions; functions for managing the Xn-C interface; mobility support for UE 101 in connected mode (e.g., CM-CONNECTED), including functions for managing UE mobility in connected mode between one or more RAN nodes 111. Mobility support may include context transfer from the old (source) serving RAN node 111 to the new (target) serving RAN node 111; and control of the user plane tunnel between the old (source) serving RAN node 111 and the new (target) serving RAN node 111. The protocol stack of Xn-U may include a transport network layer built on an Internet Protocol (IP) transport layer, and a GTP-U layer on top of (one or more) UDP and / or IP layers for carrying user plane PDUs. The Xn-C protocol stack may include an application layer signaling protocol (referred to as the Xn Application Protocol (Xn-AP)) and a transport network layer built on SCTP. SCTP may be located above the IP layer and may provide guaranteed delivery of application layer messages. In the transport IP layer, point-to-point transport is used to deliver signaling PDUs. In other implementations, the Xn-U protocol stack and / or the Xn-C protocol stack may be the same or similar to the (one or more) user plane and / or control plane protocol stacks shown and described herein.

[0046] RAN 110 is shown communicatively coupled to a core network, in this embodiment, a core network (CN) 120. CN 120 may include a plurality of network elements 122 configured to provide various data and telecommunication services to customers / subscribers (e.g., users of UE 101) connected to CN 120 via RAN 110. The term "network element" may describe a physical or virtualized device used to provide wired or wireless communication network services. The term "network element" may be considered synonymous with and / or referred to as: a networked computer, network hardware, network equipment, router, switch, hub, bridge, radio network controller, radio access network equipment, gateway, server, virtualized network function (VNF), network function virtualization infrastructure (NFVI), and / or the like. The components of CN 120 may be implemented in one physical node or separate physical nodes, including components that read and execute instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In some embodiments, network function virtualization (NFV) may be used to virtualize any or all of the above-described network node functions (described in further detail below) via executable instructions stored in one or more computer-readable storage media. A logical instantiation of CN 120 may be referred to as a network slice, and a logical instantiation of a portion of CN 120 may be referred to as a network sub-slice. The NFV architecture and infrastructure may be used to virtualize one or more network functions, or to execute them by dedicated hardware onto physical resources including a combination of industry-standard server hardware, storage hardware, or switches. In other words, the NFV system may be used to perform a virtual or reconfigurable implementation of one or more EPC components / functions.

[0047] In general, the application server 130 may be an element that provides applications that use IP bearer resources with a core network (e.g., UMTS packet service (PS) domain, LTE PS data service, etc.). The application server 130 may also be configured to support one or more communication services (e.g., Voice over Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UE 101 via the EPC 120.

[0048] In an embodiment, the CN 120 may be a 5GC (referred to as “5GC 120” or the like), and the RAN 110 may be connected to the CN 120 via an NG interface 113. In an embodiment, the NG interface 113 may be divided into two parts: an NG user plane (NG-U) interface 114, which carries service data between the RAN node 111 and the user plane function (UPF); and an S1 control plane (NG-C) interface 115, which is a signaling interface between the RAN node 111 and the AMF.

[0049] In an embodiment, CN 120 may be a 5G CN (referred to as “5GC 120”, etc.), while in other embodiments, CN 120 may be an evolved packet core (EPC). In the case where CN 120 is an EPC (referred to as “EPC 120”, etc.), RAN 110 may be connected to CN 120 via an S1 interface 113. In an embodiment, S1 interface 13 may be divided into two parts: an S1 user plane (S1-U) interface 114, which carries service data between RAN node 111 and serving gateway (S-GW); and an S1-mobility management entity (MME) interface 115, which is a signaling interface between RAN node 111 and MME.

[0050] In order to notify the frequency resource allocation for multi-slot transmission, both the starting subchannel and the number of allocated subchannels are required. The starting subchannel and the number of allocated subchannels can be notified jointly or separately. First, the joint notification of frequency resource allocation for multi-slot transmission is described in detail below.

[0051] In the case where there are S available subchannels in a time slot and there are n time slots after the first time slot (the first time slot and the n time slot are to carry the same transport block (TB)), the number of different allocations (ranging from 1 to S) can be For the specific case of n=2, the number of different allocations can be The value of n may be obtained from separate time resource signaling.

[0052] Figure 2 A flow chart of a method 200 for notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown. The method 200 may be used to jointly notify a starting subchannel and the number of allocated subchannels. The method 200 may be performed by a transmitting UE and may include steps 210, 220, 230, and 240.

[0053] In 210, a first index a may be generated based on the number n of additional time slots after the first time slot, the number S of available subchannels in each additional time slot, and the number m of allocated subchannels in each additional time slot. As described above, the first time slot and the additional time slot are used to carry the same TB.

[0054] In some embodiments, the first index a may be determined by formula (1):

[0055]

[0056] Wherein, m is equal to or less than S.

[0057] In 220, the number of additional time slots n, the number of available subchannels S in each additional time slot, the number of allocated subchannels m in each additional time slot, and the index k of the starting subchannel for each additional time slot may be determined based on the number n of additional time slots, the number S of available subchannels in each additional time slot, the number m of allocated subchannels in each additional time slot, and the index k of the starting subchannel for each additional time slot. j (For example, a list of starting subchannel indices for each time slot: k 0 ,…,k n-1 ) to generate the second index b.

[0058] In some embodiments, the second index b may be determined by formula (2):

[0059]

[0060] In 230, a third index I may be generated based on the sum of the first index a and the second index b, as shown in formula (3):

[0061] I=a+b (3).

[0062] The third index I is used to notify m and k j In other words, the receiving UE can learn the frequency resource allocation for multi-slot transmission from a single third index.

[0063] In 240, the third index I may be encoded in the SCI of the PSCCH for transmission to the receiving UE.

[0064] In method 200, the sending UE may calculate the value of S, m, n and k based on the value of S, m, n and k. j A third index I is generated and included in the SCI for transmission to the receiving UE.

[0065] For example, in the case of n=2, the first index a can be determined based on formula (4), the second index b can be determined based on formula (5), and the third index I can be determined based on the above formula (3).

[0066]

[0067] b=k 0 +(S+1-m)k 1 (5)

[0068] For example, in the case where n=3, the first index a can be determined based on formula (6), the second index b can be determined based on formula (7), and the third index I can be determined based on the above formula (3).

[0069]

[0070] b=k 0 +(S+1-m)k 1+(S+1-m) 2 k 2 (7)

[0071] Figure 3 An example of notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown.

[0072] exist Figure 3 In the example of , it is assumed that there are three available subchannels in each time slot, and two time slots after the first time slot in the same TB, that is, S=3 and n=2 are defined as part of the pool definition. Figure 3 As shown, k 0 =0,k 1 =1. In addition, one subchannel is allocated in each time slot, that is, m=1. According to formulas (1) and (2) (or formulas (4) and (5)), a=0, b=3 are determined. According to formula (3), I=3 is determined.

[0073] In another example, n=1 is applicable. In yet another example, other values ​​of n are also applicable. The present disclosure is not limited in this respect.

[0074] Combination of the above Figure 2 and Figure 3 The embodiments described above are from the perspective of a transmitting UE. In other words, these embodiments describe an encoding process for notifying frequency resource allocation for multi-slot transmission. Some embodiments will be described below from the perspective of a receiving UE, i.e., a decoding process for notifying frequency resource allocation for multi-slot transmission will be described.

[0075] Figure 4 A flow chart of a method 400 for notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown. The method 400 may be performed by a receiving UE and may include steps 410, 420, 430, and 440.

[0076] In 410, the SCI of the PSCCH received from the transmitting UE may be decoded to obtain a single index I. The index I may inform the frequency resource allocation for multi-slot transmission.

[0077] In 420, the time resource signaling received from the transmitting UE may be decoded to obtain the number n of additional time slots after the first time slot. The first time slot and the additional time slot are used to carry the same TB.

[0078] In 430, the number S of available subchannels in each additional time slot may be obtained according to the resource pool configuration.

[0079] In 440, the number m of allocated subchannels in each additional time slot and the index k of the starting subchannel for each additional time slot may be determined based on the index I, the number n of additional time slots, and the number S of available subchannels in each additional time slot. j .

[0080] In some embodiments, the first sub-index a can be determined based on formula (8): m :

[0081]

[0082] The number m of allocated subchannels in each additional time slot can be determined based on formula (9):

[0083] a m ≤I m+1 , where a 1 =0,a S+1 =∞ (9).

[0084] In some embodiments, the value of a can be calculated based on I minus a. m To determine the second sub-index b, as shown in formula (10):

[0085] b=Ia m (10).

[0086] The index k of the starting subchannel for each additional time slot can be determined based on formula (11): j :

[0087]

[0088] Among them, modulo represents the modulo operation.

[0089] Figure 5 An example of notifying frequency resource allocation for multi-slot transmission according to some embodiments of the present disclosure is shown.

[0090] exist Figure 5 In the example of , it is assumed that there are three available subchannels in each time slot, and there are two time slots after the first time slot in the same TB, that is, the receiving UE obtains S=3 and n=2 from the resource pool configuration and time resource signaling, respectively. Figure 5 In the example, it is assumed that the receiving UE receives I=11 from the sending UE. According to formula (8), a is determined m = {0,9,13,∞}. According to formula (9), m = 2. According to formula (10), b = 2. According to formula (11), k 0 = 0 and k 1 =1. ​

[0091] Using the above method for notifying frequency resource allocation for multi-slot transmission according to some embodiments, the receiving UE can determine the number m of allocated subchannels in each additional time slot and the index k of the starting subchannel for each additional time slot according to the single index I received in the SCI. j Both. In other words, using the above method, the receiving UE can know the frequency resource allocation for multi-slot transmission based on the single index I received in the SCI. In this way, the minimum number of bits in the SCI is transmitted. This enables the control channel to obtain the maximum coverage with the minimum signaling overhead.

[0092] Some embodiments of jointly notifying frequency resource allocation for multi-slot transmission are described above. There are also some other methods for jointly notifying frequency resource allocation for multi-slot transmission. For example, if only one time slot is allocated after the first time slot, that is, n=1, then only the number of subchannels allocated for the time slot can be notified. If two time slots are allocated after the first time slot, that is, n=2, the standard resource indication value (RIV) of the frequency resource of the second time slot of the n time slots can be notified. If more than two time slots are allocated after the first time slot, that is, n>2, the above notification method for frequency resource allocation for multi-slot transmission can be adopted.

[0093] In some embodiments, the frequency resource allocation for multi-slot transmission may be signaled separately. For example, RIV signaling may be used for each of the n time slots separately. In the case of only allocating a single time slot, only the number of subchannels allocated for that time slot is notified.

[0094] It can be seen that the frequency resource allocation for multi-slot transmission can be jointly or individually notified. Similarly, the time resource allocation for multi-slot transmission can be jointly or individually notified.

[0095] In some embodiments, a single index may be encoded by the transmitting UE to notify the receiving UE. The receiving UE may then determine the number n of additional time slots after the first time slot and the offset of the additional time slots relative to the first time slot based on the index.

[0096] In some embodiments, the number n of the additional time slots may be encoded in the first time resource signaling to notify the receiving UE, and the offset of the additional time slot relative to the first time slot may be encoded in another second time resource signaling to notify the receiving UE. The receiving UE may then decode the two different time resource signalings respectively to obtain the number n and the offset of the additional time slot relative to the first time slot.

[0097] The above notification of frequency resource and time resource allocation for multi-slot transmission can be joint or separate. These different notification methods can be combined in any way. For example, joint notification of frequency resource allocation for multi-slot transmission and separate notification of time resource allocation for multi-slot transmission can be used to notify time and frequency resources. For another example, joint notification of frequency resource allocation for multi-slot transmission and joint notification of time resource allocation for multi-slot transmission can be used to notify time and frequency resources. For another example, separate notification of frequency resource allocation for multi-slot transmission and separate notification of time resource allocation for multi-slot transmission can be used to notify time and frequency resources. For another example, separate notification of frequency resource allocation for multi-slot transmission and joint notification of time resource allocation for multi-slot transmission can be used to notify time and frequency resources. The present disclosure is not limited in this respect.

[0098] Figure 6 Example components of a device 600 according to some embodiments are shown. In some embodiments, the device 600 may include at least an application circuit 602, a baseband circuit 604, a radio frequency (RF) circuit 606, a front end module (FEM) circuit 608, one or more antennas 610, and a power management circuit (PMC) 612 coupled together as shown. The components of the device 600 shown may be included in a UE or an AN. In some embodiments, the device 600 may include fewer elements (e.g., the AN may not use the application circuit 602, but may include a processor / controller to process IP data received from the EPC). In some embodiments, the device 600 may include additional elements, such as a memory / storage device, a display, a camera, a sensor, or an input / output (I / O) interface. In other embodiments, the components described below may be included in more than one device (e.g., for a Cloud-RAN (C-RAN) implementation, the circuit may be separately included in more than one device).

[0099] The application circuit 602 may include one or more application processors. For example, the application circuit 602 may include circuits such as, but not limited to, one or more single-core or multi-core processors. The (one or more) processors may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, etc.). The processor may be coupled to or may include a memory / storage device, and may be configured to run instructions stored in the memory / storage device to enable various applications and / or operating systems to run on the device 600. In some embodiments, the processor of the application circuit 602 may process IP packets received from the EPC.

[0100] The baseband circuit 604 may include circuits such as, but not limited to, one or more single-core or multi-core processors. The baseband circuit 604 may include one or more baseband processors or control logic to process baseband signals received from the receive signal path of the RF circuit 606 and generate baseband signals for the transmit signal path of the RF circuit 606. The baseband processing circuit 604 may interface with the application circuit 602 to generate and process baseband signals and control the operation of the RF circuit 606. For example, in some embodiments, the baseband circuit 604 may include a third generation (3G) baseband processor 604A, a fourth generation (4G) baseband processor 604B, a fifth generation (5G) baseband processor 604C, or other baseband processors (one or more) 604D for other existing generations, generations under development, or generations to be developed in the future (e.g., the sixth generation (6G), etc.). The baseband circuit 604 (e.g., one or more of the baseband processors 604A-D) may handle various radio control functions that support communication with one or more radio networks via the RF circuit 606. In other embodiments, some or all of the functions of the baseband processors 604A-D may be included in the modules stored in the memory 604G and these functions may be performed via the central processing unit (CPU) 604E. The radio control functions may include, but are not limited to: signal modulation / demodulation, encoding / decoding, radio frequency shifting, etc. In some embodiments, the modulation / demodulation circuitry of the baseband circuitry 604 may include fast Fourier transform (FFT), precoding, and / or constellation mapping / demapping functions. In some embodiments, the encoding / decoding circuitry of the baseband circuitry 604 may include convolution, tail-biting convolution, turbo, Viterbi, and / or low-density parity check (LDPC) encoder / decoder functions. The embodiments of the modulation / demodulation and encoder / decoder functions are not limited to these examples, and may include other suitable functions in other embodiments.

[0101] In some embodiments, the baseband circuit 604 may include one or more audio digital signal processors (DSPs) 604F. (One or more) audio DSPs 604F may include elements for compression / decompression and echo cancellation, and may include other appropriate processing elements in other embodiments. In some embodiments, the components of the baseband circuit may be appropriately combined in a single chip, a single chipset, or arranged on the same circuit board. In some embodiments, some or all of the components of the baseband circuit 604 and the application circuit 602 may be implemented together, for example, on a system on a chip (SOC).

[0102] In some embodiments, the baseband circuit 604 may provide communications compatible with one or more radio technologies. For example, in some embodiments, the baseband circuit 604 may support communications with an Evolved Universal Terrestrial Radio Access Network (EUTRAN) or other wireless metropolitan area network (WMAN), wireless local area network (WLAN), wireless personal area network (WPAN). Embodiments in which the baseband circuit 604 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuits.

[0103] RF circuit 606 may support communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In various embodiments, RF circuit 606 may include switches, filters, amplifiers, etc. to assist in communication with a wireless network. RF circuit 606 may include a receive signal path, which may include circuitry for down-converting RF signals received from FEM circuit 608 and providing baseband signals to baseband circuit 604. RF circuit 606 may also include a transmit signal path, which may include circuitry for up-converting baseband signals provided by baseband circuit 604 and providing RF output signals to FEM circuit 608 for transmission.

[0104] In some embodiments, the receive signal path of the RF circuit 606 may include a mixer circuit 606a, an amplifier circuit 606b, and a filter circuit 606c. In some embodiments, the transmit signal path of the RF circuit 606 may include a filter circuit 606c and a mixer circuit 606a. The RF circuit 606 may also include a synthesizer circuit 606d, which is used to synthesize the frequency used by the mixer circuit 606a for the receive signal path and the transmit signal path. In some embodiments, the mixer circuit 606a of the receive signal path may be configured to down-convert the RF signal received from the FEM circuit 608 based on the synthesized frequency provided by the synthesizer circuit 606d. The amplifier circuit 606b may be configured to amplify the down-converted signal, and the filter circuit 606c may be a low pass filter (LPF) or a band pass filter (BPF) configured to remove unwanted signals from the down-converted signal to generate an output baseband signal. The output baseband signal may be provided to the baseband circuit 604 for further processing. In some embodiments, the output baseband signal may be a zero frequency baseband signal, but this is not required.In some embodiments, the mixer circuit 606a of the receive signal path may include a passive mixer, but the scope of the embodiments is not limited in this respect.

[0105] In some embodiments, mixer circuit 606a of the transmit signal path may be configured to up-convert an input baseband signal based on a synthesized frequency provided by synthesizer circuit 606d to generate an RF output signal for FEM circuit 608. The baseband signal may be provided by baseband circuit 604 and may be filtered by filter circuit 606c.

[0106] In some embodiments, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may include two or more mixers and may be arranged for quadrature down-conversion and / or up-conversion, respectively.

[0107] In some embodiments, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may be arranged for direct down-conversion and / or direct up-conversion, respectively. In some embodiments, the mixer circuit 606a of the receive signal path and the mixer circuit 606a of the transmit signal path may be configured for superheterodyne operation.

[0108] In some embodiments, the output baseband signal and the input baseband signal may be analog baseband signals, but the scope of the embodiments is not limited in this respect. In some alternative embodiments, the output baseband signal and the input baseband signal may be digital baseband signals. In these alternative embodiments, the RF circuit 606 may include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) circuit, and the baseband circuit 604 may include a digital baseband interface to communicate with the RF circuit 606.

[0109] In some dual-mode embodiments, separate radio IC circuits may be provided to process signals for each spectrum, although the scope of the embodiments is not limited in this respect.

[0110] In some embodiments, synthesizer circuit 606d may be a fractional-N synthesizer or a fractional-N / N+1 synthesizer, but the scope of the embodiments is not limited in this respect, as other types of frequency synthesizers may be suitable. For example, synthesizer circuit 606d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase-locked loop with a frequency divider.

[0111] Synthesizer circuit 606d may be configured to synthesize an output frequency for use by mixer circuit 606a of RF circuit 606 based on the frequency input and the divider control input. In some embodiments, synthesizer circuit 606d may be a fractional-N / N+1 synthesizer.

[0112] In some embodiments, the frequency input may be provided by a voltage controlled oscillator (VCO), but this is not required. The divider control input may be provided by the baseband circuit 604 or the application processor 602 according to the desired output frequency. In some embodiments, the divider control input (e.g., N) may be determined from a lookup table based on the channel indicated by the application processor 602.

[0113] The synthesizer circuit 606d of the RF circuit 606 may include a frequency divider, a delay locked loop (DLL), a multiplexer, and a phase accumulator. In some embodiments, the frequency divider may be a dual-mode frequency divider (DMD), and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by N or N+1 (e.g., based on a carry output) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded tunable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In these embodiments, the delay element may be configured to decompose the VCO cycle into at most Nd equal phase groups, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0114] In some embodiments, the synthesizer circuit 606d can be configured to generate a carrier frequency as an output frequency, while in other embodiments, the output frequency can be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used with an orthogonal generator and divider circuit to generate multiple signals with multiple different phases from each other at the carrier frequency. In some embodiments, the output frequency can be an LO frequency (fLO). In some embodiments, the RF circuit 606 can include an IQ / polarity converter.

[0115] The FEM circuitry 608 may include a receive signal path that may include circuitry configured to operate on RF signals received from one or more antennas 610, amplify the received signals, and provide an amplified version of the received signals to the RF circuitry 606 for further processing. The FEM circuitry 608 may also include a transmit signal path that may include circuitry configured to amplify signals provided by the RF circuitry 606 for transmission by one or more of the one or more antennas 610. In various embodiments, amplification via the transmit signal path or the receive signal path may be accomplished only in the RF circuitry 606, only in the FEM 608, or in both the RF circuitry 606 and the FEM 608.

[0116] In some embodiments, the FEM circuit 608 may include a TX / RX switch to switch between transmit mode and receive mode operation. The FEM circuit may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuit may include a low noise amplifier (LNA) to amplify the received RF signal and provide the amplified received RF signal as an output (e.g., to the RF circuit 606). The transmit signal path of the FEM circuit 608 may include a power amplifier (PA) for amplifying the input RF signal (e.g., provided by the RF circuit 606) and one or more filters for generating an RF signal for subsequent transmission (e.g., through one or more of the one or more antennas 610).

[0117] In some embodiments, PMC 612 can manage the power provided to baseband circuit 604. Specifically, PMC 612 can control power selection, voltage scaling, battery charging, or DC-DC conversion. When device 600 is capable of being powered by a battery, for example, when the device is included in a UE, PMC 612 can generally be included. PMC 612 can improve power conversion efficiency while providing a desired implementation size and heat dissipation characteristics.

[0118] Although Figure 6 PMC 612 is shown coupled only to baseband circuitry 604. However, in other embodiments, PMC 612 may additionally or alternatively be coupled to other components, such as, but not limited to, application circuitry 602, RF circuitry 606, or FEM 608, and perform similar power management operations for the other components.

[0119] In some embodiments, the PMC 612 may control or otherwise be a part of various power saving mechanisms of the device 600. For example, if the device 600 is in the RRC_Connected state, in which the device 600 remains connected to the RAN node when it expects to receive traffic soon, it may then enter a state known as discontinuous reception mode (DRX) after a period of inactivity. During this state, the device 600 may be powered off for brief intervals to save power.

[0120] If there is no data traffic activity for an extended period of time, the device 600 may transition to the RRC_Idle state, in which the device 600 is disconnected from the network and does not perform operations such as channel quality feedback, handover, etc. The device 600 enters a very low power state and performs paging, in which the device 600 periodically wakes up again to listen to the network and then powers off again. The device 600 may not receive data in this state, and in order to receive data, it may transition back to the RRC_Connected state.

[0121] An additional power saving mode may allow a device to be unavailable to the network for periods longer than the paging interval, ranging from a few seconds to a few hours. During this time, the device is completely unable to access the network and may be completely powered off. Any data sent during this time will incur significant delays, assuming the delay is acceptable.

[0122] The processor of the application circuit 602 and the processor of the baseband circuit 604 can be used to execute elements of one or more instances of the protocol stack. For example, the processor of the baseband circuit 604 (alone or in combination) can be used to perform layer 3, layer 2, or layer 1 functions, and the processor of the application circuit 604 can utilize data received from these layers (e.g., packet data) and further perform layer 4 functions (e.g., Transport Communication Protocol (TCP) and User Datagram Protocol (UDP) layers). As mentioned herein, layer 3 may include an RRC layer. As mentioned herein, layer 2 may include a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer. As mentioned herein, layer 1 may include a physical (PHY) layer of a UE / RAN node.

[0123] Figure 7 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. Specifically, Figure 7 A diagrammatic representation of hardware resources 700 is shown, including one or more processors (or processor cores) 710, one or more memory / storage devices 720, and one or more communication resources 730, each of which may be communicatively coupled via a bus 740. For embodiments utilizing node virtualization (e.g., NFV), a hypervisor 702 may be executed to provide an execution environment for one or more network slices / sub-slices utilizing hardware resources 700.

[0124] Processor 710 (e.g., a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a radio frequency integrated circuit (RFIC), another processor, or any suitable combination thereof) may include, for example, processor 712 and processor 714.

[0125] The memory / storage device 720 may include main memory, disk storage, or any suitable combination thereof. The memory / storage device 720 may include, but is not limited to, any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state storage, etc.

[0126] The communication resources 730 may include interconnect or network interface components or other suitable devices to communicate with one or more peripheral devices 704 or one or more databases 706 via the network 708. For example, the communication resources 730 may include a wired communication component (e.g., for coupling via a universal serial bus (USB)), a cellular communication component, an NFC component, a Bluetooth component (e.g., Bluetooth low energy), a Wi-Fi component, and other communication components.

[0127] The instructions 750 may include software, programs, applications, applet programs, apps, or other executable code for causing at least any processor 710 to perform any one or more of the methods discussed herein. The instructions 750 may reside in whole or in part in at least one of the processor 710 (e.g., in a buffer memory of the processor), the memory / storage device 720, or any suitable combination thereof. In addition, any portion of the instructions 750 may be transmitted to the hardware resources 700 from any combination of the peripheral device 704 or the database 706. Therefore, the memory of the processor 710, the memory / storage device 720, the peripheral device 704, and the database 706 are examples of computer-readable and machine-readable media.

[0128] Figure 8An example of an infrastructure device 800 according to various embodiments is shown. The infrastructure device 800 (or "system 800") may be implemented as a base station, a radio head, a RAN node, etc., such as the RAN nodes 111 and 112 and / or AP106 previously shown and described. In other examples, the system 800 may be implemented in or by a UE, (one or more) application servers 130, and / or any other element / device discussed herein. The system 800 may include one or more of the following: an application circuit 805, a baseband circuit 810, one or more radio front-end modules 815, a memory 820, a power management integrated circuit (power management integrated circuitry, PMIC) 825, a power three-way circuit 830, a network controller 835, a network interface connector 840, a satellite positioning circuit 845, and a user interface 850. In some embodiments, the device 800 may include additional elements, such as memory / storage, a display, a camera, a sensor, or an input / output (I / O) interface element. In other embodiments, the components described below may be included in more than one device (eg, for a Cloud RAN (C-RAN) implementation, the circuitry may be split and included in more than one device).

[0129] As used herein, the term "circuit" may refer to a hardware component configured to provide the described functions, be part of such a hardware component, or include such a hardware component: an electronic circuit, a logic circuit, a processor (shared, dedicated, or group) and / or a memory (shared, dedicated, or group), an Application Specific Integrated Circuit (ASIC), a field-programmable device (FPD) (e.g., a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex PLD (CPLD), a high-capacity PLD (HCPLD), a structured ASIC, or a programmable system on a chip (SoC), a digital signal processor (DSP), etc. In some embodiments, the circuit may execute one or more software or firmware programs to provide at least some of the described functions. In addition, the term "circuit" may also refer to a combination of one or more hardware elements (or circuits used in electrical or electronic systems) and program code to perform the functions of the program code. In these embodiments, the combination of hardware elements and program code may be referred to as a specific type of circuit.

[0130] The terms "application circuitry" and / or "baseband circuitry" may be considered synonymous with "processor circuitry" and may be referred to as "processor circuitry". As used herein, the term "processor circuitry" may refer to, be part of, or include a circuit that is capable of sequentially and automatically performing a sequence of arithmetic or logical operations; and recording, storing, and / or transmitting digital data. The term "processor circuitry" may refer to one or more application processors, one or more baseband processors, a physical central processing unit (CPU), a single-core processor, a dual-core processor, a triple-core processor, a quad-core processor, and / or any other device capable of executing or otherwise operating computer-executable instructions such as program code, software modules, and / or functional processes.

[0131] In addition, various components of the core network 120 (or CN 120 discussed previously) may be referred to as "network elements". The term "network element" may describe a physical or virtualized device used to provide wired or wireless communication network services. The term "network element" may be considered synonymous with and / or referred to as the following terms: networked computer, networking hardware, network device, network node, router, switch, hub, bridge, radio network controller, radio access network device, gateway, server, virtualized network function (virtualized network function, VNF), network functions virtualization infrastructure (network functions virtualization infrastructure, NFVI), etc.

[0132] The application circuit 805 may include one or more central processing unit (CPU) cores and one or more of the following: cache memory, low drop-out (LDO) regulator, interrupt controller, serial interface such as SPI, I2C or general programmable serial interface module, real time clock (RTC), timer-counter including interval and watchdog timer, general input / output (I / O or IO), memory card controller such as Secure Digital (SD) / MultiMediaCard (MMC), Universal Serial Bus (USB) interface, Mobile Industry Processor Interface (MIPI) interface and Joint Test Access Group (JTAG) test access port. As an example, the application circuit 805 may include one or more Intel or Processor; Advanced Micro Devices (AMD) Processor, Accelerated Processing Unit (APU) or processor; etc. In some embodiments, system 800 may not utilize application circuit 805, but may, for example, include a dedicated processor / controller to process IP data received from the EPC or 5GC.

[0133] Additionally or alternatively, the application circuit 805 may include circuits such as (but not limited to): one or more field programmable devices (FPDs), such as field programmable gate arrays (FPGAs), etc.; programmable logic devices (PLDs), such as complex PLDs (CPLDs), high capacity PLDs (HCPLDs), etc.; ASICs, such as structured ASICs, etc.; programmable SoCs (PSoCs); etc. In such embodiments, the circuits of the application circuit 805 may include logic blocks or logic architectures, including other interconnected resources, which may be programmed to perform various functions, such as the processes, methods, functions, etc. of the various embodiments discussed herein. In such an embodiment, the circuitry of the application circuit 805 may include a storage unit (e.g., an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a static memory (e.g., a static random access memory (SRAM), an antifuse, etc.) for storing logic blocks, logic architectures, data, etc. in a lookup table (LUT), etc.), and the like.

[0134] The baseband circuit 810 may be implemented, for example, as a solder-in substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, or a multi-chip module including two or more integrated circuits. Although not shown, the baseband circuit 810 may include one or more digital baseband systems, which may be coupled to a CPU subsystem, an audio subsystem, and an interface subsystem via an interconnect subsystem. The digital baseband subsystem may also be coupled to a digital baseband interface and a mixed signal baseband subsystem via another interconnect subsystem. Each interconnect subsystem may include a bus system, a point-to-point connection, a network on chip (NOC) structure, and / or some other appropriate bus or interconnect technology, such as those discussed herein. The audio subsystem may include a digital signal processing circuit, a buffer memory, a program memory, a voice processing accelerator circuit, a data converter circuit such as an analog-to-digital and a digital-to-analog converter circuit, an analog circuit including one or more amplifiers and filters, and / or other similar components. In one aspect of the present disclosure, the baseband circuitry 810 may include a protocol processing circuit having one or more instances of a control circuit (not shown) to provide control functionality for digital baseband circuitry and / or radio frequency circuitry (e.g., radio front end module 815).

[0135] The user interface circuit 850 may include one or more user interfaces designed to enable interaction with a user of the system 800 or a peripheral component interface designed to enable interaction with a peripheral component of the system 800. The user interface may include, but is not limited to, one or more physical or virtual buttons (e.g., a reset button), one or more indicators (e.g., a light emitting diode (LED)), a physical keyboard or keypad, a mouse, a touch pad, a touch screen, a speaker or other audio emitting device, a microphone, a printer, a scanner, a headset, a display screen or display device, etc. The peripheral component interface may include, but is not limited to, a non-volatile memory port, a universal serial bus (USB) port, an audio jack, a power supply interface, etc.

[0136] The radio front end module (RFEM) 815 may include a millimeter wave RFEM and one or more sub-millimeter wave radio frequency integrated circuits (RFICs). In some implementations, the one or more sub-millimeter wave RFICs may be physically separated from the millimeter wave RFEM. The RFIC may include connections to one or more antennas or antenna arrays, and the RFEM may be connected to multiple antennas. In alternative implementations, both millimeter wave and sub-millimeter wave radio functions may be implemented in the same physical radio front end module 815. The RFEM 815 may contain both millimeter wave antennas and sub-millimeter wave antennas.

[0137] The memory circuit 820 may include one or more of the following: volatile memory, including dynamic random access memory (DRAM) and / or synchronous dynamic random access memory (SDRAM); and nonvolatile memory (NVM), including high-speed electrically erasable memory (commonly referred to as flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), etc., and may include from and The memory circuit 820 may be implemented as one or more of a solder-in package integrated circuit, a socketed memory module, and a plug-in memory card.

[0138] The PMIC 825 may include a voltage regulator, a surge protector, a power alarm detection circuit, and one or more backup power sources such as a battery or capacitor. The power alarm detection circuit may detect one or more of a brownout (undervoltage) and a surge (overvoltage) condition. The power tee circuit 830 may provide power drawn from the network cable to provide both power supply and data connectivity to the infrastructure device 800 using a single cable.

[0139] The network controller circuitry 835 may provide connectivity to the network using a standard network interface protocol such as Ethernet, Ethernet based on GRE tunnels, Ethernet based on Multiprotocol Label Switching (MPLS), or some other suitable protocol. Network connectivity may be provided to / from the infrastructure device 800 via the network interface connector 840 using a physical connection, which may be electrical (commonly referred to as a "copper interconnect"), optical, or wireless. The network controller circuitry 835 may include one or more dedicated processors and / or FPGAs to communicate using one or more of the above-mentioned protocols. In some implementations, the network controller circuitry 835 may include multiple controllers to provide connectivity to other networks using the same or different protocols.

[0140] The positioning circuit 845 may include circuits to receive and decode signals sent by one or more navigation satellite constellations of a global navigation satellite system (GNSS). Examples of navigation satellite constellations (or GNSS) may include the United States' Global Positioning System (GPS), Russia's Global Navigation System (GLONASS), the European Union's Galileo system, China's Beidou navigation satellite system, regional navigation systems or GNSS augmentation systems (e.g., Navigation with Indian Constellation (NAVIC), Japan's Quasi-Zenith Satellite System (QZSS), France's Doppler Orbitography and Radio-positioning Integrated by Satellite (DORIS), etc.), etc. The positioning circuit 845 may include various hardware elements (e.g., hardware devices such as switches, filters, amplifiers, antenna elements, etc., to facilitate communication over-the-air (OTA) communication) to communicate with components of a positioning network (e.g., navigation satellite constellation nodes).

[0141] A node or satellite of a (one or more) navigation satellite constellation ("GNSS node") may provide positioning services by continuously transmitting or broadcasting GNSS signals along a line of sight, which may be used by a GNSS receiver (e.g., positioning circuitry 845 and / or positioning circuitry implemented by UE 101, etc.) to determine its GNSS position. The GNSS signal may include a pseudo-random code (e.g., a sequence of ones and zeros) known to the GNSS receiver and a message including a time of transmission (ToT) of a code epoch (e.g., a defined point in the pseudo-random code sequence) and the GNSS node position at the ToT. The GNSS receiver may monitor / measure GNSS signals transmitted / broadcasted by multiple GNSS nodes (e.g., four or more satellites) and solve various equations to determine the corresponding GNSS position (e.g., spatial coordinates). The GNSS receiver also implements a clock that is generally not as stable and accurate as the atomic clock of the GNSS node, and the GNSS receiver may use the measured GNSS signals to determine the deviation of the GNSS receiver relative to true time (e.g., the deviation of the GNSS receiver clock relative to the GNSS node time). In some embodiments, the positioning circuit 845 may include a Micro-Technology for Positioning, Navigation, and Timing (Micro-PNT) IC that uses a master timing clock to perform position tracking / estimation without GNSS assistance.

[0142] The GNSS receiver may measure the time of arrival (ToA) of GNSS signals from multiple GNSS nodes based on its own clock. The GNSS receiver may determine a time of flight (ToF) value for each received GNSS signal based on ToA and ToT, and may then determine a three-dimensional (3D) position and clock bias based on ToF. The 3D position may then be converted into latitude, longitude, and altitude. The positioning circuit 845 may provide data to the application circuit 805, which may include one or more of position data or time data. The application circuit 805 may use the time data to synchronize operations with other radio base stations (e.g., RAN nodes 111, 112, etc.).

[0143] Figure 8The components shown can communicate with each other using interface circuits. As used herein, the term "interface circuit" may refer to a circuit that supports information exchange between two or more components or devices, is a part of such a circuit, or includes such a circuit. The term "interface circuit" may refer to one or more hardware interfaces, such as a bus, an input / output (I / O) interface, a peripheral component interface, a network interface card, etc. Any appropriate bus technology may be used in various implementations, and the bus technology may include any number of technologies, including industry standard architecture (ISA), extended ISA (EISA), peripheral component interconnect (PCI), extended peripheral component interconnect (PCIx), fast PCI (PCI express, PCIe) or any number of other technologies. The bus may be a dedicated bus used in a system based on SoC, for example. Other bus systems may be included, such as I2C interface, SPI interface, point-to-point interface, and power bus, etc.

[0144] The following paragraphs describe examples of various embodiments.

[0145] Example 1 includes an apparatus for a user equipment (UE), the apparatus comprising: a radio frequency (RF) interface; and a processor circuit coupled to the RF interface, wherein the processor circuit is used to: generate a first index a based on the number n of additional time slots after a first time slot, the number S of available subchannels in each of the additional time slots, and the number m of allocated subchannels in each of the additional time slots, wherein the first time slot and the additional time slot are used to carry the same transport block (TB); based on the number n of additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and the index k for the starting subchannel of each of the additional time slots j , to generate a second index b; generating a third index I based on the sum of the first index a and the second index b, wherein the third index I is used to notify the number m of the allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots in the additional time slots j Both; and encoding the third index I in the sidelink control information (SCI) of the physical sidelink control channel (PSCCH) for transmission to the receiving UE via the RF interface.

[0146] Example 2 includes the apparatus of Example 1, wherein the processor circuit is configured to encode the number n of the additional time slots in a first time resource signaling for transmission to the receiving UE via the RF interface.

[0147] Example 3 includes the apparatus of Example 2, wherein the processor circuit is configured to encode an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiving UE via the RF interface.

[0148] Example 4 includes the apparatus of Example 1, wherein the processor circuit is used to: encode a single index for transmission to the receiving UE, the single index being used to notify both the number n of the additional time slots and the offset of the additional time slots relative to the first time slot.

[0149] Example 5 includes the apparatus of Example 1, wherein the processor circuit is configured to generate the first index a based on the following formula:

[0150]

[0151] Example 6 includes the apparatus of Example 1, wherein the processor circuit is configured to generate the second index b based on the following formula:

[0152]

[0153] Example 7 includes the apparatus of any one of Examples 1 to 6, wherein n=1 or n=2.

[0154] Example 8 includes an apparatus for a user equipment (UE), the apparatus comprising: a radio frequency (RF) interface; and a processor circuit coupled to the RF interface, wherein the processor circuit is used to: decode sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting UE via the RF interface to obtain a single index I; decode time resource signaling received from the transmitting UE via the RF interface to obtain the number n of additional time slots after a first time slot; obtain the number S of available subchannels in each of the additional time slots according to a resource pool configuration; and determine the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots based on the index I, the number n of additional time slots, and the number S of available subchannels in each of the additional time slots. j .

[0155] Example 9 includes the apparatus of Example 8, wherein the processor circuit is configured to: To determine the first sub-index a m ; and based on formula a m ≤I m+1 To determine the number m of allocated subchannels in each of the additional time slots, where a 1 =0,a S+1 =∞.

[0156] Example 10 includes the apparatus of Example 9, wherein the processor circuit is configured to: m To determine the second sub-index b; and based on the formula To determine the index k of the starting subchannel for each of the additional time slots j .

[0157] Example 11 includes the apparatus of Example 8, wherein the processor circuit is used to: decode the time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0158] Example 12 includes the apparatus of Example 8, wherein the processor circuit is to decode additional time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0159] Example 13 includes the apparatus of any of Examples 8 to 12, wherein n=1 or n=2.

[0160] Example 14 includes a computer-readable medium having instructions stored thereon, which, when executed by a processor circuit, causes the processor circuit to: generate a first index a based on a number n of additional time slots following a first time slot, a number S of available subchannels in each of the additional time slots, and a number m of allocated subchannels in each of the additional time slots, wherein the first time slot and the additional time slot are used to carry the same transport block (TB); generate a first index a based on the number n of additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and an index k for a starting subchannel of each of the additional time slots j , to generate a second index b; generating a third index I based on the sum of the first index a and the second index b, wherein the third index I is used to notify the number m of the allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots in the additional time slots j ​Both; and encoding the third index I in sidelink control information (SCI) of a physical sidelink control channel (PSCCH) for transmission to a receiving user equipment (UE), wherein n=1 or n=2.

[0161] Example 15 includes the computer-readable medium of Example 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encode the number n of the additional time slots in a first time resource signaling for transmission to the receiving UE.

[0162] Example 16 includes the computer-readable medium of Example 15, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: encode an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiving UE.

[0163] Example 17 includes the computer-readable medium described in Example 14, wherein the instruction, when executed by the processor circuit, also causes the processor circuit to: encode a single index for transmission to the receiving UE, wherein the single index is used to notify both the number n of the additional time slots and the offset of the additional time slots relative to the first time slot.

[0164] Example 18 includes the computer readable medium of Example 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to generate the first index a based on the following formula:

[0165]

[0166] Example 19 includes the computer readable medium of Example 14, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to generate the second index b based on the following formula:

[0167]

[0168] Example 20 includes a computer-readable medium having instructions stored thereon, which, when executed by a processor circuit, causes the processor circuit to: decode sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting user equipment (UE) to obtain a single index I; decode time resource signaling received from the transmitting UE to obtain the number n of additional time slots after a first time slot; obtain the number S of available subchannels in each of the additional time slots according to a resource pool configuration; and determine the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots based on the index I, the number n of additional time slots, and the number S of available subchannels in each of the additional time slots. j , where n=1 or n=2.

[0169] Example 21 includes the computer-readable medium of Example 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: To determine the first sub-index a m ; and based on formula a m ≤I m+1 To determine the number m of allocated subchannels in each of the additional time slots, where a 1 =0,a S+1 =∞.

[0170] Example 22 includes the computer-readable medium of Example 21, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: m To determine the second sub-index b; and based on the formula To determine the index k of the starting subchannel for each of the additional time slots j .

[0171] Example 23 includes the computer-readable medium of Example 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: decode the time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0172] Example 24 includes the computer-readable medium of Example 20, wherein the instructions, when executed by the processor circuit, further cause the processor circuit to: decode additional time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0173] ​Example 25 includes a device for a user equipment (UE), the device comprising: a device for generating a first index a based on the number n of additional time slots after a first time slot, the number S of available subchannels in each of the additional time slots, and the number m of allocated subchannels in each of the additional time slots, wherein the first time slot and the additional time slot are used to carry the same transport block (TB); a device for generating a first index a based on the number n of additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and an index k for a starting subchannel of each of the additional time slots. j , to generate a second index b; a device for generating a third index I based on the sum of the first index a and the second index b, wherein the third index I is used to notify the number m of the allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots j Both; and a device for encoding the third index I in the sidelink control information (SCI) of the physical sidelink control channel (PSCCH) for transmission to the receiving UE.

[0174] Example 26 includes the apparatus of Example 25, further comprising: means for encoding the number n of the additional time slots in a first time resource signaling for transmission to the receiving UE.

[0175] Example 27 includes the apparatus of Example 26, further comprising: means for encoding an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiving UE.

[0176] Example 28 includes the apparatus of Example 25, further comprising: a device for encoding a single index for transmission to the receiving UE, wherein the single index is used to notify both the number n of the additional time slots and the offset of the additional time slot relative to the first time slot.

[0177] Example 29 includes the apparatus of Example 25, further comprising means for generating the first index a based on the following formula:

[0178]

[0179] Example 30 includes the apparatus of Example 25, further comprising means for generating the second index b based on the following formula:

[0180]

[0181] Example 31 includes the apparatus of any of Examples 25 to 30, wherein n=1 or n=2.

[0182] Example 32 includes a device for a user equipment (UE), the device comprising: a device for decoding sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting UE to obtain a single index I; a device for decoding time resource signaling received from the transmitting UE to obtain the number n of additional time slots after a first time slot; a device for obtaining the number S of available subchannels in each of the additional time slots according to a resource pool configuration; and a device for determining the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots based on the index I, the number n of additional time slots, and the number S of available subchannels in each of the additional time slots. j device.

[0183] Example 33 includes the apparatus of Example 32, further comprising: a method for To determine the first sub-index a m A device for based on formula a m ≤I m+1 means for determining the number m of allocated subchannels in each of said additional time slots, wherein a 1 =0,a S+1 =∞.

[0184] Example 34 includes the apparatus of Example 33, further comprising: a m means for determining a second sub-index b based on the formula; and To determine the index k of the starting subchannel for each of the additional time slots j device.

[0185] Example 35 includes the apparatus of Example 32, further comprising: means for decoding the time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0186] Example 36 includes the apparatus of Example 32, further comprising: means for decoding additional time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0187] Example 37 includes the apparatus of any of Examples 32 to 36, wherein n=1 or n=2.

[0188] ​Example 38 includes a method for a user equipment (UE), the method comprising: generating a first index a based on a number n of additional time slots after a first time slot, a number S of available subchannels in each of the additional time slots, and a number m of allocated subchannels in each of the additional time slots, wherein the first time slot and the additional time slot are used to carry the same transport block (TB); generating a first index a based on the number n of additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and an index k for a starting subchannel of each of the additional time slots j , to generate a second index b; generating a third index I based on the sum of the first index a and the second index b, wherein the third index I is used to notify the number m of the allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots in the additional time slots j Both; and encoding the third index I in the sidelink control information (SCI) of the physical sidelink control channel (PSCCH) for transmission to the receiving UE.

[0189] Example 39 includes the method of Example 38, further comprising: encoding the number n of the additional time slots in the first time resource signaling for transmission to the receiving UE.

[0190] Example 40 includes the method of Example 39, further comprising: encoding an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiving UE.

[0191] Example 41 includes the method of Example 38, further comprising: encoding a single index for transmission to the receiving UE, wherein the single index is used to notify both the number n of the additional time slots and the offset of the additional time slot relative to the first time slot.

[0192] Example 42 includes the method of Example 38, further comprising generating the first index a based on the following formula:

[0193]

[0194] Example 43 includes the method of Example 38, further comprising generating the second index b based on the following formula:

[0195]

[0196] Example 44 includes the method of any one of Examples 38 to 43, wherein n=1 or n=2.

[0197] Example 45 includes a method for a user equipment (UE), the method comprising: decoding sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting UE to obtain a single index I; decoding time resource signaling received from the transmitting UE to obtain the number n of additional time slots after a first time slot; obtaining the number S of available subchannels in each of the additional time slots according to a resource pool configuration; and determining the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots based on the index I, the number n of additional time slots, and the number S of available subchannels in each of the additional time slots. j .

[0198] Example 46 includes the method of Example 45, further comprising: based on the formula To determine the first sub-index a m ; and based on formula a m ≤I m+1 To determine the number m of allocated subchannels in each of the additional time slots, where a 1 =0,a S+1 =∞.

[0199] Example 47 includes the method of Example 46, further comprising: based on I minus a m To determine the second sub-index b; and based on the formula To determine the index k of the starting subchannel for each of the additional time slots j .

[0200] Example 48 includes the method of Example 45, further comprising: decoding the time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0201] Example 49 includes the method of Example 45, further comprising: decoding additional time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

[0202] Example 50 includes the method of any one of Examples 45 to 49, wherein n=1 or n=2.

[0203] Example 51 comprises a user equipment (UE) as described and shown in the specification.

[0204] Example 52 includes a method performed at a user equipment (UE) as described and shown in the specification.

[0205] ​Although certain embodiments are illustrated and described herein for descriptive purposes, various alternative and / or equivalent embodiments or implementations planned to achieve the same purpose may replace the embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptation or variation of the embodiments discussed herein. Therefore, it is readily understood that the embodiments described herein are limited only by the appended claims and their equivalents.

Claims

1. An apparatus for a user equipment (UE), the apparatus comprising: Radio frequency (RF) interface; and a processor circuit coupled to the RF interface, Wherein, the processor circuit is used for: generating a first index a based on a number n of additional time slots following a first time slot, a number S of available subchannels in each of the additional time slots, and a number m of allocated subchannels in each of the additional time slots, wherein the first time slot and the additional time slot are used to carry the same transport block (TB); Based on the number n of the additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and the index k of the starting subchannel for each of the additional time slots. j , to generate the second index b, where j∈{0,…,n-1}; A third index I is generated based on the sum of the first index a and the second index b, wherein the third index I is used to notify the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots. j Both; and The third index I is encoded in sidelink control information (SCI) of a physical sidelink control channel (PSCCH) for transmission to a receiving UE via the RF interface.

2. The device according to claim 1, wherein: The processor circuit is configured to encode the number n of the additional time slots in a first time resource signaling for transmission to the receiving UE via the RF interface.

3. The device according to claim 2, wherein: The processor circuit is configured to encode an offset of the additional time slot relative to the first time slot in a second time resource signaling for transmission to the receiving UE via the RF interface.

4. The device according to claim 1, wherein: The processor circuit is configured to encode a single index for transmission to the receiving UE, the single index being used to signal both the number n of the additional time slots and the offset of the additional time slots relative to the first time slot.

5. The device according to claim 1, wherein: The processor circuit is configured to generate the first index a based on the following formula:

6. The device according to claim 1, wherein: The processor circuit is configured to generate the second index b based on the following formula:

7. The device according to any one of claims 1 to 6, wherein: n=1 or n=2.

8. An apparatus for a user equipment (UE), the apparatus comprising: Radio frequency (RF) interface; and a processor circuit coupled to the RF interface, Wherein, the processor circuit is used for: Decoding sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting UE via the RF interface to obtain a single index I; decoding time resource signaling received from the transmitting UE via the RF interface to obtain a number n of additional time slots following the first time slot; Obtaining the number S of available subchannels in each of the additional time slots according to the resource pool configuration; and Based on the index I, the number n of the additional time slots, and the number S of available subchannels in each of the additional time slots, determine the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots. j , where j∈{0,…,n-1}.

9. The device according to claim 8, wherein: The processor circuit is configured to: Based on the formula To determine the first sub-index a m ; as well as Based on the formula a m ≤I m+1 To determine the number m of allocated subchannels in each of the additional time slots, where a1=0, a S+1 =∞.​ 10. The device according to claim 9, wherein: The processor circuit is configured to: Based on I minus a m To determine the second sub-index b; as well as Based on the formula To determine the index k of the starting subchannel for each of the additional time slots j .

11. The device according to claim 8, wherein: The processor circuit is configured to decode the time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

12. The device according to claim 8, wherein: The processor circuit is configured to decode additional time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

13. The device according to any one of claims 8 to 12, wherein: n=1 or n=2.

14. A computer readable medium having stored thereon instructions which, when executed by a processor circuit, cause the processor circuit to: A first index a is generated based on the number n of additional time slots following the first time slot, the number S of available subchannels in each of the additional time slots, and the number m of allocated subchannels in each of the additional time slots, wherein, The first time slot and the additional time slot are used to carry the same transport block (TB); Based on the number n of the additional time slots, the number S of available subchannels in each of the additional time slots, the number m of allocated subchannels in each of the additional time slots, and the index k of the starting subchannel for each of the additional time slots. j , to generate the second index b, where j∈{0,…,n-1}; A third index I is generated based on the sum of the first index a and the second index b, wherein the third index I is used to notify the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots. j Both; and The third index I is encoded in the sidelink control information (SCI) of the physical sidelink control channel (PSCCH) for transmission to the receiving user equipment (UE), Wherein, n=1 or n=2.

15. The computer-readable medium of claim 14, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to: encode the number n of the additional time slots in first time resource signaling for transmission to the recipient UE.

16. The computer-readable medium of claim 15, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to: encode an offset of the additional time slot relative to the first time slot in second time resource signaling for transmission to the recipient UE.

17. The computer-readable medium of claim 14, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to: encode a single index for transmission to the receiving UE, the single index being used to signal both the number n of the additional time slots and the offset of the additional time slots relative to the first time slot.

18. The computer-readable medium of claim 14, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to generate the first index a based on the following formula:

19. The computer-readable medium of claim 14, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to generate the second index b based on the following formula:

20. A computer readable medium having stored thereon instructions which, when executed by a processor circuit, cause the processor circuit to: Decoding sidelink control information (SCI) of a physical sidelink control channel (PSCCH) received from a transmitting user equipment (UE) to obtain a single index I; Decoding the time resource signaling received from the transmitting UE to obtain the number n of additional time slots after the first time slot; Obtaining the number S of available subchannels in each of the additional time slots according to the resource pool configuration; as well as Based on the index I, the number n of the additional time slots, and the number S of available subchannels in each of the additional time slots, determine the number m of allocated subchannels in each of the additional time slots and the index k of the starting subchannel for each of the additional time slots. j , where j∈{0,…,n-1}, Wherein, n=1 or n=2.

21. The computer readable medium of claim 20, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to: Based on the formula To determine the first sub-index a m ; as well as Based on the formula a m ≤I m+1 To determine the number m of allocated subchannels in each of the additional time slots, where a1=0, a S+1 =∞.​ 22. The computer-readable medium of claim 21, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to: Based on I minus a m To determine the second sub-index b; as well as Based on the formula To determine the index k of the starting subchannel for each of the additional time slots j .

23. The computer-readable medium of claim 20, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to: decode the time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

24. The computer-readable medium of claim 20, wherein: The instructions, when executed by the processor circuit, further cause the processor circuit to: decode additional time resource signaling to obtain an offset of the additional time slot relative to the first time slot.

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