Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a base substrate, a plurality of sub-pixels, a plurality of data lines, a test circuit, a plurality of data leads, at least one test pad, and at least one first test signal line. The plurality of data lines are electrically connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; the plurality of data leads are electrically connected to the plurality of data lines and the test circuit; at least one test pad is located on at least one side of the test circuit; at least one first test signal line is electrically connected to at least one test pad and the test circuit, wherein at least a portion of at least one first test signal line includes at least two conductive layers that are connected in parallel and electrically connected to each other, thereby reducing the wiring resistance of the first test signal line, so that during the aging process, the heat generation of the first test signal line is reduced and the heat diffusion is increased, thereby helping to solve the problem of wiring burns during the aging process and improve the product yield of the display panel.

Description

[0001] This application claims priority to Chinese Patent Application No. 201911155559.0 filed on November 22, 2019. Technical Field

[0002] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0003] In the display industry, with the continuous development of display technology, the market for flexible organic light-emitting diode (OLED) display panels is growing. In order to occupy a certain proportion in future market competition, manufacturers are paying more and more attention to improving the yield rate. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a plurality of sub-pixels, a plurality of data lines, a test circuit, a plurality of data leads, at least one test pad, and at least one first test signal line. The base substrate includes a display area and a peripheral area at least located on one side of the display area; a plurality of sub-pixels are located in the display area; a plurality of data lines are located in the display area and are electrically connected to the plurality of sub-pixels, and are configured to provide data signals to the plurality of sub-pixels; the test circuit is located in the peripheral area; a plurality of data leads are located in the peripheral area and are electrically connected to the plurality of data lines and the test circuit; at least one test pad is located in the peripheral area and is located on at least one side of the test circuit; and at least one first test signal line is located in the peripheral area, and the at least one first test signal line is electrically connected to the at least one test pad and the test circuit, wherein at least a portion of the at least one first test signal line includes at least two conductive layers that are connected in parallel and electrically connected to each other.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least a portion of the at least one first test signal line includes three conductive layers that are connected in parallel and electrically connected to each other.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the at least one first test signal line includes a first part and a second part, the first part extends along the first direction, the second part extends along a direction intersecting the first direction, the first part is electrically connected to the at least one test pad and the second part, and the second part is also electrically connected to the test circuit.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first part of the at least one first test signal line includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer, and the first sub-conductive layer, the second sub-conductive layer and the third sub-conductive layer are insulated by an insulating layer and are electrically connected in parallel through vias in the insulating layer.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the plurality of sub-pixels includes a pixel structure, and the pixel structure includes a pixel driving circuit, wherein the pixel driving circuit includes a first metal layer, a second metal layer and a third metal layer, the first metal layer is located on the base substrate, the second metal layer is located on a side of the first metal layer away from the base substrate, the third metal layer is located on a side of the second metal layer away from the base substrate, and the first sub-conductive layer, the second sub-conductive layer and the third sub-conductive layer are respectively arranged on the same layer as the first metal layer, the second metal layer and the third metal layer.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit also includes a driving transistor, a storage capacitor, a first insulating layer, a second insulating layer and an interlayer insulating layer, the first insulating layer is located on the side of the first metal layer close to the base substrate, the second insulating layer is located between the first metal layer and the second metal layer, and the interlayer insulating layer is located between the second metal layer and the third metal layer, the first transistor includes a gate, a source, a drain and an active layer, the storage capacitor includes a first electrode plate and a second electrode plate, the active layer is located on the side of the first insulating layer close to the base substrate, the gate and the first electrode plate are located in the first metal layer, the second electrode plate is located in the second metal layer, the source and the drain are located in the third metal layer, the first sub-conductive layer and the second sub-conductive layer are electrically connected in parallel through a via hole penetrating the second insulating layer, and the second sub-conductive layer and the third sub-conductive layer are electrically connected in parallel through a via hole penetrating the interlayer insulating layer.

[0010] For example, the display substrate provided by at least one embodiment of the present disclosure also includes multiple test pad leads and multiple second test signal lines, the at least one first test signal line includes multiple first test signal lines, the at least one test pad includes multiple test pads, the multiple test pad leads extend along a second direction different from the first direction and are electrically connected to the multiple test pads respectively, some of the multiple test pad leads are electrically connected to the first part of the multiple first test signal lines, the multiple second test signal lines are electrically connected to the test circuit and the multiple first test signal lines, and the second part of the multiple first test signal lines and the multiple second test signal lines overlap in their orthographic projections on the substrate.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second portion of each of the plurality of first test signal lines includes a first sub-conductive layer and a second sub-conductive layer, and the plurality of second test signal lines are arranged in the same layer as the third metal layer.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the test circuit includes a plurality of test units, at least one of the plurality of test units includes a first multiplexing switch, a second multiplexing switch, a third multiplexing switch, a first control line, a second control line, a third control line, a first signal line, a second signal line, and a third signal line, the plurality of second test signal lines are electrically connected to the first control line, the second control line, the third control line, the first signal line, the second signal line, and the third signal line, at least one gate of the first multiplexing switch is electrically connected to the first control line or the third control line, and at least one source of the first multiplexing switch is electrically connected to the first signal line. or the second signal line, at least one drain of the first multiplexing switch is electrically connected to one of the plurality of data leads, at least one gate of the second multiplexing switch is electrically connected to the first control line or the third control line, at least one source of the second multiplexing switch is electrically connected to the first signal line or the second signal line, at least one drain of the second multiplexing switch is electrically connected to another of the plurality of data leads, at least one gate of the third multiplexing switch is electrically connected to the second control line, at least one source of the third multiplexing switch is electrically connected to the third signal line, and at least one drain of the third multiplexing switch is electrically connected to one of the plurality of data leads and another of the plurality of data leads.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first multiplexing switch includes a first multiplexing switch active layer, a first multiplexing switch first gate, a first multiplexing switch second gate, a first multiplexing switch drain, a first multiplexing switch first source and a first multiplexing switch second source, the first multiplexing switch active layer is located on the base substrate, the first multiplexing switch first gate and the first multiplexing switch second gate are located on the side of the first multiplexing switch active layer away from the base substrate, the orthographic projection of the first multiplexing switch first gate on the base substrate and the orthographic projection of the first multiplexing switch second gate on the base substrate are staggered, the first multiplexing switch drain, the first multiplexing switch first source and the first multiplexing switch second source are staggered, and the first multiplexing switch drain, the first multiplexing switch first source and the first multiplexing switch second source are staggered. Located on a side of the first gate of the first multiplexing switch and the second gate of the first multiplexing switch away from the substrate substrate, the first multiplexing switch drain is located between the first source of the first multiplexing switch and the second source of the first multiplexing switch, wherein the orthographic projection of the first gate of the first multiplexing switch on the substrate substrate is located between the orthographic projection of the first source of the first multiplexing switch and the first drain of the first multiplexing switch on the substrate substrate, the orthographic projection of the second gate of the first multiplexing switch on the substrate substrate is located between the orthographic projection of the second source of the first multiplexing switch and the first drain of the first multiplexing switch on the substrate substrate, the first gate of the first multiplexing switch is electrically connected to the first control line, and the first gate of the first multiplexing switch is electrically connected to the third control line.

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second multiplexing switch includes a second multiplexing switch active layer, a second multiplexing switch first gate, a second multiplexing switch second gate, a second multiplexing switch drain, a second multiplexing switch first source and a second multiplexing switch second source, the second multiplexing switch active layer is located on the base substrate, the second multiplexing switch first gate and the second multiplexing switch second gate are located on the side of the second multiplexing switch active layer away from the base substrate, the orthographic projection of the second multiplexing switch first gate on the base substrate and the orthographic projection of the second multiplexing switch second gate on the base substrate are staggered, and the second multiplexing switch drain, the second multiplexing switch first source and the second multiplexing switch second source are staggered. The first gate of the second multiplexing switch and the second gate of the second multiplexing switch are located on a side away from the substrate substrate, and the drain of the second multiplexing switch is located between the first source of the second multiplexing switch and the second source of the second multiplexing switch, wherein the orthographic projection of the first gate of the second multiplexing switch on the substrate substrate is located between the orthographic projection of the first source of the second multiplexing switch and the drain of the second multiplexing switch on the substrate substrate, the orthographic projection of the second gate of the second multiplexing switch on the substrate substrate is located between the orthographic projection of the second source of the second multiplexing switch and the drain of the second multiplexing switch on the substrate substrate, the first gate of the second multiplexing switch is electrically connected to the first control line, and the second gate of the second multiplexing switch is electrically connected to the third control line.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the third multiplexing switch includes a third multiplexing switch active layer, a third multiplexing switch first gate, a third multiplexing switch second gate, a third multiplexing switch source, a third multiplexing switch first drain and a first multiplexing switch second drain, the third multiplexing switch active layer is located on the base substrate, the third multiplexing switch first gate and the third multiplexing switch second gate are located on the side of the third multiplexing switch active layer away from the base substrate, the orthographic projection of the third multiplexing switch first gate on the base substrate and the orthographic projection of the third multiplexing switch second gate on the base substrate are staggered, the third multiplexing switch source, the third multiplexing switch first drain and the third multiplexing switch second drain are located on the third multiplexing switch active layer. The first gate of the multiplexing switch and the second gate of the third multiplexing switch are located away from one side of the substrate, and the source of the third multiplexing switch is located between the first drain of the third multiplexing switch and the second drain of the third multiplexing switch, wherein the orthographic projection of the first gate of the third multiplexing switch on the substrate is located between the first drain of the third multiplexing switch and the orthographic projection of the source of the third multiplexing switch on the substrate, the orthographic projection of the second gate of the third multiplexing switch on the substrate is located between the second drain of the third multiplexing switch and the orthographic projection of the source of the third multiplexing switch on the substrate, the first drain of the third multiplexing switch is electrically connected to one of the multiple data leads, and the second drain of the third multiplexing switch is electrically connected to another of the multiple data leads.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the peripheral area also includes a first bonding area, the first bonding area is located on a side of the test circuit away from the display area, in a first direction, the first bonding area and the at least one test pad are spaced apart, the first bonding area is configured to bond with a signal input element and includes a plurality of contact pads, and some of the plurality of contact pads are electrically connected to the test circuit.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first bonding area also includes a plurality of signal leads, the plurality of signal leads electrically connecting part of the plurality of contact pads with the test circuit, at least one drain of the first multiplexing switch is also electrically connected to one of the plurality of signal leads, and at least one drain of the second multiplexing switch is also electrically connected to another one of the plurality of signal leads.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of contact pads include a plurality of first contact pads, the second portion of each of the plurality of first test signal lines and each of the plurality of second test signal lines respectively extend to an end of the plurality of first contact pads away from the first bonding area, and are electrically connected one-to-one with an end of the plurality of first contact pads away from the first bonding area.

[0019] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a first power line and a second power line located in the peripheral area, the first power line is located on a side of the second power line close to the at least one test pad, the multiple contact pads also include multiple second contact pads, the multiple second contact pads are located on a side of the multiple first contact pads close to the at least one test pad, the first power line is configured to provide a first power signal to the multiple sub-pixels, the first power line is electrically connected to a portion of the multiple second contact pads and surrounds the display area, the second power line is configured to provide a second power signal to the multiple sub-pixels, the second power signal is electrically connected to another portion of the multiple second contact pads and extends to the display area, the first power line and the second power line are located on a side of the second portion of the multiple first test signal lines away from the base substrate, and the orthographic projections on the base substrate overlap with the orthographic projections of the second portion of the multiple first test signal lines on the base substrate.

[0020] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: at least one first electrostatic release unit, wherein the at least one first electrostatic release unit is located on a side of the multiple test pads close to the display area, and at least part of the multiple test pad leads pass through the at least one first electrostatic release unit and are electrically connected to the at least one first electrostatic release unit.

[0021] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: at least one second electrostatic release unit and at least one electrostatic lead located in the peripheral area, the at least one second electrostatic release unit is located between the multiple test pads and the first bonding area in the first direction, the at least one electrostatic lead extends along the second direction and electrically connects at least one of the multiple first test signal lines with the at least one second electrostatic release unit, respectively.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the at least one electrostatic lead includes a plurality of electrostatic leads, the plurality of electrostatic leads are arranged side by side in the first direction, the first parts of the plurality of first test signal lines are arranged side by side in the second direction and are electrically connected to the plurality of electrostatic leads respectively, the first parts of the plurality of first test signal lines overlap with the orthographic projections of the plurality of electrostatic leads on the base substrate, and the portion where the first parts of the plurality of first test signal lines overlap with the plurality of electrostatic leads includes the first sub-conductive layer and the second sub-conductive layer.

[0023] For example, the display substrate provided by at least one embodiment of the present disclosure also includes: a shift register unit located in the peripheral area, a light-emitting control unit, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a first trigger signal line, a second trigger signal line, a third power line, a fourth power line and an initialization signal line, the shift register unit is configured to provide a gate scan signal to the plurality of sub-pixels, the light-emitting control unit is configured to provide a light-emitting control signal to the plurality of sub-pixels, the first clock signal line, the second clock signal line and the first trigger signal line are electrically connected to the shift register unit to respectively provide a first clock signal, a second clock signal and a first trigger signal, the third clock signal line, the fourth clock signal line and the second trigger signal line are electrically connected to the light-emitting control unit to respectively provide a third clock signal, a fourth clock signal and a second trigger signal, the third power line and the fourth power line are respectively connected to the shift register unit and the light-emitting The control unit is electrically connected to provide a third power signal and a fourth power signal respectively, the initialization signal line is configured to provide an initialization signal to the multiple sub-pixels, the display substrate also includes a plurality of bending lines located on a side of the multiple first test signal lines close to the display area, the multiple bending lines are respectively electrically connected to at least two of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the first trigger signal line, the second trigger signal line, the third power line, the fourth power line, and the initialization signal line, the multiple bending lines are also respectively electrically connected to another part of the contact pads located in the contact pads, the orthographic projections of the multiple bending lines on the substrate overlap with the orthographic projections of the first power line, the second power line and the second test signal line on the substrate, each of the multiple bending lines includes two conductive layers, and the two conductive layers of the multiple bending lines are respectively arranged on the same layer as the first metal layer and the second metal layer.

[0024] For example, in the display substrate provided in at least one embodiment of the present disclosure, the multiple bending lines are also electrically connected to another part of the test pad leads among the multiple test pad leads, the orthographic projection of the first part of the multiple first test signal lines on the base substrate overlaps with the orthographic projection of the test pad leads respectively electrically connected to the multiple bending lines on the base substrate, and the part where the first part of the multiple first test signal lines overlaps with the test pad leads respectively electrically connected to the multiple bending lines includes the first sub-conductive layer and the second sub-conductive layer.

[0025] At least one embodiment of the present disclosure provides a display device, comprising any of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0027] Figure 1 A schematic diagram of a display substrate provided in one embodiment of the present disclosure;

[0028] Figure 2A A schematic diagram of a display substrate provided in another embodiment of the present disclosure;

[0029] Figure 2B A schematic diagram of a display substrate provided in yet another embodiment of the present disclosure;

[0030] Figure 3 for Figure 2A A magnified schematic diagram of the middle B1 region;

[0031] Figure 4 for Figure 2A A magnified schematic diagram of the middle B2 region;

[0032] Figure 5 for Figure 2A A magnified schematic diagram of the middle B3 area;

[0033] Figure 6 For along Figure 4 Schematic diagram of the cross section along the midline A1-A2;

[0034] Fig. 7A An embodiment of the present disclosure provides Figure 4 A schematic diagram of the circuit principle of the second electrostatic release unit;

[0035] Figure 7B Another embodiment of the present disclosure provides Figure 4 A schematic diagram of the circuit principle of the second electrostatic release unit;

[0036] Fig. 8A A schematic diagram of a test unit provided in one embodiment of the present disclosure;

[0037] Figure 8B An embodiment of the present disclosure provides Fig. 8A A partial enlarged schematic diagram of

[0038] Fig. 9 for Figure 2B A magnified schematic diagram of the middle B4 region;

[0039] Fig.10 A schematic cross-sectional view of a display area of ​​a display substrate provided in one embodiment of the present disclosure;

[0040] Fig.11 A schematic diagram of a display device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate a quantitative limitation, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents. For the convenience of description, in some drawings, "up", "down", "front" and "back" are given. In the embodiment of the present disclosure, the vertical direction is the direction from top to bottom, the vertical direction is the direction of gravity, the horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction from right to left is the direction from front to back.

[0043] In the process of display panel preparation, after the display panel packaging process is completed, aging process, lighting detection, leakage current inspection and other processes are required. Aging process is an important transistor aging method in the panel display industry. The high voltage process of aging process allows the transistors in the display panel to age to a stable state and reduce leakage current. For AMOELD (Active-matrix organic light-emitting diode), another important function of this process is to eliminate poor characteristic bright spots, especially flexible OLED products. Due to the critical temperature of some organic film layers (such as planarization layer) (for example, flexible display panel <450℃, rigid display panel <<550℃), the film defects (the main cause of characteristic bright spots) caused during the doping process of the active layer or the deposition process of some conductive film layers cannot be diffused and filled by high-temperature thermal process, so the characteristic bright spots of flexible OLED require higher aging process voltage to repair, thereby improving the product yield of display panels. However, excessive aging process voltage will quickly generate heat on the backplane wiring of the display panel, causing the organic film layer to deform violently and damage the circuit wiring (hereinafter referred to as burns), resulting in display abnormalities.

[0044] Therefore, the aging process needs to strike a balance between reducing the risk of burns and eliminating the characteristic highlights, in order to minimize the decline in product yield. However, due to the influence of the aging process, burns and characteristic highlights are in a dynamic balance, and the engineering feasibility is poor. Therefore, reducing the risk of burns on display panels during the aging process and further improving product yield are technical issues that need to be solved at present.

[0045] At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate, a plurality of sub-pixels, a plurality of data lines, a test circuit, a plurality of data leads, at least one test pad, and at least one first test signal line. The base substrate includes a display area and a peripheral area at least located on one side of the display area; a plurality of sub-pixels are located in the display area; a plurality of data lines are located in the display area and are electrically connected to the plurality of sub-pixels, and are configured to provide data signals to the plurality of sub-pixels; the test circuit is located in the peripheral area; a plurality of data leads are located in the peripheral area and are electrically connected to the plurality of data lines and the test circuit; at least one test pad is located in the peripheral area and is located on at least one side of the test circuit; and at least one first test signal line is located in the peripheral area, and the at least one first test signal line is electrically connected to the at least one test pad and the test circuit, wherein at least a portion of the at least one first test signal line includes at least two conductive layers that are connected in parallel and electrically connected to each other.

[0046] In the display substrate provided by the above embodiment, at least a portion of at least one first test signal line includes at least two conductive layers connected in parallel and electrically connected to each other, so that the routing resistance of the first test signal line can be reduced, so that during the aging process, the heat generation of the first test signal line is reduced and the heat diffusion is increased, which is beneficial to solve the problem of routing burns during the aging process and improve the product yield of the display panel.

[0047] At least one embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.

[0048] The embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] Figure 1 Schematic diagram of a display substrate provided by an embodiment of the present disclosure. Figure 1 As shown, the display substrate 1 includes a base substrate 100. For example, the display substrate 1 is a partial structural diagram of a product of a COF (chip on film, or chip on flex) structure. The base substrate 100 includes a display area 10 and a peripheral area 20 at least located on one side of the display area 20. For example, as shown in the example in the figure, the peripheral area 20 surrounds the display area 10.

[0050] Manufacturers of display devices, such as mobile phone manufacturers, usually pursue smaller and smaller bezels, especially narrower bottom bezels, and therefore try every means to reduce the "chin" of the display device to achieve a mobile phone screen with a larger screen-to-body ratio.

[0051] For example, the base substrate 100 may be a glass plate, a quartz plate, a metal plate or a resin plate, etc. For example, the material of the base substrate may include an organic material, such as a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate; for example, the base substrate 100 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.

[0052] For example, Figure 2A FIG. 1 is a schematic diagram of a display substrate provided by another embodiment of the present disclosure. Figure 2A As shown, the display substrate 1 includes a plurality of sub-pixels 101, a plurality of data lines 102, a test circuit CT, a plurality of data leads 21, at least one test pad ET1, at least one first test signal line 22, a plurality of gate lines GN, and a plurality of light-emitting control lines EM. The plurality of sub-pixels 101 are located in the display area 10 and are arranged in an array along a first direction X and a second direction Y. The plurality of data lines 102 are located in the display area 10 and are electrically connected to the plurality of column pixels 101, that is, each of the plurality of data lines 102 is electrically connected to each column of the plurality of sub-pixels 101 (for example, the column direction refers to Figure 1The plurality of data lines 102 are electrically connected one by one (in the vertical direction in the figure), and the plurality of data lines 102 are configured to provide data signals to the plurality of columns of sub-pixels 101. The plurality of gate lines GN are horizontally (for example, in the horizontal direction in the figure) through the display area 10 and the shift register GOA ( Figure 1 As shown) and a plurality of sub-pixels 101 (arranged in a horizontal row) are electrically connected, and a plurality of light emitting control lines EM are connected to a light emitting controller EOA ( Figure 1 As shown in the figure, the sub-pixels 101 are electrically connected to each other (arranged in a horizontal row) to provide the sub-pixels 101 with gate scanning signals and light emitting control signals.

[0053] The data signal provided by the data line 102 can make the sub-pixel 101 emit light in cooperation with the gate scanning signal and the light-emitting control signal to display the picture. For example, the data signal can be a numerical value within a predetermined grayscale value range, such as grayscales 255, 127, etc. corresponding to the grayscale value range of 0 to 255. The test circuit CT is located in the peripheral area 20, that is, below the display area 10 in the figure. A plurality of data leads 21 are located in the peripheral area 20, and are electrically connected to the plurality of data lines 102 and the test circuit CT respectively, that is, the plurality of data leads 21 are electrically connected to the plurality of data lines 102 one by one. The plurality of data leads 21 can also be regarded as the portion of the plurality of data lines 102 extending to the peripheral area 20. The plurality of data leads 21 and the plurality of data lines 102 can provide the electrical signal of the test circuit CT to the sub-pixel 101.

[0054] At least one test pad ET1 is located in the peripheral area 20 and at least one side of the test circuit CT. As shown in the figure, the at least one test pad ET1 may include a plurality of test pads ET1, and for example, are symmetrically arranged at intervals on both sides of the test circuit CT. The test pad ET1 is configured to be electrically connected (e.g., bonded, probe contacted, etc.) to an external test circuit during the lighting test phase, so as to apply a test signal to the sub-pixel 101 through the test circuit CT, and the sub-pixel 101 receives the test signal to display at least one test picture, thereby testing the performance of the sub-pixel 101 of the display substrate 1 in terms of displaying black and white pictures, monochrome pictures, and grayscale pictures.

[0055] At least one first test signal line 22 may include, for example, a plurality of first test signal lines 22. The first test signal line 22 is located in the peripheral area 20, and the first test signal line 22 is electrically connected to the test pad ET1 and the test circuit CT. The first test signal line 22 includes at least two conductive layers that are connected in parallel and electrically connected to each other, that is, at least part of the first test signal line 22 may be a double-layer parallel routing, a three-layer parallel routing, etc., or part of the first test signal line 22 may be a double-layer routing, and another part may be a three-layer routing, etc. By increasing the number of conductive film layers of the first test signal line 22, the routing resistance of the first test signal line may be reduced as a whole, so that during the aging process, the heat generation of the first test signal line is reduced and the heat diffusion is increased, which is beneficial to solve the problem of routing burns during the aging process and improve the product yield of the display panel.

[0056] For example, Figure 2A As shown, the peripheral area 20 also includes a first bonding area 24. The first bonding area 24 is located on a side of the test circuit CT away from the display area 10, and is located below the test circuit CT. In the first direction X, the first bonding area 24 and the test pads ET1 located on both sides of the test circuit CT are spaced apart. The first bonding area 24 is configured to bond with a signal input element, for example, the signal input element includes an integrated circuit (IC), and for another example, the signal input element includes a data driving circuit IC. The signal input element provides a display signal to the display substrate 1 in the display stage so that the sub-pixel 101 displays a picture.

[0057] For example, in some embodiments, Figure 3 for Figure 2A A magnified schematic diagram of the middle B1 region; Figure 4 for Figure 2A A magnified schematic diagram of the middle B2 region; Figure 5 for Figure 2A A magnified schematic diagram of the B3 area.

[0058] like Figure 3 , Figure 4 as well as Figure 5 As shown, the first test signal line 22 includes a first portion 221 and a second portion 222. The first portion 221 extends along a first direction X (horizontal direction in the figure), and the second portion 222 extends along a direction intersecting the first direction X. Figure 4As shown in , the second portion 222 is deflected and bent relative to the extension direction of the first portion 221, so as to continue to extend in the direction close to the first bonding area 24, and then electrically connected to the test circuit CT. That is, the first portion 221 of the first test signal line 22 is a horizontally extending portion, and extends from the side of the test pad ET1 close to the display area 10 to the portion close to the test circuit, and the second portion 222 of the first test signal line 22 is a portion bent and extended relative to the first portion 221. The first portion 221 is electrically connected to the test pad ET1 and the second portion 222, and the second portion 222 is also electrically connected to the test circuit CT, so that the test signal of the external test circuit electrically connected to the test pad ET1 is provided to the sub-pixel 101 through the test circuit CT.

[0059] For example, in some embodiments, at least a portion of at least one first test signal line includes three conductive layers connected in parallel to each other. Figure 6 For an example along Figure 4 Schematic diagram of a cross section of the center line A1-A2. The line A1-A2 is a section line of a portion of the first portion 221 of the first test signal line 22. Figure 4 and Figure 6 As shown, the first part 221 of the first test signal line 22 includes a first sub-conductive layer 201, a second sub-conductive layer 202 and a third sub-conductive layer 203. The first sub-conductive layer 201, the second sub-conductive layer 202 and the third sub-conductive layer 203 are insulated by an insulating layer, and are electrically connected through vias in the insulating layer to be arranged in parallel. The first test signal line 22 can reduce the routing resistance of the first test signal line as a whole by arranging three conductive layers in parallel. The calculation formula for the heat generated by the resistance heating is as follows:

[0060] I 2 ×R×t=Q (1)

[0061] In the above formula, I represents the current flowing through the line, R represents the resistance of the line, t represents time, and Q represents heat. According to formula (1), when the resistance of the first test signal line 22 decreases, the heat generated by the first test signal line 22 will decrease under the same time and current.

[0062] In addition, the heat conduction formula is as follows:

[0063] Q=CMΔT (2)

[0064] In formula (2), C represents specific heat capacity, ΔT represents temperature change, and M represents mass. Therefore, increasing the number of conductive film layers of the first test signal line 22 also increases the mass of the first test signal line 22. According to formula (2), when other influencing factors remain unchanged, the temperature change will decrease, thereby reducing the heat transferred from the first test signal line 22 to other film layers. Therefore, during the aging process, reducing the heat generation of the first test signal line and increasing heat diffusion are beneficial to solving the problem of wiring burns during the aging process and improving the product yield of the display panel.

[0065] For example, Figure 6 As shown, the display substrate 1 further includes a first insulating layer 142 (i.e., a first gate insulating layer), a second insulating layer 143 (i.e., a second gate insulating layer), and an interlayer insulating layer 144. The first insulating layer 142 is located on the base substrate 100 and is located on the side of the first sub-conductive layer 201 close to the base substrate 100, the second insulating layer 143 is located between the first sub-conductive layer 201 and the second sub-conductive layer 202, and the interlayer insulating layer 144 is located between the second sub-conductive layer 202 and the third sub-conductive layer 203. The third sub-conductive layer 203 can be electrically connected to the second sub-conductive layer 202 through a plurality of vias V1 penetrating through the interlayer insulating layer 144, thereby realizing the parallel electrical connection of the third sub-conductive layer 203 and the second sub-conductive layer 202. The first sub-conductive layer 201 and the second sub-conductive layer 202 can be electrically connected through a plurality of vias penetrating through the second insulating layer 143, thereby realizing the parallel electrical connection of the first sub-conductive layer 201 and the second sub-conductive layer 202.

[0066] It should be noted that the number of vias V1 can be multiple. Figure 6 The number of vias connecting the first sub-conductive layer 201 and the second sub-conductive layer 20 is not limited to two as shown in the figure, for example, it can be a plurality of vias distributed (uniformly arranged) on the first test signal line 22, and the embodiment of the present disclosure is not limited thereto.

[0067] For example, the materials of the first sub-conductive layer 201, the second sub-conductive layer 202, and the third sub-conductive layer 203 may include metal materials or alloy materials, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0068] For example, one or more of the first insulating layer 142, the second insulating layer 143 and the interlayer insulating layer 144 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the first insulating layer 142, the second insulating layer 143 and the interlayer insulating layer 144 may be the same or different.

[0069] For example, Figure 6 As shown, the display substrate 1 may further include a third insulating layer 145 (e.g., a peripheral area planarization layer or a passivation layer). The third insulating layer 145 is located on a side of the third sub-conductive layer 203 away from the base substrate 100 to provide a planarized surface and to protect the first test signal line 22 and the electrostatic lead ESL.

[0070] For example, Figure 6 As shown, the display substrate 1 may further include a buffer layer 141. The buffer layer 141 is located between the first insulating layer 142 and the base substrate 100. The buffer layer 141 serves as a transition layer, which can prevent harmful substances in the base substrate from invading the interior of the display substrate and increase the adhesion of the film layer in the display substrate on the base substrate 100. The material of the buffer layer 141 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0071] For example, Figure 3 As shown, the number of the first test signal lines 22 is 6. However, the example disclosed in the present invention is not limited thereto, and the number of the first test signal lines 22 can also be changed according to the requirements of the display panel design. Figure 3 Introduced as an example.

[0072] For example, Figure 2A , Figure 3 as well as Figure 5 As shown, the display substrate 1 further includes a plurality of test pad leads EL and a plurality of second test signal lines 23, and the at least one test pad ET1 includes a plurality of test pads ET1. The plurality of test pad leads EL extend along the second direction Y (i.e., the vertical direction in the figure) and are electrically connected to the plurality of test pads ET1 in a one-to-one correspondence. For example, Figure 2A The multiple test pads ET1 shown in FIG. are distributed on both sides of the test circuit CT. Figure 3 In the example, the multiple test pads ET1 located on one side of the test circuit CT are taken as an example. The arrangement of the multiple test pads ET1 located on the other side of the test circuit CT and the connection with the wiring are as follows: Figure 3 The same as in, no longer detailed description.

[0073] For example, Figure 3 As shown, some of the test pad leads EL of the plurality of test pad leads EL are electrically connected to the first parts 221 of the plurality of first test signal lines 22. That is, the first test pad lead EL to the fifth test pad lead EL and the ninth test pad lead EL from the left in the figure are electrically connected to the first parts 221 of the six first test signal lines 22, respectively, so that the test signal of the external test circuit electrically connected to the test pad ET1 is transmitted to the first test signal line 22.

[0074] It should be noted that the embodiments of the present disclosure are not limited to Figure 3 The connection mode of the test pad lead EL and the first test signal line 22 is shown. In other embodiments, the first to sixth test pad lead EL on the left side may be electrically connected to the first parts 221 of the six first test signal lines 22 respectively.

[0075] For example, Figure 2A as well as Figure 5 As shown, the plurality of second test signal lines 23 are electrically connected to the test circuit CT and the plurality of first test signal lines 22, respectively, that is, the plurality of second test signal lines 23 are electrically connected to the plurality of first test signal lines 22 in a one-to-one correspondence. The orthographic projections of the second portions 222 of the plurality of first test signal lines 22 and the plurality of second test signal lines 23 on the substrate 100 at least partially overlap. The second portions 222 of the plurality of first test signal lines 22 and the plurality of second test signal lines 23 both extend to the first bonding area 24 and are connected to each other, and the second portions 222 of the plurality of first test signal lines 22 and the plurality of second test signal lines 23 cross each other. The display signal provided by the signal input element bonded to the first bonding area 24 and the test signal transmitted by the first test signal line 22 can be provided to the sub-pixel 101 through the second test signal line 23 via the CT unit.

[0076] For example, Figure 2A as well as Figure 5 As shown, the second portion 222 of the first test signal line 22 includes the first sub-conductive layer 201 and the second sub-conductive layer 202, and the second test signal line 23 is disposed in the same layer as the third sub-conductive layer 203. The second test signal line 23 is located at a side of the second portion 222 of the first test signal line 22 away from the base substrate 100, and is spaced and insulated from the first test signal line 22, so that when the orthographic projections of the second portions 222 of the plurality of first test signal lines 22 and the plurality of second test signal lines 23 on the base substrate 100 overlap, no signal crosstalk occurs.

[0077] For example, Figure 2A as well as Figure 5 As shown, the first bonding region 24 includes a plurality of contact pads 241. The plurality of contact pads 241 are configured to bond with the signal input element. Parts of the plurality of contact pads 241 are electrically connected to the test circuit CT to provide display signals to the plurality of sub-pixels 101.

[0078] For example, Figure 5As shown, the plurality of contact pads 241 include a plurality of first contact pads 243 (for example, located on the left side of the figure). The second portion 222 of each of the plurality of first test signal lines 22 and each of the plurality of second test signal lines 23 extend to one end of the plurality of first contact pads 243 away from the first bonding area 24, respectively, and are electrically connected to one end of the plurality of first contact pads 243 away from the first bonding area 24 in a one-to-one correspondence. That is, the plurality of first test signal lines 22 and the plurality of second test signal lines 23 extend to one end of the plurality of first contact pads 243 away from the first bonding area 24 in a one-to-one correspondence, so that at the location of one end of the plurality of first contact pads 243 away from the first bonding area 24, the plurality of first test signal lines 22, the plurality of second test signal lines 23 and the plurality of first contact pads 243 are electrically connected in a one-to-one correspondence. Since the second portion 222 of the first test signal line 22 and the second test signal line 23 are located in different film layers, the second portion 222 of the first test signal line 22 and the second test signal line 23 are connected through a jumper. For example, the second test signal line 23 is electrically connected to the second portion 222 of the first test signal line 22 through a via hole penetrating the interlayer insulating layer 144 .

[0079] For example, Figure 2A as well as Figure 3 As shown, the display substrate 1 further includes at least one first electrostatic discharge unit ESD1. Figure 3 The at least one first electrostatic discharge unit ESD1 shown includes a plurality of first electrostatic discharge units ESD1. The first electrostatic discharge unit ESD1 is located on one side of the plurality of test pads ET1 close to the display area 10, and portions of the plurality of test pad leads EL pass through the first electrostatic discharge unit ESD1 and are electrically connected to the first electrostatic discharge unit ESD1. For example, in the portions of the plurality of test pad leads EL located on both sides in the figure, each test pad lead EL is electrically connected to a first electrostatic discharge unit ESD1, respectively. The first electrostatic discharge unit ESD1 is configured to remove or reduce static electricity in the test pad leads EL to ensure signal stability in the test pad leads EL.

[0080] It should be noted that each of the plurality of test pad leads EL may be electrically connected to a first electrostatic discharge unit ESD1. The embodiment of the present disclosure is not limited to Figure 3 In other embodiments, whether the test pad lead EL is electrically connected to the first electrostatic discharge unit ESD1 can also be set according to the signal transmitted in the test pad lead EL.

[0081] For example, Figure 3As shown, among the multiple test pad leads EL, other test pad leads EL except the test pad leads EL electrically connected to the multiple first test signal lines 22 extend in a direction away from the test pad ET1, thereby overlapping with the first portion 221 of the first test signal line 22, and the orthographic projection of the test pad lead EL not electrically connected to the first test signal line 22 on the base substrate 100 overlaps with the orthographic projection of the first portion 221 of the first test signal line 22 on the base substrate 100. For example, the first portion 221 of the first test signal line 22 includes the first sub-conductive layer 201 and the second sub-conductive layer 202 at the portion overlapping with the test pad lead EL, and the test pad lead EL is arranged in the same layer as the third sub-conductive layer 203. That is, in Figure 3 In the embodiment, the first part 221 of the first test signal line 22 includes the first sub-conductive layer 201, the second sub-conductive layer 202 and the third sub-conductive layer 203 except the part overlapping with the test pad lead EL. In this case, the part overlapping with the first part 221 of the first test signal line 22 is located in different film layers to avoid signal crosstalk, and at the same time, the heat generation of the first test signal line can be reduced and the heat diffusion can be increased during the aging process, which is beneficial to solve the problem of wiring burns during the aging process and improve the product yield of the display panel.

[0082] For example, Figure 4 As shown, the display substrate 1 further includes at least one second electrostatic discharge unit ESD2 and at least one electrostatic lead ESL located in the peripheral area 20. Figure 4 The display substrate 1 shown may include a plurality of second electrostatic discharge units ESD2, for example, the number of the plurality of second electrostatic discharge units ESD2 may be 6 to correspond to the number of the first test signal lines 22, but the disclosed embodiment is not limited thereto. For example, at least one electrostatic lead line ESL includes a plurality of electrostatic leads ESL, and the plurality of electrostatic leads ESL are electrically connected to the plurality of second electrostatic discharge units ESD2 in a one-to-one correspondence.

[0083] like Figure 2A As shown, the plurality of second electrostatic discharge units ESD2 are located between the plurality of test pads ET1 and the first bonding region 24 in the first direction X, and the plurality of second electrostatic discharge units ESD2 are arranged along the first direction X.

[0084] For example, Figure 4 As shown, the electrostatic lead ESL extends along the second direction Y and is electrically connected to a plurality of first test signal lines 22 , so that the static electricity in the first test signal lines 22 is removed or reduced by the second electrostatic discharge unit ESD2 to ensure signal stability in the first test signal lines 22 .

[0085] For example, Figure 4As shown, the display substrate 1 may further include one or more resistors R1 connected to the second electrostatic discharge unit ESD2, and both ends of the resistor R1 are electrically connected to the same second electrostatic discharge unit ESD2 (eg, the second electrostatic discharge unit ESD2 on the right side of the figure).

[0086] For example, Fig. 7A An embodiment of the present disclosure provides Figure 4 A schematic diagram of the circuit principle of the second electrostatic release unit; Figure 7B Another embodiment of the present disclosure provides Figure 4 Schematic diagram of the circuit principle of the second electrostatic release unit in FIG.

[0087] Fig. 7A FIG. 2 shows an exemplary circuit schematic diagram of a second electrostatic discharge unit ESD2 electrically connected to the resistor R1. Fig. 7A As shown, the electrostatic lead ESL is electrically connected to the first thin film transistor T1, for example, one of the source and drain electrodes of the first thin film transistor T1 is short-circuited with its gate to form a diode structure to have a unidirectional conduction characteristic, and a resistor R1 is electrically connected between one of the source and drain electrodes of the first thin film transistor T1 and its gate to improve the conductivity of the first thin film transistor T1. When the signal transmitted by the first test signal line 22 electrically connected to the electrostatic lead ESL is a high-level signal, the first thin film transistor T1 is turned on to conduct the static charge on the first test signal line 22.

[0088] Figure 7B FIG. 2 shows an exemplary circuit schematic diagram of a second electrostatic discharge unit ESD2 that is not electrically connected to the resistor R1. Figure 7B As shown, the electrostatic lead ESL is electrically connected to the second thin film transistor T2, for example, one of the source and drain electrodes of the second thin film transistor T2 is short-circuited with its gate to form a diode structure to have a unidirectional conduction characteristic. When the signal transmitted by the first test signal line 22 electrically connected to the electrostatic lead ESL is a high level signal, the second thin film transistor T2 is turned on to conduct the electrostatic charge on the first test signal line 22.

[0089] For example, Figure 4As shown, a plurality of electrostatic leads ESL are arranged side by side in a first direction X (e.g., horizontal direction), and a plurality of first parts 221 of a plurality of first test signal lines 22 are arranged side by side in a second direction Y (e.g., vertical direction), and are electrically connected to the plurality of electrostatic leads ESL one by one. That is, the extension directions of the plurality of electrostatic leads ESL and the plurality of first test signal lines 22 intersect with each other and are electrically connected accordingly. The orthographic projections of the first parts 221 of the first test signal lines 22 and the electrostatic leads ESL on the base substrate 100 overlap. As shown in the figure, the electrostatic lead ESL located on the far right is electrically connected to the first part 221 of the first test signal line 22 farthest from the second electrostatic unit ESD2, and overlaps with other first test signal lines 22 (other five first test signal lines 22); the second to last electrostatic lead ESL located on the right is electrically connected to the first part 221 of the second (counted from the side far away from the second electrostatic release unit ESD2) first test signal line 22, and overlaps with other first test signal lines 22 (other four first test signal lines 22) closer to the second electrostatic release unit ESD2 relative to the second first test signal line 22, and so on. For example, the third to last electrostatic lead ESL located on the right overlaps with three first test signal lines 22. The part where the first part 221 of multiple first test signal lines 22 overlaps with multiple electrostatic leads ESL includes the first sub-conductive layer 201 and the second sub-conductive layer 202. That is, Figure 4 The portion of the first portion 221 of the plurality of first test signal lines 22 that does not overlap with the electrostatic lead ESL includes the first sub-conductive layer 201, the second sub-conductive layer 202, and the third sub-conductive layer 203. For example, the electrostatic lead ESL and the third sub-conductive layer 203 are arranged in the same layer. In this case, the portion where the electrostatic lead ESL overlaps with the first portion 221 of the first test signal line 22 is located in a different film layer to avoid signal crosstalk, and at the same time, the heat generated by the first test signal line can be reduced and heat diffusion can be increased during the aging process, thereby helping to solve the problem of wiring burns during the aging process and improve the product yield of the display panel.

[0090] For example, Figure 2A As shown, the display substrate further includes a plurality of signal leads 242. The plurality of signal leads 242 electrically connect a portion of the plurality of contact pads 241 of the first bonding region 24 with the test circuit CT.

[0091] For example, Fig. 8A A schematic diagram of the layout of a test unit provided in one embodiment of the present disclosure. Figure 8B An embodiment of the present disclosure provides Fig. 8A A partial enlarged schematic diagram of Fig. 8A and Figure 8BAs shown, the test circuit CT includes a plurality of test units CT1. The test unit CT1 includes a first multiplexing switch K1, a second multiplexing switch K2, a third multiplexing switch K3, a first control line SWR, a second control line SWG, a third control line SWB, a first signal line DR, a second signal line DB, and a third signal line DG. A plurality of second test signal lines 23 are electrically connected to the first control line SWR, the second control line SWG, the third control line SWB, the first signal line DR, the second signal line DB, and the third signal line DG in a one-to-one correspondence to transmit the test signal provided by the first test signal line 22 to the test unit CT1.

[0092] For example, Fig. 8A and Figure 8B As shown, at least one gate of the first multiplexing switch K1 (for example, including the first multiplexing switch first gate G11 and the first multiplexing switch second gate G12) is electrically connected to the first control line SWR or the third control line SWB, at least one source of the first multiplexing switch K1 (for example, including the first multiplexing switch first source S11 and the first multiplexing switch second source S12) is electrically connected to the first signal line DR or the second signal line DB, and at least one drain of the first multiplexing switch K1 (for example, including the first multiplexing switch drain D11) is electrically connected to one data lead of the multiple data leads 21.

[0093] At least one gate of the second multiplexing switch K2 (for example, including the second multiplexing switch first gate G21 and the second multiplexing switch second gate G22) is electrically connected to the first control line SWR or the third control line SWB, at least one source of the second multiplexing switch K2 (for example, including the second multiplexing switch first source S21 and the second multiplexing switch second source S22) is electrically connected to the first signal line DR or the second signal line DB, and at least one drain of the second multiplexing switch K2 (for example, including the second multiplexing switch drain D21) is electrically connected to another data lead of the multiple data leads 21.

[0094] At least one gate of the third multiplexing switch K3 (for example, including the third multiplexing switch first gate G31 and the third multiplexing switch second gate G32) is electrically connected to the second control line SWG, at least one source of the third multiplexing switch K3 (for example, including the third multiplexing switch first source S31) is electrically connected to the third signal line DG, and at least one drain of the third multiplexing switch K3 (for example, including the third multiplexing switch first drain D31 and the third multiplexing switch second drain D32) is electrically connected to one data lead line among the multiple data leads 21 and another data lead line among the multiple data leads 21 (that is, two data leads 21 electrically connected to at least one drain of the second multiplexing switch K2 and at least one drain of the first multiplexing switch K1, respectively).

[0095] For example, Fig. 8AAs shown, the first multiplexing switch K1 includes a first multiplexing switch active layer P11, a first multiplexing switch first gate G11, a first multiplexing switch second gate G12, a first multiplexing switch drain D11, a first multiplexing switch first source S11, and a first multiplexing switch second source S12. The first multiplexing switch active layer P11 is located on the base substrate 100, and the first multiplexing switch first gate G11 and the first multiplexing switch second gate G12 are located on the side of the first multiplexing switch active layer P11 away from the base substrate 100 and separated by a first insulating layer 142 (not shown in the figure for simplicity of the figure). The orthographic projection of the first multiplexing switch first gate G11 on the base substrate 100 and the orthographic projection of the first multiplexing switch second gate G12 on the base substrate 100 are staggered.

[0096] The first multiplexing switch drain D11, the first multiplexing switch first source S11 and the first multiplexing switch second source S12 are located on the side of the first multiplexing switch first gate G11 and the first multiplexing switch second gate G12 away from the base substrate 100 and separated by the second insulating layer 143 and the interlayer insulating layer 144 (not shown in the figure). The first multiplexing switch drain D11 is located between the first multiplexing switch first source S11 and the first multiplexing switch second source S12.

[0097] The orthographic projection of the first gate G11 of the first multiplexing switch on the substrate 100 is located between the orthographic projections of the first source S11 of the first multiplexing switch and the drain D11 of the first multiplexing switch on the substrate 100, and the orthographic projection of the second gate G12 of the first multiplexing switch on the substrate 100 is located between the orthographic projections of the second source S12 of the first multiplexing switch and the drain D11 of the first multiplexing switch on the substrate 100.

[0098] The first gate electrode G11 of the first multiplexing switch is electrically connected to the first control line SWR, and the second gate electrode G12 of the first multiplexing switch is electrically connected to the third control line SWB. The first source electrode S11 of the first multiplexing switch is electrically connected to the first signal line DR through the first transfer electrode TLS1, and the second source electrode S12 of the first multiplexing switch is electrically connected to the third signal line DB through the second transfer electrode TLS2. The first drain electrode D11 of the first multiplexing switch is electrically connected to the signal lead 242 ( Fig. 8A The first multiplexing switch K1 is electrically connected to the data lead 21 (left side in 8A), and the first drain electrode D11 of the first multiplexing switch is also electrically connected to the data lead 21 (left side in 8A), so as to provide the display signal provided by the signal input element bound by the first bonding area 24 to the sub-pixel 101 in the display stage. In the test stage, the first multiplexing switch K1 is turned on under the control of the control signals provided by the first control line SWR and the third control line SWB, and transmits the signals provided by the first signal line DR and the third signal line DB to the sub-pixel 101 through the first drain electrode D11 of the first multiplexing switch.

[0099] For example, Fig. 8A As shown, the first transfer electrode TLS1, the second transfer electrode TLS2 and the third transfer electrode TLS3 are located between the gate of the first multiplexing switch K1 and the source and drain of the first multiplexing switch K1, that is, the first transfer electrode TLS1, the second transfer electrode TLS2 and the third transfer electrode TLS3 are separated from the first gate G11 of the first multiplexing switch and the second gate G12 of the first multiplexing switch by the second insulating layer 143, and the first transfer electrode TLS1, the second transfer electrode TLS2 and the third transfer electrode TLS3 are separated from the first multiplexing switch drain D11, the first source S11 of the first multiplexing switch and the second source S12 of the first multiplexing switch by the interlayer insulating layer 144.

[0100] For example, Fig. 8A and Figure 8B As shown, the second multiplexing switch K2 includes a second multiplexing switch active layer P21, a second multiplexing switch first gate G21, a second multiplexing switch second gate G22, a second multiplexing switch drain D21, a second multiplexing switch first source S21, and a second multiplexing switch second source S22. The second multiplexing switch active layer P21 is located on the base substrate 100, the second multiplexing switch first gate G21 and the second multiplexing switch second gate G22 are located on the side of the second multiplexing switch active layer P21 away from the base substrate 100 and separated by a first insulating layer 142 (not shown in the figure), and the orthographic projection of the second multiplexing switch first gate G21 on the base substrate 100 and the orthographic projection of the second multiplexing switch second gate G22 on the base substrate 100 are staggered.

[0101] The second multiplexing switch drain D21, the second multiplexing switch first source S21 and the second multiplexing switch second source S22 are located on the side of the second multiplexing switch first gate G21 and the second multiplexing switch second gate G22 away from the base substrate 100 and are separated by the second insulating layer 143 and the interlayer insulating layer 144 (not shown in the figure), and the second multiplexing switch drain D21 is located between the second multiplexing switch first source S21 and the second multiplexing switch second source S22.

[0102] The orthographic projection of the first gate G21 of the second multiplexing switch on the base substrate 100 is located between the orthographic projections of the first source S21 of the second multiplexing switch and the drain D21 of the second multiplexing switch on the base substrate 100, and the orthographic projection of the second gate G22 of the second multiplexing switch on the base substrate 100 is located between the orthographic projections of the second source S22 of the second multiplexing switch and the drain D21 of the second multiplexing switch on the base substrate 100.

[0103] The first gate electrode G21 of the second multiplexing switch is electrically connected to the first control line SWR, and the second gate electrode G22 of the second multiplexing switch is electrically connected to the third control line SWB. The first source electrode S21 of the second multiplexing switch is electrically connected to the third signal line DB through the fourth transfer electrode TLS4, and the second source electrode S22 of the second multiplexing switch is electrically connected to the first signal line DR through the fifth transfer electrode TLS5. The first drain electrode D21 of the second multiplexing switch is electrically connected to the signal lead 242 ( Fig. 8A The first drain electrode D21 of the second multiplexing switch is also electrically connected to the data lead 21 ( Fig. 8A The second multiplexing switch K2 is electrically connected to the sub-pixel 101 (right side in the middle) to provide the display signal provided by the signal input element bonded to the first bonding area 24 to the sub-pixel 101 in the display stage. In the test stage, the second multiplexing switch K2 is turned on under the control of the control signals provided by the first control line SWR and the third control line SWB, and transmits the signals provided by the first signal line DR and the third signal line DB to the sub-pixel 101 through the first drain D21 of the second multiplexing switch.

[0104] For example, Fig. 8A As shown, the fourth transfer electrode TLS4, the fifth transfer electrode TLS5 and the sixth transfer electrode TLS6 are located between the gate of the second multiplexing switch K2 and the source and drain of the second multiplexing switch K2, that is, the fourth transfer electrode TLS4, the fifth transfer electrode TLS5 and the sixth transfer electrode TLS6 are separated from the first gate G21 of the second multiplexing switch and the second gate G22 of the second multiplexing switch by the second insulating layer 143, and the fourth transfer electrode TLS4, the fifth transfer electrode TLS5 and the sixth transfer electrode TLS6 are separated from the drain D21 of the second multiplexing switch, the first source S21 of the second multiplexing switch and the second source S22 of the second multiplexing switch by the interlayer insulating layer 144.

[0105] For example, Fig. 8A and Figure 8B As shown, the third multiplexing switch K3 includes a third multiplexing switch active layer P31, a third multiplexing switch first gate G31, a third multiplexing switch second gate G32, a third multiplexing switch source S31, a third multiplexing switch first drain D31 and a first multiplexing switch second drain D32. The third multiplexing switch active layer P31 is located on the base substrate 100, and the third multiplexing switch first gate G31 and the third multiplexing switch second gate G32 are located on the side of the third multiplexing switch active layer P31 away from the base substrate 100 and separated by a first insulating layer 142 (not shown in the figure). The orthographic projection of the third multiplexing switch first gate G31 on the base substrate 100 and the orthographic projection of the third multiplexing switch second gate G32 on the base substrate 100 are staggered.

[0106] The third multiplexing switch source S31, the third multiplexing switch first drain D31 and the third multiplexing switch second drain D32 are located on the side of the third multiplexing switch first gate G31 and the third multiplexing switch second gate G32 away from the base substrate 100 and separated by the second insulating layer 143 and the interlayer insulating layer 143 (not shown in the figure). The third multiplexing switch source S31 is located between the third multiplexing switch first drain D31 and the third multiplexing switch second drain D32.

[0107] The orthographic projection of the first gate G31 of the third multiplexing switch on the substrate substrate 100 is located between the orthographic projections of the first drain D31 of the third multiplexing switch and the source S31 of the third multiplexing switch on the substrate substrate 100, and the orthographic projection of the second gate G32 of the third multiplexing switch on the substrate substrate 100 is located between the orthographic projections of the second drain D32 of the third multiplexing switch and the source S32 of the third multiplexing switch on the substrate substrate 100.

[0108] The first drain electrode D31 of the third multiplexing switch is electrically connected to the data lead line 21 (located at Fig. 8A The second drain electrode D32 of the third multiplexing switch is electrically connected to the data lead 21 (located at Fig. 8A The third multiplexing switch first gate G31 and the third multiplexing switch second gate G32 are electrically connected to the second control line SWG, and the third multiplexing switch source S31 is electrically connected to the third signal line DG through the seventh transfer electrode TSL7. In the test phase, the third multiplexing switch K3 is turned on under the control of the control signal provided by the second control line SWG, and transmits the signal provided by the third signal line DG to the sub-pixel 101 through the third multiplexing switch first drain D31 and the third multiplexing switch second drain D32.

[0109] For example, Fig. 8A As shown, the seventh transfer electrode TSL7 is located between the gate of the third multiplexing switch K3 and the source and drain of the third multiplexing switch K3, that is, the seventh transfer electrode TSL7 and the third multiplexing switch first gate G31 and the third multiplexing switch second gate G32 are separated by the second insulating layer 143, and the seventh transfer electrode TSL7 and the third multiplexing switch source S31, the third multiplexing switch first drain D31 and the third multiplexing switch second drain D32 are separated by the interlayer insulating layer 144.

[0110] It should be noted that the first multiplexing switch K1 , the second multiplexing switch K2 and the third multiplexing switch K3 are electrically connected to the sub-pixels 101 in different columns via the data leads 21 .

[0111] For example, Figure 2B A schematic diagram of a display substrate provided in yet another embodiment of the present disclosure; Fig. 9 for Figure 2B A magnified schematic diagram of the B4 region in Figure 2. Figure 2B as well as Fig. 9 As shown, the display substrate 1 further includes a first power line VSS and a second power line VDD located in the peripheral area 20 , and the first power line VSS is located on a side of the second power line VDD close to the test pad ET1 .

[0112] For example, Fig. 9 As shown, the plurality of contact pads 241 further include a plurality of second contact pads 244, and the plurality of second contact pads 244 are located between the plurality of first contact pads 243 ( Figure 5 A portion of the plurality of second contact pads 244 is configured to be electrically connected to the first power line VSS, and another portion is electrically connected to the second power line VDD, so that the signal provided by the signal input element electrically connected to the first bonding region 24 is provided to the sub-pixel 101.

[0113] For example, Figure 2B as well as Fig. 9 As shown, the first power line VSS is configured to provide a first power signal to the plurality of sub-pixels 101, and the first power line VSS is connected to a portion of the plurality of second contact pads 244 ( Fig. 9 The second power line VDD is electrically connected to the second contact pad 244 and extends around the display area 10. The second power line VDD is configured to provide a second power signal to the plurality of sub-pixels 101. The second power line VDD is electrically connected to another portion of the plurality of second contact pads 244 ( Fig. 9 The display substrate 1 further includes a plurality of second power signal lines VDD1 located in the display area 10, the second power signal lines VDD1 are electrically connected to the second power lines VDD, and each of the second power signal lines VDD1 is electrically connected to each column of sub-pixels 101.

[0114] It should be noted that the second power line VDD is a power line for providing a high voltage to the plurality of sub-pixels 101, and the first power line VSS is a power line for providing a low voltage (lower than the aforementioned high voltage) to the plurality of sub-pixels 101. Figure 2B In the illustrated embodiment, the second power line VDD provides a constant second power voltage, which is a positive voltage; the first power line VSS provides a constant first power voltage, which may be a negative voltage, etc. For example, in some examples, the first power voltage may be a ground voltage.

[0115] For example, Fig. 9As shown, the first power line VSS and the second power line VDD are located on a side of the second portion 222 of the plurality of first test signal lines 22 away from the base substrate 100, and the orthographic projections of the first power line VSS and the second power line VDD on the base substrate 100 overlap with the orthographic projections of the second portion 222 of the plurality of first test signal lines 22 on the base substrate 100. Since the first power line VSS and the second power line VDD are located in different film layers from the second portion 222 of the plurality of first test signal lines 22, signal crosstalk can be avoided.

[0116] For example, Figure 1 as well as Figure 2A As shown, the display substrate 1 also includes a shift register GOA and a light emitting controller EOA located in the peripheral area 20 (for example, located on both sides of the display area 10 of the display substrate 1). The shift register GOA includes a plurality of cascaded shift register units, such as n-stage shift register units (for example, a first-stage shift register unit GOA1, a second-stage shift register unit GOA2..., and an n-th-stage shift register unit GOAn). Each stage of the shift register unit is configured to provide a gate scanning signal to the sub-pixels 101 located in a row through the gate line GN in the display area 10. The light emitting controller EOA includes a plurality of cascaded light emitting control units, such as m-stage light emitting control units (for example, a first-stage light emitting control unit EOA1, a second-stage light emitting control unit EOA2,..., and an m-th-stage light emitting control unit EOAm). Each stage of the light emitting control unit is configured to provide a light emitting control signal to the sub-pixels 101 in at least one row (for example, two rows of sub-pixels 101) through the light emitting control line EM in the display area 10. For example, the light emitting control unit is also a shift register unit, for example, having the same circuit structure as the shift register unit of the shift register GOA.

[0117] For example, Figure 2AAs shown, the display substrate 1 also includes a first clock signal line GCB, a second clock signal line GCK, a third clock signal line ECB, a fourth clock signal line ECK, a first trigger signal line GSTV, a second trigger signal line ESTV, a third power line VGH, a fourth power line VGL and an initialization signal line VINT. The first clock signal line GCB, the second clock signal line GCK and the n-stage shift register unit are electrically connected, and the first trigger signal line GSTV and the first-stage shift register unit GOA1 are electrically connected to provide the first clock signal, the second clock signal and the first trigger signal respectively. The third clock signal line ECB, the fourth clock signal line ECK and the m-stage light emitting control unit are electrically connected, and the second trigger signal line ESTV and the first-stage light emitting control unit EOA1 are electrically connected to provide the third clock signal, the fourth clock signal and the second trigger signal respectively. The third power line VGH and the fourth power line VGL are electrically connected to the n-stage shift register unit and the m-stage light emitting control unit, respectively, to provide the third power signal and the fourth power signal respectively. The initialization signal line VINT is configured to be electrically connected to the plurality of sub-pixels 101 and provide the initialization signal to the plurality of sub-pixels 101. For example, the initialization signal line VINT also provides a constant low voltage, which may be a negative voltage, etc. For example, in some examples, the low voltage may be a ground voltage.

[0118] It should be noted that in Figure 2A In the embodiment, the n-stage shift register unit, the m-stage light emitting control unit, the first clock signal line GCB, the second clock signal line GCK, the third clock signal line ECB, the fourth clock signal line ECK, the first trigger signal line GSTV, the second trigger signal line ESTV, the third power line VGH, the fourth power line VGL and the initialization signal line VINT are symmetrically arranged on both sides of the display area 10, that is, double-sided driving. According to the circuit setting requirements of the display substrate 1, single-sided driving can also be adopted, and the embodiments of the present disclosure are not limited thereto.

[0119] For example, Figure 2A As shown, the display substrate 1 further includes a plurality of bending lines 25 located on one side of the plurality of first test signal lines 22 close to the display area 10, and the plurality of bending lines 25 are arranged in parallel to reduce the wiring space. The plurality of bending lines 25 are electrically connected to the first clock signal line GCB, the second clock signal line GCK, the third clock signal line ECB, the fourth clock signal line ECK, the first trigger signal line GSTV, the second trigger signal line ESTV, the third power line VGH, the fourth power line VGL, and the initialization signal line VINT, respectively.

[0120] For example, Figure 5As shown, a plurality of bending lines 25 extend to the first bonding region 24 and are electrically connected to the contact pad 241, so as to provide the signal provided by the signal input element bonded to the first bonding region 24 to the sub-pixel 101. For example, the contact pad 241 is electrically connected to the bending line 25 through a via hole. For example, the contact pad 241 is electrically connected to the bending line 25 through a via hole penetrating the interlayer insulating layer 144.

[0121] For example, Figure 5 as well as Fig. 9 As shown, the orthographic projections of the plurality of bending lines 25 on the substrate 100 overlap with the orthographic projections of the first power line VSS, the second power line VDD and the second test signal line 23 on the substrate 100. The bending line 25 includes two conductive layers, for example, the two conductive layers are respectively Figure 6 The first sub-conductive layer 201 and the second sub-conductive layer 202 are arranged on the same layer.

[0122] In other embodiments, the bending line 25 may include a single conductive layer, for example, the conductive layer is disposed in the same layer as the first sub-conductive layer 201 or the second sub-conductive layer 202 , but the embodiments of the present disclosure are not limited thereto.

[0123] For example, Figure 3 As shown, the multiple test pad leads EL that are not electrically connected to the first test signal lines 22 are electrically connected to the multiple bending lines 25 in a one-to-one correspondence. The test pad leads EL that are electrically connected to the bending lines 25 overlap with the first parts 221 of the multiple first test signal lines 22, that is, the orthographic projections of the first parts 221 of the multiple first test signal lines 22 on the base substrate 100 overlap with the orthographic projections of the test pad leads EL that are electrically connected to the multiple bending lines 25 on the base substrate 100. The portion where the first parts 221 of the multiple first test signal lines 22 overlap with the test pad leads EL that are electrically connected to the multiple bending lines 25 includes the first sub-conductive layer 201 and the second sub-conductive layer 202. Figure 3 In the embodiment, the first part 221 of the first test signal line 22 includes the first sub-conductive layer 201, the second sub-conductive layer 202 and the third sub-conductive layer 203, except for the part overlapping with the test pad lead EL respectively electrically connected to the plurality of bending lines 25. In this case, the part overlapping with the first part 221 of the first test signal line 22 is located in different film layers to avoid signal crosstalk, and at the same time, the heat generation of the first test signal line can be reduced and the heat diffusion can be increased during the aging process, which is beneficial to solve the problem of wiring burns during the aging process and improve the product yield of the display panel.

[0124] For example, Fig.10 FIG. 1 is a cross-sectional schematic diagram of a display area of ​​a display substrate provided by an embodiment of the present disclosure. Fig.10As shown, each of the multiple sub-pixels 101 includes a pixel structure, and the pixel structure includes a pixel driving circuit 103. The pixel driving circuit 103 includes a first metal layer 301, a second metal layer 302, and a third metal layer 303. The first metal layer 301 is located on the base substrate 100, that is, between the first insulating layer 1242 of the display area and the second insulating layer 1243 of the display area. The second metal layer 302 is located on the side of the first metal layer 301 away from the base substrate 100, that is, between the second insulating layer 1243 of the display area and the interlayer insulating layer 1244 of the display area. The third metal layer 303 is located on the side of the second metal layer 302 away from the base substrate 100, that is, on the side of the interlayer insulating layer 1244 of the display area away from the base substrate 100. For example, Figure 6 The first sub-conductive layer 201 , the second sub-conductive layer 202 and the third sub-conductive layer 203 of the first test signal line 22 are respectively disposed on the same layer as the first metal layer 301 , the second metal layer 302 and the third metal layer 303 and are made of the same material.

[0125] It should be noted that in the embodiments of the present disclosure, "same-layer arrangement" includes two functional layers or structural layers being formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed of the same material layer and can be formed into the required pattern and structure by the same composition process. A single composition process, for example, includes the formation of photoresist, exposure, development, etching and other processes.

[0126] For example, Fig.10As shown, the pixel driving circuit 103 also includes a plurality of transistors and capacitors, the plurality of transistors including transistors directly electrically connected to the light emitting device, the transistors being, for example, switch transistors (e.g., light emitting control transistors) or driving transistors. The plurality of capacitors include storage capacitors (to store written data signals). In one embodiment, the pixel driving circuit 103 includes a driving transistor 12 and a storage capacitor 13. The driving transistor 12 includes a gate 122, a source 123, a drain 124, and an active layer 121. The display substrate 1 also includes a display area buffer layer 1241, a display area first insulating layer 1242, a display area second insulating layer 1243, and a display area interlayer insulating layer 1244. The storage capacitor 13 includes a first electrode 131 and a second electrode 132. The first electrode 131 and the second electrode 132 are stacked relative to each other. The display area buffer layer 1241 is located on the base substrate 100. The active layer 121 is arranged on the base substrate 100 and is located on the side of the display area buffer layer 1241 away from the base substrate 100. The first insulating layer 1242 of the display area is located on the side of the active layer 121 away from the substrate 100, and the gate electrode 122 and the first electrode plate 131 are arranged in the same layer on the side of the first insulating layer 1242 of the display area away from the substrate 100. The second insulating layer 1243 of the display area is located on the side of the gate electrode 122 and the first electrode plate 131 away from the substrate 100. The second electrode plate 132 is arranged on the side of the second insulating layer 1243 of the display area away from the substrate 100. The interlayer insulating layer 1244 of the display area is located on the side of the second electrode plate 132 away from the substrate 100. The source electrode 123 and the drain electrode 124 are arranged on the side of the interlayer insulating layer 1244 of the display area away from the substrate 100, and are electrically connected to the active layer 121 through the via holes in the first insulating layer 1242 of the display area, the second insulating layer 1243 of the display area, and the interlayer insulating layer 1244 of the display area. The gate electrode 122 and the first electrode plate 131 are located in the first metal layer 301 , the second electrode plate 132 is located in the second metal layer 302 , and the source electrode 123 and the drain electrode 124 are located in the third metal layer 303 .

[0127] For example, Fig.10 as well as Figure 6 As shown, the display area buffer layer 1241, the display area first insulating layer 1242, the display area second insulating layer 1243 and the display area interlayer insulating layer 1244 are respectively arranged on the same layer as the buffer layer 141, the first insulating layer 142, the second insulating layer 143 and the interlayer insulating layer 144 and are made of the same material.

[0128] For example, the material of the active layer 121 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)). The material of the gate 122 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The material of the source 123 and the drain 124 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0129] For example, Fig.10 As shown, the display substrate 1 further includes a first planarization layer 1245. The first planarization layer 1245 is located on the side of the source electrode 123 and the drain electrode 124 away from the base substrate 100 to provide a first planarized surface to planarize the surface of the pixel driving circuit 103 away from the base substrate 100. The first planarization layer 1245 includes a via hole, and the pixel driving circuit 103 is electrically connected to the light-emitting device through the via hole. The first planarization layer 1245 is arranged on the same layer as the third insulating layer 145.

[0130] For example, the material of the first planarization layer 1245 includes inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, which is not limited in the embodiments of the present disclosure.

[0131] For example, a passivation layer may be further provided between the first planarization layer 1245 and the source electrode 123 and the drain electrode 124. The passivation layer may be provided to include a via hole to expose one of the source electrode 123 and the drain electrode 124, for example, to expose the drain electrode 124. The passivation layer may protect the source electrode 123 and the drain electrode 124 from being corroded by water vapor. For example, the material of the passivation layer may include an organic insulating material or an inorganic insulating material, for example, a silicon nitride material, which has a high dielectric constant and good hydrophobicity, and can well protect the pixel driving circuit 103 from being corroded by water vapor.

[0132] For example, Fig.10As shown, the display substrate 1 also includes a pixel defining layer 146 and a light emitting device 11. The pixel defining layer 146 is located on the side of the first planarization layer 1245 away from the base substrate 14, and includes a first pixel opening 1461. The first pixel opening 1461 is arranged corresponding to the light emitting device 11. The light emitting device 11 includes a first electrode 113 (e.g., an anode), a light emitting layer 112, and a second electrode 111 (e.g., a cathode). The first electrode 113 is located on the side of the first planarization layer 1245 away from the base substrate 100, and is electrically connected to the pixel driving circuit 103 (e.g., the drain 124 of the driving transistor 12) through the via hole of the first planarization layer 1245. The second electrode 111 is located on the side of the pixel defining layer 146 away from the base substrate 100. The light emitting layer 112 is located in the first pixel opening 1461 and between the first electrode 113 and the second electrode 111. A portion of the light emitting layer 112 directly sandwiched between the first electrode 113 and the second electrode 111 will emit light after being powered on, so that the area occupied by this portion corresponds to the light emitting region of the light emitting device 11 .

[0133] For example, the pixel driving circuit 103 generates a light-emitting driving current under the control of a data signal provided by the data driving circuit through the data line 102, a gate scanning signal provided by the shift register unit through the gate line GN, a light-emitting control signal provided by the light-emitting control unit through the light-emitting control line EM, a power signal provided by the second power signal line VDD1, etc. The light-emitting driving current enables the light-emitting device 11 to emit red light, green light, blue light, or white light, etc.

[0134] For example, the pixel driving circuit 103 includes a conventional 7T1C (ie, seven transistors and one capacitor) pixel circuit, wherein the seven transistors include at least one switch transistor and one drive transistor (eg, Fig.10 The driving transistor 103 is provided, the gate of the switching transistor is electrically connected to the shift register unit to receive the signal behind the gate, and the source or drain of the switching transistor is connected to the data line 102 to receive the data signal. In different embodiments, the pixel driving circuit 103 may further include a compensation circuit, which includes an internal compensation circuit or an external compensation circuit, and the compensation circuit may include a transistor, a capacitor, etc. For example, as needed, the pixel circuit may also include a reset circuit, a light emitting control circuit, a detection circuit, etc. The embodiments of the present disclosure do not limit the type of the first light emitting device and the specific structure of the pixel circuit.

[0135] For example, the material of the pixel defining layer 146 may include an organic insulating material such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, or an inorganic insulating material such as silicon oxide or silicon nitride, which is not limited in the embodiments of the present disclosure.

[0136] For example, the material of the first electrode 113 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 113 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0137] For example, for OLED, the light-emitting layer 112 may include small molecule organic materials or polymer molecule organic materials, may be fluorescent materials or phosphorescent materials, may emit red light, green light, blue light, or may emit white light; and, as needed, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0138] For QLED, the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc., and the particle size of the quantum dots is 2-20nm.

[0139] For example, the second electrode 111 may include various conductive materials, such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), and the like.

[0140] For example, Fig.10 As shown, the display substrate 1 also includes an encapsulation layer 147. The encapsulation layer 147 is located on the side of the second electrode 111 away from the base substrate 100. The encapsulation layer 147 seals the light-emitting device 11 (light-emitting device 11), thereby reducing or preventing the degradation of the light-emitting device 11 caused by moisture and / or oxygen included in the environment. The encapsulation layer 147 can be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. The encapsulation layer 147 includes at least one encapsulation sublayer. For example, the encapsulation layer 147 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.

[0141] For example, the material of the encapsulation layer 147 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and to relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that intrude into the interior.

[0142] At least one embodiment of the present disclosure further provides a display device. Fig.11Schematic diagram of a display device provided by an embodiment of the present disclosure. Fig.11 As shown, the display device 2 includes a display substrate 1 and a signal input element provided by any embodiment of the present disclosure. For example, the display substrate 1 adopts Figure 2B The display substrate 1 shown in FIG.

[0143] like Fig.11 As shown, the portion of the display substrate 1 located in the peripheral area 20 is bent to the back side of the portion of the display substrate 1 located in the display area 10. For example, the back side refers to the operating side of the display substrate 1 (or the side where multiple sub-pixels 101 are arranged ( Figure 2B When the substrate 100 is a flexible substrate, it is convenient to bend. The display device 2 formed by the bending process has a narrow frame. For example, the signal input element includes a data driving circuit IC. The data driving circuit IC provides a display signal of the display substrate 1 in the display stage so that the sub-pixel 101 displays the picture.

[0144] It should be noted that the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device 2 can also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0145] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all the components of the display device. To realize the substrate function of the display device, those skilled in the art may provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0146] The technical effects of the display device 2 provided in the above embodiment may refer to the technical effects of the display substrate 1 provided in the embodiment of the present disclosure, which will not be described in detail here.

[0147] There are a few points to note:

[0148] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0149] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0150] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area at least located on one side of the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels, and configured to provide data signals to the plurality of sub-pixels; A test circuit, located in the peripheral area; a plurality of data leads, located in the peripheral area and electrically connected to the plurality of data lines and the test circuit; at least one test pad located in the peripheral area and located on at least one side of the test circuit; and at least one first test signal line located in the peripheral area, the at least one first test signal line being electrically connected to the at least one test pad and the test circuit; Wherein, at least a portion of the at least one first test signal line comprises at least two conductive layers connected in parallel and electrically connected to each other; At least a portion of the at least one first test signal line includes three conductive layers connected in parallel and electrically connected to each other; Each of the at least one first test signal line comprises a first portion and a second portion, the first portion extending along a first direction, and the second portion extending along a direction intersecting the first direction. The first portion is electrically connected to the at least one test pad and the second portion, and the second portion is also electrically connected to the test circuit; The first portion of the at least one first test signal line includes a first sub-conductive layer, a second sub-conductive layer and a third sub-conductive layer; The first sub-conductive layer, the second sub-conductive layer and the third sub-conductive layer are insulated by an insulating layer and are electrically connected in parallel through via holes in the insulating layer; Each of the plurality of sub-pixels comprises a pixel structure, wherein the pixel structure comprises a pixel driving circuit; The pixel driving circuit includes a first metal layer, a second metal layer and a third metal layer, the first metal layer is located on the base substrate, the second metal layer is located on a side of the first metal layer away from the base substrate, and the third metal layer is located on a side of the second metal layer away from the base substrate; The first sub-conductive layer, the second sub-conductive layer and the third sub-conductive layer are respectively disposed on the same layer as the first metal layer, the second metal layer and the third metal layer.

2. The display substrate according to claim 1, wherein: The pixel driving circuit further includes a driving transistor, a storage capacitor, a first insulating layer, a second insulating layer and an interlayer insulating layer. The first insulating layer is located on a side of the first metal layer close to the substrate, the second insulating layer is located between the first metal layer and the second metal layer, and the interlayer insulating layer is located between the second metal layer and the third metal layer. The driving transistor includes a gate, a source, a drain and an active layer, and the storage capacitor includes a first plate and a second plate. The active layer is located on a side of the first insulating layer close to the substrate, the gate and the first electrode are located on the first metal layer, the second electrode is located on the second metal layer, and the source and the drain are located on the third metal layer. The first sub-conductive layer and the second sub-conductive layer are electrically connected in parallel through a via hole penetrating the second insulating layer, and the second sub-conductive layer and the third sub-conductive layer are electrically connected in parallel through a via hole penetrating the interlayer insulating layer.

3. The display substrate according to claim 1, further comprising a plurality of test pad leads and a plurality of second test signal lines, The at least one first test signal line includes a plurality of first test signal lines, the at least one test pad includes a plurality of test pads, The plurality of test pad leads extend along a second direction different from the first direction and are electrically connected to the plurality of test pads respectively. Some of the test pad leads of the plurality of test pad leads are electrically connected to a first portion of the plurality of first test signal lines, and the plurality of second test signal lines are electrically connected to the test circuit and the plurality of first test signal lines. The second portions of the plurality of first test signal lines overlap with orthographic projection portions of the plurality of second test signal lines on the substrate.

4. The display substrate according to claim 3, wherein: The second portion of each of the plurality of first test signal lines comprises a first sub-conductive layer and a second sub-conductive layer, The plurality of second test signal lines are arranged on the same layer as the third metal layer.

5. The display substrate according to claim 3, wherein: The test circuit includes a plurality of test units, at least one of the plurality of test units includes a first multiplexing switch, a second multiplexing switch, a third multiplexing switch, a first control line, a second control line, a third control line, a first signal line, a second signal line, and a third signal line. The plurality of second test signal lines are electrically connected to the first control line, the second control line, the third control line, the first signal line, the second signal line and the third signal line, At least one gate of the first multiplexing switch is electrically connected to the first control line or the third control line, at least one source of the first multiplexing switch is electrically connected to the first signal line or the second signal line, and at least one drain of the first multiplexing switch is electrically connected to one of the plurality of data leads. At least one gate of the second multiplexing switch is electrically connected to the first control line or the third control line, at least one source of the second multiplexing switch is electrically connected to the first signal line or the second signal line, and at least one drain of the second multiplexing switch is electrically connected to another one of the plurality of data leads. At least one gate of the third multiplexing switch is electrically connected to the second control line, at least one source of the third multiplexing switch is electrically connected to the third signal line, and at least one drain of the third multiplexing switch is electrically connected to one of the multiple data leads and another of the multiple data leads.

6. The display substrate according to claim 5, wherein: The first multiplexing switch includes a first multiplexing switch active layer, a first multiplexing switch first gate, a first multiplexing switch second gate, a first multiplexing switch drain, a first multiplexing switch first source and a first multiplexing switch second source, The first multiplexing switch active layer is located on the base substrate, The first gate of the first multiplexing switch and the second gate of the first multiplexing switch are located on a side of the active layer of the first multiplexing switch away from the base substrate, and the orthographic projection of the first gate of the first multiplexing switch on the base substrate is staggered with the orthographic projection of the second gate of the first multiplexing switch on the base substrate. The first multiplexing switch drain, the first multiplexing switch first source and the first multiplexing switch second source are located on a side of the first multiplexing switch first gate and the first multiplexing switch second gate away from the substrate, and the first multiplexing switch drain is located between the first multiplexing switch first source and the first multiplexing switch second source. The orthographic projection of the first gate of the first multiplexing switch on the substrate is located between the orthographic projections of the first source of the first multiplexing switch and the drain of the first multiplexing switch on the substrate, and the orthographic projection of the second gate of the first multiplexing switch on the substrate is located between the orthographic projections of the second source of the first multiplexing switch and the drain of the first multiplexing switch on the substrate. The first gate of the first multiplexing switch is electrically connected to the first control line, and the second gate of the first multiplexing switch is electrically connected to the third control line.

7. The display substrate according to claim 5, wherein: The second multiplexing switch includes a second multiplexing switch active layer, a second multiplexing switch first gate, a second multiplexing switch second gate, a second multiplexing switch drain, a second multiplexing switch first source and a second multiplexing switch second source. The second multiplexing switch active layer is located on the base substrate, The first gate of the second multiplexing switch and the second gate of the second multiplexing switch are located on a side of the active layer of the second multiplexing switch away from the base substrate, and the orthographic projection of the first gate of the second multiplexing switch on the base substrate and the orthographic projection of the second gate of the second multiplexing switch on the base substrate are staggered, The second multiplexing switch drain, the second multiplexing switch first source and the second multiplexing switch second source are located on a side of the second multiplexing switch first gate and the second multiplexing switch second gate away from the substrate, and the second multiplexing switch drain is located between the second multiplexing switch first source and the second multiplexing switch second source. The orthographic projection of the first gate of the second multiplexing switch on the substrate is located between the orthographic projections of the first source of the second multiplexing switch and the drain of the second multiplexing switch on the substrate, and the orthographic projection of the second gate of the second multiplexing switch on the substrate is located between the orthographic projections of the second source of the second multiplexing switch and the drain of the second multiplexing switch on the substrate. The first gate of the second multiplexing switch is electrically connected to the first control line, and the second gate of the second multiplexing switch is electrically connected to the third control line.

8. The display substrate according to claim 5, wherein: The third multiplexing switch includes a third multiplexing switch active layer, a third multiplexing switch first gate, a third multiplexing switch second gate, a third multiplexing switch source, a third multiplexing switch first drain and a first multiplexing switch second drain. The third multiplexing switch active layer is located on the substrate. The first gate of the third multiplexing switch and the second gate of the third multiplexing switch are located on a side of the active layer of the third multiplexing switch away from the base substrate, and the orthographic projection of the first gate of the third multiplexing switch on the base substrate is staggered with the orthographic projection of the second gate of the third multiplexing switch on the base substrate. The third multiplexing switch source, the third multiplexing switch first drain and the third multiplexing switch second drain are located on a side of the third multiplexing switch first gate and the third multiplexing switch second gate away from the substrate, and the third multiplexing switch source is located between the third multiplexing switch first drain and the third multiplexing switch second drain. The orthographic projection of the first gate of the third multiplexing switch on the substrate is located between the orthographic projection of the first drain of the third multiplexing switch and the source of the third multiplexing switch on the substrate, and the orthographic projection of the second gate of the third multiplexing switch on the substrate is located between the orthographic projection of the second drain of the third multiplexing switch and the source of the third multiplexing switch on the substrate. The first drain of the third multiplexing switch is electrically connected to one of the plurality of data leads, and the second drain of the third multiplexing switch is electrically connected to another one of the plurality of data leads.

9. The display substrate according to any one of claims 5 to 8, wherein: The peripheral area also includes a first bonding area, The first bonding area is located at a side of the test circuit away from the display area, the first bonding area and the at least one test pad are spaced apart in a first direction, the first bonding area is configured to bond with a signal input element and includes a plurality of contact pads, A portion of the plurality of contact pads is electrically connected to the test circuit.

10. The display substrate according to claim 9, further comprising a plurality of signal leads, wherein the plurality of signal leads electrically connect part of the plurality of contact pads with the test circuit, At least one drain of the first multiplexing switch is also electrically connected to one of the plurality of signal leads, and at least one drain of the second multiplexing switch is also electrically connected to another of the plurality of signal leads.

11. The display substrate according to claim 9, wherein: The plurality of contact pads include a plurality of first contact pads, The second portion of each of the plurality of first test signal lines and each of the plurality of second test signal lines respectively extend to one end of the plurality of first contact pads away from the first bonding region, and are electrically connected one-to-one with one end of the plurality of first contact pads away from the first bonding region.

12. The display substrate according to claim 11, further comprising: a first power line and a second power line located in the peripheral area, wherein the first power line is located on a side of the second power line close to the at least one test pad, The plurality of contact pads further include a plurality of second contact pads, and the plurality of second contact pads are located on one side of the plurality of first contact pads close to the at least one test pad. The first power line is configured to provide a first power signal to the plurality of sub-pixels, the first power line is electrically connected to a portion of the plurality of second contact pads and surrounds the display area, The second power line is configured to provide a second power signal to the plurality of sub-pixels, the second power signal is electrically connected to another portion of the plurality of second contact pads and extends to the display area, The first power line and the second power line are located on a side of the second portion of the plurality of first test signal lines away from the base substrate, and their orthographic projections on the base substrate overlap with the orthographic projections of the second portion of the plurality of first test signal lines on the base substrate.

13. The display substrate according to claim 3, further comprising: at least one first electrostatic release unit, The at least one first electrostatic discharge unit is located at a side of the plurality of test pads close to the display area, and at least a portion of the plurality of test pad leads passes through the at least one first electrostatic discharge unit and is electrically connected to the at least one first electrostatic discharge unit.

14. The display substrate according to claim 9, further comprising: at least one second electrostatic discharge unit and at least one electrostatic lead located in the peripheral area, wherein the at least one second electrostatic discharge unit is located between the plurality of test pads and the first bonding area in the first direction, The at least one electrostatic lead extends along the second direction and electrically connects at least one of the plurality of first test signal lines and the at least one second electrostatic release unit respectively.

15. The display substrate according to claim 14, wherein: The at least one electrostatic lead includes a plurality of electrostatic leads, and the plurality of electrostatic leads are arranged side by side in the first direction, The first parts of the plurality of first test signal lines are arranged side by side in the second direction and are electrically connected to the plurality of electrostatic leads respectively. The first parts of the first test signal lines overlap with the orthographic projections of the electrostatic leads on the substrate, and the overlapping parts of the first parts of the first test signal lines and the electrostatic leads include the first sub-conductive layer and the second sub-conductive layer.

16. The display substrate according to claim 9, further comprising: A shift register unit, a light emitting control unit, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a first trigger signal line, a second trigger signal line, a third power line, a fourth power line and an initialization signal line located in the peripheral area, the display substrate further comprising a first power line and a second power line located in the peripheral area; The shift register unit is configured to provide a gate scanning signal to the plurality of sub-pixels, and the light emitting control unit is configured to provide a light emitting control signal to the plurality of sub-pixels. The first clock signal line, the second clock signal line and the first trigger signal line are electrically connected to the shift register unit to provide a first clock signal, a second clock signal and a first trigger signal respectively. The third clock signal line, the fourth clock signal line and the second trigger signal line are electrically connected to the light emitting control unit to provide a third clock signal, a fourth clock signal and a second trigger signal respectively. The third power line and the fourth power line are electrically connected to the shift register unit and the light emitting control unit respectively to provide a third power signal and a fourth power signal respectively. The initialization signal line is configured to provide an initialization signal to the plurality of sub-pixels, The display substrate further comprises a plurality of bending lines located on one side of the plurality of first test signal lines close to the display area, the plurality of bending lines being electrically connected to at least two of the first clock signal line, the second clock signal line, the third clock signal line, the fourth clock signal line, the first trigger signal line, the second trigger signal line, the third power line, the fourth power line, and the initialization signal line, respectively. The plurality of bending lines are also electrically connected to another part of the plurality of contact pads, respectively, and the orthographic projections of the plurality of bending lines on the substrate overlap with the orthographic projections of the first power line, the second power line, and the second test signal line on the substrate. Each of the plurality of bending lines includes two conductive layers, and the two conductive layers of the plurality of bending lines are respectively arranged on the same layer as the first metal layer and the second metal layer.

17. The display substrate according to claim 16, wherein the plurality of bending lines are also electrically connected to another part of the plurality of test pad leads. The orthographic projection of the first part of the plurality of first test signal lines on the base substrate overlaps with the orthographic projection of the test pad leads respectively electrically connected to the plurality of bending lines on the base substrate, The portion where the first portion of the plurality of first test signal lines overlaps with the test pad leads respectively electrically connected to the plurality of meander lines includes the first sub-conductive layer and the second sub-conductive layer.

18. A display device, comprising the display substrate according to any one of claims 1 to 17.

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