Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device can include a plurality of lower electrodes on a substrate, a first electrode support between adjacent lower electrodes and comprising a metallic material, a dielectric layer on the lower electrodes and the first electrode support to extend along a contour of the first electrode support and each lower electrode, and an upper electrode on the dielectric layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0151871, filed on November 25, 2019, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a conductive electrode extending in one direction and a support structure supporting the conductive electrode. Background Technology

[0003] As the integration density of semiconductor devices increases, larger capacitance and higher integration density become beneficial, leading to a continuous reduction in design rules. This trend is evident in Dynamic Random Access Memory (DRAM), a type of semiconductor memory device that occupies a relatively small footprint in a highly integrated device. However, for DRAM devices to function, each cell requires a capacitance greater than a certain level, which can be hampered by the small footprint, since capacitance is a function of the surface area of ​​the capacitor's electrodes.

[0004] To this end, research is being conducted on utilizing a dielectric layer with a high dielectric constant in capacitors and / or increasing the contact area between the lower electrode of the capacitor and the dielectric layer. For example, a capacitor is provided in which the contact area between the capacitor and the dielectric layer increases as the height of the lower electrode increases, thereby increasing the capacitance of the capacitor.

[0005] To prevent the lower electrode from tilting or collapsing due to the increased height of the lower electrode, a support structure capable of supporting the lower electrode has been proposed. Summary of the Invention

[0006] Aspects relating to various exemplary embodiments of the inventive concept provide a semiconductor device in which an electrode support supporting a lower electrode is connected to a ground voltage to improve the device’s performance and reliability.

[0007] Aspects relating to various exemplary embodiments of the inventive concept also provide a method of manufacturing a semiconductor device, wherein an electrode support supporting a lower electrode is connected to a ground voltage to improve the performance and reliability of the device.

[0008] According to some exemplary embodiments of the present invention, a semiconductor device includes: a plurality of lower electrodes on a substrate; a first electrode support between adjacent lower electrodes and including a conductive material; a dielectric layer extending over the plurality of lower electrodes and the first electrode support along the contours of the plurality of first electrode supports and each lower electrode; and an upper electrode on the dielectric layer.

[0009] According to some exemplary embodiments of the present invention, a semiconductor device includes: a plurality of lower electrodes on a substrate; an electrode support comprising a conductive material between adjacent lower electrodes of the plurality of lower electrodes, the electrode support including a support exposure region on its upper surface; a dielectric layer on the electrode support and the lower electrodes but not on the support exposure region of the electrode support; an upper electrode on the dielectric layer; an upper plate electrode on the upper electrode and electrically connected to the electrode support; and a ground plug connected to the upper plate electrode.

[0010] According to some exemplary embodiments of the present invention, a semiconductor device includes: an electrode support on a substrate and defining a plurality of lower electrode holes; an insulating spacer on a sidewall of each lower electrode hole; a plurality of lower electrodes in the lower electrode holes and spaced apart from the electrode support by the insulating spacer; a dielectric layer on the lower electrodes and the electrode support; and an upper electrode on the dielectric layer and electrically connected to the electrode support. However, aspects of the exemplary embodiments of the present invention are not limited to those set forth herein. These and other aspects of the exemplary embodiments will become more apparent to those skilled in the art upon reference to the following detailed description of exemplary embodiments of the present invention. Attached Figure Description

[0011] These and / or other aspects will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 and Figure 2 This is a plan view of a semiconductor device according to at least one exemplary embodiment of the present invention;

[0013] Figure 3 and Figure 4 It is along Figure 2 Cross-sectional views of AA and BB;

[0014] Figure 5 yes Figure 4 A magnified view of part P;

[0015] Figure 6 and Figure 7 Semiconductor devices according to at least one exemplary embodiment of the present invention are shown respectively;

[0016] Figure 8 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown;

[0017] Figures 9 to 11 Semiconductor devices according to at least one exemplary embodiment of the present invention are shown respectively;

[0018] Figure 12A semiconductor device according to at least one example embodiment of the concept of the present invention is shown;

[0019] Figure 13 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown;

[0020] Figure 14 and Figure 15 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown;

[0021] Figure 16 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown;

[0022] Figures 17 to 19 Semiconductor devices according to at least one exemplary embodiment of the present invention are shown respectively;

[0023] Figure 20 and Figure 21 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown;

[0024] Figures 22 to 34 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention;

[0025] Figure 35 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention;

[0026] Figures 36 to 39 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention; and

[0027] Figure 40 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention. Detailed Implementation

[0028] The accompanying drawings, relating to a semiconductor device based on an exemplary embodiment of the invention, illustrate capacitors and electrode supports included in a dynamic random access memory (DRAM).

[0029] Although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the scope of this disclosure.

[0030] When a component is described as "on another component," "connected to another component," "coupled to another component," or "adjacent to another component," the component may be directly on another component, connected to another component, coupled to another component, or adjacent to another component, or one or more other intermediate components may exist. Conversely, when a component is described as "directly on another component," "directly connected to another component," "directly coupled to another component," or "immediately adjacent to another component," no intermediate components exist.

[0031] For ease of description, spatial relative terms such as “below” and “above” may be used herein to describe the relationship of one element or feature to another (or other) element or feature, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings were flipped, an element described as “below” other elements or features would be oriented as “above” other elements or features. Thus, the example terms “below” and “above” can cover both orientations of “above” and “below”. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly. Furthermore, when an element is referred to as “between two elements,” the element may be the only element between the two elements, or one or more other intermediate elements may be present.

[0032] Figure 1 and Figure 2 This is a plan view of a semiconductor device according to at least one exemplary embodiment of the present invention. Figure 3 and Figure 4 It is along Figure 2 The cross-sectional view of AA and BB. Figure 5 yes Figure 4 A magnified view of part P.

[0033] For reference only. Figure 1 This is a plan view of the lower electrode 210 and the second electrode support 150 of the semiconductor device. Figure 2 It is formed in Figure 1An example plan view of the lower electrode 210 and the upper electrode 230 on the second electrode support 150. Figure 3 and Figure 4 yes Figure 2 Example of a cross-sectional view of the upper plate electrode 240 and the first grounding plug 270 on the upper electrode 230.

[0034] Reference Figures 1 to 5 The semiconductor device according to the embodiment may include a plurality of lower electrodes 210, a first electrode support 130, a second electrode support 150, an insulating spacer 160, a capacitor dielectric layer 220, an upper electrode 230, an upper plate electrode 240, and a first ground plug 270.

[0035] The first landing pad 115 may be on the substrate 100. The first landing pad 115 may be connected to the substrate 100. The first landing pad 115 may be electrically connected to a conductive area formed on or in the substrate 100. The first landing pad 115 may be connected to the substrate 100 via the first storage contact 105. The first landing pad 115 may be on the first storage contact 105.

[0036] The first interlayer insulating film 110 may be on the substrate 100. The first storage contact 105 and the first landing pad 115 may be in the first interlayer insulating film 110 on the substrate 100. The substrate 100 may be a silicon substrate, such as bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be, but is not limited to, a semiconductor substrate, such as substrates including silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and / or gallium antimonide. In the following description, the substrate 100 will be described as a silicon substrate.

[0037] The first interlayer insulating film 110 may include an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and / or combinations thereof. The first storage contact 105 may, for example, include at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a metal, and / or combinations thereof. The first landing pad 115 may, for example, include at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a metal, and / or combinations thereof. In the semiconductor device according to an example embodiment, the first landing pad 115 may include tungsten (W). The first landing pad 115 and the first storage contact may include the same or different materials.

[0038] The first etch stop layer 120 may be on the first interlayer insulating film 110. The first etch stop layer 120 may expose at least a portion of each first landing pad 115. For example, the first etch stop layer 120 may be on the first landing pad 115. The first etch stop layer 120 may include electrode pad openings that at least partially expose the first landing pad 115. The first etch stop layer 120 may, for example, include at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBn), silicon carbide (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon carbonitride (SiOCN). In this document, unless otherwise specifically indicated, atomic abbreviations indicate the atomic composition of a material but do not include or limit the proportion of atoms in the material. For example, silicon carbide (SiCO) indicates that it contains silicon (Si), carbon (C), and oxygen (O), but does not indicate that a specific ratio of silicon (Si), carbon (C), and oxygen (O) is 1:1:1.

[0039] The lower electrode 210 may be on the substrate 100. The lower electrode 210 may be on and connected to the first landing pad 115. A portion of each lower electrode 210 may be in the first etch stop layer 120. The lower electrode 210 may extend through the first etch stop layer 120 and be connected to the first landing pad 115.

[0040] For example, each lower electrode 210 may have a pillar-like shape. For instance, the lower electrode 210 may comprise a cylinder (e.g., having a circular or oval cross-section) and / or may comprise a polygonal cross-section. The lower electrode 210 may extend along the thickness direction of the substrate 100 (e.g., extending in a direction away from the upper surface of the substrate 100). The length of the lower electrode 210 extending along the thickness direction of the substrate 100 may be greater than the length of the lower electrode 210 extending in a direction DR1, DR2, or DR3 parallel to the substrate 100.

[0041] The lower electrode 210 can be repeatedly aligned along a first direction DR1 and a second direction DR2. The first direction DR1 and the second direction DR2 can be orthogonal to each other. The lower electrode 210 repeatedly aligned along the first direction DR1 can also be repeatedly aligned along the second direction DR2. The lower electrode 210 repeatedly aligned along the second direction DR2 can be arranged non-linearly along the second direction DR2. The lower electrode 210 repeatedly aligned along the second direction DR2 can be arranged in a zigzag pattern. The lower electrode 210 can be arranged linearly along a third direction DR3.

[0042] The lower electrode 210 may include, but is not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, or tantalum), and / or conductive metal oxides (e.g., iridium oxide or niobium oxide). In a semiconductor device according to an example embodiment, the lower electrode 210 may include titanium nitride (TiN). Alternatively, in a semiconductor device according to another example embodiment, the lower electrode 210 may include niobium nitride (NbN).

[0043] The first electrode support 130 may be on the first etch stop layer 120. The first electrode support 130 may be spaced apart from the first etch stop layer 120. The first electrode support 130 may be between adjacent lower electrodes 210.

[0044] The first electrode support 130 may include a plurality of first electrode holes 130h formed at positions corresponding to the lower electrode 210. The lower electrode 210 may penetrate the first electrode holes 130h along the thickness direction of the substrate 100. The first electrode support 130 may contact the lower electrode 210. The first electrode support 130 may partially contact the sidewall of the lower electrode 210. The first electrode support 130 may contact the lower electrode 210 at the first electrode holes 130h.

[0045] The first electrode support 130 may include a first through-pattern 130tp formed between adjacent lower electrodes 210. The description of the first through-pattern 130tp may be similar to the description of the second through-pattern 150tp given later.

[0046] The first electrode support 130 may include an insulating material, such as at least one of silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbon oxynitride, silicon oxynitride, silicon oxide, and silicon carbonitride.

[0047] The second electrode support 150 may be on the first electrode support 130. The second electrode support 150 may be spaced apart from the first electrode support 130. The second electrode support 150 may be between adjacent lower electrodes 210. The second electrode support 150 may include a plurality of second electrode holes 150h formed at positions corresponding to the lower electrodes 210. The lower electrodes 210 may penetrate the second electrode holes 150h. The second electrode support 150 may be spaced apart from the lower electrodes 210 and therefore does not contact the lower electrodes 210.

[0048] The second electrode support 150 may include a second through-pattern 150tp formed between adjacent lower electrodes 210. The second through-pattern 150tp may be formed at a position corresponding to the first through-pattern 130tp. The first through-pattern 130tp and the second through-pattern 150tp may overlap along the thickness direction of the substrate 100. The first through-pattern 130tp and the second through-pattern 150tp may be formed during the formation of the first electrode support 130 and the second electrode support 150.

[0049] The second electrode support 150 may include a conductive material, such as a metallic material. The second electrode support 150 may, for example, include at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. In the following description, the second electrode support 150 will be described as including a metallic material.

[0050] Each of the first through-pattern 130tp and the second through-pattern 150tp can be formed on a plurality of adjacent lower electrodes 210. In a semiconductor device according to an example embodiment, each of the first through-pattern 130tp and the second through-pattern 150tp can be formed between four adjacent lower electrodes 210. The four lower electrodes 210 connected to one of the second through-pattern 150tp can be located at the vertices of a quadrilateral. The lower electrodes 210 are not in the first through-pattern 130tp and the second through-pattern 150tp.

[0051] exist Figure 1 In this embodiment, a lower electrode 210 not connected to the second through-pattern 150tp is located between adjacent second through-patterns 150tp along the first direction DR1. However, the embodiment is not limited to this. For example, there may be no lower electrode 210 not connected to the second through-pattern 150tp located between adjacent second through-patterns 150tp along the first direction DR1. Alternatively, two or more lower electrodes 210 not connected to the second through-pattern 150tp may be located between adjacent second through-patterns 150tp along the first direction DR1.

[0052] The second electrode support 150 may include an electrode support portion 150_1 in which a second electrode hole 150h is formed, and an edge portion 150_2 along the edge of the electrode support portion 150_1, and surrounds the electrode support portion 150_1. The edge portion 150_2 of the second electrode support 150 may define the boundary of the second electrode support 150. The edge portion 150_2 of the second electrode support 150 may be a portion located further outward than the outermost lower electrode 210.

[0053] The electrode support portion 150_1 of the second electrode support member 150 may include an inner support region 150_11 in which a second through pattern 150tp is formed and an outer support region 150_12 in which the second through pattern 150tp is not formed.

[0054] The second electrode support 150 includes an upper surface 150us and a lower surface 150bs facing each other. For example, the lower surface 150bs of the second electrode support 150 may face the substrate 100. A second electrode hole 150h can connect the upper surface 150us and the lower surface 150bs of the second electrode support 150. Although the upper surface 150us of the second electrode support 150 is shown to be in the same plane as the upper surface 210us of each lower electrode 210, the embodiment is not limited to this. For example, some and / or all of the lower electrodes 210 may also protrude above the upper surface 150us of the second electrode support 150.

[0055] The upper surface 150us of the second electrode support 150 may include a first boundary line 150sb extending along a first direction DR1 and a second boundary line 150sa extending along a second direction DR2. The first boundary line 150sb and the second boundary line 150sa of the second electrode support 150 may form the boundary of the second electrode support 150.

[0056] exist Figure 1 In this embodiment, the first boundary line 150sb and the second boundary line 150sa of the second electrode support 150 are directly connected to each other. However, this is merely an example used for ease of description, and the embodiment is not limited to this example. The first boundary line 150sb and the second boundary line 150sa of the second electrode support 150 can also be connected by a connecting boundary, and the connecting boundary can include various shapes, such as straight lines, curves, stepped shapes, and / or wavy shapes.

[0057] The upper surface 150us of the second electrode support 150 may include an unexposed area 150us_1 covered by the capacitor dielectric layer 220 and the upper electrode 230, and an exposed area 150us_2 not covered by the capacitor dielectric layer 220 and the upper electrode 230. The exposed area 150us_2 of the upper surface 150us of the second electrode support 150 is the portion thereon where the capacitor dielectric layer 220 and the upper electrode 230 are not formed. The edge portion 150_2 of the second electrode support 150 includes the exposed area 150us_2 of the upper surface 150us of the second electrode support 150. For example, the exposed area 150us_2 of the upper surface 150us of the second electrode support 150 may be shaped as a rectangle, for example, extending along a first direction DR1 or a second direction DR2.

[0058] In a semiconductor device according to an example embodiment, the exposed area 150us_2 of the upper surface 150us of the second electrode support 150 may extend along the first boundary line 150sb of the second electrode support 150 and the second boundary line 150sa of the second electrode support 150.

[0059] exist Figure 2 In the figure, the exposed areas 150us_2 of the second electrode support 150 extending along each first boundary line 150sb and the exposed areas 150us_2 of the second electrode support 150 extending along each second boundary line 150sa are not connected to each other. However, the embodiment is not limited to this case. Unlike in the figure, the exposed areas 150us_2 of the upper surface 150us of the second electrode support 150 may also extend along the entire boundary of the second electrode support 150. Unlike in the figure, the exposed areas 150us_2 of the upper surface 150us of the second electrode support 150 may also extend along one of the two first boundary lines 150sb that face each other. In addition, the exposed areas 150us_2 of the upper surface 150us of the second electrode support 150 may extend along one of the two second boundary lines 150sa that face each other.

[0060] In the semiconductor device according to the embodiment, the thickness t11 of the second electrode support 150 along the thickness direction of the substrate 100 may be greater than the thickness t12 of the first electrode support 130. Unlike in the figures, the first electrode support 130, which includes insulating material, may not be located between the second electrode support 150 and the first etch stop layer 120. That is, only one electrode support can support the lower electrode 210.

[0061] An insulating spacer 160 may be located between the second electrode support 150 and the lower electrode 210. The insulating spacer 160 may be located along the boundary between the second electrode support 150 and the lower electrode 210.

[0062] The lower electrode 210 and the second electrode support 150 can be separated by an insulating spacer 160. The insulating spacer 160 can electrically insulate the lower electrode 210 from the second electrode support 150, which includes a conductive material.

[0063] An insulating spacer 160 may be formed on the sidewall of the second electrode hole 150h. The insulating spacer 160 may integrally cover the sidewall of the lower electrode 210, defining the second electrode hole 150h that forms a boundary with the lower electrode 210.

[0064] Each lower electrode 210 may include an overlapping region 210_1 that laterally overlaps with the insulating spacer 160 and a non-overlapping region 210_2 that does not laterally overlap with the insulating spacer 160. The insulating spacer 160 may partially cover the sidewall of each lower electrode 210. The insulating spacer 160 may cover the sidewall 210_1sw of the overlapping region 210_1 of each lower electrode 210. The insulating spacer 160 does not cover the sidewall 210_2sw of the non-overlapping region 210_2 of each lower electrode 210.

[0065] In the semiconductor device according to the embodiment, the distance t14 from the upper surface 150µs of the second electrode support 150 to the bottom of each insulating spacer 160 can be greater than the thickness t11 of the second electrode support 150.

[0066] Each insulating spacer 160 may include a portion whose thickness d1 increases with increasing distance from the substrate 100. For example, a portion of the insulating spacer 160 on a portion of each sidewall 210_1sw of each lower electrode 210 may become thicker with increasing distance from the substrate 100. Figure 5 In this embodiment, the thickness d1 of each insulating spacer 160 increases and then decreases with increasing distance from the substrate 100, but the embodiment is not limited to this. That is, the thickness d1 of each insulating spacer 160 may increase with increasing distance from the substrate 100 and then remain constant.

[0067] In each portion forming the second through-pattern 150tp, the upper portion of the lower electrode 210 that connects to the second through-pattern 150tp may be chamfered. In the semiconductor device according to the embodiment, the height t13 of each chamfered portion of the lower electrode 210 may be greater than the distance t14 from the upper surface 150us of the second electrode support 150 to the bottom of each insulating spacer 160. For example, in each portion forming the second through-pattern 150tp, the insulating spacer 160 may not be on the sidewall of the lower electrode 210 that connects to the second through-pattern 150tp. The insulating spacer 160 may not be on the sidewall of the lower electrode 210 in each portion overlapping the second through-pattern 150tp.

[0068] The insulating spacer 160 may include an insulating material, such as at least one selected from silicon oxide, silicon carbonitride, silicon nitride, silicon carbide, silicon oxynitride, and a high-k material containing a metal. The high-k material containing a metal may include, for example, one selected from hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. In the semiconductor device according to the example embodiment, the insulating spacer 160 may include an insulating material with a dielectric constant higher than that of silicon oxide. For example, the insulating spacer 160 may include silicon carbonitride.

[0069] A capacitor dielectric layer 220 may be formed on the lower electrode 210, the first electrode support 130, and the second electrode support 150. The capacitor dielectric layer 220 may extend along the contour of the lower electrode 210, the upper and lower surfaces of the first electrode support 130, the upper surface 150µs of the second electrode support 150, and the lower surface 150bs of the second electrode support 150. The capacitor dielectric layer 220 does not extend between the second electrode support 150 and the insulating spacer 160. The capacitor dielectric layer 220 may include an insulating material, such as at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and / or a high-k material containing a metal. Although the capacitor dielectric layer 220 is shown as a single layer, this is merely an example used for ease of description and illustration, and the embodiments are not limited to this example. For example, according to an example embodiment, the capacitor dielectric layer 220 in a semiconductor device may include a structure having dielectric layers stacked in sequence, such as a structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence.

[0070] In the semiconductor device according to the example embodiment, the capacitor dielectric layer 220 may include a dielectric layer comprising hafnium (Hf). In the semiconductor device according to the example embodiment, the capacitor dielectric layer 220 may have a stacked structure of a ferroelectric material layer and a paraelectric material layer.

[0071] A ferroelectric material layer can possess ferroelectric properties. A ferroelectric material layer can be thick enough to possess ferroelectric properties. The thickness range of a ferroelectric material layer with ferroelectric properties can vary depending on the ferroelectric material.

[0072] For example, the ferroelectric material layer may include a single metal oxide. The ferroelectric material layer may include a single metal oxide layer. Here, the single metal oxide may be a binary compound composed of a metal and oxygen. The ferroelectric material layer including the single metal oxide may have an orthorhombic crystal system.

[0073] In one example, the metal included in the single metal oxide layer may be hafnium (Hf). The single metal oxide layer may be a hafnium oxide (HfO) layer. Here, the hafnium oxide layer may have a stoichiometric chemical formula or it may have a non-stoichiometric chemical formula.

[0074] In another example, the metal included in the single metal oxide layer can be one of the rare earth metals belonging to the lanthanides. The single metal oxide layer can include a rare earth metal oxide layer comprising a metal belonging to the lanthanides. Here, the rare earth metal oxide layer comprising a metal belonging to the lanthanides can have a stoichiometric chemical formula or a non-stoichiometric chemical formula. When the ferroelectric material layer comprises a single metal oxide layer, its thickness can be, for example, from 1 nm to 10 nm.

[0075] In another example embodiment, the ferroelectric material layer may include a bimetallic oxide. The ferroelectric material layer may include a bimetallic oxide layer. Here, the bimetallic oxide may be a ternary compound comprising two metals and oxygen. The ferroelectric material layer comprising a bimetallic oxide may have an orthorhombic crystal system.

[0076] The metals included in the bimetallic oxide layer can be, for example, hafnium (Hf) and zirconium (Zr). The bimetallic oxide layer can be hafnium zirconium oxide (HfZrO). For example, the bimetallic oxide layer can include (Hf... x Zr (1-x) The hafnium zirconium oxide (HfZrO) layer can have a stoichiometric chemical formula or a non-stoichiometric chemical formula.

[0077] When the ferroelectric material layer includes a bimetallic oxide layer, its thickness can be, for example, 1 nm to 20 nm.

[0078] The paraelectric material layer can be a dielectric layer comprising zirconium (Zr) or a stacked layer comprising zirconium (Zr). The paraelectric material layer can include the same chemical formula as the ferroelectric material layer. Although the chemical formula can be the same, the ferroelectric and / or paraelectric properties exhibited by the material layer can depend on the crystal structure of the dielectric material.

[0079] In a specific portion of the capacitor dielectric layer 220, the paraelectric material can have a positive dielectric constant, while the ferroelectric material can have a negative dielectric constant. That is, the paraelectric material can have a positive capacitance, while the ferroelectric material can have a negative capacitance.

[0080] Generally, when two or more capacitors with positive capacitance are connected in series, the sum of their capacitances decreases. However, when a capacitor with negative capacitance and a capacitor with positive capacitance are connected in series, the sum of their capacitances increases.

[0081] The upper electrode 230 may be on the capacitor dielectric layer 220. The upper electrode 230 may extend along the contour of the capacitor dielectric layer 220. The upper electrode 230 may include, but is not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, or tantalum), and / or conductive metal oxides (e.g., iridium oxide or niobium oxide). In the semiconductor device according to the embodiment, the upper electrode 230 may include titanium nitride (TiN) and / or niobium nitride (NbN).

[0082] The upper electrode 240 may be on the upper electrode 230. The upper electrode 240 may be above the region defined within the exposed area 150us_2 of the upper surface 150us of the second electrode support 150 and on the unexposed area 150us_1 of the upper surface 150us of the second electrode support 150. For example, the upper electrode 240 may not be formed on the exposed area 150us_2 of the upper surface of the second electrode support 150 and / or the upper electrode 240 may not cover the exposed area 150us_2 of the upper surface of the second electrode support 150.

[0083] The upper electrode 240 may include, for example, at least one of an elemental semiconductor material layer and / or a compound semiconductor material layer. The upper electrode 240 may include doped n-type or p-type impurities.

[0084] The support connection pattern 250 can be on the exposed area 150µs_2 of the upper surface of the second electrode support 150. The support connection pattern 250 can cover the exposed area 150µs_2 of the upper surface of the second electrode support 150, where the capacitor dielectric layer 220, the upper electrode 230, and the upper plate electrode 240 are not formed. The support connection pattern 250 can be connected to the second electrode support 150. The support connection pattern 250 can be connected to the upper plate electrode 240. The support connection pattern 250 can connect the second electrode support 150 and the upper plate electrode 240. The second electrode support 150 can be electrically connected to the upper plate electrode 240 through the support connection pattern 250. The upper plate electrode 240 can be electrically connected to the second electrode support 150 through the exposed area 150µs_2 of the upper surface of the second electrode support 150.

[0085] In an example embodiment, a portion of the support connection pattern 250 may protrude further than the sidewall of the second electrode support 150 in the lateral direction (e.g., the first direction DR1). Although in Figure 3 The middle support connection pattern 250 protrudes more in the lateral direction than the sidewall of the upper plate electrode 240, but the embodiment is not limited to this case.

[0086] For example, when with Figure 2Unlike in the case where the exposed area 150us_2 on the upper surface of the second electrode support 150 does not extend to the first boundary line 150sb and / or the second boundary line 150sa, the support connection pattern 250 may not protrude more than the sidewall of the second electrode support 150 in the lateral direction.

[0087] The support connection pattern 250 may include a conductive material, such as at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal oxide, and / or a metal.

[0088] The second interlayer insulating film 260 can be on the upper plate electrode 240. The second interlayer insulating film 260 can cover the upper surface and sidewalls of the supporting connection pattern 250.

[0089] The first grounding plug 270 can be in the second interlayer insulating film 260 and connected to the upper plate electrode 240. The first grounding plug 270 can fill the first grounding plug hole 270h in the second interlayer insulating film 260.

[0090] The first grounding plug 270 can be electrically connected to the upper plate electrode 240, the support connection pattern 250, the upper electrode 230, and the second electrode support 150. The first grounding plug 270 can be electrically connected to the second electrode support 150 via the upper plate electrode 240 and the support connection pattern 250. The first grounding plug 270 can be electrically connected to the second electrode support 150 through an exposed area 150µs_2 on the upper surface of the second electrode support 150.

[0091] The first grounding plug 270 can be connected to a specific voltage, such as ground. The upper plate electrode 240, the support connection pattern 250, the upper electrode 230, and the second electrode support 150 can be connected to ground. The first grounding plug 270 may include a conductor, such as at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal oxide, and a metal.

[0092] As the distance between the lower electrodes 210 decreases, leakage current may occur between adjacent lower electrodes 210. The leakage current generated between adjacent lower electrodes 210 will reduce the reliability and performance of the semiconductor device.

[0093] However, since the second electrode support 150 includes a conductive material and is connected to ground voltage, leakage current between adjacent lower electrodes 210 can be prevented, thereby improving the reliability and performance of the semiconductor device. Furthermore, since the second electrode support 150 is electrically connected to the upper electrode 230, each insulating spacer 160 between the second electrode support 150 and the lower electrode 210 can serve as a dielectric layer for a capacitor, thereby increasing the capacitance of the semiconductor device.

[0094] Figure 6 and Figure 7 Semiconductor devices according to at least one example embodiment of the present invention are shown. Figure 8 A semiconductor device according to at least one exemplary embodiment of the present invention is illustrated. For ease of description, in the drawings, the same reference numerals are used for the same constituent elements and their repeated descriptions will be omitted, and the main description will be consistent with the above references. Figures 1 to 5 The differences between the described semiconductor devices.

[0095] Reference Figure 6 and Figure 7 In the semiconductor device according to the embodiment, the thickness d1 of each insulating spacer 160 can remain constant as the distance from the substrate 100 increases.

[0096] exist Figure 6 In this configuration, each insulating spacer 160 can be mounted on the non-overlapping region 210_2 of the lower electrode 210. Figure 7 In this configuration, each insulating spacer 160 can be mounted between the second electrode support 150 and the first electrode support 130 on the capacitor dielectric layer 220 and the upper electrode 230.

[0097] Reference Figure 8 In the semiconductor device according to the example embodiment, the upper plate electrode 240 may be on the exposed area 150us_2 of the upper surface 150us of the second electrode support 150.

[0098] The upper plate electrode 240 can cover the exposed area 150us_2 of the upper surface 150us of the second electrode support 150. The first grounding plug 270 can be electrically connected to the second electrode support 150 via the upper plate electrode 240.

[0099] Figures 9 to 11 Semiconductor devices according to at least one exemplary embodiment of the present invention are shown. For ease of description, the same reference numerals are used for the same constituent elements in the drawings and repeated descriptions thereof will be omitted, and the main description will be consistent with the above references. Figures 1 to 5 The differences between the described semiconductor devices.

[0100] Reference Figures 9 to 11 Each semiconductor device according to the embodiment may further include a second ground plug 271 that is directly connected to an exposed area 150us_2 on the upper surface 150us of the second electrode support 150.

[0101] The second grounding plug 271 can fill the second grounding plug hole 271h in the second interlayer insulating film 260. The second grounding plug 271 can be directly connected to the second electrode support 150. The second grounding plug 271 can be electrically connected to the second electrode support 150 without being connected through the upper plate electrode 240. The second grounding plug 271 can be connected to ground voltage, for example.

[0102] exist Figure 9 In this configuration, a portion of the second grounding plug 271 may be located on the exposed area 150us_2 of the upper surface 150us of the second electrode support 150, while another portion of the second grounding plug 271 may be located on the unexposed area 150us_1 of the upper surface 150us of the second electrode support 150. A portion of the second grounding plug 271 may be located on the upper plate electrode 240. Alternatively, the second grounding plug 271 may completely and / or partially penetrate the upper plate electrode 240, the upper electrode 230, and / or the capacitor dielectric layer 220 in the unexposed area 150us_1 of the upper surface 150us of the second electrode support 150.

[0103] exist Figure 10 In this configuration, the second grounding plug 271 can be located on the exposed area 150us_2 of the upper surface 150us of the second electrode support 150. The entire bottom surface of the second grounding plug 271 can be located on the exposed area 150us_2 of the upper surface 150us of the second electrode support 150.

[0104] exist Figure 11 In this configuration, a portion of the second grounding plug 271 may be located on the exposed area 150us_2 of the upper surface 150us of the second electrode support 150, while another portion of the second grounding plug 271 may not be located on the upper surface 150us of the second electrode support 150. The portion of the second grounding plug 271 that is not located on the upper surface 150us of the second electrode support 150 may extend along the thickness direction toward the substrate beyond the upper surface 150us and partially contact the sidewall of the second electrode support 150. A portion of the second grounding plug 271 may be located on the second electrode support 150.

[0105] exist Figure 9 and Figure 11 In this configuration, the first ground plug 270 is located on the upper plate electrode 240. However, the embodiments are not limited to this configuration. For example, the semiconductor device may include only the second ground plug 271, without the first ground plug 270.

[0106] Figure 12 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown. Figure 13 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown. Figure 14and Figure 15 A semiconductor device according to at least one example embodiment of the concept of the present invention is shown. Figure 16 A semiconductor device according to at least one exemplary embodiment of the present invention is illustrated. For ease of description, in the drawings, the same reference numerals are used for the same constituent elements and their repeated descriptions will be omitted, and the main description will be consistent with the above references. Figures 1 to 5 The differences described are those between semiconductor devices. For reference, Figure 13 and Figure 14 These are example plan views of the lower electrode 210 and the upper electrode 230 on the second electrode support 150.

[0107] Reference Figure 12 In the semiconductor device according to the example embodiment, the height t13 of the chamfered portion of the lower electrode 210 may be greater than the distance t14 from the upper surface 150µs of the second electrode support 150 to the bottom of each insulating spacer 160 (see [reference]). Figure 5 In the portion forming the second through-pattern 150tp, the insulating spacer 160 may be on the sidewall of the lower electrode 210 that is in contact with the second through-pattern 150tp. The insulating spacer 160 may be on the sidewall of the lower electrode 210 in the portion that overlaps with the second through-pattern 150tp.

[0108] Reference Figure 13 In the semiconductor device according to the example embodiment, the exposed region 150us_2 of the upper surface 150us of the second electrode support 150 may be along the second boundary line 150sa of the second electrode support 150. However, the exposed region 150us_2 of the upper surface 150us of the second electrode support 150 does not follow the first boundary line 150sb of the second electrode support 150.

[0109] The exposed area 150us_2 of the upper surface 150us of the second electrode support 150 may be defined along the first boundary line 150sb or the second boundary line 150sa of the second electrode support 150, wherein the second boundary line 150sa extends in a direction different from the first boundary line 150sb.

[0110] Reference Figure 14 and Figure 15 The semiconductor device according to the example embodiment may also include a second grounding plug 271 connected to the edge portion 1502 of the second electrode support 150 in the upper surface 150us of the second electrode support 150.

[0111] The second grounding plug 271 can fill the second grounding plug hole 271h in the second interlayer insulating film 260. The upper surface 150us of the second electrode support 150 does not include a rectangular exposed area extending along the first boundary line 150sb and the second boundary line 150sa of the second electrode support 150.

[0112] Despite Figure 15 Only the second ground plug 271 is shown, but the embodiment is not limited to this. A first ground plug 270 connected to the upper plate electrode 240 may also be included in the semiconductor device (see [reference]). Figure 3 ).

[0113] Reference Figure 16 In the semiconductor device according to the embodiment, each lower electrode 210 may be shaped as, for example, a cylinder.

[0114] Each lower electrode 210 may include a bottom extending along the upper surface of the first landing pad 115 and a sidewall extending from the bottom in the thickness direction of the substrate 100. An upper electrode 230 may extend in the thickness direction to fill the internal gaps within the sidewall of the lower electrode 210. A capacitor dielectric layer 220 may be located between the upper electrode 230 and the lower electrode 210. The thickness of the upper electrode 230 in the region overlapping with the second electrode support 150 may be less than the thickness of the upper electrode 230 in the region overlapping with the first electrode support 130.

[0115] Figures 17 to 19 Semiconductor devices according to at least one exemplary embodiment of the present invention are shown. For ease of description, the same reference numerals are used for the same constituent elements in the drawings and repeated descriptions thereof will be omitted, and the main description will be consistent with the above references. Figures 1 to 5 The differences described are those between semiconductor devices. For reference, Figures 17 to 19 Both are plan views of the lower electrode 210 and the second electrode support 150 of the semiconductor device.

[0116] Reference Figure 17 In a semiconductor device according to at least one example embodiment of the present invention, each second through pattern 150tp may be formed between three adjacent lower electrodes 210.

[0117] The three lower electrodes 210 connected to a second through pattern 150tp can be located at the vertices of a triangle or trianguloid.

[0118] The first through-pattern 130tp included in the first electrode support 130 (see...) Figure 4It can be located at a position corresponding to each second through pattern 150tp, and can have a shape corresponding to the shape of each second through pattern 150tp.

[0119] Reference Figure 18 In a semiconductor device according to at least one example embodiment of the present invention, each second through pattern 150tp may be shaped as a strip extending, for example, along a first direction DR1.

[0120] Each second through-pattern 150tp can be formed on three lower electrodes 210 adjacent to each other along the first direction DR1 and four lower electrodes 210 adjacent to each other along the first direction DR1. However, this is merely an example used for ease of description, and the embodiment is not limited to this example. For example, the number of lower electrodes 210 may be greater than or less than the number depicted.

[0121] Reference Figure 19 In a semiconductor device according to at least one example embodiment of the present invention, the lower electrode 210, which is repeatedly aligned along the second direction DR2, can be arranged linearly along the second direction DR2.

[0122] The lower electrode 210, which is repeatedly aligned along the first direction DR1, can be arranged along the first direction DR1. Additionally, the lower electrode 210, which is repeatedly aligned along the second direction DR2, can be arranged along the second direction DR2.

[0123] Figure 20 and Figure 21 A semiconductor device according to at least one exemplary embodiment of the concept according to the present invention is shown. For reference, Figure 21 It is along Figure 20 The cross-sectional view taken by CC.

[0124] although Figure 20 An example layout view of DRAM excluding capacitors (CAP) is shown, but the embodiment is not limited to this. Figure 20 The first direction DR1 and the second direction DR2 can be Figure 1 The first direction DR1 and the second direction DR2. However, the embodiments are not limited to this case. Figure 20 The first direction DR1 can also correspond to Figure 1 The second direction DR2, and Figure 20 The second direction DR2 can also correspond to Figure 1 The first direction DR1.

[0125] Reference Figure 20 The semiconductor device according to the example embodiment may include a plurality of active regions ACT. The active regions ACT may be formed on the substrate 100 (see Figure 21 Component isolation layer 305 in ) (see Figure 21 )limited.

[0126] As design rules for semiconductor devices become less restrictive, the active region ACT can take the shape of a rib or stripe, as shown in the figure. The active region ACT can be shaped, for example, into a stripe extending along the fourth direction DR4.

[0127] Multiple gate electrodes may intersect the active region ACT along a first direction DR1. The gate electrodes may extend parallel to each other. The gate electrodes may be, for example, multiple word lines WL. The word lines WL may be spaced according to a regular pattern. The width of each word line WL or the gap between word lines WL can be determined according to design rules. Multiple bit lines BL may extend along the word lines WL along a second direction DR2 orthogonal to the word lines WL. The bit lines BL may extend parallel to each other. The bit lines BL may be spaced according to a regular pattern. The width of each bit line BL or the gap between bit lines BL can be determined according to design rules.

[0128] The semiconductor device according to an embodiment may include various contact arrays formed on an active region ACT. The various contact arrays may, for example, include direct contacts DC, buried contacts BC, and landing pads LP. Here, the direct contact DC may be a contact that electrically connects the active region ACT to the bit line BL. The buried contact BC may be a contact that connects the active region ACT to the capacitor CAP (see...). Figure 21 The lower electrode 210 (see) Figure 21 The contact part of ).

[0129] In the arrangement, the contact area between each buried contact BC and the corresponding active region ACT can be very small. Therefore, a conductive second landing pad LP can be introduced to increase the contact area with the corresponding active region ACT and the corresponding lower electrode 210 of the capacitor CAP (see...). Figure 21 The second landing pad LP can be located between each buried contact BC and the corresponding active region ACT, or between each buried contact BC and the corresponding lower electrode 210 of the capacitor CAP. In the semiconductor device according to the embodiment, the second landing pad LP can be located between each buried contact BC and the corresponding lower electrode 210 of the capacitor CAP. The increased contact area by introducing the second landing pad LP can reduce the contact resistance between each active region ACT and the corresponding lower electrode 210 of the capacitor CAP.

[0130] In the semiconductor device according to the embodiment, each direct contact DC can be located in the central portion of the corresponding active region ACT. Buried contacts BC can be located at both ends of each active region ACT. Since the buried contacts BC are located at both ends of each active region ACT, the second landing pad LP can be adjacent to both ends of each active region ACT to partially overlap with the buried contacts BC. For example, each buried contact BC can be formed as an isolation layer 305 between the active region ACT and the adjacent word lines WL and BL (see [link]). Figure 21 )overlapping.

[0131] The word line WL can be buried in the substrate 100. The word line WL can intersect with the active region ACT between the direct contact DC or the buried contact BC.

[0132] As shown in the figure, the two word lines WL can intersect an active region ACT. Since the active region ACT is tilted, the word lines WL can form an angle of less than 90 degrees with the active region ACT.

[0133] The direct contact DC and the buried contact BC can be symmetrical. Therefore, the direct contact DC and the buried contact BC can be located on a straight line along the first direction DR1 and the second direction DR4. Unlike the direct contact DC and the buried contact BC, the second landing pad LP can be in a zigzag pattern along the second direction DR2 extending along the bit line BL. In addition, the second landing pad LP can overlap with the same side of each bit line BL along the first direction DR1 extending along the word line WL. For example, each second landing pad LP in the first line can overlap with the left side of the corresponding bit line BL, and each second landing pad LP in the second line can overlap with the right side of the corresponding bit line BL.

[0134] Reference Figure 20 and Figure 21 The semiconductor device according to the example embodiment may include gate structures 315_1 and 315_2, a second storage contact 350, and a capacitor CAP.

[0135] A device isolation layer 305 can be formed in the substrate 100. The device isolation layer 305 can have a shallow trench isolation (STI) structure with device isolation features. The device isolation layer 305 can define an active region ACT on the substrate 100.

[0136] Gate structures 315_1 and 315_2 can be formed in the substrate 100 and the device isolation layer 305. Gate structures 315_1 and 315_2 can be formed to intersect with the device isolation layer 305 and the active region ACT defined by the device isolation layer 305. Gate structures 315_1 and 315_2 include gate structure 315_1 in the active region ACT of the substrate 100 and gate structure 315_2 in the device isolation layer 305. Each of gate structures 315_1 and 315_2 may include a buried gate trench 320t, a gate insulating layer 330, a gate electrode 320, and a gate blocking pattern 340 formed in the substrate 100 or the device isolation layer 305. The gate electrode 320 may correspond to each word line WL. For example, the depth of the buried gate trench 320t formed in the substrate 100 may be different from the depth of the buried gate trench 320t formed in the device isolation layer 305.

[0137] The gate insulating layer 330 may extend along the sidewalls and bottom surface of the buried gate trench 320t. The gate insulating layer 330 may extend along the contour of at least a portion of the buried gate trench 320t. The gate insulating layer 330 may, for example, comprise at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material containing a metal.

[0138] A gate electrode 320 can be formed on the gate insulating layer 330. The gate electrode 320 can fill a portion of the buried gate trench 320t.

[0139] The gate electrode 320 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal oxide, a conductive metal oxynitride, and / or a metal.

[0140] A gate blocking pattern 340 may be formed on the gate electrode 320. The gate blocking pattern 340 may fill any remaining buried gate trench 320 after the gate electrode 320 is formed. The gate blocking pattern 340 may include an insulator, such as at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon carbonitride, and / or combinations thereof.

[0141] The third lower interlayer insulating film 370 may be on the substrate 100 and the device isolation layer 305. The third lower interlayer insulating film 370 may cover the gate structures 315_1 and 315_2.

[0142] A second storage contact 350 may be formed in the third lower interlayer insulating film 370. The second storage contact 350 may be connected to the substrate 100. More specifically, the second storage contact 350 may be connected to the source / drain regions formed in the active region ACT of the substrate 100. The second storage contact 350 may be on at least one side of each of the gate structures 315_1 and 315_2. For example, the second storage contact 350 may be on both sides of each of the gate structures 315_1 and 315_2, respectively. The second storage contact 350 may correspond to the buried contact BC and may act as a contact plug for the source / drain regions. Additionally, the second storage contact 350 may correspond to... Figure 3 and Figure 4 The first storage contact 105.

[0143] A storage pad 360 can be formed on the second storage contact 350. The storage pad 360 can be electrically connected to the second storage contact 350. Here, the storage pad 360 can correspond to the second landing pad LP. Additionally, the storage pad 360 can correspond to... Figure 3 and Figure 4 The first landing pad is 115.

[0144] A third upper interlayer insulating film 375 can be formed on the third lower interlayer insulating film 370. The third upper interlayer insulating film 375 can cover the storage pad 360. The third upper interlayer insulating film 375 and the third lower interlayer insulating film 370 can correspond to Figure 3 and Figure 4 The first interlayer insulating film 110. A second etch stop layer 380 can be formed on the third upper interlayer insulating film 375 and the storage pad 360. The second etch stop layer 380 can correspond to Figure 3 and Figure 4 The first etch stop layer 120.

[0145] The capacitor CAP can be on the storage pad 360. The capacitor CAP can be connected to the storage pad 360. The capacitor CAP can be electrically connected to the second storage contact 350.

[0146] The capacitor CAP may include a lower electrode 210, a capacitor dielectric layer 220, an upper electrode 230, and an upper plate electrode 240. A first electrode support 130 and a second electrode support 150 may be formed on the second etch stop layer 380.

[0147] The capacitor CAP includes a lower electrode 210, a capacitor dielectric layer 220, an upper electrode 230, an upper plate electrode 240, a first electrode support 130, and a second electrode support 150, which can be referenced above. Figures 1 to 19 The descriptions are basically the same.

[0148] Figures 22 to 34 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention.

[0149] For reference only. Figure 22 , Figure 24 , Figure 26 , Figure 28 and Figure 29 This is a plan view showing the intermediate operations. Figure 23 , Figure 25 , Figure 27 and Figure 31 It is along Figure 22 , Figure 24 , Figure 26 and Figure 29 A cross-sectional view of BB. Figure 30 It is along Figure 29 The cross-sectional view taken from AA.

[0150] Reference Figure 22 and Figure 23 A mold structure including multiple lower electrode holes 210h can be formed on the substrate 100. The lower electrode holes 210h can expose the first landing pad 115. The mold structure may include a first mold layer 125p, a first electrode support layer 130p, a second mold layer 135p, and a second electrode support layer 150p sequentially stacked on the substrate 100.

[0151] A first mold layer 125p, a first electrode support layer 130p, a second mold layer 135p, and a second electrode support layer 150p can be sequentially formed on a substrate 100. A lower electrode hole 210h can then be formed, thereby forming a mold structure on the substrate 100. The lower electrode hole 210h can be formed by etching the sequentially stacked first mold layer 125p, first electrode support layer 130p, second mold layer 135p, and second electrode support layer 150p using a wet and / or dry etching process. The etching process may include a mask (not shown) to protect the mold structure and define the lower electrode hole 210h during the etching process.

[0152] Reference Figure 24 and Figure 25 An insulating spacer layer 160p can be formed on the upper surface and sidewall of the lower electrode hole 210h. The insulating spacer layer 160p can cover a portion of the sidewall of the lower electrode hole 210h and the upper surface of the second electrode support layer 150p. The insulating spacer layer 160p can completely cover the sidewall of the second electrode support layer 150p defining the lower electrode hole 210h.

[0153] The insulating spacer layer 160p can be formed using a stepped coverage deposition method. By using this deposition method, the insulating spacer layer 160p can be formed to cover only the upper part of the mold structure, and therefore the insulating spacer layer 160p is not formed on the exposed upper surface of the first landing pad 115.

[0154] Reference Figure 26 and Figure 27 The lower electrode layer can fill the lower electrode hole 210h in which an insulating spacer layer 160p is formed.

[0155] A portion of the lower electrode layer and insulating spacer layer 160p on the upper surface of the second electrode support layer 150p can be removed, for example, by an etching process or a chemical mechanical polishing process, to form a lower electrode 210 that fills the lower electrode hole 210h. Therefore, an insulating spacer 160 can be formed between the lower electrode 210 and the second electrode support layer 150p.

[0156] and Figures 24 to 27 Unlike other methods, a sacrificial layer can be formed to fill a portion of each lower electrode hole 210h. After the insulating spacer 160 is formed on the sidewall of the lower electrode hole 210h exposed by the sacrificial layer, the sacrificial layer can be removed. After removing the sacrificial layer, the lower electrode 210 can be formed to fill the lower electrode hole 210h.

[0157] Reference Figure 28 A first mask pattern 155, including a first opening 155op, can be formed on the second electrode support layer 150p and the lower electrode 210.

[0158] The first mask pattern 155 may be used to form the second electrode support 150 (see...). Figure 3 ) and the first electrode support 130 (see Figure 3 The mask of ). Additionally, the first opening 155op can be located at the same position as the first through pattern 130tp (see Figure 4 ) and second through pattern 150tp (see Figure 4 (The corresponding position.)

[0159] Reference Figures 29 to 31 The second electrode support layer 150p and the first electrode support layer 130p can be patterned using the first mask pattern 155. Therefore, the first electrode support 130 and the second electrode support 150 can be formed on the substrate 100.

[0160] While forming the first electrode support 130 and the second electrode support 150, a first through pattern 130tp and a second through pattern 150tp can be formed.

[0161] The second electrode support layer 150p can be patterned using the first mask pattern 155 to form the second electrode support 150. Simultaneously with forming the second electrode support 150, the second electrode support layer 150p exposed by the first opening 155op can be removed to form a second through-pattern 150tp. Simultaneously with forming the second through-pattern 150tp, the upper portion of each lower electrode 210 exposed by the first opening 155op can be chamfered.

[0162] Then, the exposed second mold layer 135p is removed. Removing the second mold layer 135p exposes a portion of the sidewall of each lower electrode 210.

[0163] After removing the second mold layer 135p, the exposed first electrode support layer 130p can be patterned using the first mask pattern 155. Thus, the first electrode support 130 can be formed. Simultaneously with forming the first electrode support 130, the first electrode support layer 130p exposed by the first opening 155op can be removed to form the first through-pattern 130tp.

[0164] Then, the exposed first mold layer 125p is removed. Removing the first mold layer 125p exposes another portion of the sidewall of each lower electrode 210. After removing the first mold layer 125p, the first mask pattern 155 can be removed.

[0165] Reference Figure 32 A capacitor dielectric layer 220 and an upper electrode 230 can be sequentially formed on the exposed sidewall of the lower electrode 210 and on the upper surface 210us of the lower electrode 210.

[0166] The capacitor dielectric layer 220 and the upper electrode 230 are also sequentially formed on the upper surface 150µs of the second electrode support 150.

[0167] An upper plate electrode 240 can be formed on the upper electrode 230. While forming the upper plate electrode 240, the upper electrode 230 can be partially patterned to correspond to the size of the upper plate electrode 240.

[0168] Reference Figure 33 The capacitor dielectric layer 220, the upper electrode 230, and the upper plate electrode 240 can be partially removed to expose a portion of the second electrode support 150. Therefore, an exposure area 150µs_2 of the upper surface 150µs of the second electrode support 150 can be defined.

[0169] More specifically, a second lower interlayer insulating film 260_1 can be formed on the first etch stop layer 120 to cover the upper plate electrode 240. The second lower interlayer insulating film 260_1 can expose the upper surface of the upper plate electrode 240, but the embodiment is not limited to this. A second mask pattern 156 can be formed on the second lower interlayer insulating film 260_1. The second mask pattern 156 can be used to partially remove the capacitor dielectric layer 220, the upper electrode 230, and the upper plate electrode 240. Therefore, a connecting pattern trench 250t can be formed to expose an exposure area 150us_2 of the upper surface 150us of the second electrode support 150.

[0170] Then, the second mask pattern 156 can be removed.

[0171] Reference Figure 34 A support connection pattern 250 can be formed to fill the connection pattern groove 250t. The support connection pattern 250 can cover the exposed area 150us_2 of the upper surface 150us of the second electrode support 150.

[0172] The support connection pattern 250 can be connected to the second electrode support 150 through the exposed area 150us_2 of the upper surface 150us of the second electrode support 150.

[0173] A second upper interlayer insulating film 260_2 can be formed on the second lower interlayer insulating film 260_1 to cover the upper surface of the supporting connection pattern 250 and the upper plate electrode 240.

[0174] Reference Figure 3 A first grounding plug 270 may be formed in a second upper interlayer insulating film 260_2, which is part of a second interlayer insulating film 260. The first grounding plug 270 may be connected to the upper plate electrode 240. The first grounding plug 270 may be electrically connected to the exposed second electrode support 150.

[0175] Figure 35 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention. Figure 35 It can be in Figure 33 The process that follows.

[0176] Reference Figure 35 A second upper interlayer insulating film 260_2 can be formed on the second lower interlayer insulating film 260_1 to fill the connecting pattern groove 250t.

[0177] The second upper interlayer insulating film 260_2 can cover the exposed area 150us_2 of the upper surface 150us of the second electrode support 150.

[0178] Reference Figures 9 to 11A first grounding plug 270 and a second grounding plug 271 can be formed in a second upper interlayer insulating film 260_2, which is part of a second interlayer insulating film 260.

[0179] The first grounding plug 270 can be connected to the upper plate electrode 240, and at least a portion of the second grounding plug 271 can be connected to the second electrode support 150.

[0180] Figures 36 to 39 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention. Figure 36 It can be in Figures 29 to 31 The process that follows.

[0181] Reference Figure 36 A capacitor dielectric layer 220 and an upper electrode 230 can be sequentially formed on the exposed sidewall of the lower electrode 210 and on the upper surface 210us of the lower electrode 210.

[0182] Then, a sacrificial interlayer insulating film 260sd can be formed on the first etch stop layer 120. The sacrificial interlayer insulating film 260sd can expose the upper electrode 230 on the upper surface 150us of the second electrode support 150 and the upper surface 210us of the lower electrode 210.

[0183] Reference Figure 37 A third mask pattern 157 can be formed on the upper electrode 230 and the sacrificial interlayer insulating film 260sd.

[0184] The capacitor dielectric layer 220 and the upper electrode 230 can be partially removed using the third mask pattern 157 to expose a portion of the second electrode support 150. Therefore, an exposure area 150µs_2 of the upper surface 150µs of the second electrode support 150 can be defined.

[0185] Then, the third mask pattern 157 can be removed. Additionally, the sacrificial interlayer insulating film 260sd can be removed.

[0186] Reference Figure 38 An upper plate electrode 240 can be formed on the upper electrode 230. The upper plate electrode 240 can cover the exposed area 150us_2 of the upper surface 150us of the second electrode support 150.

[0187] The upper plate electrode 240 can be connected to the second electrode support 150 through the exposed area 150us_2 of the upper surface 150us of the second electrode support 150.

[0188] Reference Figure 39 A second interlayer insulating film 260 can be formed on the upper plate electrode 240.

[0189] Reference Figure 8 A first grounding plug 270 can be formed in the second interlayer insulating film 260.

[0190] Figure 40 This is a view illustrating the operation of a method for manufacturing a semiconductor device according to at least one exemplary embodiment of the concept of the present invention. Figure 40 It can be in Figure 32 The process that follows.

[0191] Reference Figure 15 and Figure 40 A second interlayer insulating film 260 can be formed on the upper plate electrode 240.

[0192] The second grounding plug 271 can pass through the second interlayer insulating film 260, the upper plate electrode 240, the upper electrode 230, and the capacitor dielectric layer 220, and then be connected to the second electrode support 150. The second grounding plug 271 can be connected to the edge portion 150_2 of the second electrode support 150.

[0193] In concluding this detailed description, those skilled in the art will understand that various changes and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments of the inventive concept disclosed herein are used only in a general and descriptive sense, and not for limiting purposes.

Claims

1. A semiconductor device, comprising: Multiple lower electrodes are located on the substrate. A first electrode support is located between adjacent lower electrodes among the plurality of lower electrodes, and the first electrode support comprises a conductive material. A dielectric layer is provided on the plurality of lower electrodes and the first electrode support and extends along the contour of the first electrode support and each of the plurality of lower electrodes. The upper electrode is located on the dielectric layer. Upper plate electrode, on the upper electrode, The first electrode support is not disposed on the upper surface of each of the plurality of lower electrodes. The first electrode support includes an electrode support portion and an edge portion surrounding the electrode support portion. Wherein, the upper surface of the edge portion of the first electrode support is in contact with the upper plate electrode, and The dielectric layer is in contact with the upper surface of the electrode support portion of the first electrode support.

2. The semiconductor device according to claim 1, further comprising: An insulating spacer is provided between the first electrode support and each of the plurality of lower electrodes.

3. The semiconductor device according to claim 2, wherein, The insulating spacer comprises an insulating material with a dielectric constant greater than that of silicon oxide.

4. The semiconductor device according to claim 2, wherein, The first electrode support includes a first surface and a second surface that face each other. The first surface of the first electrode support faces the substrate, and The distance from the second surface of the first electrode support to the bottom of the insulating spacer is greater than the thickness of the first electrode support.

5. The semiconductor device according to claim 1, further comprising: A grounding plug is connected to the upper electrode. The first electrode support is electrically connected to the grounding plug.

6. The semiconductor device according to claim 1, further comprising: A second electrode support is located between the substrate and the first electrode support, and the second electrode support includes an insulating material.

7. The semiconductor device according to claim 1, wherein, The lower electrode and the first electrode support do not contact each other.

8. The semiconductor device according to claim 1, wherein, Each of the lower electrodes has a columnar shape extending away from the upper surface of the substrate.

9. A semiconductor device, comprising: Multiple lower electrodes are located on the substrate. An electrode support, comprising a conductive material, is located between adjacent lower electrodes among the plurality of lower electrodes, and the electrode support includes a support exposed area and an unexposed area on its upper surface. A dielectric layer is present on the electrode support and the lower electrode, but not on the exposed support area of ​​the electrode support. The upper electrode is located on the dielectric layer. An upper plate electrode, located on the upper electrode and in contact with the exposed support area; as well as A grounding plug is connected to the upper plate electrode. The dielectric layer is in contact with the unexposed area, and The electrode support is not disposed on the upper surface of each of the plurality of lower electrodes.

10. The semiconductor device according to claim 9, wherein, The electrode support includes an electrode support portion and an edge portion surrounding the electrode support portion. The lower electrode is located in the electrode support portion, and The edge portion of the electrode support includes the exposed support area.

11. The semiconductor device according to claim 10, wherein, The upper surface of the electrode support includes a first boundary line extending along a first direction and a second boundary line extending along a second direction different from the first direction, and The exposed support area extends along the first boundary line of the upper surface of the electrode support.

12. The semiconductor device according to claim 11, wherein, The exposed support area extends along the second boundary line of the upper surface of the electrode support.

13. The semiconductor device according to claim 9, wherein, The upper plate electrode completely covers the exposed support area.

14. The semiconductor device according to claim 9, wherein, The grounding plug is electrically connected to the electrode support through the exposed support area.

15. The semiconductor device according to claim 9, further comprising: An insulating spacer is provided between the electrode support and each of the lower electrodes.

16. A semiconductor device, comprising: Trench, in the substrate; The gate electrode fills a portion of the trench; The source / drain region is adjacent to the gate electrode and laterally overlaps a portion of the gate electrode. Contact plug, connected to the source / drain area; Landing pad, on the contact plug; An etch stop layer is applied to the landing pads, exposing at least a portion of the landing pads; The lower electrode is connected to the landing pad; A first electrode support is located on the sidewall of the lower electrode and spaced apart from the etch stop layer, the first electrode support comprising an insulating material; A second electrode support is located on the sidewall of the lower electrode and spaced apart from the first electrode support, the second electrode support comprising a conductive material; An insulating spacer is located between the second electrode support and the lower electrode; A dielectric layer extends along the contours of the lower electrode, the first electrode support, and the second electrode support on the lower electrode, the first electrode support, and the second electrode support; The upper electrode, on the dielectric layer, and Upper plate electrode, on the upper electrode, The second electrode support is not disposed on the upper surface of the lower electrode. The upper surface of the second electrode support includes an unexposed area on which the dielectric layer and the upper electrode are disposed, and an exposed support area in contact with the upper plate electrode.

17. The semiconductor device according to claim 16, wherein, The insulating spacer includes a portion whose thickness increases with the distance from the substrate.

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