Pad-constrained configurable logic devices

Abstract

An integrated circuit provides a semiconductor die with I / O bonding pads (1710), power bonding pads, and circuit ground pads. Each I / O bonding pad is associated with an input circuit (1802) having an input circuit output lead (1814). Multiple sets of digital logic function circuitry (1804) on the die provide different digital logic functions. Each function includes a logic input lead (1844) and a logic output lead (1846). Output circuits (1806) have output circuit lead-in leads (1820) and output circuit lead-out leads (1822), respectively. Connection structures such as vias formed in the semiconductor die electrically couple the input circuits to a selected set of digital logic functions and couple the selected set of digital logic functions to the output circuit lead-in leads. Upper-level metal conductors couple the output circuit lead-out leads to the selected I / O bonding pads.

Description

Background Technology

[0001] Standard digital logic integrated circuits, or IC logic families, were among the first IC components designed and developed in the 1960s, and now offer hundreds of different components and specifications. Digital logic circuits provide basic Boolean logic functions such as inverters, AND gates, NAND gates, OR gates, NOR gates, XOR gates, or XOR gates. Digital logic circuits also provide complex functions such as flip-flops, multiplexers, demultiplexers, line buffers, and line drivers.

[0002] Over time, the standard logic IC family has been designed and developed with increasingly complex manufacturing processes, multiple logic functions, various voltage, current and timing specifications, and various different packaging options.

[0003] Many of these logic ICs were originally designed and developed piecemeal by large design teams over several decades using the technology available at the time. This design approach was commercially viable in the early days of the semiconductor industry. However, as these logic families have become commercialized, it is no longer economically feasible to generate new logic families using this outdated method.

[0004] Furthermore, the variety of features or specifications of logic ICs can slow down the delivery speed to customers or require a large inventory of logic ICs. Without sufficient inventory of multiple logic ICs, new customer orders for specific logic ICs must be placed in production alerts as earlier orders, and then the production of a new batch of logic ICs must be awaited, which slows down delivery to customers. Alternatively, fully finished and tested ICs can be used to immediately fulfill customer orders, but this requires a large inventory of ICs with various specifications to await unknown orders that may never materialize, which is expensive.

[0005] Inventory and customer delivery time issues are exacerbated by the large number of logic IC families and the wide range of logic functions available within each family. These families offer a variety of electrical specifications, such as supply voltage, bipolar, CMOS and BiCMOS technologies, overvoltage-tolerant inputs, different input specifications, different output drive specifications, hot-plug capability, and input-to-output propagation delay. Each family also offers a variety of logic functions, such as buffers / line drivers, flip-flops, combinational logic, counters, shift registers, encoders / multiplexers, decoders / demultiplexers, gates, transceivers, level shifters, phase-locked loops, and bus switches.

[0006] The goal is to reduce the cost of existing and new logic devices while maintaining current electrical specifications. Summary of the Invention

[0007] The electronic device comprises a package material with an outer surface. Fourteen external terminals are exposed on the outer surface. An integrated circuit is formed on a semiconductor die. The integrated circuit and the semiconductor die are encapsulated in the package material, and the fourteen external terminals are connected to fourteen bonding pads on the semiconductor die via bonding wires or other conductors. Each bonding pad has a minimum area on the semiconductor die.

[0008] One of the bonding pads is a power bonding pad for circuit power supply, and the other bonding pad is a ground bonding pad for circuit grounding.

[0009] The other twelve bond pads are used for functional input and output signals. In this disclosure, reference to bond pads generally refers to bond pads used for functional input and output signals.

[0010] The power bonding pad and twelve bonding pads respectively cover the electrostatic discharge circuit of the bonding pad.

[0011] The semiconductor die has an input circuit for each bonding pad. Each input circuit has an input lead coupled to a bonding pad and an output lead.

[0012] The core circuit system provides several sets of digital logic circuits, each providing a different digital logic function on a semiconductor die. Each set of digital logic circuits or functions provides a limited number of identical logic functions, such as four logic gates, six inverters, six buffers, and two flip-flops.

[0013] The disclosed core circuit system includes multiple sets of digital logic circuits or functions, including: a set of four two-input NAND gates; a set of four two-input NOR gates; a set of four two-input AND gates; a set of four bus buffer gates with tri-state outputs; a set of four bus buffers with tri-state outputs; a set of four two-input OR gates; a set of four two-input XOR gates; a set of four two-input XOR gates; a set of two D flip-flops; a hex inverter; a set of six inverters with open-drain; a set of six inverters; a set of three three-input NAND gates; a set of three three-input AND gates; a set of three three-input NOR gates; a set of four two-input NOR gates with Schmitt trigger inputs; and a set of four two-input NAND gates with open-drain outputs.

[0014] The core circuit system includes logic input leads and logic output leads for each of the inputs and outputs used in the digital logic functions. The logic input leads can be coupled to the input circuit output leads.

[0015] Each of the six output circuits has an output circuit in-line lead and an output circuit out-line lead. The output circuit in-line lead can be coupled to the logic output lead of the selected digital logic function, and the output circuit out-line lead can be coupled to the selected bonding pad according to the configuration requirements of the electronic device.

[0016] The first conductive lead is connected to the output lead of the input circuit. The second conductive lead is adjacent to the first conductive lead and is connected to the logic input lead.

[0017] The third conductive lead is connected to the logic output lead. The fourth conductive lead is adjacent to the third conductive lead and is connected to the output circuit input lead.

[0018] The vias connect the configured first and second conductive leads together, and the configured third and fourth conductive leads together, and according to the configuration requirements of the electronic device, the fifth conductive lead is connected to the output leads of the output circuit and the bonding pads. Attached Figure Description

[0019] Figure 1A and Figure 1B These are the symbols for two-input NAND gates, and a planar representation of a packaged integrated circuit providing a set of four two-input NAND gates.

[0020] Figure 2A and Figure 2B These are the symbols for four two-input NOR gates, and a planar representation of a packaged integrated circuit providing a set of four two-input NOR gates.

[0021] Figure 3A and Figure 3B These are the symbols for a two-input AND gate, and a planar representation of a packaged integrated circuit providing a set of four two-input AND gates.

[0022] Figure 4A and Figure 4B These are, respectively, symbols for a set of four bus buffer gates with tri-state outputs, and planar representations of a packaged integrated circuit providing a set of four bus buffer gates with tri-state outputs.

[0023] Figure 5A and Figure 5B These are the symbols for a set of four tri-state buffers, and the planar representation of a packaged integrated circuit that provides a set of four tri-state buffers.

[0024] Figure 6A and Figure 6B These are the symbols for a two-input OR gate and a planar representation of a packaged integrated circuit providing a set of four two-input OR gates.

[0025] Figure 7A and Figure 7B These are the symbols for a two-input XOR gate, and a planar representation of a packaged integrated circuit providing a set of four two-input XOR gates.

[0026] Figure 8A and Figure 8B These are the symbols for four two-input XOR gates, and a planar representation of a packaged integrated circuit providing a set of four two-input XOR gates.

[0027] Figure 9A and Figure 9B These are schematic diagrams of D-type flip-flops and planar representations of a packaged integrated circuit providing a set of two D-type flip-flops.

[0028] Figure 10A and Figure 10B These are the symbols for inverters and a planar representation of a packaged integrated circuit providing a set of six inverters.

[0029] Figure 11A and Figure 11B These are the symbols for an inverter with open-drain outputs and a planar representation of a packaged integrated circuit providing a set of six inverters with open-drain outputs.

[0030] Figure 12A and Figure 12B These are the symbols for a three-input NAND gate, and a planar representation of a packaged integrated circuit providing a set of three three-input NAND gates.

[0031] Figure 13A and Figure 13B These are the symbols for three three-input AND gates, and a planar representation of a packaged integrated circuit providing a set of three three-input AND gates.

[0032] Figure 14A and Figure 14B These are the symbols for three three-input NOR gates, and the planar representation of a packaged integrated circuit providing a set of three three-input NOR gates.

[0033] Figure 15A and Figure 15B These are, respectively, symbols for two-input NOR gates with Schmitt trigger inputs, and planar representations of a packaged integrated circuit providing a set of four two-input NOR gates with Schmitt trigger inputs.

[0034] Figure 16A and Figure 16B These are, respectively, the symbols for two-input NAND gates with open-drain outputs, and a planar representation of a packaged integrated circuit providing a set of four two-input NAND gates with open-drain outputs.

[0035] Figure 17A and Figure 17B These are, respectively, a planar representation of an integrated circuit die according to the present disclosure, and a planar representation of a packaged integrated circuit based on a die according to the present disclosure.

[0036] Figure 18 yes Figure 17A A schematic diagram of the circuitry inside the die.

[0037] Figure 19A and Figure 19B These are schematic diagrams of circuits with optional straps.

[0038] Figure 20 This is a schematic diagram of a logic circuit that provides a set of four two-input NAND gates.

[0039] Figure 21 Figure 17 is a partial exploded plan view of the die, which depicts the conductive leads, indicates the strapping via with dashed lines, and indicates the cross-section line 22-22.

[0040] Figure 22 Along the direction of the arrow Figure 21 The sectional view is taken from line 22-22 and depicts the through holes of the connecting structure.

[0041] Figure 23 It is an ideal plan view of semiconductor dies, bonding wires, and lead frames.

[0042] Figure 24 It is an ideal plan view of the connection between the output circuit and the bonding pad as disclosed in Figures 1, 3, 4, 5, 6, 7, 15 and 16.

[0043] Figure 25 It is an ideal plan view of the connection between the output circuit and the bonding pad as shown in Figure 2.

[0044] Figure 26 It is an ideal plan view of the connection between the output circuit and the bonding pad as shown in Figure 8.

[0045] Figure 27 It is an ideal plan view of the connection between the output circuit and the bonding pad as shown in Figure 9.

[0046] Figure 28 It is an ideal plan view of the connection between the output circuit and the bonding pad as shown in Figures 10 and 11.

[0047] Figure 29 It is an ideal plan view of the connection between the output circuit and the bonding pad as shown in Figures 12, 13 and 14.

[0048] Figure 30 This is a plan view of the intermediate stage of die processing before adding upper-level metal interconnects. Detailed Implementation

[0049] The description in this specification is prepared for those skilled in the art, and many process and structural details that are not essential for understanding this disclosure are omitted. The figures in the accompanying drawings are abstract, high-level representations of semiconductor dies implementing gate and flip-flop logic functions. The figures intentionally omit implementation details, such as the multiple layers of individual transistors and their fabrication within the semiconductor die, to simplify the description and facilitate understanding of this disclosure. Those skilled in the art will understand the description of these abstract representations and will understand that more detailed structures or elements are omitted in the following description of this disclosure.

[0050] The actual implementations of integrated circuits on semiconductor dies disclosed in this specification will be very small and difficult to image. The accompanying drawings must be greatly enlarged to represent the actual semiconductor dies they depict, and are not intended to depict all well-known individual circuits present in such integrated circuits.

[0051] The word "connection" may or may not indicate a direct connection without an intermediate circuit. The word "coupled" can infer that a described or other intelligible undescribed structure may exist between "coupled" elements.

[0052] Using a master design with a set of digital logic functions in early semiconductor processing steps, and then applying differentiated post-processing steps to individual logic functions, can more efficiently address inventory and customer lead time issues. Post-processing steps can use upper-level metal layer leads, such as through-hole interconnects, to configure the desired logic functions from the set of logic functions available in the master design.

[0053] One consideration for achieving this technological advancement is reducing a large number of known logic functions to a smaller, initial set of logic functions that can be implemented in a single master design and differentiated in later processing steps. This consideration involves selecting a limited set of logic functions with mechanical specifications matching the number of package pins and compatible electrical and timing specifications for operation, input, and output.

[0054] Another consideration in achieving this advancement is that the size of the main die for implementing the master design used for the first set of logic functions will be limited by the number and size of the bonding pads formed on the main die. The number of bonding pads is influenced by the number of inputs and outputs of the first set of logic functions, as well as the bonding pads for power supply and circuit ground. The minimum size of the bonding pads is limited by the assembly manufacturability of the main die within the package. Because the number of bonding pads is influenced by the first set of logic functions, the semiconductor die area is essentially determined by the area required for the bonding pads.

[0055] Another consideration is the placement of circuitry on the main die. One way to effectively utilize die area in this regard is to place electrostatic discharge (ESD) protection circuitry below the bonding pads for inputs and outputs. With this arrangement of bonding pads and ESD circuitry, the functional logic circuitry can be centrally located on the main die. Connection leads and configuration structures (such as vias) can be positioned between the bonding pads and the centrally located functional logic.

[0056] Among these considerations, a non-limiting example of the set of known logical functionalities to be implemented in the master chip may include the set of logical functions described in the following paragraphs.

[0057] Figure 1A and Figure 1B The diagrams depict the symbol of a NAND inverter 100 and a plan view of a packaged quad NAND integrated circuit (IC) 110. The NAND gate 100 has an A input lead, a B input lead, and a Y output lead.

[0058] IC 110 has a package body 112 and 14 pins or terminals 114 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first NAND gate. Pin 4 is labeled Input 2A, pin 5 is labeled Input 2B, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of a second NAND gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3B. Pins 8, 9, and 10 provide the output and input of a third NAND gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4B. Pins 11, 12, and 13 provide the output and input of a fourth NAND gate. Pin 14 provides a connection to Vcc or circuit power supply.

[0059] An example of IC 110 is a four-way two-input NAND gate with part numbers SN54HC00 and SN74HC00 from Texas Instruments Incorporated.

[0060] Figure 2A and Figure 2B The symbols for four two-input NOR gates 202, 204, 206, and 208 are depicted, along with a planar representation of the packaged four-way NOR gate integrated circuit 210. Each of the NOR gates 202, 204, 206, and 208 has an A input, a B input, and a Y output.

[0061] IC 210 has a package body 212 and 14 pins or terminals 214 numbered 1 through 14. Pin 1 is labeled Output 1Y, pin 2 is labeled Input 1A, and pin 3 is labeled Input 1B. Pins 1, 2, and 3 provide the output and input of a first NOR gate. Pin 4 is labeled Output 2Y, pin 5 is labeled Input 2A, and pin 6 is labeled Input 2B. Pins 4, 5, and 6 provide the output and input of a second NOR gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Input 3A, pin 9 is labeled Input 3B, and pin 10 is labeled Output 3Y. Pins 8, 9, and 10 provide the input and output of a third NOR gate. Pin 11 is labeled Input 4A, pin 12 is labeled Input 4B, and pin 13 is labeled Output 4Y. Pins 11, 12, and 13 provide the input and output of a fourth NOR gate. Pin 14 provides a connection to Vcc or circuit power supply.

[0062] An example of IC 210 is a four-way two-input positive NOR gate with part numbers SN54HC02 and SN74HC02 from Texas Instruments Incorporated.

[0063] Figure 3A and Figure 3B The diagrams depict the symbol and package of the four-way AND gate integrated circuit 310, respectively. The AND gate 300 has A input, B input, and Y output.

[0064] IC 310 has a package body 312 and 14 pins or terminals 314 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first AND gate. Pin 4 is labeled Input 2A, pin 5 is labeled Input 2B, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of a second AND gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3B. Pins 8, 9, and 10 provide the output and input of a third AND gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4B. Pins 11, 12, and 13 provide the output and input of a fourth AND gate. Pin 14 provides a connection to Vcc or the circuit power supply.

[0065] An example of IC 310 is a four-way two-input positive AND gate with part numbers SN54HC08 and SN74HC08 from Texas Instruments Incorporated.

[0066] Figure 4A and Figure 4B Symbols for four bus buffer gates 402, 404, 406, and 408 with tri-state outputs are depicted, along with a planar representation of a packaged quad-bus buffer gate integrated circuit 420. Each bus buffer gate 402, 404, 406, and 408 has an inverter 412 and a buffer 414. The inverter 412 has an output enable input OE_ and an output, and the buffer 414 has a tri-state enable input, an A input, and a Y output connected to the output of the inverter 412.

[0067] IC 420 has a package body 422 and 14 pins or terminals 424 numbered 1 through 14. Pin 1 is labeled Input 1OE_, pin 2 is labeled Input 1A, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first bus buffer gate. Pin 4 is labeled Input 2OE_, pin 5 is labeled Input 2A, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of a second bus buffer gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3OE_. Pins 8, 9, and 10 provide the output and input of a third bus buffer gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4OE_. Pins 11, 12, and 13 provide the output and input of a fourth bus buffer gate. Pin 14 provides a connection to Vcc or the circuit power supply.

[0068] An example of IC 410 is a four-way bus buffer gate with tri-state outputs, part numbers SN54HC125 and SN74HC125, from Texas Instruments Incorporated.

[0069] Figure 5A and Figure 5B The symbols for four buffers 502, 504, 506, and 508 with tri-state outputs are depicted, along with a planar representation of a packaged quad-bus buffer integrated circuit 520. Each bus buffer 502, 504, 506, and 508 has a tri-state enable input OE, an A input, and a Y output.

[0070] IC 520 has a package body 522 and 14 pins or terminals 524 numbered 1 through 14. Pin 1 is labeled Input 1OE, pin 2 is labeled Input 1A, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of the first bus buffer. Pin 4 is labeled Input 2OE, pin 5 is labeled Input 2A, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of the second bus buffer. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3OE. Pins 8, 9, and 10 provide the output and input of the third bus buffer. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4OE. Pins 11, 12, and 13 provide the output and input of the fourth bus buffer. Pin 14 provides a connection to Vcc or circuit power supply.

[0071] An example of IC 510 is a quad buffer with tri-state outputs, part numbers SN54HC126 and SN74HC126, from Texas Instruments Incorporated.

[0072] Figure 6A and Figure 6B The diagrams depict the symbol and package of the OR gate 600, and a planar representation of the quad OR gate integrated circuit 610. The OR gate 600 has A input, B input, and Y output.

[0073] IC 610 has a package body 612 and 14 pins or terminals 614 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first OR gate. Pin 4 is labeled Input 2A, pin 5 is labeled Input 2B, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of a second OR gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3B. Pins 8, 9, and 10 provide the output and input of a third OR gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4B. Pins 11, 12, and 13 provide the output and input of a fourth OR gate. Pin 14 provides a connection to Vcc or the circuit power supply.

[0074] An example of IC 610 is a four-way two-input positive OR gate with part numbers SN54HC32 and SN74HC32 from Texas Instruments Incorporated.

[0075] Figure 7A and Figure 7B The symbol of the XOR gate 700 and the planar representation of the packaged quad XOR gate integrated circuit 710 are shown. The XOR gate 600 has A input, B input and Y output.

[0076] IC 710 has a package body 712 and 14 pins or terminals 714 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first XOR gate. Pin 4 is labeled Input 2A, pin 5 is labeled Input 2B, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of a second XOR gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3B. Pins 8, 9, and 10 provide the output and input of a third XOR gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4B. Pins 11, 12, and 13 provide the output and input of a fourth XOR gate. Pin 14 provides a connection to Vcc or circuit power supply.

[0077] An example of IC 710 is a four-way two-input XOR gate with part numbers SN54HC86 and SN74HC86 from Texas Instruments Incorporated.

[0078] Figure 8A and Figure 8B The symbols for four two-input XOR gates 802, 804, 806, and 808 are depicted, along with a planar representation of the packaged four-way XOR gate integrated circuit 210. Each of the XOR gates 802, 804, 806, and 808 has an A input, a B input, and a Y output.

[0079] IC 810 has a package body 812 and 14 pins or terminals 814 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first XOR gate. Pin 4 is labeled Output 2Y, pin 5 is labeled Input 2A, and pin 6 is labeled Input 2B. Pins 4, 5, and 6 provide the output and input of a second XOR gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Input 3A, pin 9 is labeled Input 3B, and pin 10 is labeled Output 3Y. Pins 8, 9, and 10 provide the output and input of a third XOR gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4B. Pins 11, 12, and 13 provide the output and input of a fourth XOR gate. Pin 14 provides a connection to Vcc or the circuit power supply.

[0080] An example of IC 610 is a four-way two-input XOR gate with part numbers SN54HC32 and SN74HC32 from Texas Instruments Incorporated.

[0081] Figure 9A and Figure 9B The symbols for a D-type flip-flop 900 and a plan view representation of a dual D-type flip-flop packaged with clear and preset integrated circuits 910 are depicted. Each flip-flop 900 has a D input, a CLK or clock input, a PRE_ or preset input, a CLR_ or clear input, a Q output, and a Q_ output.

[0082] IC 910 has a package body 912 and 14 pins or terminals 914 numbered 1 through 14. Pin 1 is labeled Input 1CLR_, pin 2 is labeled Input 1D, pin 3 is labeled Input 1CLK, pin 4 is labeled Input 1PRE_, pin 5 is labeled Output 1Q, and pin 6 is labeled Output 1Q_. Pins 1, 2, 3, 4, 5, and 6 provide the inputs and outputs of a first D-type flip-flop. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 2Q_, pin 9 is labeled Output 2Q, pin 10 is labeled Input 2PRE_, pin 11 is labeled Input 2CLK, pin 12 is labeled Input 2D, and pin 13 is labeled Input 2CLR_. Pins 8, 9, 10, 11, 12, and 13 provide the outputs and inputs of a second D-type flip-flop. Pin 14 provides a connection to Vcc or circuit power supply.

[0083] An example of IC 910 is a dual-D positive edge triggered flip-flop with clear and preset functions, part number SN54HC74 or SN74HC74 from Texas Instruments Incorporated.

[0084] Figure 10A and Figure 10B The symbol for inverter 1000 and a planar representation of the packaged hexagonal inverter integrated circuit 1010 are shown. Inverter 1000 has A input and Y output.

[0085] IC 1010 has a package body 1012 and 14 pins or terminals 1014 numbered 1 through 14. Pin 1 is labeled Input 1A, and pin 2 is labeled Output 1Y. Pins 1 and 2 provide the input and output of the first inverter. Pin 3 is labeled Input 2A, and pin 4 is labeled Output 2Y. Pins 3 and 4 provide the input and output of the second inverter. Pin 5 is labeled Input 3A, and pin 6 is labeled Output 3Y. Pins 5 and 6 provide the input and output of the third inverter. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 4Y, and pin 9 is labeled Input 4A. Pins 8 and 9 provide the output and input of the fourth inverter. Pin 10 is labeled Output 5Y, and pin 11 is labeled Input 5A. Pins 10 and 11 provide the output and input of the fifth inverter. Pin 12 is labeled Output 6Y, and pin 13 is labeled Input 6A. Pins 12 and 13 provide the output and input of the sixth inverter. Pin 14 provides a connection to Vcc or the circuit power supply.

[0086] An example of IC 1010 is a six-channel inverter with part numbers SN54HC04 and SN74HC04 from Texas Instruments Incorporated.

[0087] Figure 11A and Figure 11B The symbols for an inverter 1100 with open-drain outputs and a planar representation of a hexagonal inverter 1110 with an open-drain output integrated circuit package are shown, respectively. The inverter 1100 has an A input and a Y output with an open-drain output.

[0088] IC 1110 has a package body 1112 and 14 pins or terminals 1114 numbered 1 through 14. Pin 1 is labeled Input 1A, and pin 2 is labeled Output 1Y. Pins 1 and 2 provide the input and output of the first inverter. Pin 3 is labeled Input 2A, and pin 4 is labeled Output 2Y. Pins 3 and 4 provide the input and output of the second inverter. Pin 5 is labeled Input 3A, and pin 6 is labeled Output 3Y. Pins 5 and 6 provide the input and output of the third inverter. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 4Y, and pin 9 is labeled Input 4A. Pins 8 and 9 provide the output and input of the fourth inverter. Pin 10 is labeled Output 5Y, and pin 11 is labeled Input 5A. Pins 10 and 11 provide the output and input of the fifth inverter. Pin 12 is labeled Output 6Y, and pin 13 is labeled Input 6A. Pins 12 and 13 provide the output and input of the sixth inverter. Pin 14 provides a connection to Vcc or the circuit power supply.

[0089] An example of IC 1110 is a six-way inverter with open-drain output, part numbers SN54HC05 and SN74HC05, from Texas Instruments Incorporated.

[0090] Figure 12A and Figure 12B The symbol of a three-input NAND gate 1200 and a planar representation of a packaged three-way three-input NAND gate integrated circuit 1210 are depicted. The NAND gate 1200 has A input, B input, C input, and Y output.

[0091] IC 1210 has a package body 1212 and 14 pins or terminals 1214 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, pin 13 is labeled Input 1C, and pin 12 is labeled Output 1Y. Pins 1, 2, 13, and 14 provide the input and output of a first NAND gate. Pin 3 is labeled Input 2A, pin 4 is labeled Input 2B, pin 5 is labeled Input 2C, and pin 6 is labeled Output 2Y. Pins 3, 4, 5, and 6 provide the input and output of a second NAND gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, pin 10 is labeled Input 3B, and pin 11 is labeled Input 3C. Pins 8, 9, 10, and 11 provide the output and input of a third NAND gate. Pin 14 provides a connection to Vcc or circuit power supply.

[0092] An example of IC 1210 is a three-way, three-input positive NAND gate with part numbers SN54HC10 and SN74HC10 from Texas Instruments Incorporated.

[0093] Figure 13A and Figure 13B The symbols for three three-input AND gates 1302, 1304, and 1306 are depicted, along with a planar representation of a packaged three-way three-input AND gate integrated circuit 1310. Each of the AND gates 1302, 1304, and 1306 has an A input, a B input, a C input, and a Y output.

[0094] IC 1310 has a package body 1312 and 14 pins or terminals 1314 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, pin 13 is labeled Input 1C, and pin 12 is labeled Output 1Y. Pins 1, 2, 13, and 14 provide the input and output of a first AND gate. Pin 3 is labeled Input 2A, pin 4 is labeled Input 2B, pin 5 is labeled Input 2C, and pin 6 is labeled Output 2Y. Pins 3, 4, 5, and 6 provide the input and output of a second AND gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, pin 10 is labeled Input 3B, and pin 11 is labeled Input 3C. Pins 8, 9, 10, and 11 provide the output and input of a third AND gate. Pin 14 provides a connection to Vcc or circuit power supply.

[0095] An example of IC 1310 is a three-way, three-input AND gate with part numbers SN54HC11 and SN74HC11 from Texas Instruments Incorporated.

[0096] Figure 14A and Figure 14B The symbols for three three-input NOR gates 1402, 1404, and 1406 are depicted, along with a planar representation of the packaged three-way three-input NOR gate integrated circuit 1410. Each of the NOR gates 1402, 1404, and 1406 has an A input, a B input, a C input, and a Y output.

[0097] IC 1410 has a package body 1412 and 14 pins or terminals 1414 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, pin 13 is labeled Input 1C, and pin 12 is labeled Output 1Y. Pins 1, 2, 13, and 14 provide the input and output of a first NOR gate. Pin 3 is labeled Input 2A, pin 4 is labeled Input 2B, pin 5 is labeled Input 2C, and pin 6 is labeled Output 2Y. Pins 3, 4, 5, and 6 provide the input and output of a second NOR gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, pin 10 is labeled Input 3B, and pin 11 is labeled Input 3C. Pins 8, 9, 10, and 11 provide the output and input of a third NOR gate. Pin 14 provides a connection to Vcc or circuit power supply.

[0098] An example of IC 1410 is a three-way, three-input NOR gate with part numbers CD54HC27 and CD74HC27 from Texas Instruments Incorporated.

[0099] Figure 15A and Figure 15B The symbols for a NOR gate 1500 with Schmitt trigger inputs and a planar representation of a quad NOR gate 1510 with a package containing an integrated circuit with Schmitt trigger inputs are depicted. The NOR gate 1500 has A input, B input, and Y output.

[0100] IC 1510 has a package body 1512 and 14 pins or terminals 1514 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first NOR gate. Pin 4 is labeled Input 2A, pin 5 is labeled Input 2B, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of a second NOR gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3B. Pins 8, 9, and 10 provide the output and input of a third NOR gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4B. Pins 11, 12, and 13 provide the output and input of a fourth NOR gate. Pin 14 provides a connection to Vcc or the circuit power supply.

[0101] An example of IC 1510 is a quad positive NOR gate with Schmitt trigger inputs, part numbers SN54HC7002 and SN74HC7002 from Texas Instruments Incorporated.

[0102] Figure 16A and Figure 16B The symbols for a NAND gate 1600 with open-drain outputs are depicted, along with a planar representation of a quad NAND gate 1610 packaged with an open-drain output integrated circuit. The NAND gate 1600 has A input, B input, and Y output.

[0103] IC 1610 has a package body 1612 and 14 pins or terminals 1614 numbered 1 through 14. Pin 1 is labeled Input 1A, pin 2 is labeled Input 1B, and pin 3 is labeled Output 1Y. Pins 1, 2, and 3 provide the input and output of a first NAND gate. Pin 4 is labeled Input 2A, pin 5 is labeled Input 2B, and pin 6 is labeled Output 2Y. Pins 4, 5, and 6 provide the input and output of a second NAND gate. Pin 7 provides a connection to circuit ground (GND). Pin 8 is labeled Output 3Y, pin 9 is labeled Input 3A, and pin 10 is labeled Input 3B. Pins 8, 9, and 10 provide the output and input of a third NAND gate. Pin 11 is labeled Output 4Y, pin 12 is labeled Input 4A, and pin 13 is labeled Input 4B. Pins 11, 12, and 13 provide the output and input of a fourth NOR gate. Pin 14 provides a connection to Vcc or the circuit power supply.

[0104] An example of IC 1610 is a quad two-input positive NAND gate with open-drain outputs, part numbers SN54HC03 and SN74HC03, manufactured by Texas Instruments Incorporated.

[0105] Figure 17A A representation of a main die 1700 is depicted, having a first side 1702, a second side 1704, a third side 1706 opposite to the first side 1702, and a fourth side 1708 opposite to the second side 1704. This representation of the main die 1700 generally shows the relative positions of the circuit elements and is not intended to depict any particular circuit element. The die 1700 has a total of fourteen bonding pad regions 1710, numbered 1 to 14, around its periphery. In the finished die, each bonding pad region will carry an actual bonding pad; in the following description, the bonding pads rather than bonding pad regions will be used. Bond pad number 14 is used to provide circuit power, and bonding pad 7 is used to provide circuit ground for all configurations. All bonding pads 1-6 and 8-13 are configured to be used as digital logic function inputs, and any one of bonding pads 1-6 and 8-13 can be configured to be used as a digital logic function output. Each of the bonding pads 1-6 and 8-13 can be described as an I / O bonding pad or a functional bonding pad.

[0106] Bonding pads 1-6 and bonding pads 8-14 cover the protective electrostatic discharge circuitry not depicted separately.

[0107] Each of the bonding pads 1-6 and 8-13 also has an input circuit or input buffer coupled to and arranged adjacent to the bonding pad. The ESD circuit and the input circuit are not separately identified by reference numerals in this figure.

[0108] Die 1700 includes multiple sets of digital functional logic circuits 1722 in its central portion. The digital functional logic circuits 1722 are surrounded by a ring 1724 with two metal-level layers. The metal-level layers of the ring 1724 provide interconnections between the die's circuitry.

[0109] Die 1700 includes six output circuits 1726 numbered OUT1 to OUT6, which are arranged between the bonding pad region 1710 and the ring 1724 of the metal layer 1724.

[0110] Figure 17B An encapsulated integrated circuit, or IC 1750, is depicted, having a package body 1752 and 14 pins or terminals 1754 numbered 1 to 14. IC 1750 represents a completed digital logic IC that includes a die 1700 configured to provide a desired set of digital logic functions from one of a plurality of sets of digital logic functions disposed in digital function logic 1722.

[0111] Figure 18 A schematic diagram 1800 depicts the circuitry of a main core 1700 having twelve input circuits 1802, a digital logic function circuit system 1804, and six output circuits 1806. Each input circuit has an input lead 1810 coupled to an input bonding pad 1710, an output lead 1814, and an output enable input 1816. Each output circuit 1818 has an input lead 1820, an output lead 1822, and an output enable input 1824.

[0112] Digital logic function 1804 includes: multiple sets of NAND / AND gate circuitry 1830; multiple sets of NOR / OR gate circuitry 1832; multiple sets of XNOR / XOR gate circuitry 1834; multiple sets of inverter and buffer circuitry 1836; a set of D-type flip-flop circuitry (DFF) 1838; multiple sets of three-input NAND / AND3 gate circuitry 1840; and multiple sets of three-input NOR / OR3 gate circuitry 1842. Each set of digital logic functions has one input lead (such as input lead 1844) and one output lead (such as output lead 1846).

[0113] The 1830 provides multiple NAND / AND gate circuit systems, such as... Figure 1A and Figure 1B as well as Figure 16A and Figure 16B The four two-input NAND gates shown, and as... Figure 3A and Figure 3B The four two-input AND gates shown are illustrated.

[0114] The 1832 provides a multi-group NOR / OR gate circuit system, such as Figure 2A and Figure 2B as well as Figure 15A and Figure 15B The four two-input NOR gates shown, and as... Figure 6A and Figure 6B The four two-input OR gates shown are shown.

[0115] The 1834 provides a multi-group XOR NOT / XOR gate circuit system, such as... Figure 8A and Figure 8B The four two-input XOR gates shown, and as... Figure 7A and Figure 7B The four two-input XOR gates shown are illustrated.

[0116] The 1836 provides multiple inverters and buffer circuits, such as Figure 10A and Figure 10B as well as Figure 11A and Figure 11B The four inverter circuits shown, and as follows Figure 4A and Figure 4B , Figure 5A and Figure 5B The four buffer circuits shown are shown.

[0117] This set of D-type flip-flop circuits, DFF 1838, provides such... Figure 9A and Figure 9B The two D-type flip-flops shown.

[0118] The 1840 provides multiple NAND gate three-input / AND gate three-input circuits, such as... Figure 12A and Figure 12B The three three-input NAND gates shown, and as... Figure 13A and Figure 13B The three three-input AND gates shown are shown.

[0119] The 1842 provides multiple sets of three-input NOR gates / OR gates, such as... Figure 14A and Figure 14B The diagram shows three three-input NOR gates and three three-input OR gates.

[0120] Schematic diagram 1800 also depicts a first selection function structure 1850, a second selection function structure 1852, and a third selection function structure 1854. Selection function structures 1850 and 1852 are formed by a ring 1724 of an upper-level metal layer for configuring die 1700 into a desired digital logic function. The first selection structure 1850 electrically connects the output 1814 of input circuit 1818 to a selected input 1844 of digital logic function circuit 1804. The second selection structure 1852 electrically connects the output 1846 of digital logic function 1804 to a selected input 1820 of output circuit 1806. The third selection structure 1854 electrically connects the output 1822 of output circuit 1818 to a selected bonding pad 1710.

[0121] Schematic 1800 illustrates a circuit system that processes the main control chip to an intermediate stage before configuring it as one of the configurable digital logic functions. Input 1844 of digital logic function circuit 1804 remains unconnected to output 1814 of input circuit 1808, output 1846 of digital logic function circuit 1804 remains unconnected to input 1820 of output circuit 1818, and output 1822 of output circuit remains unconnected to output bonding pad 1710.

[0122] Figure 19A A representative input circuit 1808 is depicted, including an inverter 1902 having an input lead 1810 connected to one of the input bonding pads 1710 and an output lead 1904 connected to the input of an AND gate 1906. The AND gate 1906 has another input connected to an output enable lead 1816 and an output lead 1910 connected to the input of the inverter 1916, which has an input circuit output lead 1814. The output enable lead 1816 can be selectively connected to circuit ground 1912 via a strapping structure 1914, which can be implemented in vias between layers of metal layers, such as ring 1724.

[0123] When the output enable lead 1816 is not used in a selected configured digital logic function, connecting the output enable lead 1816 to circuit ground 1912 has the effect of disabling the input circuit 1808. When the output enable lead 1816 is not connected to ground, the input circuit is enabled. When the configured digital logic function is active, the disabled input circuit 1808 draws very little current.

[0124] Figure 19AThe linkage structure 1914 is depicted as an open-circuit switch. In an actual implementation of the main conductor, the open-circuit switch can be implemented as needed, such as by not forming an electrical connection between conductive leads. In this example, the open-circuit linkage structure can be implemented without vias between upper metal layers. In an actual implementation of the main conductor, a closed switch can be implemented as needed, such as by forming a connection between conductive leads. In this example, the closed linkage structure can be implemented as vias between upper metal layers. The form of the switch or electrical connection can appear as needed. This description of linkage structure 1914 applies to all descriptions of linkage structures in this specification, including output circuits.

[0125] Figure 19B A representative NOR gate 1950 with input A, input B, and output Y is depicted. Inputs A and B correspond to two of the digital logic function inputs 1844, while the output Y corresponds to one of the digital logic function outputs 1846. Inputs A and B are selectively connected to circuit ground via strip structures 1952 and 1954, which can be implemented in vias between layers of metal layers, such as ring 1724. When the configured digital logic function is operational, the digital logic function gate, whose inputs are connected to circuit ground, draws a very small current.

[0126] Figure 19A and Figure 19B The connection structure depicted can also be used to electrically connect the enable input lead of the output circuit 1806 (such as enable input lead 1824) to the circuit ground 1912.

[0127] Figure 20 The component 2000 is described as a master chip 1700 configured to implement a set of four-way two-input AND gate digital logic functions, such as... Figure 3A and Figure 3B As shown. Using corresponding reference numerals from earlier figures, component 2000 has bonding pads 1710 numbered 1-6 and 8-13, input circuit 1802, first selection function structure 1850, digital logic functions AND gates numbered 1-4 1830, second selection function structure 1852, output circuits numbered 1-6 1806, and third selection function structure 1854. Input circuit 1808 and output circuit 1818 use reference numerals from earlier figures. Figure 18 The attached figures are labeled with reference to the figures.

[0128] As an example, Figure 20A configuration of AND gate 2008 is depicted, which has an A input coupled to bonding pad number 1 via input circuit 1808, a B input coupled to bonding pad number 2 via input circuit 2010, and a Y output coupled to bonding pad 3 via output circuit OUT1 1818.

[0129] AND gate 2012 has an A input coupled to the bonding pad numbered 4 via input circuit 2014, a B input coupled to the bonding pad numbered 2 via input circuit 2016, and a Y output coupled to the bonding pad 6 via output circuit OUT3.

[0130] AND gate 2018 has an A input coupled to the bonding pad numbered 9 via input circuit 2020, a B input coupled to the bonding pad numbered 10 via input circuit 2022, and a Y output coupled to the bonding pad 8 via output circuit OUT4.

[0131] AND gate 2024 has an A input coupled to the bonding pad numbered 12 via input circuit 2026, a B input coupled to the bonding pad numbered 13 via input circuit 2028, and a Y output coupled to the bonding pad 11 via output circuit OUT5.

[0132] Output circuits OUT1 and OUT6 remain unconnected to the digital logic circuitry and bonding pads, as they are not required in this configuration. The enable lead 2030 of output circuit OUT2 is connected to circuit ground 1912 via stripe 2032 to disable operation of output circuit OUT2. The enable lead 2034 of output circuit OUT6 is also connected to circuit ground 1912 via stripe 2036 to disable operation of output circuit OUT6.

[0133] Input circuits 2040, 2042, 2044, and 2046 connect their inputs to bonding pads 3, 4, 8, and 11, respectively, and connect their enable lead ENA to circuit ground 1912 via a strap or via 1914. Since bonding pads 3, 4, 8, and 11 are used as output bonding pads, this disables the operation of these input circuits.

[0134] The enable leads of input circuits 1802, 201, 2014, 2016, 2020, 2022, 2026, and 2028, as well as output circuits OUT1 and OUT3-OUT5, are not connected to circuit ground to enable them to operate.

[0135] This configuration, which provides a set of four two-input AND gates, means that the other sets of digital logic function circuits 1804 are not connected to the input and output circuits.

[0136] Figure 21 A portion of the main core 1700 and a portion of the ring 1724 are depicted. The first-level metal layer has 14 conductive leads, such as conductive leads 2102, 2104, 2106, and 2108, which are placed in one direction as indicated by arrow 2109. A second-level metal layer, drawn as a dashed output line, has four leads (such as conductive leads 2110, 2112, 2114, and 2116) and is located below the first-level metal layer conductors 2102, 2104, 2106, and 2108, and is placed in a second direction as indicated by arrow 2118.

[0137] A via in region 2120 (shown by the dashed outline) electrically connects conductive lead 2102 to conductive lead 2112. A via in region 2122 (shown by the dashed outline) electrically connects conductive lead 2104 to conductive lead 2110. A via in region 2124 (shown by the dashed outline) electrically connects conductive lead 2106 to conductive lead 2114. A via in region 2126 (shown by the dashed outline) electrically connects conductive lead 2108 to conductive lead 2116.

[0138] Figure 22 A substrate of semiconductor material 2200 is depicted, through which a main core 1700 is formed. This substrate carries a second-level metal layer conductive lead (such as conductive lead 2112), an insulating layer 2202, and a first-level metal layer conductive lead (such as conductive lead 2102). A via 2106 is formed to pass through the insulating layer 2204 and electrically connect the conductive lead 2102 to the conductive lead 2112.

[0139] In a similar manner, other vias can provide electrical connections or couplings between conductive leads anywhere on the main conductor. These other vias can... Figure 18 The selected leads in the shown selective functional structures 1850, 1852, and 1854 are coupled together. Similarly, other vias can be provided to... Figure 19A and Figure 19B The connection structures identified in 1914, 1954, 1952, and 1954 are grounded.

[0140] Figure 23 A completed and configured master core 2300 is depicted, which is attached to a connection pad portion 2302 of a leadframe. The leadframe provides leadframe leads, such as leadframe leads 2304 numbered 1-14, whose relationships to each other are the same as those depicted in the encapsulated packaged integrated circuits in the previous figures. Bond wires (such as bond wires 2306) extend between bond pads (such as bond pads 2308) and leadframe leads (such as leadframe leads 2304).

[0141] Figure 24The die 2400 is depicted with bonding pads 1710 numbered 1-14 and output circuits 1806 numbered OUT1-OUT6. The output circuits OUT1-OUT6 are depicted with dashed outlines because they are formed within the semiconductor die beneath the upper-level metal shown in this plan view. For the same reason, Figures 25 to 29 The output circuits OUT1-OUT6 are also depicted with dashed outlines.

[0142] Upper-level metal conductor 2402 couples output circuit OUT1 to bonding pad 3. Upper-level metal conductor 2404 couples output circuit OUT3 to bonding pad 6. Upper-level metal conductor 2406 couples output circuit OUT4 to bonding pad 8. Upper-level metal conductor 2408 couples output circuit OUT5 to bonding pad 11. Output circuits OUT2 and OUT6 remain unconnected to bonding pads. This is the configuration for coupling output circuits to bonding pads used for the multiple sets of digital logic functions shown in Figures 1, 3, 4, 5, 6, 7, 15, and 16.

[0143] Die 2400 also has stubs 2410 and 2412 that are connected to output circuits OUT2 and OUT6, respectively, but not connected to any bonding pads. These stubs 2410 and 2412 are formed in a process step prior to the final process step. Among other things, the final process step forms upper-level metal conductors to couple the stubs from the output circuits to the bonding pads and configure the die for the desired digital logic function. These stubs are also depicted in the die in the accompanying figures below, but without reference numerals.

[0144] Die 2400 also has two power leads formed by upper-level metal conductors 2414 and 2416, which extend from bonding pad 14 across the die. Two circuit ground leads formed by upper-level metal conductors 2418 and 2420 extend from bonding pad 7 across the die together with the power leads. These power leads and circuit ground leads are also depicted in the die in the following figures, but without reference numerals.

[0145] Figure 25A die 2500 is depicted with bonding pads 1710 numbered 1-14 and output circuits 1806 numbered OUT1-OUT6. Upper-level metal conductor 2502 couples output circuit OUT1 to bonding pad 1. Upper-level metal conductor 2504 couples output circuit OUT2 to bonding pad 4. Upper-level metal conductor 2506 couples output circuit OUT4 to bonding pad 10. Upper-level metal conductor 2508 couples output circuit OUT6 to bonding pad 13. Output circuits OUT3 and OUT5 remain unconnected to bonding pads. This is the configuration for coupling the output circuits to bonding pads used for the set of digital logic functions shown in Figure 2.

[0146] Figure 26 A die 2600 is depicted with bonding pads 1710 numbered 1-14 and output circuits 1806 numbered OUT1-OUT6. Upper-level metal conductor 2602 couples output circuit OUT1 to bonding pad 3. Upper-level metal conductor 2604 couples output circuit OUT2 to bonding pad 4. Upper-level metal conductor 2606 couples output circuit OUT4 to bonding pad 10. Upper-level metal conductor 2608 couples output circuit OUT5 to bonding pad 11. Output circuits OUT3 and OUT6 remain unconnected to bonding pads. This is the configuration for coupling the output circuits to bonding pads used for the set of digital logic functions shown in Figure 8.

[0147] Figure 27 A die 2700 is depicted with bonding pads 1710 numbered 1-14 and output circuits 1806 numbered OUT1-OUT6. Upper-level metal conductor 2702 couples output circuit OUT2 to bonding pad 5. Upper-level metal conductor 2704 couples output circuit OUT3 to bonding pad 6. Upper-level metal conductor 2706 couples output circuit OUT4 to bonding pad 8. Upper-level metal conductor 2708 couples output circuit OUT5 to bonding pad 9. Output circuits OUT1 and OUT6 remain unconnected to bonding pads. This is the configuration for coupling the output circuits to bonding pads used for the set of digital logic functions shown in Figure 9.

[0148] Die 2700 provides a space 2710 between bonding pads 9-13 and bonding pads 8 and 14 and the power leads in the upper-level conductor 2714. This space is wide enough to accommodate two conductors 2706 and 2708 side-by-side without shorting each other or with the bonding pad 10 or power leads in the upper-level conductor 2714. Die 2700 provides a similar space 2712 between bonding pads 2-6 and bonding pads 1 and 7 and the power leads in the upper-level conductor 2716. These spaces 2710 and 2712 are characteristic of the layout of die 2700 and all other dies disclosed in this application, and provide space or areas for coupling output circuitry to the bonding pads in different configurations during final processing steps.

[0149] Figure 28 A die 2800 is depicted with bonding pads 1710 numbered 1-14 and output circuits 1806 numbered OUT1-OUT6. Upper-level metal conductor 2802 couples output circuit OUT1 to bonding pad 2. Upper-level metal conductor 2804 couples output circuit OUT2 to bonding pad 4. Upper-level metal conductor 2806 couples output circuit OUT3 to bonding pad 6. Upper-level metal conductor 2808 couples output circuit OUT4 to bonding pad 8. Upper-level metal conductor 2810 couples output circuit OUT5 to bonding pad 10. Upper-level metal conductor 2812 couples output circuit OUT6 to bonding pad 12. All output circuits OUT1-OUT6 are connected to bonding pads. This is a configuration for coupling the output circuits to bonding pads used for the multiple sets of digital logic functions shown in Figures 10 and 11.

[0150] Figure 29 A die 2900 is depicted with bonding pads 1710 numbered 1-14 and output circuits 1806 numbered OUT1-OUT6. Upper-level metal conductor 2902 couples output circuit OUT3 to bonding pad 6. Upper-level metal conductor 2904 couples output circuit OUT4 to bonding pad 8. Upper-level metal conductor 2906 couples output circuit OUT6 to bonding pad 12. Output circuits OUT1, OUT2, and OUT5 remain unconnected to bonding pads. This is the configuration for coupling the output circuits to bonding pads used for the set of digital logic functions shown in Figures 12, 13, and 14.

[0151] exist Figures 24 to 29In this design, the upper-level metal conductor coupling the output circuit to the bonding pad is wider than the conductor used to couple the input circuit to the digital logic circuit, and also wider than the conductor used to couple the digital logic circuit to the output circuit. The reason for using these wider conductors is that the drive current supplied by the output circuit to the output terminal must be much larger than the drive current that other conductors need to carry. To accommodate these wider conductors from the output circuit to the bonding pad, the die must have ample space, such as the spaces 2710 and 2712 between the output circuit and the bonding pad.

[0152] Figure 30 The die 3000 is depicted as being processed in the intermediate steps leading to circuit implementation before any overlay metal-level interconnects are formed. Die 3000 includes thirteen electrostatic discharge (ESD) circuits 3002, numbered 1-6 and 8-14; the ESD circuit numbered 14 is located below the circuit power bond pad and is larger than the other ESD circuits. There is no ESD circuit between ESD circuits 6 and 8 because this area will be located below the circuit ground bond pad.

[0153] Die 3000 includes twelve input circuits 3004-3026 arranged adjacent to ESD circuits 1-6 and 8-13, a centrally located digital logic circuit 3028 providing the desired digital logic function, and six output circuits 3030 numbered OUT1-OUT6 located between the digital logic circuits and the input circuits. Additional digital logic circuitry 3032 is formed in the region between ESD circuits 6 and 8, and a circuit ground bonding pad is formed below this region.

[0154] This arrangement of logic functions in a design reduces engineering time by designing multiple configurable components at once instead of eight separate components. It also reduces inventory and customer order delivery time. By only sending the IC 1700 to the intermediate manufacturing step, keeping only that intermediate product in inventory, and then completing manufacturing by configuring the desired logic functions according to the customer order, this design reduces inventory requirements and delivery time after a customer order is placed.

[0155] This specification and accompanying drawings disclose and depict a limited number of digital logic functions implemented and configured on a semiconductor die, as examples of possible digital logic functions that can be implemented and configured. Within the scope of this disclosure, other digital logic functions are conceivable and can be implemented and configured on similar semiconductor dies.

Claims

1. An integrated circuit formed on a semiconductor die, comprising: (a) Circuit power bonding pads, circuit ground bonding pads, and logic function input and output I / O bonding pads, each of the bonding pads having a minimum area on the semiconductor die; (b) An input circuit coupled to the I / O bonding pad and having input circuit output leads; (c) An output circuit having output circuit inlet leads and output circuit outlet leads; (d) A core circuit system of multiple sets of digital logic function circuits, each set having different digital logic functions, the core circuit system including logic input leads and logic output leads for each of the inputs and outputs of the digital logic functions; (e) A first conductive lead connected to the output lead of the input circuit; (f) A second conductive lead adjacent to the first conductive lead and connected to the logic input lead; (g) A third conductive lead connected to the logic output lead; (h) A fourth conductive lead adjacent to the third conductive lead and connected to the output circuit lead-in; (i) a through-hole connecting the first conductive lead and the second conductive lead together, and connecting the third conductive lead and the fourth conductive lead together; and (j) Connect the output lead of the output circuit to the fifth conductive lead of the I / O bonding pad.

2. The integrated circuit according to claim 1, comprising: (a) Multiple input circuits, each input circuit being coupled to an I / O bonding pad and having an input circuit output lead; (b) Multiple output circuits, each output circuit having an output circuit lead-in lead and an output circuit lead-out lead; (c) A plurality of first conductive leads, each of which is connected to an output lead of the input circuit; (d) A plurality of second conductive leads adjacent to the first conductive lead, and each second conductive lead is connected to a logic input lead; (e) Multiple third conductive leads, each of which is connected to a logic output lead; (f) A plurality of fourth conductive leads adjacent to the third conductive lead, and each fourth conductive lead is connected to an output circuit lead; (g) A via connecting the first conductive lead and the second conductive lead together, and connecting the third conductive lead and the fourth conductive lead together, to couple only one set of digital logic function circuitry between the input circuit and the output circuit; and (h) Multiple fifth conductive leads, each fifth conductive lead connecting the output circuit output lead to the I / O bonding pad.

3. The integrated circuit according to claim 1, wherein the first conductive lead, the second conductive lead, the third conductive lead and the fourth conductive lead are located between the core circuit system and the output circuit, and the fifth conductive lead is located between the output circuit and the I / O bonding pad.

4. The integrated circuit of claim 1, wherein the first conductive lead and the second conductive lead are arranged at right angles to each other, one of the first conductive lead and the second conductive lead is above the other of the first conductive lead and the second conductive lead, and the first conductive lead and the second conductive lead are separated by an insulating layer.

5. The integrated circuit of claim 1, wherein the third conductive lead and the fourth conductive lead are arranged at right angles to each other, one of the third conductive lead and the fourth conductive lead is above the other of the third conductive lead and the fourth conductive lead, and the conductive leads are separated by an insulating layer.

6. The integrated circuit of claim 1, wherein the core circuit system is formed at the center of the semiconductor die, the bonding pad is formed at the periphery of the semiconductor die, the output circuit is formed between the core circuit system and the bonding pad, and the fifth conductive lead is formed between the output circuit and the bonding pad.

7. The integrated circuit of claim 1, wherein there are 14 bonding pads.

8. The integrated circuit of claim 1, wherein the die is encapsulated in a package having 14 leads.

9. The integrated circuit according to claim 1, wherein the core circuit system comprises: A set of NAND gate circuit systems, a set of AND gate circuit systems, a set of NOR gate circuit systems, a set of OR gate circuit systems, a set of XOR gate circuit systems, a set of XOR gate circuit systems, a set of inverter circuit systems, and a set of D-type flip-flop circuit systems, wherein the die is encapsulated in a package with only 14 leads.

10. The integrated circuit of claim 1, wherein the core circuit system comprises a set of four two-input NAND gates.

11. The integrated circuit of claim 1, wherein the core circuit system comprises a set of four two-input AND gate circuit systems.

12. The integrated circuit of claim 1, wherein the core circuit system comprises a set of four two-input NOR gates.

13. The integrated circuit of claim 1, wherein the core circuit system comprises a set of four two-input OR gate circuit systems.

14. The integrated circuit of claim 1, wherein the core circuit system comprises a set of four two-input XOR NOT gates.

15. The integrated circuit of claim 1, wherein the core circuit system comprises a set of four two-input XOR gates.

16. The integrated circuit of claim 1, wherein the core circuit system comprises a set of six inverter circuits.

17. The integrated circuit of claim 1, wherein the core circuit system comprises a set of two D-type flip-flop circuit systems.

18. The integrated circuit of claim 1, wherein the core circuit system comprises a set of three three-input NAND gate circuit systems.

19. The integrated circuit of claim 1, wherein the core circuit system comprises a set of three three-input AND gate circuit systems.

20. The integrated circuit of claim 1, wherein the core circuit system comprises a set of three three-input NOR gate circuit systems.

21. The integrated circuit of claim 1, wherein the core circuit system comprises a set of three three-input OR gate circuit systems.

22. The integrated circuit according to claim 1, wherein the core circuit system comprises: A system of four two-input NOR gates; A system of four two-input OR gates; A system of four two-input XOR NOT gates; A system of four two-input XOR gates; A circuit with six inverters; A circuit system consisting of two D-type flip-flops; A set of three three-input NAND gate circuits; A set of three three-input AND gate circuits; A set of three three-input NOR gate circuits; as well as A set of three three-input OR gate circuits.

23. The integrated circuit of claim 1, wherein the input circuit includes an enable input and includes an option to ground the enable input.

24. The integrated circuit of claim 1, wherein the core circuit system comprises a logic gate system having logic inputs and including an option to ground the logic inputs.

25. The integrated circuit of claim 1, wherein the output circuit includes an enable input and includes an option to ground the enable input.

26. The integrated circuit of claim 2, wherein the core circuit system is formed at the center of the semiconductor die, the bonding pad is formed at the periphery of the semiconductor die, the output circuit is formed between the core circuit system and the bonding pad, and the fifth conductive lead is formed between the output circuit and the bonding pad, with two fifth conductive leads formed side-by-side between the output circuit and the bonding pad.

27. An electronic device, comprising: (a) Encapsulation material having an outer surface; (b) Fourteen external terminals exposed on the outer surface; (c) An integrated circuit formed on a semiconductor die, wherein the integrated circuit and the semiconductor die are encapsulated in the packaging material, the integrated circuit and the semiconductor die comprising: (i) Twelve input and output I / O bonding pads, each of which has a minimum area on the semiconductor die; (ii) An input circuit coupled to each I / O bonding pad and having an input circuit output lead, each input circuit including an enable input and including an option to ground the enable input; (iii) Six output circuits, each output circuit having an output circuit lead-in lead and an output circuit lead-out lead, each output circuit including an enable input and including an option to ground the enable input; (iv) A core circuit system for multiple sets of digital logic function circuits, the core circuit system comprising logic input leads for each of the inputs and logic output leads for each of the inputs and outputs of the multiple sets of digital logic function circuits, the core circuit system comprising: (A) A system of four two-input NAND gates; (B) A system of four two-input NOR gates; (C) A system of four two-input AND gates; (D) A set of four bus buffer circuits with tri-state outputs; (E) A set of four two-input OR gate circuits; (F) A set of four two-input XOR gate circuits; (G) A system of four two-input XOR NOT gates; (H) A circuit system consisting of two D-type flip-flops; (I) A set of six inverter circuits; (J) A set of six inverter circuits with open drain; (K) A circuit with six inverters; (L) A set of three three-input NAND gate circuits; (M) A set of three three-input AND gate circuits; (N) A set of three three-input NOR gate circuits; (O) A set of four two-input NOR gates with Schmitt trigger inputs; and (P) A set of four two-input NAND gates with open-drain outputs; and (v) A first conductive lead connected to the output lead of the input circuit; (vi) A second conductive lead adjacent to the first conductive lead and connected to the logic input lead; (vii) A third conductive lead connected to the logic output lead; (viii) A fourth conductive lead adjacent to the third conductive lead and connected to the output circuit lead-in; (ix) Through-hole, which connects the first conductive lead and the second conductive lead together and connects the third conductive lead and the fourth conductive lead together, so as to couple only one set of digital logic functions between the input circuit and the output circuit; (x) Couple the output circuit lead wire to the fifth conductive lead of the I / O bonding pad; (xi) A power bonding pad for circuit power supply and a ground bonding pad for circuit grounding, each having a minimum area on the semiconductor die; and (d) Couple the terminal to the bonding wire of the bonding pad.

28. An integrated circuit, comprising: (a) A semiconductor die having a first side, a second side, a third side opposite to the first side, a fourth side opposite to the second side, and a top surface; (b) Fourteen bonding pads formed on the top surface, including five bonding pads formed along the second side, five bonding pads formed along the fourth side, two bonding pads including power bonding pads formed along the first side, and two bonding pads including ground bonding pads formed along the third side, each of the bonding pads having a minimum area on the semiconductor die, and each bonding pad except the ground bonding pad covering an electrostatic discharge circuit for that bonding pad; (c) An input circuit is coupled to each bonding pad except for the power bonding pad and the ground bonding pad, and each input circuit has an input circuit output lead; (d) A core circuit system formed at the center of the semiconductor die, the core circuit system providing multiple sets of digital logic functions, the core circuit system including logic input leads and logic output leads for the digital logic functions; (e) Six output circuits, each output circuit having an output circuit lead-in lead and an output circuit lead-out lead; (f) A first conductive lead connected to the output lead of the input circuit; (g) A second conductive lead adjacent to the first conductive lead and connected to the logic input lead; (h) A third conductive lead connected to the logic output lead; (i) A fourth conductive lead adjacent to the third conductive lead and connected to the output circuit lead-in; (j) a via that connects the first conductive lead and the second conductive lead together and connects the third conductive lead and the fourth conductive lead together, so as to couple only one set of digital logic functions between the input circuit and the output circuit; and (k) Couple the output circuit lead wire to the fifth conductive lead of the bonding pad.

29. An integrated circuit semiconductor die, comprising: (a) An electrostatic discharge circuit formed in and around the periphery of the tube core; (b) Multiple sets of digital logic function circuit systems formed within and at the center of the die, each set of digital logic function circuit systems providing different digital logic functions; (c) An input circuit formed in the die adjacent to the electrostatic discharge circuit; (d) An output circuit is formed in the die between the input circuit and the multiple sets of digital logic function circuit systems; as well as (e) The electrostatic discharge circuit, the multiple digital logic function circuit system, the input circuit and the output circuit are not electrically connected to each other.

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