Electronic circuits and sensor systems

Abstract

The present invention provides an electronic circuit having characteristics that can satisfy output signal requirements and can reduce damage to the output circuit. Therefore, the electronic circuit includes: an output signal generating element (201, 202) that generates an output signal; a switch (203, 204); and a voltage monitoring circuit (205) that monitors the voltage applied to the output terminal (112). Here, the output signal generating element (201, 201) is connected to the output terminal (112) via the switch (203, 204), and the voltage monitoring circuit (205) is configured to measure a voltage higher than the power supply voltage (VDD) connected to the output signal generating element (201). When the voltage of the output terminal (112) is greater than a predetermined value set higher than the power supply voltage (VDD), the switch (203, 204) is controlled to disconnect the output signal generating element (201, 202) from the output terminal (112).

Description

Technical Field

[0001] The present invention relates to an electronic circuit and a sensor system, and for example, to a semiconductor electronic circuit for vehicle use and a sensor system using the semiconductor electronic circuit. Background Art

[0002] Patent Document 1 describes an output circuit comprising an output-stage transistor and a power supply short-circuit detection circuit that detects a high voltage exceeding the output voltage. Patent Document 1 states that when the power supply short-circuit detection circuit detects a high voltage, the output-stage transistor is controlled to a non-energized state. Furthermore, Patent Document 2 describes a semiconductor electronic circuit comprising an overvoltage protection circuit that, when the input voltage exceeds a predetermined value, disconnects a switch connected to an input terminal and outputs a voltage obtained by dividing the input voltage.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-60032

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2007-329998 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] Semiconductor electronic circuits equipped with output circuits that output signals detected by sensors and other devices are widely used. For example, vehicles such as automobiles are equipped with multiple sensors, and onboard semiconductor electronic circuits and ECUs (Engine Control Units) are supplied with the signals detected by the sensors. In-vehicle semiconductor electronic circuits have output circuits that output the signals detected by the sensors to the ECU via output wiring and other means.

[0009] When connected to an output circuit within a semiconductor electronic circuit, for example, an ECU, the output wiring connected to the output circuit may be mistakenly connected to other wiring, temporarily come into contact with power wiring that supplies voltage to other devices, or temporarily short-circuit with terminals of other devices. Due to such misconnections, a voltage higher than the power supply voltage supplied to the output circuit may be supplied to the output circuit through the output wiring, potentially damaging the output circuit.

[0010] On the other hand, in automotive semiconductor electronic circuits, the output circuits that output signals from sensors are sometimes subject to stringent waveform requirements. Specifically, for example, upper and lower limits may be set for the rise and fall times of the output signals, or benchmarks may be set for the electromagnetic radiation spectrum from the output wiring. Furthermore, if external noise is applied to the output circuit, noise immunity is also required. The output circuits within automotive semiconductor electronic circuits must meet these requirements as output circuits.

[0011] For example, in the output circuit described in Patent Document 1, when a high voltage is applied, the power supply short-circuit detection circuit detects the high voltage and turns the output transistor into a non-conducting state. This prevents damage to the output circuit. However, in Patent Document 1, the output transistor not only outputs a signal but also functions as a switch to prevent high voltage from being applied to the output circuit. Because high voltage is applied, the output transistor shown in Patent Document 1 is constructed with a high withstand voltage. Output transistors with a high withstand voltage structure have poorer current-voltage characteristics than output transistors with a low withstand voltage structure. In the output circuit of Patent Document 1, the output signal varies depending on whether the output transistor is conducting or non-conducting. Therefore, it is believed that a large current flows during the rise and fall of the output signal, and the output signal fluctuates until the current stabilizes, generating electromagnetic radiation noise and failing to meet the electromagnetic radiation spectrum standard. Furthermore, if noise is applied from the outside, it is believed that the output signal varies due to the noise.

[0012] Furthermore, Patent Document 2 does not describe or identify how to prevent the output circuit from being damaged when a high voltage is supplied to the output wiring of the output circuit.

[0013] An object of the present invention is to provide an electronic circuit and a sensor system having satisfactory output signal characteristics and capable of reducing damage to the output circuit.

[0014] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0015] Means for solving problems

[0016] Among the inventions disclosed in this application, the outline of representative inventions will be briefly described as follows.

[0017] An electronic circuit includes an element that generates an output signal, a switch, and a voltage monitoring circuit that monitors the voltage applied to an output terminal. The element is connected to the output terminal via the switch, and the voltage monitoring circuit is configured to measure a voltage higher than the voltage of a power supply connected to the element. When the voltage at the output terminal exceeds a predetermined value set higher than the voltage of the power supply, the switch is controlled to disconnect the element from the output terminal.

[0018] When the voltage at the output terminal exceeds a predetermined value, the connection between the element and the output terminal is disconnected, thereby preventing damage to the output circuit. Furthermore, the characteristics of the output signal can be determined by the characteristics of the element generating the output signal, thereby enabling the output signal characteristics to meet desired requirements.

[0019] Effects of the Invention

[0020] The effects obtained by the representative inventions among the inventions disclosed in this application will be briefly described as follows.

[0021] An electronic circuit and a sensor system can be provided that have satisfactory output signal characteristics and reduce the risk of damaged output circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a block diagram showing the configuration of the sensor system according to the first embodiment.

[0023] Figure 2 A circuit diagram showing the configuration of an output circuit according to the first embodiment.

[0024] Figure 3 3 is a characteristic diagram showing the DC characteristics of the output circuit according to the first embodiment.

[0025] Figure 4 This is a circuit diagram showing the configuration of an output circuit according to a modification of the first embodiment.

[0026] Figure 5 This is a circuit diagram showing the configuration of an output circuit according to the second embodiment.

[0027] Figure 6 This is a circuit diagram showing the configuration of an output circuit according to a third embodiment.

[0028] Figure 7 This is a cross-sectional view of an output circuit according to a third embodiment.

[0029] Figure 8 This is a circuit diagram showing the configuration of an output circuit according to a fourth embodiment.

[0030] Figure 9 This is a circuit diagram showing the configuration of an output circuit according to a fifth embodiment.

[0031] Figure 10 This is a circuit diagram showing the structure of an electronic circuit according to a sixth embodiment. DETAILED DESCRIPTION

[0032] In the following embodiments, for convenience, when necessary, they are divided into multiple parts or embodiments for description. However, except for cases where it is specifically stated, they are not unrelated to each other, but rather one is a modification, detail, supplementary explanation, etc. of part or all of the other. In addition, in the following embodiments, when the number of elements, etc. (including number, value, amount, range, etc.) is mentioned, except for cases where it is specifically stated or where it is clearly limited to a specific number in principle, it is not limited to the specific number and can be more than or less than the specific number.

[0033] Furthermore, in the following embodiments, the structural elements (including element steps, etc.) are not necessarily required, unless otherwise specified or clearly considered to be required in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of structural elements, etc., unless otherwise specified or clearly considered to be not required in principle, shapes similar to or similar to such shapes, etc. are substantially included. The same applies to the above-mentioned numerical values and ranges.

[0034] The circuit elements constituting each functional block of the embodiment are not particularly limited and can be formed on a semiconductor substrate such as single crystal silicon using well-known integrated circuit technologies such as CMOS (complementary MOS) transistors. The embodiments of the present invention are described in detail below with reference to the accompanying drawings. In principle, identical components are designated by the same reference numerals throughout the drawings used to illustrate the embodiments, and duplicate descriptions thereof are omitted.

[0035] (Implementation Method 1)

[0036] <Sensor system structure>

[0037] Figure 1 1 is a block diagram showing the configuration of a sensor system according to Embodiment 1. In the figure, reference numeral 100 denotes a sensor system. Here, a vehicle-mounted sensor system will be described as an example of the sensor system 100.

[0038] Sensor system 100 includes a sensor element 101, a semiconductor electronic circuit 102, and an ECU 107. Sensor element 101 is an element whose electrical characteristics change according to a physical quantity, and it outputs an electrical signal corresponding to the change in the detected object. For example, sensor element 101 is an airflow sensor that detects the amount of air inhaled by an engine. However, sensor element 101 is not limited to an airflow sensor; any sensor element can convert a physical quantity such as air flow, temperature, humidity, or pressure into an electrical signal and output it.

[0039] The semiconductor electronic circuit 102 has a plurality of circuit modules, but in this figure, as circuit modules, a power supply circuit 103, an analog circuit 104, a processor 105, and an output circuit 106 are exemplified. These circuit modules are formed on, for example, a single semiconductor chip. Figure 1 In FIG. 1 , numerals 111 to 114 denote terminals provided on the semiconductor electronic circuit 102 .

[0040] The semiconductor electronic circuit 102 primarily processes the electrical signal from the sensor element 101 and outputs the processing result via the output circuit 106 as a SENT (Single Edge Nibble Transmission) signal or a frequency-modulated output signal. Specifically, the analog circuit 104 performs amplification, filtering, analog-to-digital conversion, and digital-to-analog conversion on the electrical signal from the sensor element 101 supplied via terminal 114. The processor 105 processes digital data and controls peripheral circuits. The power supply circuit 103 generates an internal power supply voltage VDD from an external power supply voltage POWER supplied via power supply terminal 111 and distributes it to the analog circuit 104, processor 105, and output circuit 106. The output circuit 106 receives the processing results from the analog circuit 104 or processor 105 and outputs an output signal (e.g., a SENT signal) VOUT to the ECU 107 via output terminal 112 and output wiring 109. The ECU 107 performs processing based on the supplied output signal VOUT.

[0041] exist Figure 1In the figure, 10 represents a vehicle-mounted battery, and 11 represents a voltage converter. In addition, 12 represents other vehicle-mounted devices, such as an actuator that controls the engine. The battery voltage VBT from the battery 10 supplies power to multiple vehicle-mounted devices, but in this figure, the power supply to the sensor system 100 and the actuator 12 is described. That is, the battery voltage VBT supplies power to the voltage converter 11 and the actuator 12, etc. via the power supply wiring 13. The voltage converter 11 converts the supplied battery voltage VBT into an external power supply voltage POWER to supply power to the semiconductor electronic circuit 102. The battery voltage VBT is not particularly limited, but is approximately 12V. The voltage converter 11 steps down the battery voltage VBT to generate an external power supply voltage POWER of, for example, approximately 5V, although there is no particular limitation.

[0042] The power supply circuit 103 within the semiconductor electronic circuit 102 generates a stable 5V power supply voltage VDD from an external power supply voltage POWER of approximately 5V, although this is not particularly limited. Consequently, the 5V power supply voltage VDD is supplied to various circuit blocks within the semiconductor electronic circuit 102, such as the output circuit 106, and the blocks operate using this power supply voltage VDD as their operating voltage.

[0043] Furthermore, the ground voltage of the battery 10 and the voltage converter 11 is supplied as the ground GND to the ground terminal 113 of the semiconductor electronic circuit 102. Similarly, the ground voltage is also supplied to the ECU 107 and the actuator 12 as the ground GND.

[0044] When connecting the semiconductor electronic circuit 102, ECU 107, battery 10, voltage converter 11, and actuator 12 via wiring, if, for example, power supply wiring 13 is mistakenly connected to output terminal 112 of semiconductor electronic circuit 102, battery voltage VBT, which is higher than power supply voltage VDD supplied to output circuit 106, is supplied to terminal 112 and thus to output circuit 106. Furthermore, if output wiring 109, which is connected to output circuit 106 via output terminal 112, and power supply wiring 13 are temporarily short-circuited, the same high battery voltage VBT is supplied to output terminal 112 of output circuit 106 and to output circuit 106.

[0045] In the figure, reference numeral 108 denotes a power supply wiring line for supplying an external power supply voltage POWER, and reference numeral 110 denotes a power supply (ground GND) wiring line for supplying a ground GND.

[0046] Output circuit configuration

[0047] Figure 2This is a circuit diagram showing the configuration of an output circuit according to Embodiment 1. The output circuit 106 includes output signal generating elements 201 and 202 , switches 203 and 204 , a voltage monitoring circuit 205 , a backflow prevention element 206 , and an input unit 220 .

[0048] This specification describes an example in which output signal generating elements 201 and 202 and switches 203 and 204 are composed of field effect transistors (hereinafter referred to as MOS transistors). Output signal generating element 201 and switch 203 are composed of P-channel field effect transistors (hereinafter referred to as PMOS transistors), while output signal generating element 202 and switch 204 are composed of N-channel field effect transistors (hereinafter referred to as NMOS transistors).

[0049] Here, the method of indicating the PMOS transistors and NMOS transistors used in the following figures is explained in advance. In the figures, the gate electrode portion of the PMOS transistor is marked with a circle to distinguish it from the NMOS transistor. In addition, in the PMOS transistor and the NMOS transistor, the portion with a high-voltage withstand structure is indicated by a rectangular frame. For example, the gate electrode, source electrode, and drain electrode of the PMOS transistor serving as switch 203 are respectively indicated by rectangular frames, so the gate electrode, source electrode, and drain electrode of switch 203 are of a high-voltage withstand structure. Similarly, the gate electrode, source electrode, and drain electrode of the NMOS transistor serving as switch 204 are also indicated by rectangular frames, so the gate electrode, source electrode, and drain electrode of switch 204 are of a high-voltage withstand structure.

[0050] In contrast, the gate electrodes, source electrodes, and drain electrodes of the PMOS transistors and NMOS transistors serving as the output signal generating elements 201 and 202 are clearly indicated by lines, and therefore have a lower withstand voltage structure than the gate electrodes, source electrodes, and drain electrodes of the PMOS transistors and NMOS transistors serving as the switches 203 and 204. Regarding the high withstand voltage structure and the low withstand voltage structure, the terms "high withstand voltage structure" and "low withstand voltage structure" will be used later. Figure 7 An example will be described.

[0051] Return to Figure 2 , the output circuit 106 is further described.

[0052] One electrode of the output signal generating element 201 is connected to the power supply voltage VDD, and the other electrode is connected to one electrode of the switch 203, the other electrode of which is connected to the output terminal 112. Furthermore, one electrode of the output signal generating element 202 is connected to the ground GND, and the other electrode is connected to one electrode of the switch 204, the other electrode of which is connected to the output terminal 112. In other words, the output signal generating element 201 and the switch 203 are connected in series between the power supply voltage VDD and the output terminal 112, and the output signal generating element 202 and the switch 204 are connected in series between the ground GND and the output terminal 112. Looking at it from a different perspective, the source-drain paths of the MOS transistors that constitute the signal generating elements and the source-drain paths of the MOS transistors that constitute the switches are connected in series between the power supply voltage VDD or the ground GND and the output terminal 112.

[0053] Here, output signal generating elements 201 and 202 are not directly connected to output terminal 112 but are connected to output terminal 112 via switches 203 and 204. Therefore, when a voltage is supplied to output terminal 112, the supplied voltage is applied to the other terminal of each of switches 203 and 204.

[0054] Voltage monitoring circuit 205 is comprised of PMOS transistors 209 and 211, an NMOS transistor 212, resistors 207 and 210, and a low-voltage diode 208. The anode of low-voltage diode 208 is connected to ground GND, and the cathode is connected to output terminal 112 via resistor 207. One electrode of PMOS transistor 209 is connected to output terminal 112, and the other electrode is connected to ground GND via resistor 210. Furthermore, the gate electrode of PMOS transistor 209 is connected to the cathode of low-voltage diode 208. PMOS transistor 211 and NMOS transistor 212 are connected between power supply voltage VDD and ground GND to form an inverter. The input of the inverter formed by PMOS transistor 211 and NMOS transistor 212 is connected to the other electrode of PMOS transistor 209, and the output of the inverter is connected to the gate electrode of the NMOS transistor forming switch 204. Furthermore, the gate electrode of the PMOS transistor forming switch 203 is connected to the input of the inverter. The input and output of the inverter are control signals VCTLP and VCTLN output from the voltage monitoring circuit 205. The control signals VCTLP and VCTLN are the input and output of the inverter, and therefore are control signals with opposite phases to each other.

[0055] The gate electrodes of the PMOS transistor and the NMOS transistor constituting the output signal generating elements 201 and 202 are connected to the output of the input section 220. Figure 1The analog circuit 104 or the processor 105 shown is supplied with a signal to the input unit 220. The input unit 220 supplies a signal corresponding to the supplied signal to the gate electrodes of the PMOS transistor and the NMOS transistor constituting the output signal generating elements 201 and 202. As a result, the PMOS transistor and the NMOS transistor constituting the output signal generating elements 201 and 202 are complementary in a conductive state or a non-conductive state according to the signal supplied to the input unit 220.

[0056] The backgate electrodes of the NMOS transistors constituting the output signal generating element 202, the NMOS transistor constituting the switch 204, and the NMOS transistor 212 are connected to ground GND. Furthermore, the backgate electrode of the PMOS transistor 201 constituting the output signal generating element 201 is connected to the power supply voltage VDD. In contrast, the backgate electrodes of the PMOS transistors 209 and 211, which are identical P-channel transistors, and the PMOS transistor constituting the switch 203 are commonly connected to the cathode of the diode constituting the backflow prevention element 206. The anode of the diode constituting the backflow prevention element 206 is connected to the power supply voltage VDD.

[0057] In this figure, the dotted line diode PD represents a parasitic diode formed between the backgate electrode and one or the other electrode of the PMOS transistor. For example, when the voltage at output terminal 112 increases, parasitic diode PD formed between the other electrode and the backgate electrode of the PMOS transistor constituting switch 203 becomes forward biased, allowing current to flow through parasitic diode PD. However, the diode constituting backflow prevention element 206 becomes reverse biased, preventing reverse current from flowing from output terminal 112 to power supply voltage VDD.

[0058] <<Output Circuit Operation>>

[0059] Then, Figure 2 Here, the case where the power supply voltage VDD generated by the power supply circuit 103 is supplied to the output circuit 106 will be described. However, an external power supply voltage POWER may be supplied to the output circuit 106 instead of the power supply voltage VDD.

[0060] First, the voltage monitoring circuit 205 will be described. The voltage monitoring circuit 205 monitors the voltage at the output terminal 112. When the voltage at the output terminal 112 exceeds a predetermined threshold, the voltage monitoring circuit 205 renders switches 203 and 204 non-conductive via control signals VCTLN and VCTLP. Here, the threshold is set to a predetermined voltage VTH higher than the power supply voltage VDD. This allows the voltage monitoring circuit 205 to measure voltages higher than the power supply voltage VDD. When the voltage exceeds the predetermined voltage VTH higher than the power supply voltage VDD, the control signals VCTLN and VCTLP render switches 203 and 204 non-conductive. Furthermore, the PMOS transistors 209, 211, and 212 have gate, source, and drain electrodes with high-voltage withstand structures. Therefore, the voltage monitoring circuit 205 is configured to measure voltages exceeding the power supply voltage VDD.

[0061] Reference Figure 2 In the first embodiment, the breakdown voltage (dropout voltage) of the Zener diode 208 is used to form the threshold. That is, the voltage obtained by adding the breakdown voltage of the Zener diode 208 to the power supply voltage VDD is a predetermined voltage VTH higher than the power supply voltage VDD.

[0062] When the voltage at output terminal 112 is below power supply voltage VDD, that is, during normal operation, no voltage exceeding the breakdown voltage is supplied to Zener diode 208, which is connected between output terminal 112 and ground GND via resistor 207. Therefore, Zener diode 208 is non-conducting. As a result, the value of voltage VCHECK at the cathode of Zener diode 208 tracks the voltage at output terminal 112. Consequently, no potential difference is generated between the source and gate electrodes of PMOS transistor 209, which are one electrode. Consequently, PMOS transistor 209 is non-conducting. As a result, the voltage of control signal VCTLP is pulled down by resistor 210, reaching a low level, the same voltage as ground GND. The low level of control signal VCTLP is inverted by the inverter formed by PMOS transistor 211 and NMOS transistor 212, causing control signal VCTLN to reach a high level, the same voltage as power supply voltage VDD. Consequently, during normal operation, both switches 203 and 204 are conductive.

[0063] In contrast, during abnormal operation, such as when the voltage at output terminal 112 exceeds power supply voltage VDD, the voltage VCHECK at the cathode of Zener diode 208 also rises as the voltage at output terminal 112 rises. When voltage VCHECK exceeds the breakdown voltage of Zener diode 208, Zener diode 208 becomes conductive, and cathode voltage VCHCK remains substantially constant at the breakdown voltage of Zener diode 208. As the voltage at output terminal 112 further rises, the voltage difference between the voltage at output terminal 112 and voltage VCHECK increases. When the voltage difference between the voltage at output terminal 112 and voltage VCHECK exceeds the threshold voltage of PMOS transistor 209, PMOS transistor 209 transitions from a non-conductive state to a conductive state.

[0064] When PMOS transistor 209 is turned on, current flows through resistor 210, causing the voltage of control signal VCTLP to change from a low level to a high level. Meanwhile, the voltage of control signal VCTLN changes from a high level to a low level. As a result, both switches 203 and 204 change from a conducting state to a non-conducting state.

[0065] Thus, during abnormal operation, switches 203 and 204 are both non-conductive, electrically disconnecting output terminal 112 from output signal generating elements 201 and 202. Consequently, when a voltage exceeding power supply voltage VDD is supplied to output terminal 112, output signal generating elements 201 and 202 are prevented from being damaged, thereby preventing damage to output circuit 106. Furthermore, a large current can be prevented from flowing through power supply wiring supplied with power supply voltage VDD and ground GND via output signal generating elements 201 and 202, thereby preventing damage to output circuit 106 caused by, for example, heat generated by the large current flow.

[0066] On the other hand, during normal operation, as described above, the control signal VCTLP output from the voltage monitoring circuit 205 is at a low level, equivalent to the potential of ground GND, and the control signal VCTLN is at a high level, equivalent to the potential of the power supply voltage VDD. Consequently, switches 203 and 204 are in a low-impedance, conductive state, and the output signal generating elements 201 and 202 are electrically connected to the output terminal 112. As a result, the characteristics of the output signal VOUT output from the output terminal 112 are determined by the characteristics of the output signal generating elements 201 and 202. Specifically, the output signal generating element 201 functions as a current source on the source side relative to the load connected to the output terminal 112, while the output signal generating element 202 functions as a current source on the sink side relative to the load connected to the output terminal 112. The output signal generating elements 201 and 202 are controlled to be conductive or non-conductive by the input unit 220 , thereby operating as constant current sources, thereby varying the voltage of the output terminal 112 , ie, the output signal VOUT, by the constant current.

[0067] Furthermore, the parasitic diode PD is interposed between the electrode connected to the output terminal 112 and the back-gate electrode of the PMOS transistors 209 and 211, each of which has an electrode connected to the output terminal 112, and the PMOS transistor constituting the switch 203. During abnormal operation, a voltage higher than the power supply voltage VDD is supplied to the output terminal 112, causing the parasitic diode PD to be conductive, raising concerns about forward current flowing through the parasitic diode. In the first embodiment, a cathode-connected diode is connected to the cathode of the parasitic diode PD as a reverse current prevention element 206, between the back-gate electrodes of the PMOS transistors 209 and 211, and the PMOS transistor constituting the switch 203, and the power supply voltage VDD. This prevents reverse current from flowing from the output terminal 112 toward the power supply voltage VDD during abnormal operation.

[0068] Switches 203 and 204 are constructed with high-voltage components to withstand high voltages. For example, MOS transistors with a voltage resistance of 16V or higher are used for switches 203 and 204. On the other hand, output signal generating elements 201 and 202 have lower voltage resistance than switches 203 and 204, as their current-voltage characteristics determine the characteristics of output signal VOUT. For example, if the power supply voltage VDD is 5V, output signal generating elements 201 and 202 are constructed using MOSFET transistors with a voltage resistance of 7V.

[0069] Considering the rising and falling characteristics of the output signal VOUT, the constant current characteristics for suppressing electromagnetic radiation noise, and the low output impedance characteristics for counteracting various external noises, it is preferable to lower the threshold voltage of the MOS transistors that constitute output signal generating elements 201 and 202. Therefore, it is desirable to use low-voltage components, rather than high-voltage components, for output signal generating elements 201 and 202. When output signal generating elements 201 and 202 are formed from high-voltage components, the threshold voltage of the MOS transistors is high, resulting in poor current-voltage characteristics, high on-resistance, and a larger area. On the other hand, using low-voltage MOS transistors as output signal generating elements 201 and 202 ensures the output current characteristics and allows for a smaller area.

[0070] Figure 3 : is a characteristic diagram showing the DC characteristics of the output circuit of embodiment 1. Figure 3 2 shows the characteristics when the output signal generating element 201 is operated and the output signal VOUT is at a high level.

[0071] exist Figure 3 In the figure, the characteristic diagram on the upper side of the paper shows the relationship between the voltage of the output terminal 112 and the various voltages in the output circuit 106. In the upper characteristic diagram, the horizontal axis represents the voltage of the output terminal, and the vertical axis represents the voltage values of the control signals VCTLN, VCTLP, the voltage VCHECK, and the output voltage VOUT. In addition, the characteristic diagram on the lower side of the paper shows the relationship between the voltage of the output terminal 112 and the current 301 flowing through the output terminal 112. In the lower characteristic diagram, the horizontal axis represents the voltage of the output terminal, and the vertical axis represents the current value. On the vertical axis, currents lower than "0" represent currents flowing from the output circuit 106 to the output terminal 112, and currents higher than "0" represent currents flowing from the output terminal 112 to the output circuit 106.

[0072] When the voltage at output terminal 112 is lower than power supply voltage VDD, as shown in the upper characteristic diagram, control signal VCTLN is high and control signal VCTLP is low. As described above, switches 203 and 204 are in the on state. Within this range, current 301 flowing from output circuit 106 to output terminal 112 is generally determined by the characteristics of output signal generating element 201. In Embodiment 1, as shown in the lower characteristic diagram, within the low voltage range at output terminal 112, current 301 exhibits a substantially constant current characteristic, even when the voltage at output terminal 112 varies. In other words, within the low voltage range at output terminal 112, a constant current characteristic is achieved with low dependence on the output terminal voltage. This prevents large currents from flowing and causing fluctuations in output signal VOUT when output signal VOUT rises, thereby reducing the generation of electromagnetic radiation noise. Furthermore, the constant current characteristic reduces fluctuations in output signal VOUT due to external noise.

[0073] When the voltage at output terminal 112 is higher than the power supply voltage VDD and higher than the breakdown voltage of Zener diode 208—that is, when the voltage at output terminal 112 is higher than the voltage obtained by applying the breakdown voltage of Zener diode 208 to power supply voltage VDD—the voltage VCHECK at the cathode of Zener diode 208 approaches a constant voltage. As shown in the upper characteristic diagram, a voltage difference develops between voltage VCHECK and output voltage VOUT. This voltage difference increases as the voltage at output terminal 112 rises. When this voltage difference exceeds the threshold voltage of PMOS transistor 209, PMOS transistor 209 turns on, control signal VCTLN goes low, and control signal VCTLP goes high. In this diagram, the voltage when control signal VCTLP goes high is the predetermined voltage VTH. When control signal VCTLP goes high, switch 203 becomes non-conductive, electrically isolating output signal generating element 201 from output terminal 112. Therefore, the current flowing between the output terminal 112 and the power supply voltage VDD via the output signal generating element 201 is blocked.

[0074] While the description herein uses output signal generating element 201 as an example, the same applies when output signal generating element 202 is in operation. Switch 204 is rendered non-conductive by control signal VCTLN, thereby preventing damage to output circuit 106. Furthermore, when the voltage at output terminal 112 is lower than power supply voltage VDD, output signal generating element 202, like output signal generating element 201, exhibits a constant current characteristic. This reduces electromagnetic radiation noise and improves immunity to external radiation noise.

[0075] Thus, in the output circuit 106 of the first embodiment, even when a high voltage is applied to the output terminal 112, current can be prevented from flowing from the output terminal 112 toward the power supply voltage VDD or the ground GND, thereby protecting the output circuit 106 from the effects of the high voltage. Furthermore, the characteristics of the output signal VOUT are determined by the output signal generating elements 201 and 202, which are low-voltage elements with excellent current-voltage characteristics. Therefore, the characteristics of the output signal VOUT can be ensured.

[0076] In Embodiment 1, the predetermined voltage VTH that turns off switches 203 and 204 is determined by the breakdown voltage of Zener diode 208, the threshold voltage of PMOS transistor 209, and the resistance values of resistors 207 and 210. The predetermined voltage VTH is designed to be higher than the power supply voltage VDD and lower than the external voltage to be detected and disconnected. More specifically, a Zener diode 208 is used that has a breakdown voltage that is approximately lower than the threshold voltage of PMOS transistor 209 relative to the predetermined voltage VTH to be disconnected. Here, the breakdown voltage is determined by the device characteristics of Zener diode 208, independent of the voltage at output terminal 112. Therefore, the predetermined voltage VTH can be set to a voltage that is independent of the voltage at output terminal 112.

[0077] In the first embodiment, the output circuit 106 is described as being capable of outputting to both the sink side and the source side. However, the present invention is not limited thereto. For example, an output circuit may be configured to output to only one of the sink side and the source side. In this case, a switch may be provided on the side capable of outputting.

[0078] In addition, although a structure using a diode as the Zener diode 208 has been described, the present invention is not limited thereto. For example, the Zener diode may be formed by using a PN combination of MOS transistors. In addition, the structure of the voltage monitoring circuit 205 is not limited to Figure 2 The voltage monitoring circuit can measure voltages above the power supply voltage VDD, and any configuration is sufficient as long as it can control switches 203 and 204 using a predetermined voltage VTH determined to be above the power supply voltage VDD as a threshold. For example, a configuration is conceivable in which the voltage at the output terminal 112 is divided by a resistor to generate a voltage below the power supply voltage VDD, and the generated voltage is compared with a predetermined voltage using a comparator or the like to monitor the voltage at the output terminal 112.

[0079] Modifications

[0080] Figure 4This is a circuit diagram showing the configuration of an output circuit of a modified example of embodiment 1. In this modified example, output signal generating elements 201 and 202 are connected in series between a power supply voltage VDD and a ground GND, and a CMOS switch is connected between a connection node N40 connecting the output signal generating elements 201 and 202 and the output terminal 112. The CMOS switch is formed by connecting a switch 203 composed of a PMOS transistor and a switch 204 composed of an NMOS transistor in parallel. The PMOS transistor and the NMOS transistor that constitute the CMOS switch are connected in parallel. Figure 2 The PMOS transistors and NMOS transistors constituting the output signal generating elements 201 and 202 are also high-voltage MOS transistors. Figure 2 It is also a low-voltage MOS transistor.

[0081] and Figure 2 Similarly, switch 203 is controlled by control signal VCTLP, and switch 204 is controlled by control signal VCTLN. The back gate electrode of the PMOS transistor constituting switch 203 is connected to backflow prevention element 206, and the back gate electrode of the NMOS transistor constituting switch 204 is connected to ground GND.

[0082] When a voltage exceeding predetermined voltage VTH is supplied to output terminal 112, switches 203 and 204 are rendered non-conductive, disconnecting output signal generating elements 201 and 202 from output terminal 112. This prevents damage to output circuit 106. Furthermore, during normal operation, switches 203 and 204 are rendered conductive by control signals VCTLP and VCTLN. Consequently, the signal generated by output signal generating elements 201 and 202, which are comprised of low-voltage MOS transistors, is transmitted to output terminal 112 as output signal VOUT. Consequently, the characteristics of output signal VOUT are maintained during normal operation.

[0083] (Implementation Method 2)

[0084] Figure 5 This is a circuit diagram showing the configuration of an output circuit according to the second embodiment. Figure 5 and Figure 2 Similar, so the main differences are explained. Figure 5 In FIG, the backflow prevention element is composed of two PMOS transistors 401 and 402, and the PMOS transistors 401 and 402 are controlled by control signals VCTLP and VCTLN.

[0085] The back gate electrode of the PMOS transistor constituting switch 203 and the back gate electrodes of PMOS transistors 209, 211, 401, and 402 form a back gate electrode VBG. One electrode of PMOS transistor 401 is connected to power supply voltage VDD. Furthermore, the other electrode of PMOS transistor 401 is connected to one electrode of PMOS transistor 402, and the other electrode of PMOS transistor 402 is connected to output terminal 112. Furthermore, a control signal VCTLP is supplied from voltage monitoring circuit 206 to the gate electrode of PMOS transistor 401, and a control signal VCTLN is supplied from voltage monitoring circuit 206 to the gate electrode of PMOS transistor 402.

[0086] As described in Embodiment 1, voltage monitoring circuit 206 outputs a low-level control signal VCTLP and a high-level control signal VCTLN during normal operation. Therefore, during normal operation, PMOS transistor 401 is conductive, while PMOS transistor 402 is non-conductive. Consequently, the voltage at backgate electrode VBG is equal to power supply voltage VDD.

[0087] In contrast, during abnormal operation, that is, when a high voltage is detected to be supplied to the output terminal 112 by the voltage monitoring circuit 206 and the switches 203 and 204 are in a non-conducting state, the voltage monitoring circuit 206 outputs a high-level control signal VCTLP and a low-level control signal VCTLN. As a result, the PMOS transistor 401 is in a non-conducting state and the PMOS transistor 402 is in a conducting state. Therefore, the voltage of the back gate electrode VBG is equal to the voltage of the output terminal 112. At this time, the voltage V1 of one electrode (source electrode) of the PMOS transistor constituting the switch 203 is the voltage of the power supply voltage VDD even if it is high. Therefore, the voltage of the back gate electrode VBG becomes higher than the voltage of the source electrode, and therefore, the parasitic diode PD between the back gate electrode and the source electrode of the PMOS transistor constituting the switch 203 (see Figure 2 ) is in a non-conductive state, which can prevent current from flowing from the output electrode 112 through the back gate electrode VBG into the power supply voltage VDD.

[0088] By configuring the backflow prevention element with PMOS transistors 401 and 402 as in Embodiment 2, the backgate electrode VBG can be fixed to the power supply voltage VDD via PMOS transistor 401 during normal operation. This allows for a more stable voltage at the backgate electrode VBG compared to the case of using a diode for backflow prevention as in Embodiment 1. As a result, the noise tolerance of the output circuit 106 can be improved, ensuring stable operation. Furthermore, the PMOS transistors 401 and 402 for backflow prevention are controlled by the voltage monitoring circuit 205. Therefore, the characteristics of the output signal VOUT during normal operation can be maintained, while preventing damage when a high voltage is applied externally to the output terminal 112.

[0089] (Implementation 3)

[0090] Figure 6 1 is a circuit diagram showing the configuration of an output circuit according to a third embodiment. Figure 7 It is a cross-sectional view showing the structure of the output circuit according to the third embodiment. Figure 6 and Figure 2 The difference is that the high-voltage structure of the MOS transistor constituting the output circuit 106 is located in the Figure 6 In the middle becomes less.

[0091] In embodiment 1, as Figure 2 As shown in the middle rectangular box, PMOS transistors 209 and 211, NMOS transistor 212, the PMOS transistor constituting switch 203, and the NMOS transistor constituting switch 204 are composed of high-voltage components having a high-voltage component structure. Generally, high-voltage components have a large area and are therefore expensive. In the third embodiment, the output circuit 106 is described, which achieves a reduced area by minimizing the high-voltage component structure.

[0092] In the output circuit 106 of the third embodiment, as in the first embodiment, the PMOS transistors 509, 511, the NMOS transistor 512, the PMOS transistor constituting the switch 503, and the NMOS transistor constituting the switch 504 have a portion having a high withstand voltage structure. Figure 2 The PMOS transistors 209, 211, NMOS transistor 212, the PMOS transistor constituting the switch 203, and the NMOS transistor constituting the switch 204 described in the preceding text correspond to each other. The operations of the MOS transistors 509, 511, 512, the MOS transistor constituting the switch 503, and the MOS transistor constituting the switch 504 correspond to each other. Figure 2 The operations of the corresponding MOS transistors are the same as those described in , and therefore, detailed description of the operation of the output circuit 106 is omitted.

[0093] exist Figure 2 In the MOS transistor with high voltage resistance structure, even if Figure 6 Although the MOS transistor also has a high-voltage structure, the number of high-voltage structures in the MOS transistor is reduced. That is, in each MOS transistor, the gate electrode portion and one or the other of the pair of electrodes have a high-voltage structure, and the other or one of the pair of electrodes has a low-voltage structure.

[0094] Specifically, in PMOS transistor 509, only the gate electrode and the other electrode connected to resistor 210 have a high-voltage withstand structure. In PMOS transistor 511 and NMOS transistor 512, only the gate electrode and the electrode connected to each other have a high-voltage withstand structure. Furthermore, in the PMOS transistor constituting switch 503, only the gate electrode and the electrode connected to power supply voltage VDD via output signal generating element 201 have a high-voltage withstand structure. Furthermore, in the NMOS transistor constituting switch 504, only the gate electrode and the other electrode connected to output terminal 112 have a high-voltage withstand structure.

[0095] A MOS transistor has a pair of electrodes, and each electrode functions as either a source electrode S or a drain electrode D depending on the potential supplied to the electrodes. For example, in the case of a PMOS transistor, the electrode supplied with a high potential functions as the source electrode S, while the electrode supplied with a low potential functions as the drain electrode D. Therefore, when a high voltage, such as 16V, is applied to the output terminal 112, the other electrode of the PMOS transistor constituting the switch 503 functions as the source electrode S. The gate electrode G of this PMOS transistor has a maximum potential of 16V, and the back gate electrode B has a maximum potential of 16V. Furthermore, in this PMOS transistor, the potential of the electrode that functions as the drain electrode D is the same as the power supply voltage VDD, for example, 5V. Therefore, a large potential difference is applied between the drain electrode D and the other electrodes, requiring a high withstand voltage for the electrode portion that functions as the drain electrode D. However, if, for example, the potential difference applied between the gate electrode G and the source electrode S is small, the electrode portion that functions as the source electrode S does not require a high withstand voltage and can have a low withstand voltage structure.

[0096] In the case of the NMOS transistor constituting switch 504, when a high voltage is applied to output terminal 112, the other electrode connected to output terminal 112 functions as drain electrode D, and the electrode connected to ground GND via output signal generating element 202 functions as source electrode S. When a high voltage is applied to output terminal 112, switch 504 is rendered non-conductive by voltage monitoring circuit 505. Therefore, no high voltage is applied to source electrode S of the NMOS transistor constituting switch 504, and a voltage roughly in the range of power supply voltage VDD is supplied from ground GND. Furthermore, since the backgate electrode B of this NMOS transistor is fixed to ground GND, the withstand voltage between source electrode S and backgate electrode B can be low. Furthermore, the potential of the gate electrode G of this NMOS transistor is supplied with power supply voltage VDD during normal operation, but is supplied with a low-level control signal VCTLN when a high voltage is applied to output terminal 112. On the other hand, since the drain electrode D of this NMOS transistor is connected to output terminal 112, it can be supplied with a high voltage. Therefore, in the NMOS transistor constituting the switch 504 , a high withstand voltage is required between the other electrode functioning as the drain electrode D and other electrodes, but a high withstand voltage is not necessarily required between terminals other than the drain electrode D.

[0097] Thus, in Embodiment 3, in the PMOS transistor constituting switch 503, one electrode portion connected to the power supply voltage VDD side via the output signal generating element 201 is a high-voltage-resistant structure portion, while the other electrode portion connected to the output terminal 112 does not have a high-voltage-resistant structure. In other words, the other electrode portion has a low-voltage-resistant structure. Furthermore, in the NMOS transistor constituting switch 504, the other electrode portion connected to the output terminal 112 has a high-voltage-resistant structure, while the one electrode portion connected to the ground GND side via the output signal generating element 201 does not have a high-voltage-resistant structure. In other words, the one electrode portion has a low-voltage-resistant structure.

[0098] Similarly, in the PMOS transistor 509, the other electrode portion connected to the ground GND side via the resistor 210 has a high withstand voltage structure, and the one electrode portion connected to the output terminal 112 has a low withstand voltage structure. Furthermore, in the PMOS transistor 511 constituting the inverter, one electrode connected to the power supply voltage VDD side has a low withstand voltage structure, and the other electrode has a high withstand voltage structure. Furthermore, in the NMOS transistor 512 constituting the inverter, one electrode connected to the ground GND side has a low withstand voltage structure, and the other electrode has a high withstand voltage structure.

[0099] This can reduce the number of high-withstand-voltage structures, and thus reduce the area occupied by the output circuit 106 .

[0100] Next, the structure of the MOS transistors constituting the output circuit 106 will be described. Here, the MOS transistors constituting the switches 503 and 504 and the output signal generating elements 201 and 202 are taken as an example. Figure 7 In addition, Figure 7 In order to avoid complicating the drawings, a gate oxide film interposed between a gate electrode to be described later and the main surface of a semiconductor region, an interlayer film forming a contact layer, and the like are omitted.

[0101] exist Figure 7 In FIG, SB represents a semiconductor substrate (silicon substrate). Although not particularly limited, semiconductor substrate SB is P-type. N-type well regions NW503 and NW201 and a deep P-well region DPW are formed on the main surface of P-type semiconductor substrate SB.

[0102] In the N-type well NW503, a PMOS transistor is formed as the other electrode of the switch 503. + In addition, in the N-type well NW503, the P + The diffusion layer PDF503_2 is isolated to form a P-type well PW503_1. A P + The P-type diffusion layer PDF503_1 is formed in the N-type well NW503 and the P-type diffusion layer PDF503_1 is formed in the N-type well NW503. + The diffusion layer PDF503_1 of the type becomes one electrode of the PMOS transistor constituting the switch 503 .

[0103] When viewed from above, a gate electrode GE503 is disposed on the main surface of the N-type well NW503, between the one electrode and the other electrode of the PMOS transistor constituting the switch 503, via a gate oxide film. A field oxide film layer FOX503 is formed between the one electrode and the gate electrode GE503. Specifically, the field oxide film layer FOX503, which is thicker than the gate oxide film between the main surface of the N-type well 503 and the gate electrode GE503, is interposed between the one electrode and the gate electrode GE503. This structure increases the withstand voltage between the one electrode and the other electrode. In contrast, no field oxide film layer is interposed between the other electrode and the gate electrode 503, nor is a P-type well PW503_1 formed. Consequently, the withstand voltage of the other electrode portion is reduced. Specifically, the one electrode portion of the PMOS transistor constituting the switch 503 has a high withstand voltage structure, while the other electrode portion has a low withstand voltage structure.

[0104] In the N-type well region NW201, a PMOS transistor is formed. +The diffusion layer PDF201_1 and the P + The diffusion layer PDF201_2 of type. In addition, + A gate electrode GE201 is arranged between the diffusion layers PDF201_1 and PDF201_2 of the type φ201_1 and PDF201_2 via a gate oxide film.

[0105] P + Type of diffusion layer PDF503_1 and P + The diffusion layers PDF201_2 of the type are connected through the contact layer CT and the metal wiring layer ML. + The diffusion layer PDF201_1 is connected to the metal wiring layer supplied with the power supply voltage VDD via the contact layer CT (not shown). Figure 6 As shown by P + One electrode formed of the diffusion layer PDF201_1 of the type functions as a source electrode S of the PMOS transistor constituting the output signal generating element 201. Figure 6 As shown by P + The other electrode formed of the diffusion layer PDF201_2 of the type functions as a drain electrode D of the PMOS transistor constituting the output signal generating element 201 .

[0106] On the other hand, the P-type well PW503_1 and P + One electrode formed by the diffusion layer PDF503_1 of the type functions as the source S of the PMOS transistor constituting the switch 503 during normal operation. Figure 6 As shown, it functions as a drain electrode D. In addition, P + The other electrode formed by the diffusion layer PDF503_2 of the type functions as the drain electrode D of the PMOS transistor constituting the switch 503 during normal operation, and functions as the drain electrode D of the PMOS transistor constituting the switch 503 during abnormal operation. Figure 6 As shown, it functions as a source electrode S.

[0107] In addition, the back gate electrode B of the PMOS transistor constituting the switch 503 is formed by the N-type well NW503, and the back gate electrode B of the PMOS transistor constituting the switch 201 is formed by the N-type well NW201. Figure 6 As shown, each back gate electrode B is connected to the power supply voltage VDD and the backflow prevention element 206 .

[0108] The NMOS transistor constituting the switch 504 and the NMOS transistor constituting the output signal generating element 202 are formed in the deep P-type well region DPW.

[0109] An N-type well NW504_1 is formed in the deep P-type well region DPW, and an N-type diffusion layer NDF504_2 is formed within the N-type well NW504_1. Furthermore, the N-type diffusion layer NDF504_1 is formed separately from the N-type well NW504_1 within the deep P-type well region DPW. When viewed from above, a gate electrode GE504 is positioned between the N-type well NW504_1 and the N-type diffusion layer NDF504_1 via a gate oxide film. A field oxide film layer FOX504 is interposed between the gate electrode GE504, the N-type well NW504_1, and the N-type diffusion layer NDF504_2.

[0110] One electrode of the NMOS transistor constituting switch 504 is formed by an N-type diffusion layer NDF504_1, while the other electrode of the NMOS transistor constituting switch 504 is formed by an N-type well NW504_1 and an N-type diffusion layer NDF504_2. Furthermore, gate electrode GE504 serves as the gate electrode of the NMOS transistor constituting switch 504, and deep P-type well region DPW serves as the backgate electrode B of the NMOS transistor constituting switch 504 and the NMOS transistor constituting output signal generating element 202.

[0111] Thus, the other electrode of the NMOS transistor constituting switch 504 comprises an N-type well NW504_1 and an N-type diffusion layer NDF504_2, with a field oxide film FOX504 interposed between it and the gate electrode GE504. This provides the other electrode with a high withstand voltage structure, achieving a high withstand voltage. In contrast, one electrode of the NMOS transistor constituting switch 504 comprises an N-type diffusion layer NDF504_1, without a field oxide film FOX504 interposed between it and the gate electrode GE504. This provides the other electrode with a low withstand voltage structure.

[0112] The NMOS transistor constituting the output signal generating element 202 is formed in the deep P-type well region DPW. + One electrode of the NMOS transistor constituting the output signal generating element 202 is formed by the N-type diffusion layer NDF202_1 and NDF202_2, and the other electrode of the NMOS transistor is formed by the N-type diffusion layer NDF202_2.

[0113] The N-type diffusion layer NDF202_2 and the N-type diffusion layer NDF504_1 are connected via the contact layer CT and the metal wiring layer ML. In addition, the deep P-type well region DPW, which functions as the N-type diffusion layer NDF202_1 and the back gate electrode B, is connected to the metal wiring layer to which the ground GND is supplied via the contact layer CT (not shown). + The diffusion layer PDF503_2 is connected to the metal wiring layer ML_112 through the contact layer CT. Figure 6 The output terminals 112 are shown connected.

[0114] During normal operation and abnormal operation, one electrode of the NMOS transistor constituting the switch 504 and the output signal generating element 202 is Figure 6 As shown in FIG, one electrode functions as a source electrode S, and the other electrode functions as a drain electrode. Figure 7 As shown, one electrode portion and the other electrode portion constituting the output signal generating elements 201 and 202 , respectively, have a low withstand voltage structure.

[0115] Thus, in the PMOS transistor constituting the switch 503, one electrode that functions as the drain electrode D during abnormal operation has a high withstand voltage structure, and in the NMOS transistor constituting the switch 504, the other electrode that functions as the drain electrode D during abnormal operation has a high withstand voltage structure.

[0116] In the high-breakdown voltage structure, a field oxide film is interposed between the drain electrode D and the gate electrode, thereby improving the breakdown voltage between the gate electrode and the drain electrode D. Furthermore, the breakdown voltage between the drain electrode D and the back-gate electrode B is also increased because the P-type well PW503_1 and the N-type well NW504_1 are formed between the N-type well NW503 serving as the back-gate electrode B, the deep P-type well region DPW, and the diffusion layers PDF503_1 and NDF504_2 connected to the contact layer CT.

[0117] In contrast, in the low-voltage structure, no field oxide film is interposed between the source electrode S and the gate electrode. Therefore, the withstand voltage between the gate electrode and the source electrode S is lower than the withstand voltage between the gate electrode and the drain electrode in the high-voltage structure. In addition, no well is formed between the source electrode and the N-type well NN503 or deep P-type well region DPW, which serves as the back-gate electrode B. Therefore, the withstand voltage between the source electrode S and the back-gate electrode B is lower than the withstand voltage between the drain electrode and the back-gate electrode in the high-voltage structure.

[0118] The electrodes of the MOS transistors that comprise output signal generating elements 201 and 202 have a low withstand voltage structure. The electrodes that function as source electrodes during abnormal operation in the MOS transistors that comprise switches 503 and 504 also have a low withstand voltage structure. This allows switches 503 and 504 and output signal generating elements 201 and 202 to be formed in a small area while preventing damage during abnormal operation.

[0119] Furthermore, the N-type well NW503, which houses the PMOS transistor constituting the switch 503, and the N-type well NW201, which houses the PMOS transistor constituting the output signal generating element 201, are separated by a P-type semiconductor substrate SB. Consequently, the back-gate electrode B of the PMOS transistor constituting the output signal generating element 201 is connected to the power supply voltage VDD, and the back-gate electrode B of the PMOS transistor constituting the switch 503 can be connected to the back-current prevention element 206. By directly connecting the back-gate electrode B of the PMOS transistor constituting the output signal generating element 201 to the power supply voltage VDD, a stable output can be obtained from the output signal generating element 201. Furthermore, by connecting the back-gate electrode B of the PMOS transistor constituting the switch 503 to the back-current prevention element 206, a reverse current flow from the output terminal 112 to the power supply voltage VDD can be prevented during abnormal operation.

[0120] Similar to switches 503 and 504, PMOS transistors 509, 511, and NMOS transistor 512 constituting voltage monitoring circuit 505 also have high-voltage withstand voltage structures only for the electrodes to which high voltage is applied, while the other electrodes have low-voltage withstand voltage structures. This reduces the area occupied by output circuit 106.

[0121] (Implementation 4)

[0122] Figure 8 : is a circuit diagram showing the configuration of an output circuit according to Embodiment 4. In Embodiment 4, a specific example is provided in which the output signal from the output circuit 106 is represented as a constant current output by using an output signal generating element. Figure 8 and Figure 2 Similar, so the main differences are explained. Figure 8 , a PMOS transistor 601 and an NMOS transistor 602 connected to the output signal generating element and an added ESD (Electro Static Discharge) protection diode 603 are clearly shown.

[0123] PMOS transistor 601 has one electrode connected to power supply voltage VDD, a gate electrode connected to the gate electrode of the PMOS transistor constituting output signal element 201, another electrode connected to its own gate electrode, and a back-gate electrode connected to power supply voltage VDD. In this case, one electrode of PMOS transistor 601 functions as a source electrode, and the other electrode functions as a drain electrode. PMOS transistor 601 and the PMOS transistor constituting output signal element 201 form a current mirror circuit, operating so that a current proportional to the drain current flowing through PMOS transistor 601 flows through output signal element 201. The mirror ratio between the drain current flowing through PMOS transistor 601 and the current flowing through output signal generating element 201 is determined by the size ratio of PMOS transistor 601 to the size of the PMOS transistor 601.

[0124] NMOS transistor 602 has one electrode connected to ground GND, a gate electrode connected to the gate electrode of the NMOS transistor constituting output signal element 202, another electrode connected to its own gate electrode, and a back-gate electrode connected to ground GND. In this case, one electrode of NMOS transistor 602 functions as a source electrode, and the other electrode functions as a drain electrode. NMOS transistor 602 and the NMOS transistors constituting output signal element 202 form a current mirror circuit, operating so that a current proportional to the drain current flowing through NMOS transistor 602 flows through output signal element 202. In this case, the mirror ratio between the drain current and the current flowing through output signal generating element 202 is determined by the size ratio of NMOS transistor 602 to the size of the NMOS transistor constituting output signal generating element 202.

[0125] The input section 220_1 is coupled to the other electrode of the PMOS transistor 601 and the other electrode of the NMOS transistor 602, and receives the signal from the analog circuit 104 ( Figure 1 ) or processor 105 ( Figure 1 ) is supplied to the other electrode of the PMOS transistor 601 and the other electrode of the NMOS transistor 602. During normal operation, switches 203 and 204 are in an on state, and the other terminals of the PMOS transistors and NMOS transistors constituting the output signal generating elements 201 and 202 are connected to the output terminal 112 via the on-state switches 203 and 204. At this time, the on-resistance of the switches 203 and 204 is sufficiently small.

[0126] The output signal VOUT is composed of the current flowing through the output signal generating element 201 and the current flowing through the output signal generating element 202. In this case, the current flowing through the output signal generating element 201 is a source current for the load connected to the output terminal 112, and the current flowing through the output signal generating element 202 is a sink current for the load. A diode-connected PMOS transistor 601 is connected between the source and gate electrodes of the PMOS transistor constituting the output signal generating element 201, and a diode-connected NMOS transistor 602 is connected between the source and gate electrodes of the NMOS transistor constituting the output signal generating element 202. Therefore, the source and sink currents are constant currents, and the output signal VOUT is a constant current output.

[0127] The constant current output makes it easy to control the rise and fall times of the output signal VOUT, preventing output signal oscillation during the rise and fall periods of the output signal VOUT. Furthermore, by preventing abrupt rises and falls or oscillations, electromagnetic radiation noise can be reduced.

[0128] In addition, in Embodiment 4, an ESD protection diode 603 is connected between the output terminal 112 and ground GND. The ESD protection diode 603 is connected to the output terminal 112 to prevent damage to the output circuit 106 when, for example, a surge of several tens to several hundred volts is applied to the output terminal 112. The breakdown voltage of the ESD protection diode 603 is set to be higher than the predetermined voltage VTH at which the voltage monitoring circuit 205 activates and renders the switches 203 and 204 non-conductive. This ensures that the ESD protection diode 603 protects the output circuit 106 from high voltages applied to the output terminal 112 for a short period of time, such as pulse surges. However, if a high voltage, such as approximately 16 volts, is applied to the output terminal 112 for a relatively long period of time, the voltage monitoring circuit 205 opens the switches 203 and 204, protecting the output circuit 106.

[0129] exist Figure 8 , an example is shown in which both the output signal generating elements 201 and 202 constitute a current mirror circuit, but the present invention is not limited thereto, and either one of them may constitute a current mirror circuit and operate as a constant current source.

[0130] In addition, Figure 8 , the PMOS transistor 601 and the NMOS transistor 602 are shown to be located outside the input section 220_1, but the present invention is not limited thereto. That is, the PMOS transistor 601 and the NMOS transistor 602 may also be included in the input section 220_1.

[0131] (Implementation 5)

[0132] Figure 9 1 is a circuit diagram showing the configuration of an output circuit according to Embodiment 5. In Embodiment 5, a switch that disconnects the output signal generating element from the output terminal 112 during abnormal operation is formed of an NMOS transistor. Figure 9 and Figure 2 Similar, so the main differences are explained. Figure 9 In FIG. 1 , a switch 701 composed of an NMOS transistor is connected between the output signal generating element 201 and the output terminal 112 in place of the switch 201. An NMOS transistor 702 and a switch control circuit 703 are added.

[0133] The gate electrode of the NMOS transistor constituting the switch 701 is connected to the switch control circuit 703 and is connected to the ground GND via the NMOS transistor 702. Furthermore, the back gate electrode of the NMOS transistor constituting the switch 701 and the back gate electrode of the NMOS transistor 702 are connected to the ground GND. The gate electrode of the NMOS transistor 702 is connected to the gate electrodes of the PMOS transistor 211 and the NMOS transistor 212 constituting the inverter.

[0134] The switch control circuit 703 includes circuits such as a bootstrap circuit. During normal operation, the high level of the control signal VCTLP supplied to the switch 701 is set to a voltage higher than the power supply voltage VDD. More specifically, when the output signal generating element 201 is activated and outputs a high-level output signal VOUT, the switch control circuit 703 sets the control signal VCTLP to a high level. However, the switch control circuit 703 uses the same high-level control signal VCTLP to increase the potential of the control signal VCTLP to a level higher than the power supply voltage VDD. Alternatively, the switch control circuit 703 may include a charge pump circuit to generate a voltage higher than the power supply voltage VDD and supply the generated high voltage to the switch 701 as the control signal VCTLP. Since a voltage higher than the power supply voltage VDD is supplied to the gate electrode as the control signal VCTLP, the on-resistance of the NMOS transistor constituting the switch 701 can be sufficiently reduced.

[0135] On the other hand, when a high voltage is applied to output terminal 112, in voltage monitoring circuit 705, as described in Embodiment 1, PMOS transistor 209 is turned on, and NMOS transistor 702 is turned on. When NMOS transistor 702 is turned on, the gate electrode of the NMOS transistor constituting switch 701 is connected to ground GND via NMOS transistor 702, and switch 701 is turned off. This allows current to be blocked when a high voltage is applied to output terminal 112, preventing damage to output circuit 106. Furthermore, by being connected to the back gate GND of switch 701, current can be prevented from flowing backward from output terminal 112 to power supply voltage VDD via the back gate electrode of switch 701.

[0136] In Embodiment 5, an NMOS transistor is also used for the source-side switch 701, which functions as a source relative to the load. Generally, NMOS transistors have lower on-resistance than PMOS transistors, allowing switch 701 to be mounted in a smaller area. Furthermore, since NMOS transistors inherently prevent backflow, additional backflow prevention components are not required, enabling a smaller area.

[0137] (Implementation 6)

[0138] Figure 10 1 is a circuit diagram showing the configuration of an electronic circuit according to Embodiment 6. In Embodiment 6, an input circuit 800 using the voltage monitoring circuit 205 is provided. The input circuit 800 according to Embodiment 6 is provided at Figure 1 The semiconductor electronic circuit 102 is shown.

[0139] exist Figure 10 In FIG. 1 , 804 represents an input terminal provided in the semiconductor electronic circuit 102. The input signal VIN supplied to the input terminal 804 is supplied to the input circuit 800. The input circuit 800 is composed of the switch 203, the voltage monitoring circuit 205, the resistor 801, the NMOS transistor 802, and the PMOS transistor 803. The input signal VIN is supplied to the input signal processing module (not shown) via the inverter composed of the PMOS transistor 803 and the NMOS transistor 802.

[0140] One electrode of the PMOS transistor 203 is connected to the power supply voltage VDD via the resistor 801, and the other electrode is connected to the input terminal 804. In addition, the back gate electrode of the PMOS transistor 203 is connected to the cathode of the diode constituting the backflow prevention element 206, and the control signal VCTLP is supplied to the gate electrode from the voltage monitoring circuit 205. The voltage monitoring circuit 205 is composed of an NMOS transistor 209, a Zener diode 208, and resistors 207 and 210. The voltage monitoring circuit 205 is connected to the cathode of the diode constituting the backflow prevention element 206. Figure 2The voltage monitoring circuit shown in the figure does not include the structure of the inverter composed of the PMOS transistor 211 and the NMOS transistor 212. The operation of the NMOS transistor 209, the Zener diode 208, and the resistors 207 and 210 is similar to that of the Figure 2 The actions described are the same, so the description of the actions is omitted.

[0141] Although not particularly limited, an NMOS transistor 805 (dashed line) is provided outside the semiconductor electronic circuit 102, connected between the input terminal 804 and the ground GND. The NMOS transistor 805 is switched on / off by a signal supplied to its gate electrode, thereby supplying the input signal VIN to the input terminal 804. In other words, the NMOS transistor 805 is a MOS transistor that receives signals through an open drain. Since the signal is input through an open drain, during normal operation, the input terminal 804 is pulled up to the power supply voltage VDD via the resistor 801.

[0142] For example, when the switch 203 is not connected between the input terminal 804 and the power supply voltage VDD, if a voltage higher than the voltage assumed to be the input signal is applied to the input terminal 804, current flows from the input terminal 804 to the power supply voltage VDD via the resistor 801, and there is a concern that the input circuit 800 may be damaged.

[0143] In Embodiment 6, when a voltage higher than the assumed voltage is supplied to input terminal 804, voltage monitoring circuit 205 detects this and renders switch 203 non-conductive. This prevents current from flowing from input terminal 804 to power supply voltage VDD via pull-up resistor 801. This prevents current from flowing backward due to external high voltage and damaging the input circuit. Furthermore, since the pull-up is performed by resistor 801, a near-linear pull-up characteristic can be achieved.

[0144] <Note>

[0145] This specification discloses a plurality of inventions, some of which are described in the technical claims, but other inventions are also disclosed, and representative ones are listed below.

[0146] (A) The electronic circuit according to claim 8, wherein

[0147] The gate terminal of the high-voltage NMOS transistor is controlled by the switch control circuit to be higher than the voltage of the power supply.

[0148] (B) The electronic circuit according to claim 14, wherein

[0149] The electronic circuit has a protection diode connected to the output terminal,

[0150] A breakdown voltage of the protection diode is higher than the predetermined value set by the voltage monitoring circuit.

[0151] (C) The sensor system according to claim 16, characterized in that

[0152] The signal output by the output circuit is a frequency modulated signal.

[0153] As mentioned above, the invention completed by the present inventors has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

[0154] Description of Reference Numerals

[0155] 100 sensor system

[0156] 101 sensor element

[0157] 102 Semiconductor Electronic Circuits

[0158] 106 Output Circuit

[0159] 107 ECU

[0160] 112 output terminals

[0161] 201, 202 output signal generating elements

[0162] 203, 204, 503, 504, 701 switches

[0163] 205 Voltage Monitoring Circuit

[0164] 206 Anti-backflow element

[0165] 207, 210 resistors

[0166] 208 Zener diode

[0167] 209, 211, 401, 402, 511, 601, 803 PMOS transistors

[0168] 212, 512, 602, 802, 805 NMOS transistors

[0169] 220, 220_1 Input section

[0170] 603 ESD protection diode.

Claims

1. An electronic circuit, characterized in that have: an element connected to a power source and generating an output signal; switch; a backflow prevention element for preventing current from flowing from the output terminal to the power supply when a voltage higher than the voltage of the power supply is applied to the output terminal, one end of the element being connected to the power supply and the other end being connected to the switch; as well as A voltage monitoring circuit monitors the voltage applied to the output terminal. The voltage monitoring circuit is configured to detect a voltage higher than the voltage of the power supply, and to control the switch to disconnect the element from the output terminal when the voltage of the output terminal is equal to or higher than a predetermined value set higher than the voltage of the power supply. The element is connected to the output terminal via the switch, The withstand voltage of the element generating the output signal is lower than the withstand voltage of the element constituting the switch, The voltage monitoring circuit includes a first PMOS transistor, a second PMOS transistor, an NMOS transistor, a first resistor, a second resistor, and a low-voltage diode. The anode of the low-voltage diode is grounded, and the cathode is connected to the output terminal via the first resistor. One electrode of the first PMOS transistor is connected to the output terminal, and the other electrode is grounded via the second resistor. The gate electrode of the first PMOS transistor is connected to the cathode of the low-voltage diode. The second PMOS transistor and the NMOS transistor are connected between the power supply and ground to form an inverter. The input of the inverter is connected to the other electrode of the first PMOS transistor and to the gate electrode of the PMOS transistor forming the switch. The output of the inverter is connected to the gate electrode of the NMOS transistor forming the switch. The predetermined value is set based on characteristics of the diode that do not depend on a voltage applied to the output terminal.

2. The electronic circuit according to claim 1, wherein: The element generating the output signal comprises a first element and a second element, The first element is connected to the power supply, and the second element is grounded.

3. The electronic circuit according to claim 2, wherein: The first element is formed of a PMOS transistor, and the second element is formed of an NMOS transistor.

4. The electronic circuit according to claim 3, wherein: The first element has a back gate terminal connected to the power supply.

5. The electronic circuit according to claim 3, wherein: At least one of the first element and the second element is a current source and is formed of a current mirror circuit.

6. The electronic circuit according to claim 3, wherein: The electronic circuit further comprises: a switch control circuit, which controls the switch, The switch has a high-voltage NMOS transistor, The high-voltage NMOS transistor is connected to the output terminal and the first element.

7. The electronic circuit according to claim 1, wherein: The switch includes a first high-voltage PMOS transistor and a first high-voltage NMOS transistor. The first high-withstand-voltage PMOS transistor includes a back-gate terminal connected to the power supply via the backflow prevention element.

8. The electronic circuit according to claim 7, wherein: The backflow prevention element includes a second high withstand voltage PMOS transistor whose gate voltage is controlled by the voltage monitoring circuit. When the voltage of the output terminal is equal to or higher than the predetermined value set higher than the voltage of the power supply, the voltage monitoring circuit controls the second high withstand voltage PMOS transistor to be turned off.

9. The electronic circuit according to claim 7, wherein: The first high withstand voltage PMOS transistor has one electrode connected to the power supply via the element and another electrode connected to the output terminal. A withstand voltage between the other electrode and the gate electrode of the first high withstand voltage PMOS transistor is lower than a withstand voltage between the one electrode and the gate electrode.

10. A sensor system, have: a sensor element that outputs an electrical signal corresponding to a change in a detection object; and an electronic circuit that processes the electrical signal and outputs the result of the processing via an output circuit, The sensor system is characterized in that The output circuit has: an element connected to a power source and generating an output signal; switch; a backflow prevention element for preventing current from flowing from the output terminal to the power supply when a voltage higher than the voltage of the power supply is applied to the output terminal, one end of the element being connected to the power supply and the other end being connected to the switch; as well as a voltage monitoring circuit that monitors a voltage applied to an output terminal, the voltage monitoring circuit being configured to measure a voltage higher than the voltage of the power supply, and When the voltage of the output terminal is equal to or higher than a predetermined value set higher than the voltage of the power supply, the switch is controlled to disconnect the element from the output terminal. The element is connected to the output terminal via the switch, The withstand voltage of the element is lower than the withstand voltage of the elements constituting the switch, The voltage monitoring circuit includes a first PMOS transistor, a second PMOS transistor, an NMOS transistor, a first resistor, a second resistor, and a low-voltage diode. The anode of the low-voltage diode is grounded, and the cathode is connected to the output terminal via the first resistor. One electrode of the first PMOS transistor is connected to the output terminal, and the other electrode is grounded via the second resistor. The gate electrode of the first PMOS transistor is connected to the cathode of the low-voltage diode. The second PMOS transistor and the NMOS transistor are connected between the power supply and ground to form an inverter. The input of the inverter is connected to the other electrode of the first PMOS transistor and to the gate electrode of the PMOS transistor forming the switch. The output of the inverter is connected to the gate electrode of the NMOS transistor forming the switch. The predetermined value is set based on characteristics of the diode that do not depend on a voltage applied to the output terminal.

11. The sensor system according to claim 10, characterized in that The signal output by the output circuit is a SENT signal.

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