Display substrate and display panel

Abstract

An embodiment of the present disclosure provides a display substrate. The display substrate includes: a base substrate; a display area and a peripheral area outside the display area arranged on the base substrate, a virtual pixel unit and a virtual data line are arranged in the peripheral area, the virtual pixel unit includes a thin film transistor, the thin film transistor includes a first electrode and a second electrode, the first electrode is one of the source and the drain, the second electrode is the other of the source and the drain, the first electrode is electrically connected to the virtual data line, and the second electrode has a first part and a second part separated by a break. An embodiment of the present disclosure also provides a display panel including the above-mentioned display substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display, and in particular to a display substrate and a display panel. Background Art

[0002] In the design of thin film transistor liquid crystal display panels (TFT-LCD), the process environment of TFT devices around the display area is different from that of TFT devices in the middle of the display area, which may cause uneven display. For this reason, in practice, if the frame size space allows, a certain number of dummy pixels (Dummy Pixel) will be designed around the display area. Summary of the invention

[0003] An embodiment of the present disclosure provides a display substrate, comprising: a base substrate; a display area and a peripheral area outside the display area arranged on the base substrate, wherein a virtual pixel unit and a virtual data line are arranged in the peripheral area, the virtual pixel unit comprises a thin film transistor, the thin film transistor comprises a first electrode and a second electrode, the first electrode is one of a source and a drain, the second electrode is the other of the source and the drain, the first electrode is electrically connected to the virtual data line, and the second electrode has a first portion and a second portion separated by a first break.

[0004] In some embodiments, the virtual pixel unit also includes a pixel electrode, the second portion of the second electrode is electrically connected to the pixel electrode, the thin film transistor also includes an active layer and a gate, and in the same thin film transistor, the orthographic projection of the gate on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate, and at least partially overlaps with the orthographic projection of the first portion of the second electrode on the substrate.

[0005] In some embodiments, in the same thin film transistor, the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the first part of the second electrode on the substrate, and does not overlap with the orthographic projection of the second part of the second electrode on the substrate, and the orthographic projection of the first fracture on the substrate does not overlap with the orthographic projection of the active layer on the substrate, and does not overlap with the orthographic projection of the gate on the substrate.

[0006] In some embodiments, in the same thin film transistor, the orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the first portion of the second electrode on the substrate, and at least partially overlaps with the orthographic projection of the second portion of the second electrode on the substrate, and the orthographic projection of the first fracture on the substrate falls within the orthographic projection of the active layer on the substrate and the orthographic projection of the gate on the substrate.

[0007] In some embodiments, in the same thin film transistor, an orthographic projection of an edge of a first portion of the second electrode close to the first break on the substrate is flush with an edge of an orthographic projection of the gate on the substrate.

[0008] In some embodiments, in the same thin film transistor, an orthographic projection of the gate on the substrate completely covers an orthographic projection of the first portion of the second electrode on the substrate.

[0009] In some embodiments, in the same thin film transistor, an orthographic projection of the gate on the substrate partially overlaps with an orthographic projection of the second portion of the second electrode on the substrate.

[0010] In some embodiments, the second electrode also has a third part, the second part and the third part are separated by a second break, the orthographic projection of each of the first break and the second break on the substrate does not overlap with the orthographic projection of the gate on the substrate and does not overlap with the orthographic projection of the active layer on the substrate, the orthographic projection of at least one of the first part and the third part of the second electrode on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate and also at least partially overlaps with the orthographic projection of the active layer on the substrate, and the second part of the second electrode is electrically connected to the pixel electrode through a first via structure.

[0011] In some embodiments, the display substrate also includes a common electrode, wherein an electrode extension layer is further provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, the electrode extension layer and the first electrode, the second electrode and the virtual data line are arranged in the same layer with the same material, and the electrode extension layer is electrically connected to the virtual data line.

[0012] In some embodiments, both ends of the same virtual data line are electrically connected to the electrode extension layer to form a conductive loop passing through the same virtual data line and the electrode extension layer.

[0013] In some embodiments, the display substrate also includes a common electrode and a connecting layer, wherein an electrode extension layer is further provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, the connecting layer and the pixel electrode are made of the same material and are provided in the same layer, the connecting layer is electrically connected to the common electrode through a second via structure, and is electrically connected to the electrode extension layer through a third via structure.

[0014] In some embodiments, the common electrode includes a first common electrode extension portion and a second common electrode extension portion connected to each other, the extension direction of the first common electrode extension portion and the extension direction of the second common electrode extension portion intersect with each other, the orthographic projection of the connecting layer on the base substrate at least partially overlaps with the orthographic projection of the second common electrode extension portion on the base substrate, and the orthographic projection of the first common electrode extension portion on the base substrate at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate.

[0015] In some embodiments, the display substrate further includes a common electrode and a gate line, wherein an electrode extension layer is further provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, the electrode extension layer and the first electrode, the second electrode and the virtual data line are arranged in the same layer with the same material, the gate line and the gate are arranged in the same layer with the same material, and the orthographic projection of the gate line on the base substrate has an overlapping area with the orthographic projection of the electrode extension layer on the base substrate.

[0016] In some embodiments, the electrode extension layer includes a hollow region, and an orthographic projection of the hollow region on the base substrate at least partially overlaps with an orthographic projection of the gate line on the base substrate.

[0017] An embodiment of the present disclosure further provides a display panel, comprising the display substrate as described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0019] Figure 1A A schematic diagram showing a display substrate according to an embodiment of the present disclosure;

[0020] Figure 1B Show Figure 1A The local schematic diagram in the dashed box P in FIG.

[0021] Figure 2 A schematic diagram showing the structure of a thin film transistor in a display area of ​​a display substrate according to an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram showing the structure of a virtual thin film transistor in a peripheral area of ​​a display substrate according to some embodiments of the present disclosure;

[0023] Figure 4 A schematic diagram showing the structure of a virtual thin film transistor in a peripheral area of ​​a display substrate according to other embodiments of the present disclosure;

[0024] Figure 5 A schematic diagram showing the structure of a virtual thin film transistor in a peripheral area of ​​a display substrate according to some other embodiments of the present disclosure;

[0025] Figure 6 A schematic diagram showing a partial structure of a peripheral area in a display substrate according to some further embodiments of the present disclosure;

[0026] Figure 7 Show Figure 6 A cross-sectional view taken along line AA;

[0027] Figure 8 Show Figure 6 A cross-sectional view taken along line BB in FIG.

[0028] Fig. 9 Show Figure 6 A cross-sectional view taken along line CC. DETAILED DESCRIPTION

[0029] In order to more clearly explain the purpose, technical solutions and advantages of the present disclosure, the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be understood that the following description of the embodiments is intended to explain and illustrate the overall concept of the present disclosure and should not be understood as a limitation of the present disclosure. In the specification and the drawings, the same or similar reference numerals refer to the same or similar parts or components. For the sake of clarity, the drawings are not necessarily drawn to scale, and some well-known parts and structures may be omitted in the drawings.

[0030] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The wording "one" or "an" does not exclude multiple. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top" or "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. When an element such as a layer, a film, a region or a substrate substrate is referred to as being "on" or "under" another element, the element may be "directly" located "on" or "under" another element, or there may be an intermediate element.

[0031] An embodiment of the present disclosure provides a display substrate 100 . Figure 1A 1 shows a schematic plan view of the display substrate 100. Figure 1A A display area 20 and a peripheral area 30 are shown in FIG. Figure 1B Shows Figure 1A The local details in the lower right dashed box are Figure 1B In the figure, for the sake of clarity, the boundary between the display area 20 and the peripheral area 30 is indicated by a dotted line. The display substrate 100 comprises: a base substrate 10 (see Figures 7 to 9 sectional view) and a display area 20 and a peripheral area 30 arranged on the substrate 10. The peripheral area 30 is arranged at the periphery of the display area 20. The display area 20 is used to display images, for example, a plurality of pixel units 21 and structures such as data lines and gate lines may be arranged. The peripheral area 30 is not used to display images, but may be used, for example, to lay out wiring. Virtual pixel units 31 and virtual data lines 32 may be arranged in the peripheral area 30. The virtual pixel units 31 and the virtual data lines 32 are similar in structure to the pixel units 21 and the data lines 22 in the display area 20, which helps to provide a pixel unit 21 in the display area 20 close to the peripheral area 30 with an environment similar to that of the pixel unit 21 in the display area 20 far from the peripheral area 30. The virtual pixel unit 31 may include a thin film transistor 40.

[0032] Due to image size limitations, Figure 1A and Figure 1B The specific structures of the thin film transistor 40' in the display area 20 and the thin film transistor 40 in the peripheral area 30 are not shown. Examples of their specific structures can be found in Figures 2 to 6 .

[0033] like Figures 3 to 5 As shown, the thin film transistor 40 may include a first electrode 41 and a second electrode 42, the first electrode 41 is electrically connected to the virtual data line 32, and the second electrode 42 has a first portion 421 and a second portion 422 separated by a break (in order to distinguish it from the subsequent embodiments, it may be referred to as the first break 43 herein). In the following example, the case where the first electrode 41 is a source and the second electrode 42 is a drain is taken as an example. However, it should be understood by those skilled in the art that the embodiments of the present disclosure are not limited thereto, for example, the first electrode 41 may also be a drain and the second electrode 42 may be a source. In addition to the first electrode 41 and the second electrode 42 (one of the first electrode 41 and the second electrode 42 is a source and the other is a drain), the thin film transistor 40 may also include an active layer 44 and a gate 45, and the gate 45 is electrically connected to the gate line 52.

[0034] In the embodiment of the present disclosure, the source or drain of the thin film transistor 40 in the virtual pixel unit 31 is disconnected by a break. In this case, even if the virtual data line 32 inputs a signal, the thin film transistor 40 cannot connect the virtual data line 32 to the pixel electrode 51, so the load of the gate line 52 electrically connected to the gate 45 of the thin film transistor 40 can be reduced. This can not only reduce the power consumption caused by the virtual pixel unit 31, but also help to improve the uniformity of brightness. As mentioned above, the virtual pixel unit 31 and the virtual data line 32 are to ensure that the pixel unit 21 close to the peripheral area 30 in the display area 20 has a similar process environment to the pixel unit 21 far from the peripheral area 30 in the display area 20, without realizing a specific image display function. Therefore, in the case where the source or drain of the thin film transistor 40 is disconnected by a break (such as the first break 43), the virtual data line 32 is also disconnected from the virtual pixel unit 31, so that the virtual data line 32 can also be used to realize some independent functions, such as conducting test signals, connecting common electrodes, etc. In the embodiment of the present disclosure, the gate line 52 may be electrically connected to the gate 45 of the corresponding thin film transistor 40 , and the orthographic projection of the gate line 52 on the base substrate 10 may also intersect with the orthographic projection of the virtual data line 32 on the base substrate 10 .

[0035] Moreover, the disconnection of the source or drain of the thin film transistor 40 is achieved only through a fracture (such as the first fracture 43), which has little effect on the overall layer structure layout of the virtual pixel unit 31, so that the virtual pixel unit 31 has a high degree of similarity with the pixel unit 21 in the display area 20 in terms of layer structure, thereby achieving the purpose of providing a similar process environment for each pixel unit 21 in the display area 20. This is beneficial for maintaining the uniformity of the display brightness of the display area 20.

[0036] Figure 2 An example of a thin film transistor 40' in a pixel unit 21 in a display area 20 is shown. As shown in the figure, in the thin film transistor 40', the first electrode 41' is electrically connected to the data line 22, and the second electrode 42' is complete and does not include a break. In contrast, Figures 3 to 5 Three examples of thin film transistors 40 in the virtual pixel unit 31 in the peripheral area 30 are shown respectively. In these three examples, the first electrode 41 is electrically connected to the virtual data line 32, but the positions of the first break 43 are different. Figure 3 The examples shown and Figure 4 In the example shown, the orthographic projection of the first break 43 on the substrate does not overlap with the orthographic projection of the gate 45 on the substrate 10 and does not overlap with the orthographic projection of the active layer 44 on the substrate 10. Figure 3In the example shown, a portion of the orthographic projection of the first portion 421 of the second electrode 42 on the substrate 10 falls within the orthographic projection of the gate 45 on the substrate 10, while another portion extends beyond the orthographic projection of the gate 45 on the substrate 10. Figure 4 In the example shown, the orthographic projection of the first portion 421 of the second electrode 42 on the substrate 10 completely falls within the orthographic projection of the gate 45 on the substrate 10. Figure 5 In the example shown, the orthographic projection of the first fracture 43 on the substrate 10 falls within the orthographic projection of the gate 45 on the substrate 10 and the orthographic projection of the active layer 44 on the substrate 10, and the orthographic projection of a part of the second part 422 of the second electrode 42 on the substrate 10 falls within the orthographic projection of the gate 45 on the substrate 10 and the orthographic projection of the active layer 44 on the substrate 10.

[0037] In the embodiment of the present disclosure, when the orthographic projection of the first break 43 on the substrate 10 falls into the orthographic projection of the gate 45 on the substrate 10 and the orthographic projection of the active layer 44 on the substrate 10, a part of the second portion 422 of the second electrode 42 may overlap with the gate 45 and the active layer 44 to a certain extent. Compared with the case where the orthographic projection of the first break 43 on the substrate 10 falls outside the orthographic projection of the gate 45 and the active layer 44 on the substrate 10, this case may make the load of the gate line 52 greater. Therefore, the example in which the orthographic projection of the first break 43 on the substrate 10 falls outside the orthographic projection of the gate 45 and the active layer 44 on the substrate 10 is more advantageous. In addition, it is desired that the width of the first break 43 is as narrow as possible, so that the structure of the virtual pixel unit 31 can be as similar as possible to the structure of the pixel unit 21 in the display area 20. This is helpful for reducing the load and improving the display uniformity.

[0038] In some embodiments, in the same thin film transistor, such as Figures 3 to 6 As shown, the orthographic projection of the gate 45 on the substrate 10 at least partially (partially or completely) overlaps with the orthographic projection of the active layer 44 on the substrate 10, and also at least partially (partially or completely) overlaps with the orthographic projection of the first part 421 of the second electrode 42 on the substrate 10.

[0039] In some other embodiments, in the same thin film transistor, such as Figure 3 and Figure 4 As shown, the orthographic projection of the active layer 44 on the base substrate 10 at least partially (partially or completely) overlaps with the orthographic projection of the first part 421 of the second electrode 42 on the base substrate 10, and does not overlap with the orthographic projection of the second part 422 of the second electrode 42 on the base substrate 10.

[0040] In some embodiments, in the same thin film transistor, such as Figure 5 As shown, the orthographic projection of the active layer 44 on the base substrate 10 at least partially (partially or completely) overlaps with the orthographic projection of the first part 421 of the second electrode 42 on the base substrate 10, and at least partially (partially or completely) overlaps with the orthographic projection of the second part 422 of the second electrode 42 on the base substrate 10.

[0041] In some embodiments, in the same thin film transistor, such as Figures 3 to 6 As shown, the orthographic projection of the gate 45 on the base substrate 10 at least partially (partially or completely) overlaps with the orthographic projection of the first portion 421 of the second electrode 42 on the base substrate 10 .

[0042] In some embodiments, in the same thin film transistor, such as Figure 4 As shown, the orthographic projection of the edge 431 of the first portion 421 of the second electrode 42 close to the first break 43 on the substrate is flush with an edge 451 of the orthographic projection of the gate 45 on the substrate 10. This method can prevent the second portion 422 of the second electrode 42 from overlapping the gate 45 and reduce the width of the first break 43 as much as possible.

[0043] In some embodiments, in the same thin film transistor, such as Figure 4 and Figure 5 As shown, the orthographic projection of the gate electrode 45 on the base substrate 10 completely covers the orthographic projection of the first portion 421 of the second electrode 42 on the base substrate 10. This can prevent the first portion 421 of the second electrode 42 from being excessively extended.

[0044] In some other embodiments, in the same thin film transistor, such as Figure 5 As shown, the orthographic projection of the gate 45 on the base substrate 10 partially overlaps with the orthographic projection of the second portion 422 of the second electrode 42 on the base substrate 10 .

[0045] In some embodiments of the present disclosure, in the same thin film transistor, the orthographic projection of the gate 45 on the base substrate 10 covers the orthographic projection of the active layer 44 on the base substrate 10. However, the embodiments of the present disclosure are not limited thereto.

[0046] Figure 6 A partial structural schematic diagram of a peripheral area 30 in a display substrate according to some further embodiments of the present disclosure is given. Two virtual pixel units 31 and a virtual data line 32 are shown. Figures 3 to 5In the example shown, only one structure of the thin film transistor 40 is shown. However, in the embodiment of the present disclosure, a virtual pixel unit 31 may include not only one thin film transistor but also multiple thin film transistors. The same thin film transistor may also have a more complex structure. Figure 6 In the example shown, the thin film transistor 40" in the virtual pixel unit 31 may also include a gate 45, an active layer 44, a first electrode 41 and a second electrode 42. Two breaks are provided in the thin film transistor 40", namely a first break 43 and a second break 43'. The first electrode 41 is electrically connected to the virtual data line 32. The second electrode 42 has a first part 421, a second part 422 and a third part 421'. The first part 421 is separated from the second part 422 by the first break 43, and the second part 422 and the third part 421' are separated by the second break 43'. In the same thin film transistor 40", the third part 421' may, for example, be farther away from the virtual data line 32 connected to the first electrode 41 than the first part 421. In some embodiments, the extension direction of the third part 421' of the second electrode 42 may be parallel to the extension direction of the first part 421 of the second electrode 42.

[0047] In some embodiments, the orthographic projection of the first break 43 on the substrate substrate does not overlap with the orthographic projection of the gate 45 on the substrate substrate 10 and does not overlap with the orthographic projection of the active layer 44 on the substrate substrate 10. Similarly, in some embodiments, the orthographic projection of the second break 43' on the substrate substrate does not overlap with the orthographic projection of the gate 45 on the substrate substrate 10 and does not overlap with the orthographic projection of the active layer 44 on the substrate substrate 10. The orthographic projection of at least one of the first portion 421 and the third portion 421' of the second electrode 42 on the substrate substrate may have an overlapping portion with the orthographic projection of the gate 45 on the substrate substrate 10 and also have an overlapping portion with the orthographic projection of the active layer 44 on the substrate substrate 10.

[0048] In some embodiments, the second portion 422 of the second electrode 42 may include a first segment 427 adjacent to the first break 43 and a second segment 428 adjacent to the second break 43'. Figure 6 The width of the first segment 427 is greater than the width of the second segment 428, so that the projection of the second portion 422 of the second electrode 42 on the base substrate 10 is in an "L" shape. The first segment 427 has a larger width, which is conducive to providing a via structure in the first segment 427 to electrically connect to other conductive layers (such as the pixel electrode 51).

[0049] In some embodiments, the first electrode 41 in the thin film transistor 40 ″ may have a first extension portion 411, a second extension portion 412, and a third extension portion 413 electrically connected to each other, and the extension directions of the three extension portions may be parallel to the extension direction of the first portion 421 or the third portion 421 ′ of the second electrode 42. Figure 6 As shown, the first extension portion 411 may be located between the first portion 421 and the third portion 421' of the second electrode 42, the second extension portion 412 may be located on a side of the first portion 421 of the second electrode 42 away from the third portion 421' of the second electrode 42, and the third extension portion 413 may be located on a side of the third portion 421' of the second electrode 42 away from the first portion 421 of the second electrode 42. In some embodiments, as Figure 6 As shown, the virtual pixel unit 31 may further include a pixel electrode 51, and the second portion 422 of the second electrode 42 may be electrically connected to the pixel electrode 51. The structure of the thin film transistor 40" is as compared to the structure of Figure 3 The thin film transistor structure shown can improve the load capacity of the gate line.

[0050] In the embodiment of the present disclosure, the width of the first break 43 and the second break 43 ′ may be, for example, 2 micrometers to 5 micrometers.

[0051] Figure 7 It is along Figure 6 A cross-sectional view taken along line AA in FIG. Figure 7 The film structure of the thin film transistor 40" can be more clearly seen in FIG. Figure 7 As shown, the display substrate 100 may include a first insulating layer 71 and a second insulating layer 72. The first insulating layer 71, such as a gate insulating layer, is located between the gate 45 and the active layer 44. The second insulating layer 72, such as a planarization layer or an interlayer dielectric layer, is located between the layer where the pixel electrode 51 is located and the thin film transistor 40. As an example, the first part 421, the second part 422 and the third part 421' of the first electrode 41 and the second electrode 42 may be made of the same material (such as a metal or alloy material such as titanium aluminum) and arranged in the same layer. The first fracture 43 separates the first part 421 and the second part 422 of the second electrode 42. The active layer 44 is located between the layer where the first electrode 41 and the second electrode 42 are located and the first insulating layer 71. The pixel electrode 51 can be electrically connected to the second part 422 of the second electrode 42, for example, through a first via structure 511. The first via structure 511 can be formed by forming a through hole in the second insulating layer 72 and then coating a conductive layer in the through hole. As shown Figure 7 As shown, the conductive layer (eg, metal layer) in the first via structure 511 can be made of the same material and disposed in the same layer as the pixel electrode 51. The first via structure 511 can penetrate the second insulating layer 72 and contact the second portion 422 of the second electrode 42. Figure 6 As can be seen in FIG. 1 , the display substrate 100 may further include a common electrode 53. The common electrode 53 may apply the necessary voltage to the pixel unit together with the pixel electrode 51 to realize the display function. In some embodiments, an electrode extension layer 33 is further provided in the peripheral area 30, and the electrode extension layer 33 is electrically connected to the common electrode 53. The electrode extension layer 33 may be used to increase the area of ​​the common electrode 53 to improve the stability of the signal. The electrode extension layer 33 may be arranged in the form of a large conductive layer, such as Figure 6 In some embodiments, the electrode extension layer 33 may be made of the same material and arranged in the same layer as the first electrode 41 , the second electrode 42 , and the dummy data line 43 to simplify the process.

[0052] In some embodiments, a connection layer 34 may be further provided to facilitate electrical connection between the common electrode 53 and the electrode extension layer 33. The connection layer 34 and the pixel electrode 51 may be made of the same material and provided in the same layer. The connection layer 34 is electrically connected to the common electrode 53 through a second via structure 61, and is electrically connected to the electrode extension layer 33 through a third via structure 62. The second via structure 61 may be formed by forming a through hole through the first insulating layer 71 and the second insulating layer 72 and then coating the through hole with a conductive layer (e.g., a metal layer). The third via structure 62 may be formed by forming a through hole through the second insulating layer 72 and then coating the through hole with a conductive layer. Figure 8 It can be clearly seen that the conductive layer in the second via structure 61 can be made of the same material and disposed in the same layer as the connection layer 34. The second via structure 61 can penetrate the first insulating layer 71 and the second insulating layer 72 to contact the common electrode 53. Similarly, the third via structure 62 can be made of the same material and disposed in the same layer as the connection layer 34. The third via structure 62 can penetrate the second insulating layer 72 to contact the electrode extension layer 33. However, the embodiments of the present disclosure are not limited thereto, for example, the common electrode 53 and the electrode extension layer 33 can also be directly electrically connected without passing through the connection layer 34.

[0053] In some embodiments, Figure 6As shown, the common electrode 53 may include a first common electrode extension portion 531 and a second common electrode extension portion 532 that are interconnected. Among them, a second via structure 61 is formed at the second common electrode extension portion 532, which is used to electrically connect the second common electrode extension portion 532 to the connection layer 34. The second common electrode extension portion 532 can be arranged to extend along the edge of the electrode extension layer 33, so as to better arrange the second via structure 61, especially when a plurality of second via structures 61 are provided. The first common electrode extension portion 531 of the common electrode 53 can extend from the second common electrode extension portion 532 and the gate line 52 generally side by side. This does not mean that the extension direction of the first common electrode extension portion 531 of the common electrode 53 must be parallel to the extension direction of the gate line 52. For example, the first common electrode extension portion 531 can extend in a zigzag manner in order to bypass structures such as transistors (such as Figure 6 For example, the first common electrode extension 531 may intersect the virtual data line 32. As an example, the overall extension direction of the first common electrode extension 531 from the second common electrode extension 532 may be defined as a first direction (eg, Figure 6 The extending direction of the second common electrode extension portion 532 is defined as the second direction (eg, Figure 6 in the y direction). Figure 6 In the example shown, the first direction and the second direction are approximately 90 degrees, and the first common electrode extension 531 and the second common electrode extension 532 of the common electrode 53 form an L-shaped structure. The design of this structure is conducive to the electrical connection between the common electrode 53 and the connection layer 34. However, the embodiments of the present disclosure are not limited thereto, for example, the overall extension direction of the first common electrode extension 531 and the extension direction of the second common electrode extension 532 may not be perpendicular.

[0054] In some embodiments, Figure 6 As shown, the orthographic projection of the connection layer 34 on the base substrate 10 at least partially overlaps with the orthographic projection of the second common electrode extension 532 on the base substrate 10, for example, the orthographic projection of the connection layer 34 on the base substrate 10 completely covers the orthographic projection of the second common electrode extension 532 on the base substrate 10. This is conducive to the layout of the second via structure 61. The orthographic projection of the first common electrode extension 532 on the base substrate 10 may at least partially overlap with the orthographic projection of the pixel electrode 51 on the base substrate 10. In some embodiments, the orthographic projection of the first common electrode extension 531 on the base substrate 10 and the orthographic projection of the virtual data line 32 on the base substrate 10 intersect with each other.

[0055] In some embodiments, the electrode extension layer 33 is electrically connected to the virtual data line 32. This allows the virtual data line 32 to be electrically connected to the common electrode 53, further increasing the actual area of ​​the common electrode 53 and improving signal stability.

[0056] like Figure 6 As shown, in some embodiments, both ends of the same virtual data line 32 may be electrically connected to the electrode extension layer 33 to form a conductive loop passing through the same virtual data line 32 and the electrode extension layer 33. This structure can make the potential distribution on the common electrode 53 more uniform. For example, if the virtual data line 32 is disconnected and cannot form a conductive loop with the electrode extension layer 33, there may be a relatively large potential difference on both sides of the break of the virtual data line 32. The same virtual data line 32 and the electrode extension layer 33 forming a conductive loop helps to reduce this excessive potential difference as much as possible, which is beneficial for achieving brightness uniformity of display pixels in the display area 20.

[0057] In some embodiments, Figures 6 to 8 As shown, the first insulating layer 71 may be located on a side of the common electrode 53 away from the base substrate 10 and on a side of the electrode extension layer 33 facing the base substrate 10; the second insulating layer 72 may be located between the electrode extension layer 33 and the connecting layer 34 and on a side of the active layer 44 away from the base substrate 10.

[0058] In some embodiments, Figure 6 As shown, a gate line 52 is provided on the display substrate 100, the electrode extension layer 33 and the first electrode 42, the second electrode 42 and the virtual data line 32 are arranged in the same layer by the same material, and the gate line 52 and the gate 45 are arranged in the same layer by the same material. The orthographic projection of the gate line 52 on the base substrate 10 and the orthographic projection of the electrode extension layer 33 on the base substrate 10 have an overlapping area. The electrode extension layer 33 overlaps with the gate line 52, which is beneficial to the wiring on the display substrate 100, and can also make the electrode extension layer 33 have as large an area as possible to improve signal stability.

[0059] In some embodiments, Fig. 9As shown, the electrode extension layer 33 may include a hollow area 35. The orthographic projection of the hollow area 35 on the base substrate 10 overlaps at least partially (partially or completely) with the orthographic projection of the gate line 52 on the base substrate 10. At the hollow area 35, the conductive layer portion of the electrode extension layer 33 is removed. One or more hollow areas 35 are provided at the intersection of the gate line 52 and the electrode extension layer 33, which can reduce the parasitic capacitance between the electrode extension layer 33 (for example, the layer where the first electrode 41 and the second electrode 42 are located) and the layer where the gate line 52 is located, and avoid the increase in the area of ​​the conductive layer caused by the electrode extension layer 33 to significantly increase the parasitic capacitance, thereby preventing uneven brightness due to differences in parasitic capacitance.

[0060] It should be understood by those skilled in the art that although Figure 6 Only two virtual pixel units 31 are shown in the figure, but the embodiments of the present disclosure are not limited thereto, and the display substrate 100 may further include more virtual pixel units.

[0061] The embodiments of the present disclosure also provide a display panel, which may include the display substrate 100 according to any of the above embodiments. The display substrate and display panel according to the embodiments of the present disclosure can be used not only for thin film transistor type liquid crystal display devices, but also for other types of display devices such as organic light emitting diodes (OLEDs). The display panel in the embodiments of the present disclosure may be, for example, a thin film transistor type liquid crystal display panel, or any other type of display panel known in the art such as an organic light emitting diode (OLED) display panel. It should be noted that the display device in the embodiments of the present disclosure may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, etc.

[0062] The "same-layer arrangement" referred to in the present disclosure means that the layers involved are formed simultaneously in the same process step, and does not mean that these layers must have the same thickness or height in the cross-sectional view. The design of "same-layer arrangement" can simplify the manufacturing process of the display substrate and the display panel as much as possible.

[0063] Each conductive layer in the embodiment of the present disclosure may be made of a conductive metal or a non-metallic conductive material.

[0064] Although the present disclosure is described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to exemplify the embodiments of the present disclosure and should not be construed as limiting the present disclosure. The dimensional ratios in the drawings are merely illustrative and should not be construed as limiting the present disclosure.

[0065] The above embodiments are merely illustrative of the principles and structures of the present disclosure, and are not intended to limit the present disclosure. It should be understood by those skilled in the art that any changes and improvements made to the present disclosure without departing from the overall concept of the present disclosure are within the scope of the present disclosure. The scope of protection of the present disclosure shall be subject to the scope defined by the claims of this application.

Claims

1. A display substrate, comprising: substrate substrate; A display area and a peripheral area outside the display area are arranged on a substrate, a dummy pixel unit and a dummy data line are arranged in the peripheral area, the dummy pixel unit includes a thin film transistor, the thin film transistor includes a first electrode and a second electrode, the first electrode is one of a source electrode and a drain electrode, the second electrode is the other of the source electrode and the drain electrode, the first electrode is electrically connected to the dummy data line, and the second electrode has a first part and a second part separated by a first break; The virtual pixel unit further includes a pixel electrode, the thin film transistor further includes an active layer and a gate, and in the same thin film transistor, an orthographic projection of the gate on the substrate at least partially overlaps with an orthographic projection of the active layer on the substrate; The second electrode further has a third portion, the second portion and the third portion are separated by a second break, the orthographic projection of each of the first break and the second break on the substrate does not overlap with the orthographic projection of the gate on the substrate and does not overlap with the orthographic projection of the active layer on the substrate, the orthographic projection of at least one of the first portion and the third portion of the second electrode on the substrate at least partially overlaps with the orthographic projection of the gate on the substrate and also at least partially overlaps with the orthographic projection of the active layer on the substrate, and the second portion of the second electrode is electrically connected to the pixel electrode through a first via structure; The display substrate further includes a second insulating layer, the second insulating layer is located between the layer where the pixel electrode is located and the thin film transistor, and the first via structure penetrates the second insulating layer.

2. The display substrate according to claim 1, wherein: In the same thin film transistor, the orthographic projection of the active layer on the base substrate at least partially overlaps with the orthographic projection of the first part of the second electrode on the base substrate, and does not overlap with the orthographic projection of the second part of the second electrode on the base substrate.

3. The display substrate according to claim 1, wherein: In the same thin film transistor, an orthographic projection of an edge of a first portion of the second electrode close to the first break on the substrate is flush with an edge of an orthographic projection of the gate on the substrate.

4. The display substrate according to claim 1, wherein: In the same thin film transistor, the orthographic projection of the gate on the substrate completely covers the orthographic projection of the first part of the second electrode on the substrate.

5. The display substrate according to any one of claims 1 to 4, further comprising a common electrode, wherein: An electrode extension layer is also provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, the electrode extension layer and the first electrode, the second electrode and the virtual data line are arranged in the same layer with the same material, and the electrode extension layer is electrically connected to the virtual data line.

6. The display substrate according to claim 5, wherein: Both ends of the same virtual data line are electrically connected to the electrode extension layer to form a conductive loop passing through the same virtual data line and the electrode extension layer.

7. The display substrate according to any one of claims 1 to 4, further comprising a common electrode and a connection layer, wherein: An electrode extension layer is also provided in the peripheral area, and the electrode extension layer is electrically connected to the common electrode. The connection layer and the pixel electrode are made of the same material and are provided in the same layer. The connection layer is electrically connected to the common electrode through a second via structure, and is electrically connected to the electrode extension layer through a third via structure.

8. The display substrate according to claim 7, wherein: The common electrode includes a first common electrode extension portion and a second common electrode extension portion that are connected to each other, the extension direction of the first common electrode extension portion and the extension direction of the second common electrode extension portion intersect with each other, the orthographic projection of the connecting layer on the base substrate at least partially overlaps with the orthographic projection of the second common electrode extension portion on the base substrate, and the orthographic projection of the first common electrode extension portion on the base substrate at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate.

9. The display substrate according to any one of claims 1 to 4, further comprising a common electrode and a gate line, wherein: An electrode extension layer is also provided in the peripheral area, the electrode extension layer is electrically connected to the common electrode, the electrode extension layer and the first electrode, the second electrode and the virtual data line are arranged in the same layer with the same material, the gate line and the gate are arranged in the same layer with the same material, and the orthographic projection of the gate line on the base substrate has an overlapping area with the orthographic projection of the electrode extension layer on the base substrate.

10. The display substrate according to claim 9, wherein: The electrode extension layer includes a hollow area, and an orthographic projection of the hollow area on the base substrate at least partially overlaps with an orthographic projection of the gate line on the base substrate.

11. A display panel comprising the display substrate according to any one of claims 1 to 10.

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