Data processing system

Abstract

This invention provides a data processing system. In this system, an execution thread group can execute a set of instructions in lockstep, and multiple execution channels can perform processing operations for the execution threads. Two or more execution threads of the thread group are assigned to the same execution channel for execution. These two or more execution threads can then be processed consecutively by the execution channel, allowing the execution channel to continuously perform the same processing operations. This can reduce signal switching, thereby reducing the overall power consumption of the data processor.

Description

Technical Field

[0001] The present invention relates generally to the operation of data processing systems, and more particularly to graphics processing systems comprising one or more programmable processing stages (“shaders”). Background Technology

[0002] Graphics processing is typically pipelined, with one or more pipeline stages manipulating data to produce a final rendered output, such as a displayed frame. Many graphics processing pipelines now include one or more programmable processing stages, often called "shaders." For example, a graphics processing pipeline may include one or more of the following, and typically all of them: geometry shaders, vertex shaders, and fragment (pixel) shaders. These shaders are programmable processing stages that execute shader programs on input data values ​​to produce the desired output dataset, such as fragment data that is properly shaded and rendered in the case of a fragment shader, to be processed by the rest of the graphics pipeline and / or output. The shaders in a graphics processing pipeline may share programmable processing circuitry or may be executed by separate programmable processing units.

[0003] The graphics processing unit (GPU) shader core is therefore a processing unit that performs graphics processing by running small programs on individual graphics "work" items (in this respect, "items" are typically vertices or sampled locations, e.g., in the case of fragment shaders) in the graphics output to be generated (such as a render target, e.g., a frame). This allows for a high degree of parallelism overall, since typical render outputs, such as frames, have a large number of vertices and fragments, each of which can be processed independently.

[0004] In graphics shader operations, each work "project" is handled by an execution thread, which executes instructions for the relevant shader program for the relevant graphics work "project".

[0005] The actual data processing operations performed by the shader program are in response to instructions within the shader program and are carried out under its control by various functional units (e.g., math units) of the graphics processor. Thus, for example, an appropriate functional unit, such as a math unit, will respond to and perform data processing operations in response to instructions in the executing shader program. Typically, multiple functional units are provided in the graphics processor (GPU), and each functional unit can be started and used separately and appropriately for the execution thread when the shader program is executed.

[0006] The functional units provided in a graphics processor (GPU) for performing the operations required by shader programs (and other means) can (and typically) be shared between different shaders (shader levels) in the graphics processing pipeline executed by the GPU. Therefore, there will generally be a set of functional units set up and available for the execution of shader programs. Depending on the desired outcome, separate functional units may also be provided for individual shaders (or some functional units may be separate while others are shared).

[0007] The execution efficiency of shader programs can be improved by grouping execution threads (each thread corresponding to a vertex or a sampling location) into “groups” or “bundles” of threads, where a group of threads runs one instruction at a time in locksteps. This allows instruction fetching and scheduling resources to be shared among all threads in the group. Other terms used for such thread groups include “warp” and “wavefront.” For convenience, this article will use the term “thread group,” but unless otherwise stated, this is intended to cover all equivalent terms and settings.

[0008] In systems where execution threads can be grouped into thread groups, functional units used to process instructions in shader programs can typically operate accordingly to facilitate this thread group setup. Typically, each functional unit has multiple corresponding execution channels, allowing the functional unit to execute the same instructions in parallel for multiple threads within a thread group.

[0009] Functional units typically provide an execution channel for each execution thread that a thread group can contain. Therefore, for example, in a system where execution threads are grouped into groups (“bundles”) of four threads, functional units can each operate as four corresponding (and identical) execution channels. Each execution thread of a thread group (“bundle”) can typically be assigned to a corresponding execution channel for execution, such that each execution channel is assigned only one execution thread from the thread group. Summary of the Invention

[0010] The applicant believes there is still room for improvement in the processing of thread groups, particularly for shaders in the graphics processing pipeline.

[0011] According to a first aspect of the present invention, a method for operating a data processor is provided, wherein execution threads are capable of executing program instructions to perform data processing operations on data values, and wherein execution threads are capable of being grouped together to form a thread group, wherein multiple execution threads of a thread group are each capable of executing a set of instructions in lockstep.

[0012] The data processor includes:

[0013] An instruction execution processing circuit operatively executes instructions to perform processing operations for an execution thread of a program, wherein the instruction execution processing circuit is configured with multiple execution channels, each execution channel operatively performing processing operations for an execution thread of a thread group; and

[0014] An execution thread publishing circuit is used to publish the execution threads of the thread group to the execution channels of the plurality of execution channels of the instruction execution processing circuit for execution.

[0015] The method includes the following steps:

[0016] The execution thread publishing circuit publishes two or more execution threads from the same thread group to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution.

[0017] According to a second aspect of the present invention, a data processor is provided in which execution threads are capable of executing program instructions to perform data processing operations on data values, and in the data processor, execution threads can be grouped together to form a thread group, wherein multiple execution threads in a thread group are each capable of executing a set of instructions in lockstep.

[0018] The data processor includes:

[0019] An instruction execution processing circuit operatively executes instructions to perform processing operations for an execution thread of a program, wherein the instruction execution processing circuit is configured with multiple execution channels, each execution channel operatively performing processing operations for an execution thread of a thread group; and

[0020] An execution thread publishing circuit is used to publish the execution threads of the thread group to the execution channels of the plurality of execution channels of the instruction execution processing circuit for execution.

[0021] The execution thread publishing circuit is configured to publish two or more execution threads from the same thread group to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution.

[0022] This invention relates to a data processor, such as a graphics processing unit (GPU), which can execute execution threads to perform a set of instructions for a program to perform data processing operations on data values. The threads executing the program instructions can be grouped into thread groups (“bundles”), and the execution threads of a thread group (“bundle”) execute the program instructions in a lockstep manner, for example, such that each execution thread within the thread group (“bundle”) executes the same instruction in the program (to perform a processing operation) before the next instruction in the program is executed (and so on). The data processor (e.g., a graphics processing unit) includes instruction execution processing circuitry configured with multiple execution channels, and execution thread dispatching circuitry that dispatches the execution threads of the thread groups to the execution channels for execution.

[0023] In this invention, multiple execution threads within the same (single) thread group ("bundle") are published to the same single execution channel for execution.

[0024] As will be discussed further below, by publishing multiple execution threads from the same thread group to the same execution channel for execution, the execution channel in question will execute the same program instructions to perform the same processing operations continuously on the multiple execution threads from the same thread group.

[0025] The applicant has recognized that when an execution channel performs the same processing operations consecutively on threads from the same thread group, the data values ​​(e.g., inputs and outputs) for the processing operations are more likely (and / or can be set to be more likely) to be similar or identical to each other, for example, compared to the case where the processing operations performed consecutively by the execution channel are from threads from different thread groups. This results in fewer physical signal transitions (e.g., in registers or combinational logic) that need to be performed for those consecutive processing operations. This means that the energy used to cause signal transitions can be reduced.

[0026] In this regard, the applicant has recognized that when an execution channel performs the same processing operations consecutively for multiple execution threads it has issued, for example, when processing operations are performed consecutively for very different data values, the number of physical signal transitions that would occur (e.g., in registers or combinational logic) to perform those processing operations can be reduced if the data values ​​being processed consecutively are the same or similar to each other. Therefore, the energy required to cause these signal transitions can be saved.

[0027] For example, when the input data values ​​for threads from the same thread group to be processed consecutively by an execution channel are identical, in order to process the second thread, it is not necessary to change the input register for that execution channel from the value set when processing the first thread, and thus energy is saved that would otherwise be required to change the bits in the input register. Similarly, when the input data values ​​for (closely) successive threads are similar (but not identical), at least some bits (e.g., the most significant bit) may remain unchanged between consecutive processing operations. Moreover, when consecutive processing operations are identical, this similarity should propagate through to the results of consecutive processing operations and to any intermediate processed values, thereby reducing the number of similar signal transitions, and thus reducing energy requirements in other locations, such as output registers and combinational logic.

[0028] Therefore, compared to publishing the individual execution threads of a thread group to different execution channels for execution (and, for example, causing each execution thread to (immediately) follow threads from different thread groups), publishing multiple execution threads from the same thread group (“bundle”) to the same execution channel for execution can reduce the total number of signal transitions and thus reduce energy consumption.

[0029] This invention can therefore reduce the energy consumption of data processors, such as graphics processors, when executing programs. This is generally advantageous, but it is particularly advantageous in resource-constrained situations, such as in portable devices, like mobile phones and tablets.

[0030] Therefore, it will be recognized that the present invention provides an improved data processor.

[0031] The thread group (“bundle”) from which the thread published by the execution thread publishing circuit comes can be any suitable group of multiple execution threads (each execution thread executes a set of instructions in lockstep).

[0032] Thread groups can have any suitable and required size. In implementations, the data processor supports fixed thread group sizes. Preferably, the number of threads in a thread group is a power of 2. A thread group can contain, for example, four threads (i.e., a “bundle width” of four), or wider thread groups (bundles) can be used, such as eight or sixteen threads.

[0033] The execution thread publishing circuit should (and in a preferred embodiment does) publish each (active) execution thread in the thread group to the execution channel for execution. If there are only two threads in the thread group, the execution thread publishing circuit should publish both threads to the same execution channel for execution. If there are more than two threads in the thread group, the execution thread publishing circuit should publish at least two threads from the thread group to the same execution channel.

[0034] In the latter case, other threads in the thread group can be published to the execution channel as desired.

[0035] For example, one or more of the other threads in the thread group may also be assigned to the same execution channel as the at least two executing threads, or all the other threads may also be assigned to the same execution channel as the at least two executing threads (i.e., all threads in the thread group are assigned to the same execution channel). Alternatively, the other threads in the thread group may be assigned to one or more different execution channels of the instruction execution processing circuit.

[0036] In a preferred embodiment, the thread group is divided into multiple thread subsets of the thread group, wherein each such thread subset includes some but not all of the threads of the thread group, and preferably includes multiple threads of the thread group (“bundle”).

[0037] Dividing a thread group into subsets can be done as desired. In a preferred embodiment, the division is such that each subset includes the same number of threads as the other subsets. Preferably, the number of threads in each subset is a power of 2 (e.g., two, four, or eight). In a preferred embodiment, a thread group (“bundle”) is divided into subsets that each include exactly four execution threads.

[0038] A thread group can be divided into any desired number of subsets, for example, depending on the size of the thread group and the size of the subsets to be divided. In a preferred embodiment, the number of thread group subsets is (preferably) a power of 2, such as 2, 4, or 8. Thus, for example, and in a preferred embodiment, a thread group (“bundle”) comprising a total of sixteen execution threads is divided into four thread group subsets, each of which comprises four threads.

[0039] Other settings are also possible.

[0040] When a thread group is divided into multiple subsets, preferably, two or more (and in a preferred embodiment all) execution threads from each subset are published to the same execution channel for execution. This then means that energy savings are more likely to be achieved for each subset of thread groups.

[0041] In this scenario, in a preferred embodiment, threads from a subset of thread groups are published to a corresponding execution channel, which is different from the execution channels to which threads from other subsets of the same thread group are published. Therefore, only one subset of threads from a thread group can be published to each execution channel. Thus, in this case, the number of execution channels to which threads from the thread group are published can be equal to the number of thread group subsets.

[0042] In another implementation, threads from (two or more) different subsets of thread groups are published to the same execution channel for execution. Therefore, more than one subset of threads from a thread group can be assigned to each execution channel (and in this case, the number of execution channels to which the threads of the thread group are published can be less than the number of thread group subsets). For example, and in another implementation, an integer number (e.g., two) of the threads from the thread group subsets can be published to each execution channel (in this case, the number of execution channels to which the threads of the thread group are published can be equal to the number of thread group subsets divided by that integer (e.g., half the number of thread group subsets)).

[0043] It is also possible to distribute threads of a subset of thread groups across multiple execution channels (and this is done in the preferred embodiment). Therefore, in another embodiment, threads of a single subset of thread groups are published to two or more different execution channels (in which case the number of execution channels on which the threads of the published thread group can be greater than the number of thread group subsets). For example, two or more threads of (each) subset of thread groups can be published to (corresponding) execution channels, and two or more other threads of the same subset of thread groups can be published to another (corresponding) different execution channel.

[0044] For example, and in an implementation, the threads of each (each) thread group subset can be divided into equal parts, each part being assigned to a different execution channel. For example, and in an implementation, half of the threads of each (each) thread group subset can be assigned to a (corresponding) execution channel, while the other half of the threads of the same thread group subset can be assigned to another (corresponding) different execution channel. Therefore, each thread group subset can and preferably execute on, for example, two (different) execution channels. In this case, the number of execution channels for the threads of the assigned thread group can be equal to an integer (e.g., two) multiplied by the number of thread group subsets.

[0045] Therefore, it will be understood that the ratio of the number of threads in a thread group (“bundle”) to the number of execution channels of the threads published to the thread group should be greater than 1:1 (i.e., the number of execution channels of the published threads should be less than the number of threads in the thread group (“bundle”), that is, such that at least one execution channel is published to multiple execution threads of the thread group.

[0046] This ratio can be further selected based on desired outcomes. Increasing this ratio (increasing the number of threads per execution channel) can increase the potential for energy savings in the mathematical data path, but may degrade performance, for example, due to increased latency on a single execution and / or increased buffering requirements. Therefore, this ratio can be selected to provide an appropriate balance between energy consumption and performance requirements. Preferably, a 4:1 ratio is chosen, i.e., such that for every four execution threads (a subset of the thread group), there is one execution channel (a thread being assigned to execute).

[0047] The two or more threads published to the same execution channel for execution can be any suitable and desired threads from the (same) thread group (“bundle”). As discussed above, in a preferred embodiment, the two or more execution threads comprise a subset (some but not all) of the threads from that thread group (“bundle”).

[0048] Therefore, in a preferred embodiment, the execution thread publishing circuit publishes two or more selected execution threads of a thread group (“bundle”) to the same execution channel for execution.

[0049] While it is anticipated, as discussed above, that energy savings will be achieved by publishing any two threads from a thread group to the same execution channel, in a preferred embodiment, the two or more execution threads selected from the thread group to be published to the same execution channel (compared to other threads in the thread group) are those threads in the thread group that are expected to process the same or similar data values.

[0050] Therefore, in a preferred embodiment, when each execution thread in a thread group (“bundle”) is to (execute program instructions to) process corresponding data values, the threads published to the same execution channel for execution are preferably selected based on the probability that two or more threads published to the same execution channel will process the same or similar data values, and such probability is increased (and / or an attempt is made to increase the similarity between the data values ​​that the two or more threads published to the same execution channel will process). Thus, this selection is preferably based on the data values ​​that the threads will (likely) process, and preferably based on which threads in the thread group are more likely to have data values ​​that are the same or similar to each other.

[0051] Therefore, in a preferred embodiment, the execution thread publishing circuit publishes two or more (selected) execution threads from the same thread group that are more likely to be associated with the same or similar data (i.e., more likely to process the same or similar data) to the same execution channel for execution.

[0052] Therefore, in a preferred embodiment, instead of publishing execution threads to execution channels, for example based on the numerical or indexed order of the execution threads, the (potential) similarity between the data values ​​that the execution threads of the thread group (“bundle”) are to process or may process is considered when deciding which execution channel an execution thread should be published to, and execution threads that are associated with the same or (more) similar (e.g., input) data values ​​(expected to process the same or (more) similar (e.g., input) data values) are preferentially published to the same execution channel for execution.

[0053] By prioritizing the deployment of two or more (selected) execution threads from a thread group (“bundle”) that are more likely to be associated with the same or similar data values ​​to the same execution channel for execution, the likelihood of the execution channel performing the same processing operation on the same or similar data values ​​consecutively can be increased, thereby reducing the total number of signal transitions and (further) reducing energy usage.

[0054] It will be recognized here that the selected threads published to the same execution channel can (certainly or possibly) process data values ​​that will be (completely) identical to each other. Alternatively, the selected threads can (certainly or possibly) process data values ​​that are, for example, (not exactly identical but) similar to each other, and preferably more similar to other data values ​​that other threads in the (same) thread group will (potentially) process.

[0055] Furthermore, it will be recognized that it is likely certain that the data values ​​processed by the selected threads will be the same or similar to each other. For example, before publishing threads to the same execution channel, it can be known (certainly) that the data values ​​for the execution threads to be published to the same execution channel are the same or similar.

[0056] For example, and in an implementation, the data values ​​to be processed by the execution threads can be (explicitly) examined to determine whether those data values ​​are the same or similar to each other. For instance, this might involve comparing the data values ​​to be processed by different execution threads within a thread group, and then using the comparison results to determine whether the data values ​​are the same or similar. Threads assigned to the same execution channel can then be selected based on the comparison results, for example, such that threads determined to have similar or identical data values ​​are preferentially assigned to the same execution channel.

[0057] However, in a preferred embodiment, it may not be possible to definitively determine whether the data values ​​for the execution threads are the same or similar before the selected threads are published to the same execution channel for execution.

[0058] In this case, instead of using knowledge of the actual data values ​​to be processed to select threads to be published to the same execution channel, threads to be published to the same execution channel in the thread group can be selected using (known and / or expected) relationships (associations) between execution threads within the thread group or between data values ​​for the respective execution threads that indicate execution threads in the thread group that may process similar or the same data values.

[0059] Therefore, there may exist relationships that are inherently statistical (probabilistic), such that certain threads in a thread group are more likely (but not necessarily) to process the same or similar data values ​​than other threads in the same thread group. For example, the probability that certain threads in a thread group process the same or similar data values ​​may be greater than the probability that other threads within the same thread will (potentially) process the same or similar data values.

[0060] Therefore, threads identified and / or expected to be more likely to process the same or similar data values ​​are preferably published to the same execution channel for execution.

[0061] Threads can be identified as more likely to process the same or similar data values ​​in any appropriate and desirable manner. In implementations, when threads process individual data values ​​corresponding to different points in space and / or time, the spatial and / or temporal proximity between these points can indicate which threads are (more) likely to process similar or identical data values. Therefore, threads can and preferably be identified as more likely to process the same or similar data values ​​based on temporal and / or spatial proximity.

[0062] For example, the applicant has recognized that, in the case of a time series of data values, data values ​​representing points closer in time are generally more likely to be similar or identical to each other (more similar) than data values ​​representing points further apart in time. Similarly, in the case of a spatial array of data values ​​(e.g., images), data values ​​representing points closer in space are generally more likely to be similar or identical to each other (more similar) than data values ​​representing points further apart in space.

[0063] Therefore, in a preferred embodiment, the threads of a thread group (the data values ​​to be processed) correspond to a spatial and / or temporal point distribution, and based on the spatial and / or temporal point distribution corresponding to the threads of the thread group, the threads of the thread group are identified as more likely to process the same or similar data values. For example, it is preferable to identify threads of a thread group that correspond to points that are spatially and / or temporally close to each other (e.g., close to each other compared to other points corresponding to other threads in the thread group) as more likely to process the same or similar data values.

[0064] Therefore, two or more execution threads can be selected from the thread group to be published to the same execution channel based on the spatial and / or temporal (relative) distribution of the (data points) corresponding to the threads in the thread group, and preferably based on the fact that two or more threads need to process data values ​​corresponding to points that are close to each other in space and / or time (e.g., and preferably closer to each other than other points corresponding to other threads in the thread group).

[0065] Therefore, for example, in the case of processing spatial and / or temporal arrays of data elements, it can be expected that the data values ​​of (closely) adjacent elements of the data array will be more similar to each other (than the data values ​​of non-adjacent elements of the data array). Therefore, threads corresponding to (closely) adjacent data elements are preferably identified as more likely to process the same or similar data values ​​(and are selected to be published to the same execution channel for execution).

[0066] Therefore, in a preferred embodiment, each execution thread in the thread group will process the data values ​​of each data element of the data array, and the execution thread publishing circuit publishes two or more (selected) execution threads of the thread group that will process (closely) adjacent data elements of the data array to the same execution channel for execution.

[0067] The applicant believes that it is novel and inventive to publish execution threads that process adjacent data elements of a data array to the same execution channel for execution, for example in the context of a graphics processor.

[0068] Therefore, according to a third aspect of the invention, a method for operating a data processor is provided, in which execution threads are capable of executing program instructions to process corresponding data elements of a data array, and in the data processor, execution threads can be grouped together to form a thread group, wherein multiple execution threads of a thread group are each capable of executing a set of instructions in lockstep.

[0069] The data processor includes:

[0070] An instruction execution processing circuit operatively executes instructions to perform processing operations for an execution thread of a program, wherein the instruction execution processing circuit is configured with multiple execution channels, each execution channel operatively performing processing operations for an execution thread of a thread group; and

[0071] An execution thread publishing circuit is used to publish the execution threads of the thread group to the execution channels of the plurality of execution channels of the instruction execution processing circuit for execution.

[0072] The method includes the following steps:

[0073] When processing data elements of a data array, each thread in the thread group processes one data element of that data array:

[0074] The execution thread publishing circuit publishes two or more execution threads of adjacent data elements of the data array to be processed by the thread group to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution.

[0075] According to a fourth aspect of the present invention, a data processor is provided in which execution threads are capable of executing program instructions to process data elements of a data array, and in the data processor, execution threads can be grouped together to form a thread group, wherein multiple execution threads of a thread group are each capable of executing a set of instructions in lockstep.

[0076] The data processor includes:

[0077] An instruction execution processing circuit operatively executes instructions to perform processing operations for an execution thread of a program, wherein the instruction execution processing circuit is configured with multiple execution channels, each execution channel operatively performing processing operations for an execution thread of a thread group; and

[0078] An execution thread publishing circuit is used to publish the execution threads of the thread group to the execution channels of the plurality of execution channels of the instruction execution processing circuit for execution.

[0079] The execution thread publishing circuit is configured to, for a thread group comprising threads that will each process corresponding data elements of the data array, publish two or more execution threads of the thread group that will process adjacent data elements of the data array to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution.

[0080] As those skilled in the art will understand, these aspects and embodiments of the invention may and preferably do include one or more, and preferably all, of the preferred and optional features of the invention suitably described herein. Thus, for example, the data processor is preferably a graphics processor, and the data array is preferably an array of image elements forming an image (e.g., frames for display).

[0081] Typically, in these settings where a thread in a thread group represents and is processing the corresponding data elements of a data array, the data array can be any suitable and desired array of data elements. The data array can be a one-dimensional, two-dimensional, or higher-dimensional array of data elements, wherein each dimension preferably represents a temporal or spatial dimension.

[0082] In a preferred embodiment, the data array is a two-dimensional rectangular (e.g., square) array representing image elements (e.g., sampling positions) of an image (e.g., a frame). Each data value then preferably represents a set of color values ​​of the image. In this regard, the applicant has recognized that adjacent image elements of an image are generally more likely to be similar to each other (more similar to each other) compared to non-adjacent image elements; therefore, posting threads that process adjacent image elements to the same execution channel can result in a significant reduction in signal transitions, thereby reducing energy requirements (as discussed above).

[0083] The adjacent data (e.g., image) elements represented by threads published to the same execution channel may, for example, correspond to rows of adjacent data (e.g., image) elements (e.g., "x", "y", or "diagonal" directions in a data array (image)). In a preferred embodiment, a thread published to the same execution channel represents (processes) a set of adjacent data (e.g., image) elements corresponding to a (two-dimensional) subarray of adjacent data (e.g., image) elements, such as a 2×2 subarray of data elements (e.g., a "quadruple").

[0084] Therefore, in a preferred embodiment, the execution thread that processes the data values ​​corresponding to the (two-dimensional) subarray (block) of adjacent (continuous) data (image) elements (sampling positions) of the data array (image) being processed by the data processor is published to the same execution channel for execution.

[0085] Such subarrays of data (e.g., image) elements should include some, but not all, of the data (e.g., image) elements of the data array (e.g., image), but otherwise can be of any suitable and desired size. For example, in the case of graphics processing, the respective subarrays of data elements preferably comprise 2×2 blocks (“quadruple”) of adjacent sampled locations (image elements) of the image being processed (e.g., frames). Thus, in a preferred embodiment, the subarray comprises 2×2 blocks (“quadruple”) of adjacent data (e.g., image) elements. (However, larger subarrays are possible.)

[0086] Each subarray preferably corresponds to and is processed by a corresponding subset of threads within the same thread group. Thus, as discussed above, a thread group (“bundle”) is divided into multiple thread group subsets, each thread group subset preferably corresponding to one (and corresponding) subarray of (preferably adjacent) data elements.

[0087] Typically, the above describes selecting a (single) group of two or more execution threads from a thread group for deployment to the same (single) execution channel. However, as discussed above, in a preferred embodiment, the thread group is divided into multiple subsets of threads within the thread group, and two or more (preferably all) execution threads from each respective subset of the thread group are preferably deployed to the same (corresponding) execution channel for execution. In this case, the threads of each respective group of two or more execution threads (preferably each respective subset of the thread group) are preferably selected from the same thread group based on and according to the aforementioned criteria and considerations.

[0088] Therefore, in a preferred embodiment, the threads of a thread group are divided into multiple thread group subsets based on and in accordance with the above criteria and considerations. For example, and preferably, each such thread group subset contains threads that are likely to be associated with the same or similar data values ​​(i.e., to or may be to process the same or similar data values) compared to threads in other thread group subsets.

[0089] For example, and in a preferred embodiment, where the threads of a thread group correspond to a point distribution in space and / or time, the threads of the thread group are preferably divided into subsets of the thread group based on the distribution, for example and preferably such that each subset of the thread group contains threads that process data values ​​corresponding to points that are spatially and / or temporally close to each other, for example and preferably closer to each other than the other points corresponding to the threads of other subsets of the thread group.

[0090] For example, and in a preferred embodiment, where each execution thread in the thread group is to process data values ​​for corresponding data elements of the data array, the threads of the thread group are preferably divided into thread group subsets such that each thread group subset contains (closely) adjacent data elements of the data array, for example and preferably such that each thread group subset corresponds to (preferably adjacent) (corresponding) (e.g., 2×2 "quadruple") subarrays of data elements (and thus the thread group as a whole will correspond to and process a set of multiple subarrays (e.g., multiple "quadruples") of data elements).

[0091] Therefore, in a preferred embodiment, when processing a data array representing a set of points (data elements) distributed in space and / or time, wherein each thread in a thread group represents and processes a specific point (data element) in the array (and the thread group correspondingly represents a set of points (data elements) in the array), based on the relative spatial and / or temporal distribution of the points (data elements) corresponding to the threads in the array, the thread group is divided into multiple subsets of threads (and preferably into multiple subsets of threads, each subset including a thread representing a set of two or more points (data elements) that are spatially and / or temporally adjacent) in the array (wherein the respective subsets of thread groups are then published to corresponding (and preferably different) execution channels for processing).

[0092] In a particularly preferred embodiment, each thread group (“bundle”) is divided into multiple thread group subsets, each subset comprising four execution threads representing 2×2 blocks (e.g., “quadruple”) of adjacent data (sampling) positions in a processed data array (e.g., an image (e.g., a frame)), and an execution thread publishing circuit publishes two or more (preferably all) execution threads from each (preferably each) thread group subset to the same (corresponding) execution channel for execution.

[0093] An execution channel can process multiple execution threads published from the same thread group in any desired order. In an implementation, threads are published to the execution channel in a specific, preferably selected thread order, and then the execution channel processes those threads in that thread order (continuously).

[0094] The thread order can be any suitable and desired order. In a preferred embodiment, execution threads (from the same thread group (“bundle”)) are processed by the same execution channel in a selected order to minimize the differences between consecutive data values ​​processed by the execution channel, i.e., to minimize the possibility of signal transitions, thereby further reducing power consumption. Therefore, preferably, two or more threads are processed consecutively by the same execution channel in an order that is expected to minimize the differences between consecutive data values ​​processed by the execution channel.

[0095] For example, when threads (from the same thread group) associated with subarrays of adjacent data (e.g., images) elements (e.g., 2×2 (“quadruple”)) are assigned to the same execution channel, consecutive data values ​​processed by the execution channel are more likely to be similar or identical to each other when they represent horizontally and / or vertically separated data elements, compared to data elements that are “diagonally” separated (e.g., due to spatial proximity). Therefore, for example, and as will be further discussed below, processing a 2×2 subarray in “U” order can reduce the differences between consecutive data values ​​compared to processing the subarray in “Z” (Morton) order.

[0096] Therefore, two or more threads in the same thread group are preferably processed sequentially by the (same) execution channel in an order that is intended to reduce (minimize) the spatial and / or temporal differences between consecutive data elements processed by the execution channel.

[0097] The above describes the process of publishing the threads of a single thread group (“bundle”) to the execution channel for execution. However, in implementations, multiple (different) thread groups will be processed. In this case, the threads of each thread group can be processed in the manner described in the various implementations herein. Thus, after the execution thread publishing circuit has published all the threads of the first (that) thread group for execution (as described above), the execution thread publishing circuit then preferably publishes the threads of the next thread group for execution (preferably in the manner described above) (and so on).

[0098] Threads from a thread group to be published to a specific execution channel can be selected based on execution threads previously published from the thread group, for example, and preferably to (as far as possible) (further) minimize the differences between consecutive data values ​​processed by the execution channel. Preferably, this is based on and in accordance with the criteria and considerations discussed above for threads within a thread group. Thus, for example, different threads from the thread group corresponding to closer (e.g., adjacent) data elements can be selected to be published (continuously) to the same execution channel. This can further reduce signal conversion, thereby reducing energy consumption.

[0099] When an execution thread of a thread group has been published to an execution channel for execution, the execution channel should (and preferably is) process the execution thread (provide the processing result for the execution thread).

[0100] In the event of an unused execution channel for an execution thread that has not been published to a thread group, the unused execution channel is preferably used in any desired manner for a different thread group (“bundle”) so that it is not left idle.

[0101] As discussed above, when multiple execution threads from the same thread group are published to the same execution channel for execution, the execution channel should (preferably) process the multiple execution threads continuously (in sequence) (one thread at a time). For example, the execution channel should first provide the processing result for the first execution thread among the multiple execution threads, and then the next processing result provided by the execution channel should be for the next execution thread among the multiple execution threads in the thread group (and so on).

[0102] This means that, since multiple execution threads come from the same thread group (“bundle”) and execute program instructions sequentially in lockstep, the execution channel should (and preferably is) first perform processing operations for the execution thread of the thread group (“bundle”), and then immediately follow up with the same processing operations for another execution thread of the thread group (“bundle”).

[0103] Therefore, for example, when two or more threads (from the same thread group) that are expected to process similar or identical data values ​​are published to the same execution channel, the execution channel can continuously perform the same processing operations on the same or similar or potentially the same or similar data values, thereby achieving energy consumption reduction as discussed above.

[0104] Therefore, the method should and preferably includes (and the instruction execution processing circuitry is preferably configured accordingly) responding to two or more execution threads from the same thread group being published to (the same) execution channel for execution, the execution channel processing the two or more execution threads sequentially (providing processing results for the execution threads).

[0105] The execution channel can process the execution thread in any suitable and desired manner (providing the processing results for the execution thread).

[0106] For example, and in a preferred embodiment, the execution channel can perform processing operations on the execution thread (on the associated data value). This may involve, and preferably involves, processing the execution channel input data value (as associated with the execution thread) to provide an output data value (as associated with the execution thread). As will be discussed further below, when the execution channel is configured as a series of multiple processing stages (pipeline), the execution channel can perform a series of multiple processing operations (one for each processing stage).

[0107] However, the applicant has recognized that, in some cases, the execution channel does not always need to actually perform processing operations on the execution thread. For example, as discussed above, when a first execution thread associated with a first input data value and a second execution thread associated with a second input data value from the same thread group (“bundle”) are posted to the same execution channel for execution, the execution channel may first process the first input data value and then perform the same processing operation on the second input data value. This means that if the first and second input data values ​​are the same, the output for the second execution thread will be the same as the previous output for the first execution thread. This means that it is not necessary to perform processing operations on the second execution thread, but rather the output for the first execution thread can be used as the output for the second execution thread.

[0108] Therefore, processing of the execution thread (providing processing results for the execution thread) may include (the processing level of the execution channel) providing the previous output data value as the current output data value (without performing (omitting) this processing operation).

[0109] Therefore, the method preferably includes (and the instruction execution processing circuit is preferably configured accordingly) determining whether the current input data value for the execution channel (the execution thread of the thread group to which it is directed) (processing level) is (completely identical) to the (closely) previous input data value for the execution channel (the execution thread of the thread group to which it is directed) (processing level), and when it is determined that the current input data value is (completely identical) to the previous input data value, providing the (closely) previous output data value as the current output data value.

[0110] Therefore, the execution channel sequentially processes two or more execution threads (within the same thread group) and provides processing results for the execution threads. This preferably includes the execution channel (processing level) providing a first output data value for the first execution thread among the two or more execution threads, and then (immediately thereafter) providing a second output data value for the next execution thread among the two or more execution threads.

[0111] Specifically, the first output data value for the first execution thread is provided through the execution channel (processing level) by performing processing operations on the first input data value associated with the first execution thread; and

[0112] The second output data value for the next executing thread is provided through the following processing:

[0113] Determine whether the first input data value is the same as the second input data value associated with the next execution thread; and

[0114] When it is determined that the first input data value and the second input data value are the same, the first output data value is provided as the second output data value (and no (omitted) processing operation is performed on the second input data value); and

[0115] When it is not determined that the first input data value is the same as the second input data value (for example, when it is determined that the first input data value is different from the second input data value), the second output data value is provided by processing the second input data value through the execution channel (processing level).

[0116] The previous output data value can be provided as the current output data value as expected (and no (omitted) processing operation is performed).

[0117] In a preferred embodiment, each execution channel (processing level) is configured to store output data values ​​in an output memory (e.g., a register) during each execution cycle. Then, by preventing changes to previously stored output data values ​​from previous execution cycles in the output memory during the current execution cycle, the previously stored output data values ​​can and preferably are provided as the current output data values. This means that at the end of the current execution cycle, the previously stored output data values ​​should remain unchanged in the output memory (register), thus serving as if they were the output of the current execution cycle.

[0118] This operation can be achieved as desired, but in a preferred embodiment, clock gating is used. Therefore, it is preferable to prevent changes to the output data values ​​(for the processing level of the execution channel) stored in the output storage unit (register) by gating (blocking) the clock signal (used for the execution channel).

[0119] These implementations can further reduce power consumption because they prevent signal transitions and, moreover, reduce the power consumption of the clock tree. Moreover, these implementations are particularly advantageous because they reduce power consumption while providing appropriate output data values ​​for each execution thread without requiring cross-channel data paths, as is the case in settings where execution channels are disabled when input data values ​​are identical.

[0120] The execution channel (processing level) can perform processing operations on the execution threads that have been published to that execution channel in any suitable and expected manner. These processing operations can be any suitable and expected operation, and can be performed in any suitable and expected manner.

[0121] In a preferred embodiment, the execution channel is provided with one or more functional units, which operatively perform data processing operations on instructions executed by the execution threads. Each functional unit should, and in the embodiment, be capable of processing as many threads in parallel as the execution channel (therefore, each functional unit will include a set of multiple execution channels).

[0122] Depending on the required processing, a given thread (group) may be processed by a single functional unit (processor level) or by multiple functional units (processor levels). Therefore, each execution channel may generally comprise only a single functional unit, or it may comprise multiple functional units (and this is the case in the implementation). Each execution channel should, and in the implementation, include one or more functional units that are generally the same as those in other execution channels (so that each execution channel can operate in the same way with respect to threads).

[0123] When an execution channel comprises multiple functional units (processing levels), these units can be cascaded (e.g., a pipeline), with each unit sequentially performing its corresponding data processing operations on the execution thread. When multiple execution threads are deployed to an execution channel comprising cascaded functional units (pipelines), they can be processed in a pipelined manner. For example, different functional units (processing levels) can simultaneously perform their corresponding operations on different execution threads (deployed to the same execution channel), and new input threads can be accepted into the pipeline before the processing of a previous input thread is complete.

[0124] Each execution channel can contain any suitable number of functional units (processing levels). In a preferred embodiment, the number of functional units (processing levels) (“depth”) of an execution channel is equal to the number of threads issued to it by each thread group. Thus, for example, when four threads from a thread group (e.g., corresponding to a 2×2 “quadruple”) are issued to each execution channel, each execution channel preferably has four functional units (processing levels), and therefore has the capacity to process four threads at a time (“depth”). Other “depths” are also possible, such as two or eight functional units in each execution channel.

[0125] Functional units can include any desired and suitable functional unit that is operatively responsive to program instructions and performs data processing operations according to program instructions. Therefore, functional units in embodiments include one or more or all of the following: mathematical units (mathematical logic units) (addition, subtraction, multiplication, division, etc.), bit manipulation units (inversion, swapping, shifting, etc.), logical operation units (AND, OR, NAND, NOR, NOT, XOR, etc.), loading-type units (e.g., change, texture, or loading units in the case of graphics processors), and storage-type units (e.g., hybrid or storage units). In embodiments, functional units (at least) include mathematical units (i.e., units that operatively perform mathematical (mathematical) operations).

[0126] Functional units can be implemented as desired and in any suitable manner. They will include (be implemented as) suitable hardware elements, such as processing circuitry (logic).

[0127] In the implementation, the data processor also includes appropriate control circuitry (control logic) for controlling the execution channels (functional units that operate as execution channels) to perform desired and appropriate processing operations.

[0128] This can be accomplished using any suitable and desired control circuitry. In an implementation, the control circuitry includes an instruction fetch circuit and an instruction decode circuitry, which operatively decodes the instructions to be executed for the thread so that the execution channel executes the required instructions.

[0129] Preferably, all execution channels are provided with a common instruction fetching and decoding circuit (i.e., preferably one instruction fetching circuit and one instruction decoding circuit operatively fetch and decode the instruction that will subsequently be executed by all execution channels). In this case, all execution channels preferably execute the same instruction (at any time (within a given cycle)).

[0130] Therefore, in this implementation, a single instruction decoding circuit is provided that operatively decodes instructions for all execution channels, ensuring that all execution channels execute the same instruction at any given time (within a given cycle). This ensures that the threads of the thread group (“bundle”) run one instruction at a time in a lockstep manner.

[0131] Therefore, the method preferably includes (and the instruction execution processing circuitry is preferably configured accordingly) executing instructions in a program in response to instructions in a thread group (“bundle”), each executing thread within the thread group (“bundle”) executing instructions in the program (e.g., performing processing operations) before executing the next instruction in the program. Thus, it will be appreciated that, preferably, threads are published to the execution channel in response to (preferably each) (single) instructions in the executed program, in the manner of the invention.

[0132] The data processor can be any desired and suitable data processor, where execution threads can be processed together in a thread group. Generally, in implementations, the data processor is a data processor capable of performing vector (SIMD (Single Instruction Multiple Data)) processing, such as a graphics processor, vector processor, video processor, DSP, or CPU (when performing SIMD processing). In a preferred embodiment, the data processor is a graphics processor (graphics processing unit (GPU)).

[0133] The operations of the present invention can be performed on any suitable and desired program to be executed by the data processor. In the case of a graphics processor, the program can be, and in one embodiment, a (graphics) shader program. The program can be, for example, a geometry shader program (a program for performing geometry shading operations), a vertex shader program (a program for performing vertex shading operations), or a fragment shader program (a program for performing fragment shading operations).

[0134] The program will include a series of instructions to be executed by the execution thread. This set of instructions (sequences) to be executed by the program can be any desired and suitable instructions typically executed by multiple threads. Program instructions may include one or more, or all of the following: arithmetic (mathematical) operations (addition, subtraction, multiplication, division, etc.), bitwise operations (invert, swap, shift, etc.), logical operations (AND, OR, NAND, NOR, NOT, XOR, etc.), load-type instructions (e.g., change, texture, or load instructions in the case of graphics processing), and store-type instructions (e.g., mix or store instructions).

[0135] In one embodiment, the present invention is used when a data processor (the execution processing circuit of the data processor) is executing a (programmable) processing stage of a data processing pipeline. Therefore, in this case, the execution processing circuit executes a program (a set of instructions) to perform processing operations of the (programmable) processing stage of the data processing pipeline, wherein a thread group is published to the execution processing circuit for execution of the (programmable) processing stage in accordance with the present invention.

[0136] The operation of the present invention can be used, and in embodiments, for multiple processing stages of a data processing pipeline (wherein the pipeline includes multiple programmable processing stages). In embodiments, the operation performed in accordance with the present invention is used for all (programmable) processing stages that a data processor (e.g., a graphics processor) may need to execute.

[0137] A processing level can include any suitable and desired (programmable) processing level in a data processing pipeline.

[0138] In this implementation, the processing level is a programmable processing level in the graphics processing pipeline. In this case, the processing level in this implementation includes a programmable shading level (shader). The programmable processing level that the program is executing can be, for example, a geometry shading level (geometry shader), a vertex shading level (vertex shader), or a fragment shading level (fragment shader).

[0139] Operations performed according to the method of the invention can be performed by and for each program and / or (programmable) processing level executed by the data processor, or only for a particular class or type of program or processing level, and not for other classes or types of program or processing levels (e.g., in cases where the type of program or processing level is unlikely to involve similar input and / or output data, for different threads within a thread group).

[0140] Each execution thread and / or thread group can be associated with any suitable and / or required "work" item targeted by the program to be executed. For example, in the case of a graphics processor, each thread can correspond to a vertex or sample location, where a thread group corresponds to a suitable set of multiple vertices or sample locations. For example, each thread group ("bundle") can correspond to a graphics segment, where each thread in the thread group corresponds to a corresponding sample location represented by that segment. For example, each thread group can correspond to one or more (e.g., four) 2×2 sample location "quadruples" that will be processed through the graphics processing pipeline.

[0141] Thread groups can be provided by an appropriate thread group generator and scheduler of the data processor, which generates thread groups for execution. This can depend, for example, on what "work items" the threads and thread groups represent. For instance, if a thread corresponds to a pixel / sample point, there will be rasterization step / level generation threads. For vertex shading or graphics computation processing, there will be appropriate vertex processing / computation processing levels, which, for example, generate threads and thread groups. Of course, other setups are also possible.

[0142] The results generated by executing instructions for the active thread of the thread group can be used as desired. For example, they can be output, such as to external memory, and / or they can be provided to and used by other instructions in a set of instructions executed (in the program).

[0143] In all cases, the results can be used by the data processor as the generated output. The output generated by the data processor can be any suitable desired output, such as rendering output in the case of a graphics processor, such as frames (images) to be displayed, texture (in rendering to texture) operations, etc.

[0144] This operation can then be repeated for the next thread group, and so on.

[0145] The invention has been described above with general reference to the operation of a data processor. In the case where the data processor includes multiple processing cores, each processing core can and in one embodiment can operate in the manner of the invention (i.e., each processing core has its own corresponding execution processing circuitry, thread dispatching circuitry, etc., all of which can operate in accordance with the manner of the invention).

[0146] In some embodiments, the data processor includes and / or communicates with one or more memories and / or memory devices that store the data described herein and / or software for performing the processes described herein. The data processor may also communicate with a host microprocessor and / or with a display that displays images based on data generated by the data processor.

[0147] In one embodiment, the data processor is part of an overall data processing system that includes one or more memories and / or memory devices and a host processor (and optionally, a display). In another embodiment, the host microprocessor operatively executes applications that require data processing by the data processor, wherein the data processor operates in accordance with the manner of the invention when data needs to be processed by an application executing on the host processor.

[0148] Of course, other settings will be possible.

[0149] This invention can be used for all forms of output that can be generated using a data processor (and processing pipeline). For example, in the case of graphics processing, a graphics processing pipeline can generate frames for display, output rendered to textures, etc. Output data values ​​from the processing are exported externally (e.g., to main memory) for storage and use, such as exported to a frame buffer for display.

[0150] This invention is applicable to any suitable form or configuration of data processors and data processing systems. It is particularly applicable to tile-based graphics processors and graphics processing systems. Therefore, in embodiments, the data processor is a tile-based graphics processor (and pipeline).

[0151] In implementation, the various functions of the invention are performed on a single data processing platform that generates and outputs data, such as data for display devices (e.g., rendered fragment data written to a frame buffer).

[0152] This invention is applicable to any suitable form or configuration of data processors and data processing systems. In embodiments, the various functions of this invention are performed on a single data processing platform for generating and outputting data.

[0153] This invention can be implemented in any suitable system, such as a properly configured microprocessor-based system. In a preferred embodiment, the invention is implemented in a computer and / or microprocessor-based system.

[0154] The various functions of this invention can be implemented in any desired and suitable manner. For example, the functions of this invention can be implemented in hardware or software as needed. Thus, for example, unless otherwise stated, the various functional elements, stages, and "devices" of this invention may include suitable one or more processors, one or more controllers, functional units, circuit systems / circuits, processing logic, microprocessor architectures, etc., which perform various functions operatively, such as suitable dedicated hardware elements (processing circuits) and / or programmable hardware elements (processing circuits) that can be programmed to operate in a desired manner.

[0155] As those skilled in the art will understand, it should also be noted that the various functions of the present invention can be replicated and / or performed in parallel on a given processor. Similarly, processing levels can share processing circuitry if desired.

[0156] Depending on any hardware necessary to perform the specific functions described above, the data processing system and pipeline may additionally include any one or more or all of the conventional functional units included in the data processing system and pipeline.

[0157] Those skilled in the art will also understand that, as appropriate, all embodiments of the described embodiments of the invention may and do include any one or more or all of the preferred and optional features described herein.

[0158] The method according to the invention can be implemented at least in part using software (e.g., a computer program). Therefore, it will be understood that, in another embodiment, the invention provides: computer software specifically adapted to perform the method described herein when mounted on a data processor; computer program elements comprising computer software code portions for performing the method described herein when program elements are run on a data processor; and a computer program comprising code adapted to perform all steps of the method or the method described herein when the program is run on a data processing system. The data processor may be a microprocessor system, a programmable FPGA (Field-Programmable Gate Array), etc.

[0159] The invention also extends to computer software carriers that include such software, which, when used to operate a processor, renderer, or microprocessor system including a data processor, causes the data processor to perform the steps of the method of the invention together with the processor, renderer, or microprocessor system. Such computer software carriers can be physical storage media (such as ROM chips, CD-ROMs, RAM, flash memory, or disks) or signals (such as wired electrical signals, optical signals, or wireless signals such as those to satellites).

[0160] It will also be understood that not all steps of the method of the present invention need to be performed by computer software. Therefore, in a broader sense, the present invention provides computer software and such software is installed on a computer software carrier to perform at least one step of the method set forth herein.

[0161] Therefore, the present invention can be suitably embodied as a computer program product for use with a computer system. Such an implementation may include a series of computer-readable instructions fixed on a tangible, non-transitory medium, such as a computer-readable medium, e.g., a disk, CD-ROM, ROM, RAM, flash memory, or hard disk. Such an implementation may also include a series of computer-readable instructions capable of being transmitted to a computer system via a modem or other interface device through a tangible medium (including, but not limited to, optical or analog communication lines) or invisibly using wireless technologies (including, but not limited to, microwave, infrared, or other transmission technologies). This series of computer-readable instructions embodies all or part of the functions previously described herein.

[0162] Those skilled in the art will understand that such computer-readable instructions can be written in a variety of programming languages ​​for use with many computer architectures or operating systems. Furthermore, any current or future storage technology (including, but not limited to, semiconductor, magnetic, or optical) can be used to store such instructions, or any current or future communication technology (including, but not limited to, optical, infrared, or microwave) can be used to transmit such instructions. It is conceivable that such a computer program product can be distributed as a removable medium with accompanying printed or electronic documentation (e.g., shrink-wrapped software, such as a computer system pre-loaded on a system ROM or fixed disk), or distributed from a server or electronic bulletin board via a network (e.g., the Internet or the World Wide Web). Attached Figure Description

[0163] Various embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, wherein:

[0164] Figure 1 An exemplary graphics processing system is shown;

[0165] Figure 2A graphics processing pipeline that can operate in accordance with the present invention is illustrated schematically;

[0166] Figure 3 The compilation of a shader program executed by a graphics processing pipeline is illustrated schematically.

[0167] Figure 4 The configuration of the execution channel in an embodiment of the present invention is illustrated schematically;

[0168] Figure 5 The illustration schematically shows the configuration of the execution channel pipeline in an embodiment of the present invention;

[0169] Figure 6 The illustration schematically shows the configuration of the execution channel pipeline in an embodiment of the present invention;

[0170] Figure 7 The diagram schematically illustrates threads in a group (“bundle”) of threads divided among “quadruple” in an embodiment of the invention;

[0171] Figure 8 The settings for publishing threads to an execution channel are shown;

[0172] Figure 9 The diagram schematically illustrates a thread published to the execution channel in an embodiment of the invention;

[0173] Figure 10A The sequence of sampling location blocks that can be processed according to a preferred embodiment is shown. Figure 10B The sequence of sampling locations that can be processed is shown;

[0174] Figure 11 The illustration schematically depicts the processing for executing program instructions in an embodiment of the present invention; and

[0175] Figure 12 The illustration schematically depicts the processing for executing program instructions in another embodiment of the invention.

[0176] In the accompanying drawings, the same reference numerals are used for the same components in appropriate places. Detailed Implementation

[0177] Several embodiments of the invention will now be described in the context of processing computer graphics for display. However, it will be understood that the techniques described herein for processing execution thread groups can be used in other non-graphics contexts where thread groups are used.

[0178] Figure 1This illustrates a typical graphics processing system. An application 2 (e.g., a game) running on host processor 1 will request graphics processing operations from the associated graphics processing unit (GPU) (graphics processor) 3. To this end, the application will generate API (Application Programming Interface) calls, which are interpreted by a driver 4 running on host processor 1 for graphics processor 3 to generate appropriate commands for graphics processor 3 to produce the graphics output requested by application 2. To facilitate this, a set of "commands" is provided to graphics processor 3 in response to commands from application 2 running on host system 1 for graphics output (e.g., generating frames to be displayed).

[0179] Figure 2 The graphics processing pipeline 33 executed by the graphics processor 3 is shown in more detail.

[0180] Figure 2 The graphics processing pipeline 33 shown is a tile-based renderer that will produce a tile-based array of rendering output data (e.g., the output frames to be generated).

[0181] In tile-based rendering, instead of processing the entire render output (e.g., a frame) all at once as in immediate mode rendering, the render output (e.g., a frame to be displayed) is typically divided into multiple smaller sub-regions called "tiles". Each tile (sub-region) is rendered separately (usually one after another), and then the rendered tiles (sub-regions) are reassembled to provide the complete render output, such as the frame for display. In such a setup, the render output is typically divided into sub-regions (tiles) of regular size and shape (usually squares or rectangles, for example), but this is not crucial.

[0182] An array of render output data can typically be an output frame designed to be displayed on a display device such as a screen or printer, but it can also include, for example, intermediate data designed to be used in later rendering processes (also known as "render to texture" output), etc.

[0183] When displaying computer graphics, they are typically first defined as a series of primitives (polygons), and then these primitives are divided (rasterized) into graphic segments for subsequent graphics rendering. During regular graphics rendering operations, the renderer modifies the color (red, green, blue, RGB) and transparency (alpha, α) data associated with each segment to ensure correct display. Once the segments have been fully rendered, their associated data values ​​are stored in memory, ready for output, such as for display.

[0184] Figure 2The main elements and pipeline stages of the graphics processing pipeline 33 related to the operation of this embodiment are shown. As those skilled in the art will understand, there may be other elements not shown in the graphics processing pipeline. Figure 2 Other elements shown in the text. It should also be noted here that... Figure 2 This is merely illustrative, and the functional units and pipeline stages shown, for example, can share a significant amount of hardware circuitry in practice, even if they are... Figure 2 The middle is schematically shown as a separate level. It will also be recognized that, as Figure 2 The various stages, elements, and units of the graphics processing pipeline shown can be implemented as desired, and will accordingly include, for example, appropriate circuitry and / or processing logic for performing the necessary operations and functions.

[0185] like Figure 2 As shown, the graphics processing pipeline 33 includes multiple stages, including a vertex shader 20, a shell shader 21, a tessellation unit 22, a domain shader 23, a geometry shader 24, a rasterization stage 25, an early Z (depth) and stencil test stage 26, a fragment shader stage 27, a late Z (depth) and stencil test stage 28, a blending stage 29, a tile buffer 30, and a downsampling and write-out (multi-sample parsing) stage 31.

[0186] Vertex shader 20 acquires input data values ​​associated with vertices as defined for the output to be generated, and processes these data values ​​to generate a corresponding set of "vertex-shaded" output data values ​​for use by subsequent stages of the graphics processing pipeline 33. For example, vertex shading modifies the input data to take into account lighting effects in the image to be rendered.

[0187] The shell shader 21 operates on a set of patch control points and generates additional data called patch constants. The tessellation level 22 subdivides the geometry to create a higher-order representation of the shell. The domain shader 23 operates on the vertices output by the tessellation level (similar to a vertex shader), and the geometry shader 24 processes the entire primitive, such as a triangle, point, or line. These levels, together with the vertex shader 20, efficiently perform all necessary fragment front-end operations, such as transformation and lighting operations, and primitive setup, to set up the primitives to be rendered in response to commands and vertex data provided to the graphics processing pipeline 33.

[0188] The rasterization stage 25 of the graphics processing pipeline 33 operates to rasterize the primitives constituting the rendering output (e.g., an image to be displayed) into individual graphic fragments for processing. To this end, the rasterizer 25 receives graphic primitives for rendering, rasterizes the primitives into sample points, and generates graphic fragments with appropriate positions for rendering the primitives (representing suitable sample positions).

[0189] The segments generated by the rasterizer are then sent to the rest of the pipeline for processing.

[0190] The early Z / stencil level 26 performs a Z (depth) test on the fragments received from rasterizer 25 to see if any fragments can be discarded (culled) at this level. To do this, it compares the depth values ​​(associated with the fragments) of the fragments published from rasterizer 25 with the depth values ​​of already rendered fragments (which are stored in the depth (Z) buffer 30, which is part of the tile buffer) to determine if new fragments will be occluded by already rendered fragments. Simultaneously, an early stencil test is performed.

[0191] The fragments that pass the early Z-test and stencil test at level 26 are then sent to fragment shading level 27. Fragment shading level 27 performs appropriate fragment processing operations on the fragments that pass the early Z-test and stencil test to process the fragments to generate appropriate rendered fragment data.

[0192] The fragment processing can include any suitable and desired fragment shading processing, such as executing a fragment shader program on the fragment, applying texture to the fragment, applying fog to the fragment, or other operations, to generate appropriate fragment data. In this embodiment, fragment shading level 27 has the form of a shader pipeline (programmable fragment shader).

[0193] Then comes the "post-processing" fragment Z and stencil test level 28, which specifically performs a pipeline-end depth test on the shaded fragments to determine whether the rendered fragment will actually be seen in the final image. This depth test compares, as known in the art, the depth value (associated with the fragment) of the fragment published from fragment shading level 27 with the depth value of the rendered fragment (stored in the depth buffer), using the Z-buffer value for the fragment's position stored in the Z-buffer in the tile buffer 30 to determine whether the fragment data of the new fragment should replace the fragment data of the rendered fragment. This post-processing fragment depth and stencil test level 28 also performs any necessary "post-processing" alpha and / or stencil tests on the fragment.

[0194] Then, if necessary, the fragments from the later fragment test stage 28 will be blended with the fragments already stored in the tile buffer 30 in the mixer 29. Any other necessary remaining operations on the fragments, such as dithering, etc. (not shown), will also be performed at this stage.

[0195] Finally, the (mixed) output fragment data (values) are written to tile buffer 30, from where they can be output to frame buffer for display, for example. The depth values ​​of the output fragments are also appropriately written to the Z buffer within tile buffer 30. The tile buffer stores color and depth buffers, which store appropriate color or Z values ​​for each sample point represented by the buffer (essentially for each sample point of the tile being processed). These buffers store arrays of fragment data representing a portion (tiles) of the entire rendered output (e.g., the image to be displayed), where each group of sample values ​​in the buffer corresponds to a corresponding pixel in the entire rendered output (e.g., each 2×2 group of sample values ​​could correspond to an output pixel, where 4× multisampling is used).

[0196] The tile buffer is provided as part of the RAM located (locally) in the graphics processing pipeline (chip).

[0197] Data from tile buffer 30 is input to downsampled (multi-sample resolution) write-out unit 31 and thereby output (write-back) to an external memory output buffer, such as a frame buffer of a display device (not shown). The display device may include, for example, a monitor or printer, which includes a pixel array, such as a computer monitor.

[0198] The downsampling and write-out unit 31 downsamples the fragment data stored in the tile buffer 30 to an appropriate resolution for the output buffer (device) (i.e., such that a pixel data array corresponding to the pixels of the output device is generated) to generate output values ​​(pixels) for output to the output buffer.

[0199] While a tile of the rendered output has been processed and its data exported to main memory (e.g., to a frame buffer in main memory (not shown)) for storage, the next tile is processed, and so on, until enough tiles have been processed to generate the entire rendered output (e.g., the frame (image) to be displayed). The process is then repeated for the next rendered output (e.g., the frame), and so on.

[0200] Of course, other settings for the graphics processing pipeline 33 are also possible.

[0201] The above describes Figure 1 The diagram illustrates certain characteristics of the operation of the graphics processing system. An embodiment according to the present invention will now be described. Figure 1 Other features of the operation of the graphics processing system shown.

[0202] from Figure 2As can be seen, the graphics processing pipeline 33 includes multiple programmable processing or "shader" levels, namely vertex shader 20, shell shader 21, domain shader 23, geometry shader 24, and fragment shader 27. The programmable shader levels execute corresponding shader programs, which have one or more input variables and generate sets of output variables, and these programs are provided by the application.

[0203] To this end, Application 2 provides shader programs implemented using a high-level shader programming language (such as GLSL, HLSL, OpenCL, etc.). The shader language compiler then translates these shader programs into binary code for the target graphics processing pipeline 33. This may include creating one or more intermediate representations of the program within the compiler. The compiler may, for example, be part of Driver 4, where special API calls are provided to make the compiler run. Therefore, compiler execution can be viewed as part of the draw call preparation performed by the driver in response to API calls generated by the application. (Of course, other compiler settings are also possible.)

[0204] Figure 3 This is illustrated, and it shows that the application 2 provides the driver 4 with a shader program in the form of a high-level shader programming language 301, which the driver 4 then compiles 302 into binary code 303 for the graphics processing pipeline 33.

[0205] As described above, each shader in the graphics processing pipeline is a processing level that performs graphics processing by running applets for various "jobs" in the graphics output to be generated (in this context, "jobs" are typically vertices or sampled locations). For each job to be processed, an execution thread for executing the corresponding shader program is assigned to the appropriate programmable processing circuit, which then executes the shader program for the execution thread in question.

[0206] This implementation relates to a system in which threads that are to execute shader programs can be organized into groups (“bundles”) of threads that execute one instruction at a time in a lockstep manner.

[0207] For example, in the case of fragment shader 27, the executing fragment shader program can be run once for each sample location (or point) to be processed, generating an execution thread for each sample location. The sample locations (and therefore their corresponding execution threads) can be organized into multiple groups of multiple sample locations (and corresponding threads) and processed, each group corresponding to multiple sample locations associated with a set of one or more graphic fragments.

[0208] In this embodiment, as will be discussed further below, the sampling positions are organized into 2×2 blocks of sampling position "quadruples". The groups of four "quadruples" (corresponding fragments) are then processed in the fragment shader as corresponding thread groups ("bundles"), each thread group ("bundle") comprising a total of sixteen threads, corresponding to the sixteen sampling positions (sampling positions of four 2×2 "quadruples"). The 16 threads in the thread group ("bundle") then execute the fragment shader program one instruction at a time in lockstep. Of course, other thread groupings are also possible.

[0209] In such a setup, to execute the threads of a thread group, for example, to perform fragment coloring operations, the threads of the thread group will be appropriately assigned to the appropriate functional unit, such as the math processing unit, to perform the processing operations required by the shader program in question. Where threads can be organized into a thread group and executed, then typically, the functional unit will be configured with multiple execution channels, each capable of performing the processing operations for the threads of the thread group.

[0210] In this way, each functional unit (or a group of related functional units) will be set up and run as multiple execution channels, which can be issued threads of the thread group for execution. When the thread group is to be executed, the appropriate control logic issues the relevant data and instructions to be executed to the appropriate execution channel of the functional unit or group of functional units, so that the functional unit can execute the instructions in question on the thread of the thread group.

[0211] Figure 4 This has been illustrated, and a suitable control logic (circuit) in the form of an execution processing circuit 42 configured with four execution channels 41 and a "reserve station" 40 is shown. This control logic (circuit) is used to issue appropriate data and instructions for the individual threads of the thread group to the execution channels 41 of the set of execution channels according to this embodiment. (The reserve station (control logic) 40 will receive the threads to be executed, for example, from the thread generator or thread generation process of the graphics processor.) It should be understood that in other embodiments, the execution processing circuit 42 may be configured with fewer or more than four execution channels, such as two or eight.

[0212] Functional units may include one or more or all of the following: mathematical units (mathematical logic units) (addition, subtraction, multiplication, division, etc.), bit manipulation units (inversion, swapping, shifting, etc.), logical operation units (AND, OR, NAND, NOR, NOT, XOR, etc.), load-type units (e.g., change, texture, or load units in the case of a graphics processor), and storage-type units (e.g., hybrid or storage units, etc.).

[0213] Each execution channel 41 of the execution processing circuit 42 can also access (and have access to) a set of multiple registers 43 for storing data values ​​associated with and used by the execution channel (i.e., for storing processed data values ​​for the execution thread currently being executed by the execution channel). This then facilitates processing the execution thread and its data values ​​within the execution channel without (always) requiring access to memory (access to the memory system of the graphics processing system). The registers of the execution channels can be set in the register file library as desired and appropriate.

[0214] Figure 5 The execution channel 41 of the graphics processor 3 in the form of a mathematical unit pipeline is shown in more detail, which can perform mathematical processing operations for the execution thread that has been issued to it by the control logic 40 for execution, according to this embodiment.

[0215] Figure 5 The pipeline 41 performs graphical processing on the input data values ​​and then provides the result of the processing as the output data value. The input data values ​​are stored as binary data values ​​in the input register 501, and the output data values ​​are stored as binary data values ​​in the output register 502.

[0216] The processing operations performed in the production line can be any suitable processing operations, and in this embodiment, they are performed as a series of four processing operations. Therefore, as... Figure 5 As shown, in this embodiment, pipeline 41 is configured as a pipeline (series) of four math processing stages P0-P3, each of which operably executes one instruction during clock cycle 505. It will be understood that in other embodiments, the "depth" of the pipeline may be less than or more than four processing stages, for example, two or eight processing stages.

[0217] like Figure 5 As shown, in each processing stage P0-P3, binary data values ​​stored in flip-flops (latches) 510-513 are provided as inputs to combinational logic circuits 520-523 (functional units), which then perform, for example, mathematical operations on the inputs to produce binary outputs. The outputs of combinational logic circuits 520-523 can then be stored in flip-flops (latches) and can be provided as inputs to the next stage (functional unit), and so on. The final output data value of the pipeline is the output of combinational logic circuit 523 (functional unit) in the last stage P3 of pipeline 41.

[0218] like Figure 5As shown, the pipeline (execution channel) 41 is operated under the control of the pipeline control unit 503, which instructs the combinational logic circuits 520-523 (functional units) of each stage P0-P3 to perform operations during a clock cycle, for example by issuing appropriate opcodes to the combinational logic circuits 520-523. The pipeline control unit 503 is controlled by the instruction decoding circuit 504, which operates to decode the instructions in the executed shader program and enables the pipeline control unit 503 to control the pipeline (execution channel) 41 to perform the graphics processing operations required for executing the shader instructions in question.

[0219] Pipeline 41 may also include clock gates 530-533, which are used for clock gating under the control of clock gate control circuit 506, as will be discussed further below.

[0220] For clarity, Figure 5 Only a single execution channel 41 is shown in detail. However, in this embodiment, the execution processing circuitry 42 is configured with four execution channels 41, which share the instruction decoding circuitry 504 and the pipeline control circuitry 503, such that a single instruction in the shader program is decoded and then executed by all four execution channels in a given cycle. Therefore, instructions in the shader program are executed via a physical SIMD (Single Instruction Multiple Data) mathematical data path.

[0221] This is Figure 6 Example in. like Figure 6 As shown, in this embodiment, the execution processing circuit 42 is configured with four execution channels: channels 0-3, which are provided by four math unit pipelines 41. Each math unit pipeline 41 includes four stages P0-P3, which operate under the control of the (shared) pipeline control circuit 503, as referred to above. Figure 5 The subject of discussion.

[0222] As discussed above, it is generally possible to set up threads in groups (“bundles”) that match the number of execution channels provided. In this case (in a setting that does not constitute part of the invention), each thread in the thread group can be published to a corresponding execution channel among the multiple execution channels for execution, i.e., such that the execution channel has only one execution thread published from the thread group (“bundle”). Such a setup can allow individual shader program instructions to be executed for all threads in the thread group in a single cycle, thereby improving, for example, the performance of single-threaded execution.

[0223] However, in this embodiment, the execution threads are configured as thread groups (“bundles”) each comprising sixteen threads T0-T15, and the execution processing circuit 42 is configured with four execution channels 41. Therefore, there are fewer execution channels than execution threads in the thread groups (“bundles”). Multiple threads in the thread groups (“bundles”) are correspondingly assigned to the same execution channel and executed over multiple cycles. For example, this can allow the latency of floating-point calculations (e.g., addition or multiplication) to be hidden through multi-cycle execution of individual instructions. Furthermore, as described above, by assigning multiple execution threads of the thread groups (“bundles”) to the same execution channel for execution, the likelihood of signal transitions occurring can be reduced, thereby achieving energy savings.

[0224] To facilitate these setups, the reserve station 40 operationally publishes multiple execution threads from thread groups (“bundles”) to the same execution channel 41 for execution. For example... Figure 6 As shown, each execution channel pipeline 41 then has a corresponding input selection stage 603 to select an appropriate input thread from the multiple execution threads 601 that have been issued to it for execution. The execution channel, having been issued multiple execution threads from the same thread group (“bundle”) for execution, then executes these execution threads sequentially, one after another, over multiple cycles.

[0225] As illustrated, for example in Figure 8 and Figure 9 As illustrated, each execution channel pipeline 41 can execute multiple execution threads sent to it in a pipelined manner. For example, each pipeline stage (functional unit) P0-P3 sequentially performs its corresponding operation for the execution thread, and while the preceding pipeline stage (functional unit) is performing its corresponding operation for the second execution thread, the subsequent pipeline stage (functional unit) can perform its corresponding operation for the first execution thread. That is, the execution channel pipeline 41 can accept a new input thread before the processing of the previous input thread is completed.

[0226] When each level P0-P3 performs its corresponding operation on the execution thread to be published to the corresponding execution channel, the result allocation level 604 provides the entire processing result as output to the appropriate thread 602.

[0227] When the shader program instructions are executed for all sixteen execution threads in the thread group (“bundle”) in this manner (using only four execution channels), the next shader program instruction can be executed (in the same manner), and so on. Thus, each of the sixteen threads T0-T15 in the thread group (“bundle”) executes the fragment shader program one instruction at a time in a lockstep manner.

[0228] As discussed above, in this embodiment, each of the sixteen threads in the thread group (“bundle”) corresponds to a specific sampling position (associated with the corresponding sampling position), for example, for the output surface (frame) used for display. Figure 7 As illustrated, the sixteen threads within the thread group (“bundle”) 601 are further grouped into four thread group subsets 61A-61D, each subset comprising four threads and corresponding to four sampling positions of a 2×2 block (“quadruple”) of (closely) adjacent sampling positions 71A-71D.

[0229] Therefore, there exists a first thread subset 61A, including threads T0-T3 corresponding to the first 2×2 sampling position block (“quadruple”) 71A; a second thread subset 61B, including threads T4-T7 corresponding to the second 2×2 sampling position block (“quadruple”) 71B; a third thread subset 61C, including threads T8-T11 corresponding to the third 2×2 sampling position block (“quadruple”) 71C; and a fourth thread subset 61D, including threads T12-T15 corresponding to the fourth 2×2 sampling position block (“quadruple”) 71D.

[0230] Figure 8 This illustrates one method for dividing thread groups (“bundles”) 601 across four execution channels 41 into sixteen threads T0-T15 for execution. For example... Figure 8 As shown, in this implementation, threads are assigned to execution channels according to their index order. Therefore, the first thread T0 is assigned to the first execution channel, channel 0, the second thread T1 is assigned to the second execution channel, channel 1, and so on. Then, when an execution thread is assigned to each execution channel, the next thread in the sequence is again assigned to the first execution channel; that is, in this example, the fifth thread T4 is assigned to the first execution channel, channel 0, and so on.

[0231] Figure 9 An example of a preferred embodiment of the invention is shown for dividing threads among execution channels, which can provide further energy savings. For example... Figure 9 As shown, with Figure 8 Compared to the previous implementation, all threads of a specific subset of thread groups are published to the same execution channel for execution; that is, threads corresponding to a specific 2×2 block (“quadruple”) at the sampling position are published to the same execution channel for execution. For example... Figure 9As illustrated in this embodiment, the number of "quadruple pairs" is the same as the number of execution channels, so a thread for one of the "quadruple pairs" is assigned to each execution channel. (However, in other embodiments, threads for two (or more) "quadruple pairs" can be published to the same execution channel for processing, or two threads for a "quadruple pair" can be published to one execution channel, and the other two threads for that "quadruple pair" can be published to another execution channel.)

[0232] Therefore, as Figure 9 As shown, threads T0-T3 targeting the first "quadruple" 71A are published to the first execution channel channel 0 for execution. Threads T4-T7 targeting the second "quadruple" 71B are published to the second execution channel channel 1 for execution. Threads T8-T11 targeting the third "quadruple" 71C are published to the third execution channel channel 2 for execution. Threads T12-T15 targeting the fourth "quadruple" 71D are published to the fourth execution channel channel 3 for execution.

[0233] The applicant has recognized that, for example, in an image, data values ​​of image elements that are closer together are more likely to be similar to each other than data values ​​of image elements that are separated from each other. Since each “quadruple” corresponds to a 2×2 block of (closely) adjacent sampling locations, this means that the four data values ​​associated with a “quadruple” are more likely to be the same or similar to each other than other data values ​​in the image.

[0234] This means that by publishing threads targeting "quadruples" to the same execution channel for execution, the execution channel should be more likely to perform the same processing operations on the same or similar, or potentially the same or similar, data values ​​consecutively.

[0235] As discussed above, the applicant has recognized that when the execution channel performs the same processing operations on the same or similar data values ​​consecutively, the number of physical signal transitions (e.g., in registers or combinational logic) that occur to perform these processing operations should be less than in other cases, such as when the consecutive processing operations performed by the execution channel have very different data values. This means that energy required to cause signal transitions can be saved.

[0236] For example, refer to again Figure 5 Energy is consumed whenever the input data value stored in input register 501, the output data value stored in output register 502, or the intermediate data value stored in flip-flops 510-513 changes. Moreover, energy tends to be consumed more when the data value changes significantly compared to when the data value changes slightly, because the most significant bit may remain unchanged in the case of a small change.

[0237] Therefore, if the data value being processed by the execution channel changes frequently, it will consume more energy than if the data value changes less frequently. Furthermore, larger data value changes tend to consume more energy compared to smaller changes.

[0238] Therefore, by publishing execution threads for "quadruple" to the same execution channel for execution, the likelihood of the execution channel performing the same processing operation on the same or similar data values ​​consecutively can be increased, thereby reducing the total number of signal transitions and thus reducing energy consumption. It will thus be appreciated that the present invention can reduce the energy consumption of data processors (e.g., graphics processing units (GPUs)).

[0239] Figure 10A and Figure 10B This illustrates how further reductions in signal conversion and energy usage can be achieved according to the implementation method. Figure 10A This shows that the four sampling positions of the "quadruple" are processed by the execution channel in "Z" (Morton) order. From Figure 10A As can be seen, following this order, the execution channel first processes the top-left sampling position, then there's a "horizontal jump" to the top-right sampling position, followed by a "diagonal jump" to the bottom-left sampling position, and finally another "horizontal jump" to the bottom-right sampling position. However, it will be apparent that the diagonal distance is greater than the horizontal (or vertical) distance. This means that diagonally separated sampling positions are more likely to be different from each other than horizontally (or vertically) separated sampling positions.

[0240] Figure 10B This shows that the four sampling positions of the "quadruple" are processed by the execution channel in an alternative "U" order. From Figure 10B It can be seen that, in this order, with Figure 10A Compared to the "Z" (Morton) sequence, it performs consecutive processing operations only at horizontally or vertically separated sampling locations, thus avoiding "diagonal jumps." This then means that... Figure 10A Compared to the "Z" (Morton) sequence, with Figure 10B The "U" order makes consecutive data values ​​more likely to be similar to each other. Therefore, processing threads for "quadruple" in "U" order can further reduce the total number of signal transitions and thus reduce energy consumption.

[0241] Figure 11This illustration schematically illustrates a process according to an embodiment of executing program instructions by grouping multiple threads into bundles (thread groups). In this embodiment, a bundle (thread group) comprises multiple subsets of threads (e.g., denoted as "quadruple"), wherein each bundle subset (thread group subset) contains the same number of threads as other bundle subsets, and the number of bundle subsets is equal to the number of execution channels of the mathematical logic unit (ALU) (functional unit). The threads of each bundle subset (thread group subset) correspond to blocks of adjacent sampling positions (e.g., 2×2 "quadruple"), thus, as discussed above, it is likely that the same or similar input data values ​​(operands) will be processed.

[0242] like Figure 11 As shown, the process begins in step 1101, where the bundle input data value (operand) is read from the operand buffer, and then in step 1102 the thread selector index is initialized to 0.

[0243] In step 1103, a thread is selected from each bundle set, and in step 1104, the input for the selected thread is sent to the corresponding (different) mathematical logic unit (ALU) execution channel for processing. In step 1105, synchronously with the clock signal, each ALU execution channel performs the (same) operation on its corresponding operand, for example, according to the received opcode. Then, in step 1106, the output of each ALU execution channel is written to the appropriate output register. It should be understood that each execution channel can perform multiple operations over multiple clock cycles, for example in an implementation where each execution channel includes a pipeline of multiple ALU (functional unit) levels (where, for example, one pipeline level is executed each clock cycle).

[0244] In step 1107, the thread selector index is incremented, and in step 1108, it is determined whether there are more threads to process in the bundle. If so, processing loops back to step 1103 to process the next thread for each execution channel. Therefore, another thread is selected from each bundle (for each corresponding execution channel), and in step 1104, the input for each thus selected thread is sent to the same mathematical logic unit (ALU) execution channel as the previous thread selected from the same bundle for processing. Thus, each thread in the bundle is processed by the same mathematical logic unit (ALU) execution channel.

[0245] In step 1105, synchronized with the (next) clock signal, each ALU execution channel performs the (same) operation on its corresponding operand. Then, in step 1106, the output of each ALU execution channel is written to the appropriate output register, and in step 1107, the thread selector index is incremented again.

[0246] Then, in step 1108, it is determined again whether there are more threads to process in the bundle, and if so, steps 1103 to 1108 are repeated as described above. Otherwise, if there are no more threads to process, the output of all threads in the bundle is written to the operand buffer in step 1109.

[0247] Then you can repeat the process for the next thread group and for the next instruction in the currently executing program. Figure 11 The entire process.

[0248] Now refer to Figure 5 and Figure 12 Another implementation method is described.

[0249] As discussed above, when a first and second execution thread from the same thread group (“bundle”) are posted to the same execution channel for execution, the execution channel will first process the instructions for the first execution thread, and then process the same instructions for the second execution thread. Therefore, for example, refer to… Figure 5 The combinational logic circuits 520-523 will each perform processing operations for the first execution thread, and then perform the same processing operations for the second execution thread. This means that if the inputs for the first thread and the second thread are the same, then their outputs will also be the same.

[0250] Therefore, in this embodiment, the processing level processes the input to provide output for the first thread within a thread group (“bundle”) or subset of the thread group. It then determines whether the next input for the processing level to the next thread within the thread group (“bundle”) or subset of the thread group is the same as the first input. When it is identified that the second input is the same as the first input, it can be assumed that the second output will also be the same as the first output. Therefore, in this case, the processing level does not need to repeat the processing operation for the second thread, but can instead use the output for the first thread as the output for the second thread.

[0251] In this implementation, this is achieved through clock gating. For example... Figure 5 As shown, each processing stage P0-P3 of the execution channel pipeline 41 includes clock gates 530-533, which operate under the control of the (shared) clock gate control circuit 506. When the clock gate for a processing stage is set to "on", the clock signal from clock 505 can reach that processing stage, so that signal transitions can occur in the corresponding flip-flops (latches) 510-513 during that clock cycle. However, when the clock gate is closed, the clock signal is blocked, i.e., prevented from reaching the processing stage, so that no signal transition occurs for that processing stage during that clock cycle.

[0252] Therefore, in this embodiment, when it is identified that the current input to the processing level is the same as a previous input to the processing level (for threads in the same thread group (“bundle”), the processing level is clock-gated to prevent signal transitions from occurring within that clock cycle. Thus, the output of the processing level will remain unchanged within that clock cycle; that is, the output will be the same as the previous output. This avoids unnecessary signal transitions, thereby achieving further energy savings. Energy consumption of the clock tree can also be reduced.

[0253] Figure 12 This schematically illustrates such processing according to this embodiment when multiple threads grouped into bundles are executing program instructions. In this embodiment, as... Figure 11 In this implementation, a bundle (thread group) comprises multiple thread subsets, each bundle subset (thread group subset) containing the same number of threads as other bundle subsets, and the number of bundle subsets is equal to the number of execution channels of the mathematical logic unit (ALU) (functional unit). The threads of each bundle subset correspond to blocks of adjacent sampling positions (e.g., 2×2 "quadruples"), thus they are more likely to process the same or similar input data values ​​(operands).

[0254] like Figure 12 As shown, as in Figure 11 In this implementation, the process begins at step 1201, where bundle input data values ​​(operands) are read from the operand buffer, and then at step 1202, the thread selector index is initialized to 0. Steps 1203 to 1211 are then repeated until all threads in the bundle have been processed. Therefore, at step 1203, a thread is selected from each bundle subset, and at step 1204, the input for the selected thread is sent to the corresponding (different) mathematical logic unit (ALU) execution channel for processing. Inputs for all threads within the same bundle subset are sent to the same execution channel for processing.

[0255] However, with Figure 11 In contrast, in step 1205 (regarding threads within the same bundle (thread group), it is determined whether the input sent to the execution channel (first processing level P0) for processing is the same as the previous input sent to that execution channel (first processing level P0) for processing. (Since, as discussed above, within a given bundle (thread group), the input to a particular execution channel will come from the same bundle subset, this serves to determine whether the input to a thread within the bundle subset is the same as the input to a previous thread within the same bundle subset.)

[0256] If this is the case, that is, if the input sent to the execution channel (first processing level P0) is the same as the previous input sent to that execution channel (first processing level P0) for processing, then in step 1206, the clock gate for the first processing level P0 of that execution channel is set to off (blocked). Otherwise, if the input sent to the execution channel (first processing level P0) is not the same as the previous input sent to that execution channel (first processing level P0) for processing, then in step 1207, the clock gate for the first processing level P0 of that execution channel is set to on. Therefore, for any execution channel (with regard to threads from the same bundle (thread group)) where the current input is the same as the previous input, the clock gate for the first processing level P0 is set to off; and for any execution channel where the current input is not the same as the previous input (and any execution channel where the current and previous threads are from different thread groups (bundles)), the clock gate is set to on.

[0257] In step 1208, the first processing level P0, whose corresponding clock gate is set to open, performs the (same) operation on its corresponding input operand in sync with one or more clock signals. However, the first processing level P0, whose corresponding clock gate is set to close (blocked), does not receive clock signals during the one or more specific clock cycles (by setting the clock gate to close), and therefore does not perform any operation.

[0258] This will have the following effect: the output register for the first processing level P0, whose input value is the same as its previous input value, will remain unchanged during the clock cycle, so that the output value previously stored in the output register for the previous thread will be "reused" for the current thread (from the same bundle (thread group)).

[0259] The processing is performed at each processing level for each execution channel in each cycle. Therefore, for each subsequent processing level, for each cycle (with respect to threads in the same bundle (thread group), it is determined whether the input to the corresponding processing level is the same as its previous input. If so, the clock gate for that processing level is closed (blocked), so that the processing level does not perform any processing operations in that cycle, and the corresponding output register remains unchanged.

[0260] This will have the following effect: when a thread has the same input value as a previous thread processed by the execution channel pipeline (from the same thread bundle (thread group)), the thread will propagate through the execution channel pipeline, and no processing stage of the execution channel pipeline will perform any processing operation on that thread. Therefore, energy usage for that thread can be reduced.

[0261] In step 1209, the results of each ALU execution channel are written to the appropriate output register. As described above, when an execution thread has propagated through the execution channel pipeline and no processing stage of the execution channel pipeline has performed any processing operation on the thread, the clock gate for the last processing stage of that execution channel pipeline will be set to off (blocked), and for its final output, the thread will "reuse" the final output from a previous thread in the same thread group. Therefore, for different threads in the same thread group, the same final output will be written to multiple result channels.

[0262] In step 1210, the thread selector index is incremented, and in step 1211, it is determined whether there are more threads to process in the bundle subset. If so, the process loops back to step 1203 to process the next thread for each execution channel. Otherwise, if there are no more threads to process, the output for all threads in the bundle is written to the operand buffer in step 1212.

[0263] Then you can repeat the process for the next thread group and for the next instruction in the currently executing program. Figure 12 The entire process.

[0264] Although in the above implementation, the number of execution channels is less than the number of threads in the thread group (“bundle”), such that at least some threads in the thread group must be processed by the same execution channel, the applicant has recognized that even in cases where it is not necessary for at least some threads in the thread group to be processed by the same execution channel (e.g., when the number of execution channels is equal to the number of threads in the thread group, or when the number of threads in the thread group is less than the number of execution channels), it is still advantageous (e.g., in terms of energy use) to publish multiple threads from the same thread group to the same execution channel for execution.

[0265] The methods described in this invention can be used for any suitable and desired program and shader level to be executed by the graphics processor, such as geometry shaders, vertex shaders, or fragment shaders. It is also known to use the shader functions of the graphics processor and graphics pipeline for more general computational tasks, for example, according to computational shader APIs such as OpenCL and Vulkan. In this case, the execution channels (functional units) of the graphics processor's shader kernels will be used for more general data processing tasks that may not be particularly related to generating graphics data for graphics output (e.g., for display).

[0266] The operation performed in this embodiment can also be used with other data processors that execute programs in a similar manner. Therefore, although the invention has been described above with particular reference to a graphics processor (GPU), the invention extends to other data processors, such as central processing units (CPUs) and video processing units (VPUs).

[0267] Although the above description has referred to a subset of execution threads corresponding to 2×2 pixel blocks (“quadruple”), the applicant has recognized that if any threads from the same thread group with potentially similar input and / or output data values ​​are assigned to the same execution channel, it is highly likely that the value variations between consecutive threads in the execution channel will be small, thus reducing the likelihood of changes in the physical signal level of the execution channel (e.g., in register values, etc.), thereby reducing the energy consumed when executing these threads. Therefore, in other embodiments, threads corresponding to spatially and / or temporally related data values ​​are assigned to the same execution channel.

[0268] As will be appreciated from the above, the present invention provides, at least in its embodiments, a setup that can reduce the power consumption of data processors such as graphics processors. At least in embodiments of the invention, this is achieved by publishing multiple execution threads from the same thread group (“bundle”) to the same execution channel for execution.

[0269] The foregoing detailed description has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology described herein to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the technical principles described herein and their practical application, thereby enabling others skilled in the art to best utilize the technology described herein in various embodiments and with various modifications suitable for achieving various intended particular uses. The scope is intended to be defined by the appended claims.

Claims

1. A method of operating a data processor, wherein execution threads execute program instructions to perform data processing operations on data values, and wherein the execution threads are grouped together to form a thread group, wherein... Multiple execution threads in a thread group each execute a set of instructions in lockstep. The data processor includes: An instruction execution processing circuit operatively executes instructions to perform processing operations for an execution thread of a program, wherein the instruction execution processing circuit is configured with multiple execution channels, each execution channel operatively performing processing operations for an execution thread of a thread group; and An execution thread publishing circuit is used to publish the execution threads of the thread group to the execution channels of the plurality of execution channels of the instruction execution processing circuit for execution. The method includes the following steps: The execution thread publishing circuit publishes two or more execution threads from the same thread group to the same execution channel among the multiple execution channels of the instruction execution processing circuit for execution. In response to the execution thread publishing circuit publishing two or more execution threads of the same thread group to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution, the execution channel sequentially processes the two or more execution threads of the same thread group; Wherein, the two or more execution threads published by the execution thread publishing circuit to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution are two or more execution threads in the same thread group that are more likely to have similar data values ​​to each other compared with other execution threads in the same thread group, such that the execution channel sequentially processes the two or more execution threads that are more likely to have similar data values ​​to each other compared with other execution threads in the same thread group.

2. The method according to claim 1, wherein, The two or more execution threads process adjacent data elements of the data array that the data processor is processing.

3. The method according to claim 2, wherein, The adjacent data element is a 2×2 subarray of the adjacent data elements of the data array.

4. The method according to claim 2, wherein, The data array is an image.

5. The method according to claim 1 or 2, wherein the method comprises the following steps: The two or more execution threads are sequentially deployed to the same execution channel in an order that is intended to minimize the differences between consecutive data values ​​processed by the same execution channel.

6. The method according to claim 1 or 2, further comprising the following step: Determine whether the current input data value of the execution channel is the same as the previous input data value of the execution channel; and When it is determined that the current input data value is the same as the previous input data value, the previous output data value is provided as the current output data value.

7. The method according to claim 1 or 2, wherein, The thread group is divided into multiple thread group subsets, each thread group subset including multiple threads of the thread group, and the method includes the following steps: Threads from each subset of thread groups are assigned to the same corresponding execution channel among the plurality of execution channels of the instruction execution processing circuit for execution.

8. The method according to claim 7, wherein, The threads of the thread group correspond to point distributions in space and / or time, and based on the point distributions in space and / or time corresponding to the threads of the thread group, the thread group is divided into multiple thread group subsets.

9. The method according to claim 1 or 2, wherein, The data processor is a graphics processor.

10. A data processor, wherein execution threads execute program instructions to perform data processing operations on data values, and wherein the execution threads are grouped together to form thread groups, wherein... Multiple execution threads in a thread group each execute a set of instructions in lockstep. The data processor includes: An instruction execution processing circuit operatively executes instructions to perform processing operations for an execution thread of a program, wherein the instruction execution processing circuit is configured with multiple execution channels, each execution channel operatively performing processing operations for an execution thread of a thread group; and An execution thread publishing circuit is used to publish the execution threads of the thread group to the execution channels of the plurality of execution channels of the instruction execution processing circuit for execution. The execution thread publishing circuit is configured to publish two or more execution threads from the same thread group to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution. The two or more execution threads are those threads in the same thread group that are more likely to have similar data values ​​to each other compared to other execution threads in the same thread group. The instruction execution processing circuit is configured such that, in response to two or more execution threads in the same thread group having data values ​​that are more likely to be similar to each other compared to other execution threads in the same thread group, the execution thread publishing circuit publishes them to the same execution channel among the plurality of execution channels of the instruction execution processing circuit for execution, and the execution channel processes the two or more execution threads having data values ​​that are more likely to be similar to each other compared to other execution threads in the same thread group in turn.

11. The data processor according to claim 10, wherein, The two or more execution threads process adjacent data elements of the data array that the data processor is processing.

12. The data processor according to claim 11, wherein, The data array is an image.

13. The data processor according to claim 10, wherein, The execution thread publishing circuit is configured to: The two or more execution threads are sequentially deployed to the same execution channel in an order that is intended to minimize the differences between consecutive data values ​​processed by the same execution channel.

14. The data processor of claim 10, further comprising circuitry configured to perform the following processes: Determine whether the current input data value of the execution channel is the same as the previous input data value of the execution channel; and When it is determined that the current input data value is the same as the previous input data value, the previous output data value is provided as the current output data value.

15. The data processor according to claim 10, wherein, The thread group is divided into multiple thread group subsets, each of which includes multiple threads from the thread group, and the execution thread publishing circuit is further configured to: Threads from each subset of thread groups are assigned to the same corresponding execution channel among the plurality of execution channels of the instruction execution processing circuit for execution.

16. The data processor according to claim 15, wherein, The threads of the thread group correspond to point distributions in space and / or time, and based on the point distributions in space and / or time corresponding to the threads of the thread group, the thread group is divided into multiple thread group subsets.

17. The data processor according to claim 10, wherein, The data processor is a graphics processor.

18. A non-transitory computer-readable storage medium storing a computer program that, when executed at a data processing apparatus, causes the data processing apparatus to perform the method according to any one of claims 1 to 9.

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