Gray counter and image sensor including gray counter

Abstract

An image sensor includes: a pixel sensor that senses incident light and outputs a sampled signal having an analog shape; a sampler that compares the sampled signal with a ramp signal and outputs a comparison signal as time-axis length information; and a Gray counter that counts the length of the comparison signal synchronously with a clock signal and outputs a digital value. The Gray counter includes: a first flip-flop that divides the clock signal by 2 and generates a first Gray code signal; a second flip-flop that delays a first data signal that is a quarter-frequency signal of the clock signal and outputs a second Gray code signal; and a third flip-flop that delays the second Gray code signal that is divided by 2 and outputs a third Gray code signal.

Description

[0001] Cross - reference to related applications

[0002] Korean Patent Application No. 10 - 2019 - 0154707, filed on November 27, 2019, and titled "Gray Counter and Image Sensor Comprising the Same", is incorporated herein by reference in its entirety. Background Art 1. Technical Field

[0004] Embodiments relate to semiconductor devices, and more particularly, to a Gray code generator and an image sensor including the Gray code generator.

[0005] 2. Description of the Related Art

[0006] A counter is used to convert an effective physical quantity (such as the intensity of light, the intensity of sound, and time) into a digital signal. Summary of the Invention

[0007] Embodiments relate to an image sensor including: a pixel sensor configured to sense incident light and output an analog sampling signal; a sampler configured to compare the sampling signal with a ramp signal and output a comparison signal of time - axis length information; and a Gray counter configured to count the length of the comparison signal in synchronization with a clock signal and output a digital value, the Gray counter including: a first flip - flop configured to divide the clock signal by 2 and generate a first Gray - code signal; a second flip - flop configured to delay a first data signal that is a quarter - frequency signal of the clock signal and output a second Gray - code signal; and a third flip - flop configured to delay the second Gray - code signal that is divided by 2 and output a third Gray - code signal.

[0008] The embodiment also relates to a Gray counter that generates Gray code count values synchronously with a clock signal. The Gray counter includes: a first flip-flop configured to divide the clock signal by 2 and generate a first Gray code signal corresponding to the least significant bit Gray count value; a Johnson counter configured to divide the clock signal by 4 and output a first data signal; a second flip-flop configured to delay the first data signal by up to a length corresponding to one period of the clock signal and output a second Gray code signal; a third flip-flop configured to divide the second Gray code signal by 2 and output a third Gray code signal; and a plurality of flip-flops configured to generate a count value on top of the third Gray code signal using the clock signal and the third Gray code signal.

[0009] The embodiment also relates to a Gray counter that generates Gray code count values synchronously with a clock signal, including: a replication circuit configured to generate a first Gray code signal corresponding to the least significant bit Gray count value from a first clock signal, the first clock signal being obtained by dividing the clock signal by 2; a first flip-flop configured to delay a second clock signal and output a second Gray code signal, the second clock signal being obtained by delaying the first clock signal by up to half a period of the clock signal; a Johnson counter triggered at the second clock signal and configured to divide the second clock signal by 2 and output it; a second flip-flop configured to delay the output of the Johnson counter by up to one period of the second clock signal and output a third Gray code signal; a third flip-flop configured to divide the third Gray code signal by 2 and output a fourth Gray code signal; and a plurality of flip-flops configured to generate a count value on top of the fourth Gray code signal using the fourth Gray code signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features will become apparent to those skilled in the art by referring to the accompanying drawings in which:

[0011] Figure 1 is a block diagram showing an image sensor according to an exemplary embodiment.

[0012] Figure 2 is a block diagram showing a pixel sensor array.

[0013] Figure 3 shows Figure 2 a circuit diagram of an exemplary configuration of one of the pixel sensors shown.

[0014] Figure 4 is a block diagram showing an exemplary structure of a related double sampler, an analog-to-digital converter, and an output buffer. Figure 1 of

[0015] Figure 5 is a timing diagram showing a Gray code according to an exemplary embodiment.

[0016] Figure 6 is a diagram showing Figure 4 an embodiment of a Gray counter of

[0017] Figure 7A and Figure 7B is a diagram showing a flip-flop that generates an LSB Gray code signal in a Gray counter and the operation of the flip-flop.

[0018] Figure 8A and Figure 8B is a diagram showing a flip-flop that generates a Gray code signal in a Gray counter and the operation of the flip-flop.

[0019] Figure 9A and Figure 9B is a diagram showing a flip-flop that generates a Gray code signal in a Gray counter and the operation of the flip-flop.

[0020] Figure 10 is a diagram showing a Gray counter according to another exemplary embodiment.

[0021] Figure 11 schematically shows Figure 10 characteristics of a Gray counter of

[0022] Figure 12 is a block diagram showing an electronic system including an image sensor according to an exemplary embodiment. Detailed Description

[0023] Figure 1 is a block diagram showing an image sensor according to an exemplary embodiment.

[0024] Refer to Figure 1 , an image sensor 100 according to an exemplary embodiment may include a pixel sensor array 110, a row decoder 120, a correlated double sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, and a controller 160.

[0025] The pixel sensor array 110 may include a plurality of pixel sensors arranged in a two-dimensional manner, and each pixel sensor converts an optical signal into an electrical signal. The pixel sensor array 110 may be driven by driving signals provided by the row decoder 120, such as a selection signal SEL, a reset signal RS, and a transfer signal TG. The electrical signals generated from the corresponding pixel sensors in response to the driving signals may be provided to the correlated double sampler 130 through a plurality of column lines CL0, CL1,..., CLm-1. A pixel sensor may include a single photoelectric conversion element (e.g., a photodiode).

[0026] The row decoder 120 may select rows in the pixel sensor array 110 under the control of the controller 160. For the purpose of selecting one of a plurality of rows, the row decoder 120 may generate a selection signal SEL. The row decoder 120 may sequentially activate the reset signal RS and the transfer signal TG with respect to the pixel sensors corresponding to the selected row. In this case, the reset signal RESET and the image signal SIG generated in an analog form from each active pixel sensor of the selected row may be sequentially transmitted to the correlated double sampler 130.

[0027] The correlated double sampler 130 may sequentially sample and hold a set of the reset signal RESET and the image signal SIG provided from the pixel sensor array 110 to each of the plurality of column lines CL0, CL1,..., CLm-1. Thus, the correlated double sampler 130 may sample and hold the levels of the reset signal RESET and the image signal SIG corresponding to each column. Under the control of the controller 160, the correlated double sampler 130 may transmit the sampled reset signal RESET and the sampled image signal SIG of each column to the analog-to-digital converter 140 in units of a plurality of columns.

[0028] The analog-to-digital converter 140 may convert the sampled signal of each column output from the correlated double sampler 130 into a digital signal. The analog-to-digital converter 140 may convert the sampled signal into a digital signal by using a hybrid counter. Thus, the analog-to-digital converter 140 may use a ripple counter (not shown) and a Gray counter 141 to count the reset signal RESET and the image signal SIG. For example, the Gray counter 141 may eliminate the delay caused by an exclusive OR (XOR) logic gate or a NOR logic gate. In addition, since the replica replicates a flip-flop, the Gray counter 141 may eliminate differential nonlinearity (DNL). Additional details are described below with reference to the drawings.

[0029] The output buffer 150 may latch and output the image data provided from the analog-to-digital converter 140 in units of columns. Under the control of the controller 160, the output buffer 150 may temporarily store the image data output from the analog-to-digital converter 140, and then may output the sequentially latched image data. The output buffer 150 may be included in the image sensor 100 or may be omitted.

[0030] The controller 160 may control the pixel sensor array 110, the row decoder 120, the correlated double sampler 130, the analog-to-digital converter 140, and the output buffer 150. The controller 160 may provide control signals (e.g., a clock signal and a timing control signal) for the operations of the pixel sensor array 110, the row decoder 120, the correlated double sampler 130, the analog-to-digital converter 140, and the output buffer 150. The controller 160 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0031] The analog-to-digital converter 140 may include a Gray counter 141 for counting low bits. The Gray counter 141 may be implemented only with flip-flops, thus eliminating the delay or differential nonlinearity (DNL) caused by replicas or logic (e.g., XOR gates or NOR gates). The Gray counter 141 may be used in a high-speed image sensor and may allow an increase in the frequency of the clock signal.

[0032] Figure 2 is a block diagram showing the pixel sensor array.

[0033] See Figure 2 , the pixel sensor array 110 may include pixel sensors 111 arranged in a matrix of a plurality of rows and a plurality of columns.

[0034] Each pixel sensor 111 of the pixel sensor array 110 may include at least one of a red filter, a green filter, and a blue filter. The red filter transmits light in the red wavelength band, the green filter transmits light in the green wavelength band, and the blue filter transmits light in the blue wavelength band. In addition, the pixel sensor 111 may include a plurality of transistors and a photoelectric conversion element. Each of the plurality of pixel sensors 111 may sense light by using the photoelectric conversion element, convert the sensed light into an electrical signal, and output the electrical signal through the column line CL. In addition, in order to apply the reset multiple sampling technique, the pixel sensor 111 may be implemented to have a structure including at least two photoelectric conversion elements.

[0035] When the reset signal RS_i and the transfer signal TG_i are provided to the selected row "i" of the pixel sensor array 110, the sampling signals Vout_j, Vout_j+1, Vout_j+2, and Vout_j+3 corresponding to each of the reset signal RS_i and the transfer signal TG_i can be output to the column lines CL_j, CL_j+1, CL_j+2, and CL_j+3 of the selected row "i". The sampling signals Vout_j, Vout_j+1, Vout_j+2, and Vout_j+3 can be provided to the correlated double sampler 130 to be sampled as the reset signal RESET and the image signal SIG.

[0036] Figure 3 is a circuit diagram showing Figure 2 an exemplary configuration of one of the pixel sensors shown.

[0037] Refer to Figure 3 , the pixel sensor 111 can be implemented to have a structure including a photoelectric conversion element PD and four NMOS transistors TX, RX, DX, and SX. The pixel sensor 111 can also include transistors or capacitors for various functions.

[0038] The photoelectric conversion element PD can be a photosensitive element for generating and accumulating charges based on the amount or intensity of incident light. The photoelectric conversion element PD can be implemented using, for example, a photodiode, a phototransistor, a photogate, or a pinned photodiode (PPD).

[0039] The transfer transistor TX can transfer the charges accumulated at the photoelectric conversion element PD to the floating diffusion region FD. The transfer transistor TX can be implemented using one transistor that turns on or off in response to the transfer signal TG provided from the row decoder 120.

[0040] The floating diffusion region FD can accumulate charges corresponding to the amount of incident light. The floating diffusion region FD can accumulate the charges provided from the photoelectric conversion element PD when the transfer signal TG is activated. To accumulate charges, the floating diffusion region FD can have a capacitance C of a given size FD . The floating diffusion region FD can be connected to the gate terminal of the driving transistor DX that serves as a source follower amplifier. The floating diffusion region FD can be supplied with the power supply voltage VDD through the reset transistor RX.

[0041] The reset transistor RX can reset the floating diffusion region FD in response to a reset signal RS on a signal line RG. The source of the reset transistor RX can be connected to the floating diffusion region FD, and the drain of the reset transistor is connected to a power supply voltage (VDD) terminal. When the reset transistor RX is turned on by the bias voltage of the reset signal RS, the power supply voltage VDD connected to the drain of the reset transistor RX can be transmitted to the floating diffusion region FD, so that the charge accumulated at the floating diffusion region FD moves to the power supply voltage (VDD) terminal, and the voltage of the floating diffusion region FD is reset.

[0042] The driving transistor DX can be used as a source follower amplifier to amplify the potential change of the floating diffusion region FD and output the amplified result as a sense voltage Vout_j.

[0043] The selection transistor SX can select a pixel sensor to be read in units of rows. The selection transistor SX can be driven by a selection signal SEL provided in units of rows. When the selection transistor SX is turned on, the potential of the floating diffusion region FD can be amplified by the driving transistor DX and then transmitted to the drain of the selection transistor SX. The corresponding driving signal lines TG, RG, and SEL of the transfer transistor TX, the reset transistor RX, and the selection transistor SX can extend in the row direction (e.g., the horizontal direction) so that the unit pixel sensors included in the same row are driven simultaneously.

[0044] Figure 4 is a block diagram showing Figure 1 an exemplary structure of a related double sampler, an analog-to-digital converter, and an output buffer.

[0045] See Figure 4 In, the related double sampler 130 can include a ramp signal generator 132 and a comparator 134. The analog-to-digital converter 140 can include at least one Gray counter 141. The output buffer 150 can include memories MEM_0, MEM_1, MEM_2, and MEM_3 and a sense amplifier 154. The output buffer 150 can be included in the image sensor 100 or can be omitted.

[0046] The ramp signal generator 132 of the related double sampler 130 can output a ramp signal RAMP with a uniform falling or rising slope in response to a control signal Ramp_EN from the controller 160. Therefore, the ramp signal generator 132 can continuously generate a ramp signal RAMP with a specific slope under the control of the controller 160. By comparing with the ramp signal RAMP, each of the reset signal RESET and the image signal SIG can be converted into time axis length information.

[0047] Comparator 134 may include a plurality of comparators Comp0, Comp1, Comp2, and Comp3 provided to respective columns of pixel sensor array 110 to compare each of sampling signals Vout0, Vout1, Vout2, and Vout3 corresponding to each column with ramp signal RAMP. Each of sampling signals Vout0, Vout1, Vout2, and Vout3 may include reset signal RESET and image signal SIG sampled and held by a correlated double sampling operation.

[0048] The operation of first comparator Comp0 to compare sampling signal Vout0 and ramp signal RAMP may be implemented as follows. Ramp signal RAMP may be input to non-inverting input terminal (+) of first comparator Comp0, and sampling signal Vout0 may be input to inverting input terminal (-) of first comparator Comp0. First comparator Comp0 may output CDS output signal CDS_OUT0 by comparing ramp signal RAMP and reset signal RESET of sampling signal Vout0 in a first period and comparing ramp signal RAMP and image signal SIG of sampling signal Vout0 in a second period. Through this process, reset signal RESET and image signal SIG including level information may be converted into time axis length information. The operation characteristics of second comparator Comp1, third comparator Comp2, and fourth comparator Comp3 are substantially the same as those of first comparator Comp0, except that the columns corresponding to comparators Comp0 to Comp3 are different. Therefore, additional descriptions will be omitted to avoid redundancy.

[0049] Analog-to-digital converter 140 may include Gray counter 141, a plurality of latches LTCH_0, LTCH_1, LTCH_2, and LTCH_3, a plurality of binary counters B_CNT_0, B_CNT_1, B_CNT_2, and B_CNT_3, and a plurality of adders Adder_0, Adder_1, Adder_2, and Adder_3.

[0050] Gray counter 141 may generate Gray code GC based on clock signal CLK provided from controller 160, where Gray code GC is a counting signal that counts up or down in Gray code manner. Gray counter 141 may be implemented by using flip-flops FF without using logic gates or logic circuits (e.g., XOR or NOR) or replication circuits. Therefore, delays caused by logic gates or circuits (e.g., XOR or NOR) and deterioration of differential nonlinearity (DNL) caused by replication circuits may be avoided.

[0051] Multiple latches LTCH_0, LTCH_1, LTCH_2, and LTCH_3 can latch the lower bits of the count of the CDS output signals CDS_OUT0 to CDS_OUT3 based on the Gray code GC. Additionally, multiple latches LTCH_0, LTCH_1, LTCH_2, and LTCH_3 can transfer the most significant bits CR_0, CR_1, CR_2, and CR_3 of the counted Gray code GC to the binary counters B_CNT_0, B_CNT_1, B_CNT_2, and B_CNT_3 of the corresponding columns. Generally, the most significant bit of the Gray code GC has the same bit value as the least significant bit of the binary code. Thus, multiple binary counters B_CNT_0, B_CNT_1, B_CNT_2, and B_CNT_3 can count the CDS output signals CDS_OUT0 to CDS_OUT3 to start counting from the transferred most significant bits CR_0, CR_1, CR_2, and CR_3. Multiple adders Adder_0, Adder_1, Adder_2, and Adder_3 can convert the Gray code GC stored in multiple latches LTCH_0, LTCH_1, LTCH_2, and LTCH_3 into a binary value, add the binary value to the value counted by multiple binary counters B_CNT_0, B_CNT_1, B_CNT_2, and B_CNT_3, and output the added result as the image data value of the CDS output signal CDS_OUTj (j = 0, 1, 2, and 3).

[0052] The output buffer 150 can include a column memory 152 and a sense amplifier 154. The column memory 152 can store image data corresponding to the respective columns in response to a control signal Mem_EN from the controller 160. The column memory 152 can include multiple memories MEM_0, MEM_1, MEM_2, and MEM_3, which sequentially transfer the stored image data to the sense amplifier 154. The output buffer 150 can be included in the image sensor 100 (see Figure 1 ) or can be omitted.

[0053] In the above analog-to-digital converter 140, the use of the Gray counter 141 can avoid the delay caused by logic circuits (e.g., XOR or NOR) and can avoid the differential nonlinearity (DNL) caused by the replication circuit.

[0054] Figure 5 is a timing diagram showing the Gray code GC according to an exemplary embodiment.

[0055] See Figure 5 , Figure 4The Gray counter 141 can generate five low-order Gray code signals G<0> to G<4> synchronously with the clock signal CLK. Here, it is assumed that the initial state of the Gray counter 141 is "00000". Therefore, at time T0, the logical values of all Gray code signals G<0> to G<4> start from logical "0". The clock signal CLK can be, for example, a signal obtained by dividing the system clock of the image sensor 100 (see Figure 1 ) by 2.

[0056] In the present exemplary embodiment, the Gray code signal G<0> corresponding to the LSB value is generated as a clock signal that changes synchronously with the falling edge of the clock signal CLK. The Gray code signal G<0> is generated as a signal having a frequency that is half the frequency of the clock signal CLK. At time T1 when the first falling edge of the clock signal CLK is generated, the Gray code signal G<0> changes from logical "0" to logical "1". After that, the Gray code signal G<0> can be generated with logical values that are inverted at each falling edge of the clock signal CLK.

[0057] The Gray code signal G<1> can have a frequency corresponding to half the frequency of the Gray code signal G<0>. The Gray code signal G<1> can start changing at a time that is delayed by up to half a cycle of the clock signal CLK with respect to the time T1 corresponding to the first transition time of the LSB Gray code signal G<0>. Therefore, at time T2 when the second rising edge of the clock signal CLK is generated, the Gray code signal G<1> changes from logical "0" to logical "1". After that, the Gray code signal G<1> can be generated as a signal that switches synchronously with (or on) the rising edge of the clock signal CLK within the high period (e.g., logical "1") of the Gray code signal G<0>.

[0058] The Gray code signal G<2> can have a frequency corresponding to half the frequency of the Gray code signal G<1>. The Gray code signal G<2> can start changing at a time that is delayed by up to one cycle of the clock signal CLK with respect to the time T2 corresponding to the first transition time of the Gray code signal G<1>. Therefore, at time T3 when the third rising edge of the clock signal CLK is generated, the Gray code signal G<2> changes from logical "0" to logical "1". After that, the Gray code signal G<2> can be generated as a signal that switches synchronously with (or on) the rising edge of the clock signal CLK within the high period (e.g., logical "1") of the Gray code signal G<1>.

[0059] The Gray code signal G<3> may have a frequency corresponding to half of the frequency of the Gray code signal G<2>. The Gray code signal G<3> may start transitioning at a time T3 that is up to two cycles (2CLK) of the clock signal CLK delayed from the time corresponding to the first transition time of the Gray code signal G<2>. Thus, at the time T4 when the rising edge of the clock signal CLK is generated, the Gray code signal G<3> transitions from logic "0" to logic "1". Thereafter, the Gray code signal G<3> may be generated as a signal that switches in synchronization with (or on) the rising edge of the clock signal CLK during the high period (e.g., logic "1") of the Gray code signal G<2>.

[0060] The Gray code signal G<4> may have the same frequency as the Gray code signal G<3>. The Gray code signal G<4> may start transitioning at a time delayed from the time T4 corresponding to the first transition time of the Gray code signal G<3>, with a delay of up to four cycles (4CLK) of the clock signal CLK. Thus, at the time T5 when the rising edge of the clock signal CLK is generated, the Gray code signal G<4> transitions from logic "0" to logic "1".

[0061] Thus, as described above, Figure 4 the Gray counter 141 can generate the waveform of the 5-bit Gray code G[4:0].

[0062] Figure 6 is a diagram showing Figure 4 an exemplary embodiment of the Gray counter.

[0063] Refer to Figure 6 , the Gray counter 141a according to an exemplary embodiment can generate the 5-bit Gray code G[4:0] (or five Gray code signals G<0> to G<4>) by using only 11 flip-flops FF<0> to FF<10> without logical operations for the outputs of the flip-flops or the clock signal.

[0064] First, the flip - flop FF<0> can be used to generate a Gray - code signal G<0> corresponding to the least - significant bit. To generate the Gray - code signal G<0>, the inverted output terminal / Q of the flip - flop FF<0> is connected to the data input terminal "D". The clock signal CLK is inverted and input to the clock input terminal. The flip - flop FF<0> can trigger the output terminals Q and / Q synchronously with the inverted version of the clock signal CLK. Depending on the setting, the flip - flop FF<0> can output the LSB Gray - code signal G<0> that switches synchronously with the falling edge of the clock signal CLK. Thus, since the LSB Gray - code signal G<0> is switched at the falling edge of the clock signal CLK, the LSB Gray - code signal G<0> can start to transition to logic "1" after half a period of the clock signal. The LSB Gray - code signal G<0> can have a frequency corresponding to half of the frequency of the clock signal CLK.

[0065] The flip - flops FF<1>, FF<5> and FF<10> are used to generate the Gray - code signal G<1>. The Gray - code signal G<1> can have half the period of the LSB Gray - code signal G<0>, and can rise at a time delayed by up to half a period (1 / 2CLK) relative to the first rising edge of the Gray - code signal G<0>. Thus, the Gray - code signal G<1> can be generated by delaying the first input data D<1> having a quarter - frequency of the clock signal CLK by up to one period. The first input data D<1> is generated by a Johnson counter 143, which divides the clock signal by 4 (i.e., divides the frequency of the clock signal by a factor of 4 (thereby reducing the frequency)), and operates synchronously with the rising edge of the clock signal. The Johnson counter 143 is implemented by using two flip - flops FF<5> and FF<10>.

[0066] The Gray - code signal G<1> of the previous bit is used to generate the Gray - code signal G<2>. Two flip - flops FF<2> and FF<6> that process the Gray - code signal G<1> are used to generate the Gray - code signal G<2>. The inverted version of the Gray - code signal G<1> output from the flip - flop FF<1> is provided to the clock input terminal of the flip - flop FF<6>. The inverted output terminal / Q of the flip - flop FF<6> is connected to the data input terminal "D" of the flip - flop FF<6> for the purpose of feeding back the output of the flip - flop FF<6>. Thus, the flip - flop FF<6> acts as a T - flip - flop that divides the inverted version of the Gray - code signal G<1> by 2, and outputs the second input data D<2>. The flip - flop FF<2> delays the second input data D<2> by up to one period of the clock signal CLK, and outputs the Gray - code signal G<2>. The above operations will be described in more detail below with reference to the drawings.

[0067] The Gray code signal G<2> of the previous stage is used to generate the Gray code signal G<3>. The flip-flops FF<3>, FF<7> and FF<8> are used to generate the Gray code signal G<3>. An inverted version of the Gray code signal G<2> output from the flip-flop FF<2> is provided to the clock input terminal of the flip-flop FF<7>. The inverted output terminal / Q of the flip-flop FF<7> is connected to the data input terminal "D" of the flip-flop FF<7> for the purpose of feeding back the output of the flip-flop FF<6>. Thus, the flip-flop FF<7> divides the inverted version of the Gray code signal G<2> by 2 and outputs it. In this case, the output data of the flip-flop FF<7> is delayed by up to two cycles (2CLK) of the clock signal CLK by the flip-flops FF<8> and FF<3>. Therefore, the third input data D<3> has a waveform obtained by delaying the inverted version of the Gray code signal G<2> by up to one cycle of the clock signal CLK. The Gray code signal G<3> is generated by an additional delay of the flip-flop FF<3>, and the additional delay corresponds to one cycle of the clock signal CLK.

[0068] The Gray code signal G<3> of the previous stage is used to generate the Gray code signal G<4>. The flip-flops FF<4>, FF<9> and FF<10> are used to generate the Gray code signal G<4>. An inverted version of the Gray code signal G<3> output from the flip-flop FF<3> is provided to the data input terminal "D" of the flip-flop FF<9>, and the output of the flip-flop FF<10> is provided to the clock input terminal of the flip-flop FF<9>. The flip-flop FF<4> delays the fourth input data D<4> which is the output of the flip-flop FF<9> by up to one cycle of the clock signal CLK, and outputs the MSB Gray code signal G<4>. For example, the output of the flip-flop FF<10> provided to the clock input terminal of the flip-flop FF<9> corresponds to the output of the Johnson counter 143.

[0069] As described above, the Gray counter 141a can be implemented only by using the flip-flops FF<0> to FF<10>. In the case of the Gray counter 141a, only the delay corresponding to two flip-flops occurs at the critical path, resulting in the maximum delay of the clock signal. For example, in order to generate the Gray code signal G<2>, the clock data delay Tc-q (clock-to-data delay) may occur at two flip-flops FF<1> and FF<6>, and the setup delay Tsetup may occur at the flip-flop FF<2>. The length of the size of the delay occurring on the critical path is shorter than one cycle 1CLK which is the benchmark for becoming a high-speed bottleneck. Therefore, the size "2Tc-q + Tsetup" of the delay occurring on the critical path satisfies the following equation 1.

[0070] [Equation 1]

[0071] 2Tc - q + Tsetup < 1CLK

[0072] Therefore, even if the speed of the Gray counter 141a increases and the operating voltage is unstable, stable operation can still be performed. Additionally, since the replication circuit is not used, differential non - linearity (DNL) caused by using flip - flops and replication circuits does not occur.

[0073] Figure 7A and Figure 7B are diagrams showing the flip - flop that generates the LSB Gray - code signal G<0> in the Gray counter and the operation of the flip - flop.

[0074] Figure 7A The circuit diagram showing the flip - flop FF<0> that divides the clock signal CLKB by 2 and generates the Gray - code signal G<0>. Figure 7B The waveform of the Gray - code signal G<0> is shown, and the Gray - code signal is Figure 7A the output signal output by the flip - flop FF<0> in response to the clock signal CLK.

[0075] See Figure 7A and Figure 7B , the flip - flop FF<0> serves as a toggle flip - flop that divides the inverted clock signal CLKB by 2 and outputs the Gray - code signal G<0>. Therefore, since the inverted data output terminal / Q of the flip - flop FF<0> is connected to the data input terminal "D" of the flip - flop FF<0>, the flip - flop FF<0> serves as a circuit that divides the inverted clock signal CLKB by 2 and outputs it. Therefore, the Gray - code signal G<0> can repeatedly transition synchronously with the rising edge of the inverted clock signal CLKB.

[0076] More specifically, see Figure 7B , at time t0 corresponding to the first rising edge of the inverted clock signal CLKB, the first rising edge of the Gray - code signal G<0> (which is generated by dividing the inverted clock signal CLKB by 2) occurs. At time t1 corresponding to the second rising edge of the inverted clock signal CLKB, the first falling edge of the Gray - code signal G<0> occurs. Therefore, as shown in the waveform diagram in Figure 7B , the Gray - code signal G<0> can be switched at times t2, t3, t4, t5, and t6 corresponding to the rising edges of the inverted clock signal CLKB, respectively.

[0077] Figure 8A and Figure 8B are diagrams showing the flip - flop that generates the Gray - code signal G<1> in the Gray counter and the operation of the flip - flop.

[0078] Figure 8AA circuit diagram showing flip - flops FF<1>, FF<5> and FF<10> that divide a clock signal CLK by 4, delay the divided result by up to one cycle, and generate a Gray - code signal G<1>. Figure 8B Showing by Figure 8A The waveforms of the Gray - code signal G<1> generated by the flip - flops FF<1>, FF<5> and FF<10>.

[0079] Refer to Figure 8A and Figure 8B The Gray - code signal G<1> can have a frequency corresponding to half of the frequency of the Gray - code signal G<0>. Therefore, the frequency of the Gray - code signal G<1> can be obtained by dividing the clock signal CLK by 4. The flip - flops FF<5> and FF<10> connected as a Johnson counter 143 can be used to divide the clock signal CLK by 4. The clock signal CLK is input to the clock input terminals of the flip - flops FF<5> and FF<10>. The output Q<5> of the flip - flop FF<5> is provided to the data input terminal “D” of each of the flip - flops FF<10> and FF<1>. The inverted output terminal / Q of the flip - flop FF<10> is connected to the data input terminal “D” of the flip - flop FF<5>. The first input data D<1>(=Q<5>) corresponding to the output of the Johnson counter 143 can be delayed by the flip - flop FF<1> by up to one cycle DL(=1CLK) of the clock signal CLK and can be output as the Gray - code signal G<1>. The Johnson counter 143 is used to divide the clock signal CLK by 4, but it can be considered to divide the clock signal CLK by 4 through various frequency - dividing circuits composed of flip - flops, and then a specific value or greater delay occurs on the critical path.

[0080] Figure 9A and Figure 9B are diagrams showing the flip - flops that generate Gray - code signals G<2>, G<3> and G<4> in a Gray counter and the operations of the flip - flops.

[0081] Figure 9A A circuit diagram showing flip - flops FF<2> to FF<4> and FF<6> to FF<9> that generate Gray - code signals G<2>, G<3> and G<4>. Figure 9B Showing by Figure 9A The waveforms of the Gray - code signals G<2>, G<3> and G<4> generated by the flip - flops FF<2> to FF<4> and FF<6> to FF<9>.

[0082] Refer to Figure 9A and Figure 9B, two flip - flops FF<2> and FF<6> use the Gray - code signal G<1> to generate the Gray - code signal G<2>. The inverted Gray - code signal / G<1> output from the flip - flop FF<1> is provided to the clock input terminal of the flip - flop FF<6>. The inverted output terminal / Q of the flip - flop FF<6> is connected to the data input terminal "D" of the flip - flop FF<6> for the purpose of feeding back the output of the flip - flop FF<6>. The flip - flop FF<6> divides the inverted Gray - code signal / G<1> by 2 and outputs the second input data D<2>. When the second input data D<2> is provided to the flip - flop FF<2>, the flip - flop FF<2> delays the second input data D<2> by up to one period of the clock signal CLK and outputs the Gray - code signal G<2>.

[0083] The previous Gray - code signal G<2> is used to generate the Gray - code signal G<3>. Flip - flops FF<3>, FF<7> and FF<8> are used to generate the Gray - code signal G<3>. The inverted version of the Gray - code signal G<2> output from the flip - flop FF<2> is provided to the clock input terminal of the flip - flop FF<7>. The inverted output terminal / Q of the flip - flop FF<7> is connected to the data input terminal "D" of the flip - flop FF<7> for the purpose of feeding back the output of the flip - flop FF<7>. Thus, the flip - flop FF<7> divides the inverted Gray - code signal / G<2> by 2 and outputs it. In this case, the output data of the flip - flop FF<7> is delayed by up to two periods (2CLK) of the clock signal CLK by the flip - flops FF<8> and FF<3>. Thus, the third input data D<3> has a waveform obtained by delaying the inverted version of the Gray - code signal G<2> by up to one period of the clock signal CLK. The Gray - code signal G<3> is generated by an additional delay of the flip - flop FF<3>, and the additional delay corresponds to one period of the clock signal CLK.

[0084] Flip - flops FF<4>, FF<9> and FF<10> are used to generate the Gray - code signal G<4>. The Gray - code signal G<3> and the data signal Q<10> provided from the Johnson counter 143 are used by the flip - flops FF<4>, FF<9> and FF<10> to generate the Gray - code signal G<4>. The inverted version of the Gray - code signal G<3> output from the flip - flop FF<3> is provided to the data input terminal "D" of the flip - flop FF<9>, and the output of the flip - flop FF<10> is provided to the clock input terminal of the flip - flop FF<9>. In this case, the flip - flop FF<9> can output the fourth input data D<4> synchronously with the data signal Q<10>. The flip - flop FF<4> delays the fourth input data D<4> by up to one period of the clock signal CLK and outputs the Gray - code signal G<4>.

[0085] As described above, each of the Gray code signals G<2>, G<3>, and G<4> can be generated by binary-dividing a low-order Gray code signal and adding a delay.

[0086] Figure 10 is a diagram showing a Gray counter according to another exemplary embodiment.

[0087] Refer to Figure 10 , different from the Gray counter 141a, the Gray counter 141b generates the LSB Gray code signal G<0> by using a replication circuit 142. The Gray code signals G<1> to G<4> can be generated by using the remaining eight flip-flops FF<11> to FF<18>. Here, the first clock signal CK0 is a clock signal obtained by binary-dividing the clock signal CLK by 2. The second clock signal CK1 is a signal obtained by delaying the first clock signal CK0 by up to half a cycle of the clock signal CLK. Figure 5 The second clock signal CK1 is a signal obtained by delaying the first clock signal CK0 by up to half a cycle of the clock signal CLK.

[0088] First, the replication circuit 142 is used to generate the Gray code signal G<0> corresponding to the least significant bit. The replication circuit 142 provides a delay corresponding to the delay "Tc-q" of each of the flip-flops FF<11> to FF<14>. Therefore, the Gray code signal G<0> is generated as a signal obtained by binary-dividing the clock signal CLK by 2.

[0089] The Gray code signal G<1> can be generated by the flip-flop FF<11>. The second clock signal CK1 is input to the clock input terminal of the flip-flop FF<11>. The inverted output terminal / Q of the flip-flop FF<11> is connected to the data input terminal "D" of the flip-flop FF<11> for the purpose of feeding back the output of the flip-flop FF<11>. In this case, the flip-flop FF<11> can binary-divide the second clock signal CK1 by 2 and can output the Gray code signal G<1>.

[0090] The flip-flops FF<12>, FF<15>, and FF<18> are used to generate the Gray code signal G<2>. Each of the flip-flops FF<12>, FF<15>, and FF<18> is triggered synchronously with the second clock signal CK1. The second clock signal CK1 is a signal having the same period as the first clock signal CK0 and delayed by up to half a cycle of the clock signal CLK with respect to the clock signal CLK. Two flip-flops FF<15> and FF<18> can form a Johnson counter 144 and can binary-divide the second clock signal CK1 by 4. The output of the Johnson counter 144 can be delayed by up to one cycle of the second clock signal CK1 by the flip-flop FF<12> and can be output as the Gray code signal G<2>.

[0091] The Gray code signal G<3> can be generated by dividing the Gray code signal G<2> corresponding to the previous bit by 2 and delaying the division result by up to one period of the second clock signal CK1. To this end, the inverted Gray code signal / G<2> is supplied to the clock input terminal of the flip-flop FF<16>. The data input terminal "D" and the inverted data output terminal / Q of the flip-flop FF<16> can be connected to be used as a T flip-flop. Therefore, the flip-flop FF<16> can divide the inverted Gray code signal / G<2> by 2 and output it. In this case, the output of the flip-flop FF<16> can be delayed by up to one period of the second clock signal CK1 by the flip-flop FF<13> and output as the Gray code signal G<3>.

[0092] The Gray code signal G<3> of the previous bit is used to generate the Gray code signal G<4>. The flip-flops FF<14>, FF<17> and FF<18> are used to generate the Gray code signal G<4>. The inverted Gray code signal / G<3> output from the flip-flop FF<13> is supplied to the data input terminal "D" of the flip-flop FF<17>, and the output of the flip-flop FF<18> is supplied to the clock input terminal of the flip-flop FF<17>. The flip-flop FF<14> delays the output of the flip-flop FF<17> by up to one period of the second clock signal CK1 and outputs the MSB Gray code signal G<4>.

[0093] As described above, the Gray counter 141b according to the present exemplary embodiment uses one replication circuit 142 and eight flip-flops FF<11> to FF<18>, which can provide a slightly improved differential nonlinearity (DNL) when the operation speed is increased. Therefore, when speed is relatively important, the LSB Gray code signal G<0> operating at a high frequency can be applied to the Gray counter 141b by using the replication circuit 142.

[0094] Figure 11 is a timing diagram schematically showing Figure 10 the characteristics of the Gray counter.

[0095] Refer to Figure 11 , Figure 10 The Gray counter 141b of generates the LSB Gray code signal G<0> by using the replication circuit 142. The Gray code signals G<1> to G<4> can be generated by using eight flip-flops FF<11> to FF<18>. The replication circuit 142 operates in synchronization with the first clock signal CK0, and the flip-flops FF<11> to FF<18> are triggered in synchronization with the second clock signal CK1. The first clock signal CK0 is a signal obtained by dividing the clock signal CLK by 2, and the second clock signal CK1 is a signal obtained by delaying the first clock signal CK0 by up to half a period of the clock signal CLK.

[0096] First, the LSB Gray code signal G<0> is generated by the replication circuit 142, which delays the first clock signal CK0 by up to a given delay "Tc-q". The first clock signal CK0 is a clock signal obtained by dividing the clock signal CLK by 2. Thus, the Gray code signal G<0> is generated by delaying the signal obtained by dividing the clock signal CLK by 2 by up to the given delay of the replication circuit 142 and outputting the signal.

[0097] The Gray code signal G<1> is generated by the flip-flop FF<11>, which divides the second clock signal CK1 by 2 and outputs it. Considering the delay relationship between the first clock signal CK0 and the second clock signal CK1, the Gray code signal G<1> is generated as a signal obtained by dividing the Gray code signal G<0> by 2, delaying the division result by up to one period of the clock signal CLK, and outputting the result.

[0098] The Gray code signal G<2> is generated by the flip-flops FF<12>, FF<15>, and FF<18> triggered synchronously with the second clock signal CK1. The Johnson counter 144 composed of two flip-flops FF<15> and FF<18> divides the second clock signal CK1 by 2 and supplies the divided clock signal to the flip-flop FF<12>. In addition, the flip-flop FF<12> delays the signal obtained by dividing the clock signal CLK by 2 by up to one period of the second clock signal CK1 and outputs the Gray code signal G<2>.

[0099] Each of the Gray code signal G<3> and the Gray code signal G<4> is generated by dividing the previous Gray code signal by 2 synchronously with the second clock signal CK1, and adjusting and outputting the delay of the division result.

[0100] Figure 12 is a block diagram showing an electronic system including an image sensor according to an exemplary embodiment.

[0101] See Figure 12 , the electronic system 1000 can be implemented with a data processing device that uses or supports the Mobile Industry Processor Interface (MIPI), such as a mobile phone, a portable digital assistant (PDA), a personal media player (PMP), or a smart phone. The electronic system 1000 may include an application processor 1010, an image sensor 1040, and a display 1050.

[0102] A camera serial interface (CSI) host 1012 implemented in an application processor 1010 can perform serial communication with a CSI device 1041 of an image sensor 1040 via a camera serial interface (CSI). In this case, an optical deserialiser DES can be implemented in the CSI host 1012, and an optical serializer SER can be implemented in the CSI device 1041. Additionally, the application processor 1010 can include an image signal processor (ISP) that performs automatic white balance.

[0103] A display serial interface (DSI) host 1011 implemented in the application processor 1010 can perform serial communication with a DSI device 1051 of a display 1050 via a display serial interface (DSI). An optical serializer SER can be implemented in the DSI host 1011, and an optical deserialiser DES can be implemented in the DSI device 1051.

[0104] The electronic system 1000 can further include a radio frequency (RF) chip 1060 capable of communicating with the application processor 1010. In the electronic system 1000, a physical layer (PHY) 1013 of the application processor 1010 and a PHY 1061 of the RF chip 1060 can exchange data according to the MIPI DigRF interface.

[0105] The electronic system 1000 can further include a global positioning system (GPS) 1020, a storage device 1070, a microphone 1080, a dynamic random access memory (DRAM) 1085, and a speaker 1090, and the electronic system 1000 can communicate with external devices by using WiMAX 1030, WLAN 1033, UWB 1035, etc.

[0106] By summarizing and reviewing, an image sensor can be implemented as a device that obtains an image by using the characteristics of a semiconductor to react to incident light. An analog-to-digital converter (ADC) can be used to convert an analog signal output from a pixel array of the image sensor into a digital signal. The ADC can be implemented by using a counter that performs a counting operation based on a clock signal.

[0107] The counter can be implemented in various ways, but a hybrid counter that combines a ripple counter and a Gray counter can be used to provide high speed and low power. To improve the performance of the image sensor, the number of pixels per unit area can be increased and the operating frequency can be increased.

[0108] According to an exemplary embodiment, a Gray counter capable of avoiding delay and differential non-linearity (DNL) can be implemented. Therefore, a high-speed image sensor can be implemented by using the Gray counter.

[0109] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, as will be appreciated by those of ordinary skill in the art as of the filing of the present application, unless otherwise indicated, features, characteristics, and / or elements described for a particular embodiment may be used singly or in combination with features, characteristics, and / or elements described for other embodiments. Accordingly, those skilled in the art will appreciate that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An image sensor, comprising: a pixel sensor configured to sense incident light and output an analog sampling signal; a sampler configured to compare the sampling signal with a ramp signal and output a comparison signal of time axis length information; and a Gray counter configured to count the length of the comparison signal synchronously with a clock signal and output a digital value, the Gray counter comprising: a first flip-flop configured to divide the clock signal by 2 and generate a first Gray code signal; a second flip-flop configured to delay a first data signal that is a quarter-frequency signal of the clock signal and output a second Gray code signal; and a third flip-flop configured to delay the second Gray code signal divided by 2 and output a third Gray code signal.

2. The image sensor according to claim 1, wherein the first flip-flop is triggered at a falling edge of the clock signal.

3. The image sensor according to claim 1, wherein the second flip-flop and the third flip-flop are triggered at a rising edge of the clock signal.

4. The image sensor according to claim 1, further comprising: a Johnson counter implemented by flip-flops and configured to divide the clock signal by 4 and generate the first data signal.

5. The image sensor according to claim 4, wherein the Johnson counter comprises: a fourth flip-flop triggered in response to the clock signal; and a fifth flip-flop configured to receive data from an inverted data output terminal of the fourth flip-flop and output the first data signal to the second flip-flop in response to the clock signal, an inverted data output terminal of the fifth flip-flop being connected to a data input terminal of the fourth flip-flop.

6. The image sensor according to claim 1, wherein the Gray counter further comprises a sixth flip-flop configured to divide an inverted version of the second Gray code signal by 2 and provide the division result to the third flip-flop.

7. The image sensor according to claim 1, wherein the Gray counter further comprises: a seventh flip-flop configured to divide an inverted version of the third Gray code signal by 2 and output it; an eighth flip-flop configured to delay the output of the seventh flip-flop by up to one period of the clock signal before outputting; and a ninth flip-flop configured to delay the output of the eighth flip-flop by up to one period of the clock signal and output a fourth Gray code signal.

8. The image sensor according to claim 7, wherein the Gray counter further comprises: a tenth flip-flop configured to output an inverted version of the fourth Gray code signal synchronously with the quarter-frequency clock signal; and an eleventh flip-flop configured to delay the output of the tenth flip-flop by up to one period of the clock signal before outputting.

9. The image sensor according to claim 1, wherein an inverted output terminal of the first flip-flop is connected to a data input terminal.

10. A Gray counter that generates Gray code count values synchronously with a clock signal, the Gray counter comprising: A first flip-flop configured to divide the clock signal by 2 and generate a first Gray code signal corresponding to the least significant bit Gray count value; A Johnson counter configured to divide the clock signal by 4 and output a first data signal; A second flip-flop configured to delay the first data signal by up to a length corresponding to one period of the clock signal and output a second Gray code signal; A third flip-flop configured to divide the second Gray code signal by 2 and output a third Gray code signal; and A plurality of flip-flops configured to generate a count value using the clock signal and the third Gray code signal, the count value being one bit higher than the third Gray code signal.

11. The Gray counter according to claim 10, wherein: The first flip-flop is a D flip-flop that is triggered at the falling edge of the clock signal, and The D flip-flop is implemented by a toggle flip-flop, where the inverted output terminal and the data input terminal are connected.

12. The Gray counter according to claim 10, wherein each of the second flip-flop and the third flip-flop is a D flip-flop triggered at the rising edge of the clock signal.

13. The Gray counter according to claim 10, wherein the Johnson counter comprises: A fourth flip-flop triggered in response to the clock signal; and A fifth flip-flop configured to receive data from the inverted data output terminal of the fourth flip-flop and output the first data signal to the second flip-flop in response to the clock signal, the inverted data output terminal of the fifth flip-flop being connected to the data input terminal of the fourth flip-flop.

14. The Gray counter according to claim 10, further comprising a sixth flip-flop configured to divide the inverted version of the second Gray code signal by 2 and provide the division result to the third flip-flop.

15. The Gray counter according to claim 10, wherein the Gray code count value corresponds to a 5-bit value, and wherein the plurality of flip-flops comprises: A seventh flip-flop configured to divide the inverted version of the third Gray code signal by 2 and output; An eighth flip-flop configured to delay the output of the seventh flip-flop by up to one period of the clock signal before outputting; and A ninth flip-flop configured to delay the output of the eighth flip-flop by up to one period of the clock signal and output a fourth Gray code signal; A tenth flip-flop configured to output the inverted version of the fourth Gray code signal synchronously with the quarter-divided clock signal; and An eleventh flip-flop configured to delay the output of the tenth flip-flop by up to one period of the clock signal before outputting.

16. The Gray counter according to claim 15, wherein the quarter-divided clock signal input to the tenth flip-flop is provided using the Johnson counter.

17. A Gray counter that generates Gray code count values synchronously with a clock signal, the Gray counter comprising: A replication circuit configured to generate a first Gray code signal corresponding to the least significant bit Gray count value from a first clock signal, the first clock signal being obtained by dividing the clock signal by 2; A first flip-flop configured to delay a second clock signal and output a second Gray code signal, the second clock signal being obtained by delaying the first clock signal by up to half a period of the clock signal; A Johnson counter that is triggered at the second clock signal and configured to divide the second clock signal by 2 and output it; A second flip-flop configured to delay the output of the Johnson counter by up to one period of the second clock signal and output a third Gray code signal; A third flip-flop configured to divide the third Gray code signal by 2 and output a fourth Gray code signal; and A plurality of flip-flops configured to generate a count value using the fourth Gray code signal, the count value being one bit higher than the fourth Gray code signal.

18. The Gray counter according to claim 17, wherein the replication circuit delays the first clock signal by a delay corresponding to the delay of the first flip-flop or the second flip-flop.

19. The Gray counter according to claim 17, wherein the first clock signal transitions at the rising edge of the clock signal, and the second clock signal transitions at the falling edge of the clock signal.

20. The Gray counter according to claim 17, wherein the Gray counter is a 5-bit counter using the first Gray code signal as the least significant bit.

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