Image sensor, imaging device having the same, and operating method thereof

Abstract

An operating method of an image sensor includes: performing a first sampling operation corresponding to a first illumination in at least one pixel; performing a second sampling operation corresponding to a second illumination in the at least one pixel; and outputting a first pixel voltage corresponding to the first sampling operation or a second pixel voltage corresponding to the second sampling operation in the at least one pixel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2019-0154073 filed on November 27, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an image sensor, an imaging device having the image sensor, and an operation method thereof. Background Art

[0004] Typically, an image sensor can convert an optical image into an electrical signal. Recently, with the development of the computing and communication industries, the demand for improved image sensors in various fields is increasing. Image sensors may include charge coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors can be easily driven, and signal processing circuits can be integrated on a single chip, thereby miniaturizing the product. CMOS image sensors also have very low power consumption, so that they can be easily applied to products with limited battery capacity. Moreover, CMOS image sensors can be used interchangeably with CMOS process technology, thereby reducing manufacturing costs. Therefore, due to the high resolution achieved with technological development, the use of CMOS image sensors is rapidly increasing. Summary of the invention

[0005] Provided are an image sensor having a wide dynamic range, an imaging device having the image sensor, and an operating method thereof.

[0006] According to an embodiment, an image sensor includes: a first sampling capacitor corresponding to a first illumination and connected to a power supply terminal; a second sampling capacitor corresponding to a second illumination and connected to the power supply terminal; a third sampling capacitor connected between a first sampling node and a second sampling node; a first transistor connected between a photodiode and a floating diffusion node and configured to be controlled by a transfer gate signal; a second transistor connected between the power supply terminal and an expansion node and configured to be controlled by a reset gate signal; a third transistor connected between the expansion node and the floating diffusion node and configured to be controlled by a conversion gain gate signal; a fourth transistor having a drain connected to the power supply terminal, a source connected to the sampling node, and a gate connected to the floating diffusion node; a fifth transistor connected to the a first sampling node and a second sampling node, and configured to be controlled by a pass signal; a sixth transistor connected between the sampling node and the first sampling node, and configured to be controlled by a sampling signal; a seventh transistor connected between the first sampling capacitor and the first sampling node, and configured to be controlled by a first switch signal; an eighth transistor connected between the second sampling capacitor and the first sampling node, and configured to be controlled by a second switch signal; a ninth transistor connected between the power supply terminal and the second sampling node, and configured to be controlled by an operation signal; a tenth transistor having a drain connected to the power supply terminal and a gate connected to the second sampling node; and an eleventh transistor connected between a source of the tenth transistor and a corresponding column line, and configured to be controlled by a selection signal.

[0007] According to an embodiment, an imaging device includes: at least one pixel array having a plurality of pixels connected between a plurality of row lines and a plurality of column lines; a row driver configured to select a row line from the plurality of row lines; a readout circuit configured to receive an analog pixel signal from a column line among the plurality of column lines corresponding to a pixel among the plurality of pixels connected to the selected row line, and convert the received analog pixel signal into a digital signal; a column driver configured to output image data corresponding to the column line based on the digital signal; a timing controller configured to control the operation timing of the at least one pixel array, the row driver, the readout circuit, and the column driver; and an image signal processor configured to process the image data output from the column driver, wherein each of the plurality of pixels is configured to perform a first sampling operation corresponding to a first illuminance and a second sampling operation corresponding to a second illuminance lower than the first illuminance.

[0008] According to an embodiment, an operating method of an image sensor includes: performing a first sampling operation corresponding to a first illumination in at least one pixel; performing a second sampling operation corresponding to a second illumination in the at least one pixel; and outputting a first pixel voltage corresponding to the first sampling operation, or outputting a second pixel voltage corresponding to the second sampling operation, in the at least one pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram schematically illustrating an imaging device 10 according to an example embodiment;

[0011] Figure 2 is a diagram schematically illustrating an image sensor 100 according to example embodiments;

[0012] Figure 3 is a diagram schematically illustrating a pixel PX according to an example embodiment;

[0013] Figure 4 is a schematic diagram showing a Figure 3 A timing diagram of the operation of the pixel PX shown;

[0014] Figure 5A , Figure 5B and Figure 5C is a diagram conceptually illustrating a sampling operation of a pixel PX under high illumination according to an example embodiment;

[0015] Fig. 6A , Figure 6B and Figure 6C is a diagram conceptually illustrating a sampling operation of a pixel PX under low illumination according to an example embodiment;

[0016] Figure 7 is a diagram schematically illustrating a pixel PXa according to another example embodiment;

[0017] Figure 8 is a diagram schematically illustrating a pixel PXb according to another example embodiment;

[0018] Fig. 9 is a diagram schematically illustrating a pixel PXc according to another example embodiment;

[0019] Fig.10 is a diagram schematically illustrating a pixel PXd according to another example embodiment;

[0020] Fig.11is a diagram schematically illustrating a pixel of a 2-PD structure according to an example embodiment;

[0021] Fig.12 is a diagram schematically illustrating an image sensor 300 according to another example embodiment; and

[0022] Fig.13 is a flowchart schematically illustrating the operation of a pixel according to example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, the embodiments will be described clearly and in detail with reference to the accompanying drawings. The embodiments described below are all exemplary, and thus, the inventive concept is not limited to the embodiments disclosed below and can be implemented in various other forms.

[0024] Figure 1 is a diagram showing an imaging device 10 according to an example embodiment. Figure 1 , the imaging device 10 may include an image sensor 100 and an image signal processor (ISP) 200 .

[0025] The image sensor 100 may be configured to detect an object. The image sensor 100 may include a pixel array 110 , a row driver 120 , a readout circuit 130 , a column driver 140 , and a timing controller 150 .

[0026] The pixel array 110 may include a plurality of pixels arranged in an array along a plurality of row lines and a plurality of column lines. Each of the plurality of pixels may include a color filter to allow light of a specific wavelength to pass through. For example, the color filter may allow wavelengths of a specific color region in the visible region of the wavelength to pass through. For example, the color filter may be at least one of a red filter that allows wavelengths of a red region to pass through, a green filter that allows wavelengths of a green region to pass through, and a blue filter that allows wavelengths of a blue region to pass through. In addition, the color filter may be at least one of a cyan filter, a yellow filter, and a magenta filter.

[0027] In an example embodiment, each of the plurality of pixels may include a photoelectric conversion element. For example, each of the plurality of pixels PX may include: a photodiode that generates a charge in response to an external incident light signal, and a pixel circuit that generates an electrical signal corresponding to the charge generated from the photodiode. Here, the photodiode may be a PIN photodiode having a structure in which an intrinsic semiconductor layer is inserted between PN junctions. In addition, the photodiode may also be an avalanche photodiode (APD) having an avalanche layer between PN junctions.

[0028] In example embodiments, each of the plurality of pixels may include at least two photodiodes. For example, each pixel may include at least two diodes to generate pixel signals corresponding to light of various colors or to provide an auto-focus function.

[0029] In addition, each pixel may include a pixel circuit for generating a pixel signal based on the charge generated by the photodiode. Here, the pixel circuit may include a transfer transistor, a drive transistor (e.g., a source follower transistor), a selection transistor, a reset transistor, and at least one conversion gain transistor. The pixel circuit may obtain a pixel signal by detecting a reset voltage and a pixel voltage from each of a plurality of pixels and calculating the difference. The pixel voltage may be a voltage corresponding to the charge generated in the photodiode included in each of the plurality of pixels.

[0030] In addition, the pixel circuit can be configured to change the conversion gain. In an example embodiment, the variability of the conversion gain can be performed by turning on or off at least one transistor. For example, the pixel circuit can perform dual conversion gains depending on whether the conversion gain transistor is turned on or off.

[0031] In addition, the pixel circuit can be configured to perform sampling operations according to various illuminations. In an example embodiment, the pixel circuit can perform a double sampling operation using a sampling capacitor. For example, the pixel circuit can perform a first sampling operation corresponding to high illumination and a second sampling operation corresponding to low illumination.

[0032] In example embodiments, at least two pixels adjacent to each other may constitute a pixel group. Here, two or more pixels included in the pixel group may share at least some of a transfer transistor, a drive transistor, a selection transistor, a reset transistor, and a conversion gain transistor.

[0033] The row driver 120 may be configured to drive the pixel array 110 in row units. For example, the row driver 120 may generate a transfer control signal to control a transfer transistor of a pixel circuit, a reset control signal to control a reset transistor, or a selection control signal to control a selection transistor.

[0034] The readout circuit 130 may be configured to convert the analog pixel signal generated from the pixel array 110 into a digital signal and output the digital signal. The readout circuit 130 may include a sampling circuit and an analog-to-digital converter (ADC). The sampling circuit may include a plurality of samplers. For example, a sampler among the plurality of samplers may be a correlated double sampler (CDS). The sampler may be connected to the pixels included in the row line selected by the row driver 120 via a column line, and may detect a reset voltage and a pixel voltage from the corresponding pixel. The sampler may compare each of the reset voltage and the pixel voltage with a ramp voltage and output the result. The ADC may convert the comparison result output by the sampler into a digital signal and output the digital signal. The ADC may convert the reset voltage and the pixel voltage detected by the correlated double sampler into a digital signal and transmit the converted digital signal to the column driver 140.

[0035] The column driver 140 may include a latch or buffer circuit and an amplification circuit for temporarily storing digital signals. The column driver 140 may process the digital signal received from the readout circuit 130. For example, the column driver 140 may output image data corresponding to a column line selected from a plurality of column lines in the digital signal to the image signal processor 200.

[0036] The timing controller 150 may be configured to control the operation timing of the row driver 120, the readout circuit 130 or the column driver 140. Specifically, the timing controller 150 may adjust the pixel operation timing to change the conversion gain. In addition, the timing controller 150 may adjust the pixel operation timing to perform a multi-sampling operation according to the illumination.

[0037] The image signal processor 200 may be configured to process the image data output from the readout circuit 130. For example, the image signal processor 200 may process the image data to generate a result image, and transmit the result image to a display or store the result image in a memory. For example, the image signal processor 200 may perform signal processing operations such as color interpolation, color correction, gamma correction, color space conversion, edge correction, etc. to generate image data.

[0038] An imaging device 10 according to example embodiments may include an image sensor 100 having pixels that may change conversion gain and perform multi-sampling according to illumination, thereby ensuring a high dynamic range (HDR).

[0039] Figure 2 is a diagram schematically illustrating an image sensor 100 according to example embodiments. Figure 2 , the image sensor 100 may include a pixel array 110 , a row driver 120 , and a readout circuit 130 .

[0040] The pixel array 110 may include a plurality of pixels PX disposed at intersections of a plurality of row lines RL and a plurality of column lines CL. 11 To PX MN .

[0041] The row driver 120 can control a plurality of pixels PX through a plurality of row lines RL inputs. 11 To PX MN For example, the row driver 120 may provide a reset control signal, which may be a reset gate signal RG, a transmission control signal, which may be a transmission gate signal TG, or a selection control signal, which may be a selection signal SL, to a plurality of pixels PX through a plurality of row lines RL. 11 To PX MN The row driver 120 may sequentially select each of the plurality of row lines RL. The row driver 120 may select one of the plurality of row lines RL during a predetermined horizontal period.

[0042] The readout circuit 130 may include a ramp voltage generator 131, a sampling circuit 132, and an ADC 133. The data output from the ADC 133 may be input to, for example, Figure 1 The column driver 140 is configured to:

[0043] The ramp voltage generator 131 may be configured to generate a ramp signal RMP in response to a ramp activation signal. The ramp signal may be a signal whose voltage increases or decreases in proportion to time.

[0044] The sampling circuit 132 can obtain the information from the plurality of pixels PX 11 To PX MN Some pixels connected to the row lines scanned by the row driver 120 in the sampling circuit 132 may obtain a reset voltage and a pixel voltage. The sampling circuit 132 may include a plurality of samplers SA, and the plurality of samplers SA may include a correlated double sampler. Each of the samplers SA may receive a ramp signal RMP from the ramp voltage generator 131 through a first input terminal, and receive a ramp signal RMP from a plurality of pixels PX through a second input terminal. 11 To PX MN reset voltage / pixel voltage.

[0045] The ADC 133 may output pixel data by converting the analog signal of the sampling circuit 132 into a digital signal.

[0046] In an embodiment, the image sensor 100 may be implemented in a two-stack structure. For example, a pixel array and peripheral circuits such as a row decoder, CDS, and ADC may be provided on a first layer, and a logic circuit (e.g., a power supply circuit, an I / O interface, an ISP, etc.) may be configured on a second layer. In another example, only a pixel array may be provided on a first layer, and peripheral circuits and logic circuits may be provided on a second layer.

[0047] In embodiments, the pixel PX according to example embodiments may be implemented in a dual conversion gain and dual sampling capacitor structure.

[0048] Figure 3 is a diagram schematically illustrating a pixel PX according to an example embodiment. Figure 3 , the pixel PX may include a photodiode PD and first to eleventh transistors T1 to T11.

[0049] The photodiode PD may be connected to a ground terminal GND.

[0050] The first transistor T1 may be connected between the photodiode PD and the floating diffusion node FD and may be controlled by a transmission gate signal TG. In an embodiment, the floating diffusion node FD may include a floating diffusion capacitor C corresponding to a floating diffusion region. FD .

[0051] The second transistor T2 may be connected between a power supply terminal VPIX providing a pixel driving voltage and an extension node EXT, and may be controlled by a reset gate signal RG. EXT can be connected between the power supply terminal VPIX and the extension node EXT. In another example embodiment, the extension capacitor C EXT It can be connected between the ground terminal GND and the extension node EXT.

[0052] The third transistor T3 may be connected between the extension node EXT and the floating diffusion node FD, and may be controlled by the conversion gain gate signal DCG.

[0053] The fourth transistor T4 may include a drain connected to the power terminal VPIX, a source connected to the sampling node SN, and a gate connected to the floating diffusion node FD.

[0054] The fifth transistor T5 may be connected to the sampling node SN and the ground terminal GND, and may be controlled by the pass signal PC.

[0055] The sixth transistor T6 may be connected between the sampling node SN and the first sampling node X, and may be controlled by the sampling signal SAMP.

[0056] The seventh transistor T7 may be connected between the first sampling capacitor C1L for the first illumination and the first sampling node X, and may be controlled by the first switching signal SWL. Here, the first sampling capacitor C1L for the first illumination may be connected between the power supply terminal VPIX and the drain of the seventh transistor T7. Here, the first illumination may be a high illumination.

[0057] The eighth transistor T8 may be connected between the second sampling capacitor C1H for the second illumination and the first sampling node X, and may be controlled by the second switching signal SWH. Here, the second sampling capacitor C1H for the second illumination may be connected between the power supply terminal VPIX and the drain of the eighth transistor T8. Here, the second illumination may be a low illumination.

[0058] The ninth transistor T9 may be connected between the power supply terminal VPIX and the second sampling node Y, and may be controlled by the operation signal CAL. Here, the third sampling capacitor C2 may be connected between the first sampling node X and the second sampling node Y.

[0059] The tenth transistor T10 may include a drain connected to the power terminal VPIX and a gate connected to the second sampling node Y.

[0060] The eleventh transistor T11 may be connected between the source of the tenth transistor T10 and the corresponding column line CL, and may be controlled by the selection signal SL.

[0061] The pixel PX according to example embodiments may perform a double conversion gain, and may perform a double sampling operation according to the first illuminance and the second illuminance.

[0062] Figure 4 It is schematically shown Figure 3 The timing diagram of the operation of the pixel PX is shown in FIG. Figure 3 and Figure 4 , the pixel PX can be operated as follows.

[0063] First, the pixel PX may perform an operation of storing the overflowed charge to the sampling capacitors C1L, C1H, and C2 through the floating diffusion node FD. When the reset gate signal RG is in a high level state, the transfer gate signal TG may be in a high level state. In this case, because the conversion gain gate signal DCG is in a high level state, the charge of the photodiode PD may be transferred to the sampling capacitors C1L, C1H, and C2 formed by the floating diffusion node FD and the expansion capacitor C EXT In addition, the sampling signal SAMP, the pass signal PC, the first switch signal SWL and the second switch signal SWH are at a high level, and the floating diffusion node FD and the extended capacitor C EXT The charges in the photodiode PD may be transferred to the first sampling capacitor C1L for the first illumination, the second sampling capacitor C1H for the second illumination, and the third sampling capacitor C2. Therefore, the charges overflowing from the photodiode PD may be stored in the sampling capacitors C1L, C1H, and C2.

[0064] In an embodiment, after the overflowed charge is stored in the sampling capacitors C1L, C1H, and C2, a low illumination sampling operation may be performed. After the transmission gate signal TG is maintained in a high level state, the sampling signal SAMP and the pass signal PC may be maintained at a high level for a predetermined time. In this case, because the first switch signal SWL is in a low level state and the second switch signal SWH is in a high level state, the second sampling capacitor C1H for the second illumination may store the charge of the floating diffusion node FD. Here, the second illumination may be a low illumination with a high conversion gain (HCG). Thereafter, by changing the pass signal PC and the selection signal SL to a high level state, the signal voltage of the second sampling capacitor C1H for the second illumination may be read. Thereafter, while the sampling signal SAMP is in a high level state, the operation signal CAL may be maintained in a high level state for a predetermined time. As a result, the charge for the reset state C1H RST may be stored in the second sampling capacitor C1H for the second illumination. Thereafter, the sampling signal SAMP in a low level state may be read within a predetermined time by the reset voltage of the second sampling capacitor C1H for the second illumination. Through the above process, a low illumination sampling operation can be performed.

[0065] In an embodiment, after performing a low illumination sampling operation, a high illumination sampling operation may be performed. Because the first switch signal is in a high level state and the second switch signal SWH is in a low level state, when the selection signal SL is in a low level state, the first sampling capacitor C1L for the first illumination may store the charge of the floating diffusion node FD. Here, the first illumination may be a high illumination with a low conversion gain (LCG). Thereafter, by changing the selection signal SL to a high level state, the signal voltage of the first sampling capacitor C1L for the first illumination may be read. Thereafter, while the sampling signal SAMP is in a high level state, the operation signal CAL may be maintained in a high level state for a predetermined time. Therefore, the charge for the reset state C1L RST may be stored in the first sampling capacitor C1L for the first illumination. Thereafter, the sampling signal SAMP in a low level state may be read within a predetermined time by the reset voltage of the first sampling capacitor C1L for the first illumination. Through the above process, a high illumination sampling operation may be performed.

[0066] Figure 5A , Figure 5B ,and Figure 5C is a diagram conceptually illustrating a sampling operation of a pixel PX under high illumination according to an embodiment.

[0067] Under high illumination, an overflow of charge may occur. Figure 5A, the pixel PX can store the overflowing charge from the photodiode PD in the floating diffusion node FD and the extended capacitor C in response to the conversion gain gate signal DCG in the on state. EXT When the sampling signal SAMP and the first switch signal SWL are in a high level state, the first sampling capacitor C1L for the first illumination may store charges corresponding to the overflowed charges.

[0068] In such Figure 5A After the overflowing charge is stored in the first sampling capacitor C1L for the first illumination as shown, while the conversion gain gate signal DCG is in the off state, the transmission gate signal TG may be in the on state, as shown in FIG. Figure 5B As shown. Figure 5B In the embodiment of the present invention, the charges of the photodiode PD may be transferred to the floating diffusion node FD. As a result, the floating diffusion node FD may store the charges overflowing from the photodiode PD and the charges transferred from the photodiode PD.

[0069] In such Figure 5B After the charge of the photodiode PD is stored in the floating diffusion node FD, the transmission gate signal TG may be turned off, as shown in FIG. Figure 5B When the sampling signal SAMP and the second switch signal SWH are in a high level state, the second sampling capacitor C1H for the second illumination may store charges corresponding to the charges stored in the photodiode PD.

[0070] As mentioned above, this can be done by Figure 5A , Figure 5B and Figure 5C The process shown completes the sampling operation of the pixel PX under high illumination conditions.

[0071] Fig. 6A , Figure 6B and Figure 6C is a diagram conceptually illustrating a sampling operation of a pixel PX under low illumination according to an embodiment.

[0072] In low light conditions, Figure 5A The overflow charge shown may not occur. Fig. 6A , the pixel PX can store the charge from the photodiode PD in the floating diffusion node FD and the extended capacitor C in response to the conversion gain gate signal DCG in the on state. EXT Since no charge overflows from the photodiode PD, the charge amount of the first sampling capacitor for the first illumination will not change.

[0073] Afterwards, refer to Figure 6B , the transmission gate signal TG can be turned on while the conversion gain gate signal DCG is turned off. Figure 6B As shown, the charges of the photodiode PD may be transferred to the floating diffusion node FD. As a result, the floating diffusion node FD may store the charges transferred from the photodiode PD.

[0074] In such Figure 6B After the charge of the photodiode PD is stored in the floating diffusion node FD, refer to Figure 6C , the transmission gate signal TG may be turned off. When the sampling signal SAMP and the second switch signal SWH are in a high level state, the second sampling capacitor C1H for the second illumination may store charges corresponding to the charges stored in the photodiode PD.

[0075] As mentioned above, this can be done by Fig. 6A , Figure 6B and Figure 6C The process shown completes the sampling operation of the pixel PX under low illumination conditions.

[0076] In an embodiment, a pixel may be added with a small size photodiode for light emitting diode (LED) flicker mitigation.

[0077] Figure 7 is a diagram schematically illustrating a pixel PXa according to another example embodiment. Figure 7 , pixel PXa and Figure 3 The pixel PX shown in FIG. 1 is different in that the pixel PXa is added with a secondary photodiode (SPD) connected between the extension node EXT and the ground terminal GND, and an extension capacitor C EXT Connect to the ground terminal GND instead of the power terminal VPIX.

[0078] The pixel PXa according to example embodiments may correspond to LED flicker mitigation by using a small-sized PD only for long exposure (>10 ms).

[0079] In addition, the pixel PXa according to example embodiments may store intra-pixel HCC / LCG signal data at a minimum time interval by adding C1H and C1L. As a result, high dynamic range (HDR) and motion artifacts may be minimized.

[0080] In an embodiment, Figures 3 to 7 The pixels PX and PXa shown in are pixels with transistor T3 to implement dual conversion gain. However, the pixel may not use a transistor to implement dual conversion gain. For example, the pixel may implement dual conversion gain by using the time difference of the charge transfer of the transfer transistor. For example, the transfer transistor may transfer charge to the floating diffusion node FD at a time shorter than a reference value under high illumination, and may transfer charge to the floating diffusion node FD at a time longer than the reference value under low illumination.

[0081] Figure 8 is a diagram schematically illustrating a pixel PXb according to another example embodiment. Figure 8 , pixel PXb and Figure 3 The pixel PX shown differs in that the third transistor T3 is omitted.

[0082] In an embodiment, Figures 3 to 8 The pixels PX, PXa, and PXb shown in FIG. 1 include sampling capacitors C1L, C1H, and C2 having a gamma (Γ) structure. However, the type of the sampling capacitor is not necessarily limited to the gamma type. For example, the sampling capacitor may be implemented in a pi (Π) type structure.

[0083] Fig. 9 is a diagram schematically illustrating a pixel PXc according to another example embodiment. Fig. 9 , pixel PXc and Figure 3 The pixel PX shown is different in the connection relationship between the sampling capacitors C1L, C1H, and C2.

[0084] like Fig. 9 As shown, the sampling capacitors C1L, C1H and C2 may be connected in a pi (Π) structure. The first switch SWL and the second switch SWH may be connected to the first sampling node. The first sampling capacitor C1L for the first illumination may be connected to the first switch SWL and the ground terminal GND, and the second sampling capacitor C1H for the second illumination may be connected between the second switch SWH and the ground terminal GND. The ninth transistor T9 may connect the first sampling node X and the second sampling node Y in response to the operation signal CAL. The third sampling capacitor C2 may be connected between the second sampling node Y and the ground terminal GND.

[0085] In embodiments, pixels according to example embodiments may share a plurality of photodiodes.

[0086] Fig.10 is a diagram schematically illustrating a pixel PXd according to another example embodiment. Fig.10 , pixel PXd and Figure 3 The pixel PX shown is different in that the pixel PXd includes a plurality of photodiodes PD1, ..., PDk and a plurality of transfer transistors T1_1, ..., T1_k. Each of the plurality of transfer transistors T1_1, ..., T1_k can transfer the charge of the photodiode PD1, ..., PDk controlled by the corresponding transfer gate signal TGS1, ...TGSk to a floating diffusion region, which can correspond to a floating diffusion node FD.

[0087] In embodiments, pixels according to example embodiments may be implemented in a 2-PD structure sharing one floating diffusion region.

[0088] In addition, Figures 7 to 10 In the embodiment, the left portion including PD based on the node SN can be located on the top plate of the sensor. In addition, the right portion including the transistor T5 can be implemented in a stacked shape on the lower plate of the sensor.

[0089] In an embodiment, the global shutter may include a color filter to process RGB data. In addition, the global shutter may be driven as an IR global shutter by having a transparent layer without a color filter and absorbing infrared light.

[0090] Fig.11 Schematically shows a pixel of a 2-PD structure. Fig.11 Two pixels may be shown: a G pixel PX1 and an R pixel PX2, each of which may be a 2-PD pixel having a left PD and a right PD. Fig.11 , the 2-PD pixel can separate the left PD and the right PD by deep trench isolation (DTI) in the pixel. The floating diffusion region can be commonly connected to a pair of left PD and right PD set in the pixel. That is, the floating diffusion region can be commonly connected to four photoelectric conversion elements. For example, the floating diffusion region may include N-type impurities. The first transfer gate TG1 and the second transfer gate TG2 set on the substrate of the first pixel PX1 and the first transfer gate TG1 and the second transfer gate TG2 set on the substrate of the second pixel PX2 can share the floating diffusion region.

[0091] In an embodiment, the length of the DTI between PX1 and PX2 may be longer than the length of the intra-pixel DTI. In an embodiment, the first surface and the second surface of the substrate may be connected by a front deep trench isolation FDTI. In an embodiment, the intra-pixel DTI may be formed by extending in a portion having a microlens, such as Fig.11 In other embodiments, the intra-pixel DTI may be formed by extending near the FD. In embodiments, the intra-pixel DTI may not be connected to the substrate.

[0092] In embodiments, an image sensor according to example embodiments may be provided with a plurality of pixel arrays.

[0093] Fig.12 is a diagram schematically illustrating an image sensor 300 according to another example embodiment. Fig.12 , the image sensor 300 may include a pixel array 310 , a control unit 325 , a row decoder 333 , a row driver 335 , a column decoder 353 , a column driver 355 , and an ADC 370 .

[0094] The pixel array 310 may detect light reflected from an object to generate object information and / or image information of the object. The pixel array 310 may include a plurality of pixels arranged in a two-dimensional matrix form. The pixel array 310 may include a plurality of pixel layers 311, 313, and 315. In an example embodiment, the first pixel layer 311 may be a color pixel array (CPA). For example, the color pixel array may have pixels of a Bayer pattern. In an example embodiment, the second pixel layer 313 may be a depth pixel array (DPA). For example, the depth pixel array may include a plurality of 2-PD pixels or metal shielding pixels. In an example embodiment, the second pixel layer 313 may include at least one temperature sensor for performing depth correction according to temperature. In an embodiment, the third pixel layer 315 may be a thermal pixel array (TPA). For example, the thermal pixel array may include a plurality of temperature pixels.

[0095] In an embodiment, each of the plurality of pixel layers 311, 313, and 315 may have at least one pixel that performs double conversion gain or double sampling, such as Figures 1 to 11 shown.

[0096] In the embodiments, it should be understood that the number of pixel arrays is not limited thereto.A pixel array according to example embodiments may include at least two pixel layers that perform different functions.

[0097] The control unit 325 may generate a control signal for controlling operations of each of the row decoder 333, the row driver 335, the column decoder 353, the column driver 355, and the plurality of ADCs 371, 373, and 375. For example, the control unit 325 may generate a plurality of row control signals for selecting a specific row line among a plurality of row lines included in each of the plurality of stacked pixel layers 311, 313, and 315. In example embodiments, the control unit 325 may be disposed on a different layer from the pixel array 310.

[0098] The row decoder 333 may decode a plurality of row control signals (e.g., row address signals) output from the control unit 325, and output a plurality of row selection signals according to the decoding results. The row driver 335 may drive pixels included in at least one of a plurality of rows included in each of the plurality of pixel layers 311, 313, and 315 in response to each of the plurality of row selection signals output from the row decoder 333.

[0099] The column decoder 353 may decode a plurality of column control signals (e.g., column address signals) output from the control unit 325, and output a plurality of column selection signals according to the decoding results. The column driver 355 may drive each of a plurality of column lines included in each of the plurality of pixel layers 311, 313, and 315 in response to each of the plurality of column selection signals output from the column decoder 353.

[0100] In the embodiment, although Fig.12 The image sensor 300 shown in FIG. 1 includes one row driver 335 and one column driver 355, but the inventive concept is not necessarily limited thereto. According to example embodiments, the image sensor 300 may include a plurality of row drivers or a plurality of column drivers for driving row lines or column lines of each of the plurality of pixel layers 311, 313, and 315. In an embodiment, the image sensor 300 may include a plurality of row decoders or a plurality of column decoders.

[0101] Each of the plurality of ADCs 371, 373, and 375 may analog-to-digital convert a signal output from each of the plurality of pixel layers 311, 313, and 315, and may output the analog-to-digital converted signal as image data to the ISP 200. For example, the image data may include object information or image information.

[0102] According to example embodiments, each of the plurality of ADCs 371, 373, and 375 may further include a CDS circuit for performing correlated double sampling on a signal output from each of the plurality of pixel layers 311, 313, and 315. In this case, each of the plurality of ADCs 371, 373, and 375 may compare the correlated double sampling signal with the ramp signal and output the comparison result as image data.

[0103] An image signal processor (ISP) 200 may process to display image data.

[0104] In an embodiment, the imaging device 10 according to example embodiments may be applied to an electronic device.

[0105] Fig.13 is a flowchart schematically illustrating the operation of a pixel according to an example embodiment. Fig.13 , the pixel operation can be performed as follows.

[0106] At operation S110, a first sampling operation corresponding to a first illumination may be performed on the pixel PX. Charge corresponding to the first sampling operation may be stored in the capacitor C1L for the first illumination. At operation S120, a second sampling operation corresponding to a second illumination may be performed on the pixel PX. Charge corresponding to the second sampling operation may be stored in the capacitor C1H for the second illumination. At operation S130, a first pixel voltage corresponding to the first sampling operation may be output, or a second pixel voltage corresponding to the second sampling operation may be output.

[0107] As described above, according to example embodiments, an image sensor, an imaging device having the same, and an operating method thereof may implement a wide dynamic range by including pixels that perform double conversion gain and double sampling.

[0108] The various advantageous advantages and effects of the present invention are not limited to the above description. Although example embodiments have been shown and described above, it is apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. An image sensor, include: a first sampling capacitor corresponding to a first illumination and connected to a power supply terminal; a second sampling capacitor corresponding to a second illumination and connected to the power supply terminal; a third sampling capacitor connected between the first sampling node and the second sampling node; a first transistor connected between the photodiode and the floating diffusion node and configured to be controlled by a transfer gate signal; a second transistor connected between the power supply terminal and the expansion node and configured to be controlled by a reset gate signal; a third transistor connected between the extension node and the floating diffusion node and configured to be controlled by a conversion gain gate signal; a fourth transistor having a drain connected to the power supply terminal, a source connected to the sampling node, and a gate connected to the floating diffusion node; a fifth transistor connected between the sampling node and a ground terminal and configured to be controlled by a pass signal; a sixth transistor connected between the sampling node and the first sampling node and configured to be controlled by a sampling signal; a seventh transistor connected between the first sampling capacitor and the first sampling node and configured to be controlled by a first switching signal; an eighth transistor connected between the second sampling capacitor and the first sampling node and configured to be controlled by a second switching signal; a ninth transistor connected between the power supply terminal and the second sampling node and configured to be controlled by an operation signal; a tenth transistor having a drain connected to the power supply terminal and a gate connected to the second sampling node; as well as The eleventh transistor is connected between the source of the tenth transistor and the corresponding column line and is configured to be controlled by the selection signal. 2 . The image sensor according to claim 1 , further comprising an extension capacitor connected between the extension node and the ground terminal. 3 . The image sensor according to claim 2 , further comprising a secondary photodiode connected between the extended node and the ground terminal. 4 . The image sensor according to claim 1 , further comprising an extension capacitor connected between the extension node and the power supply terminal.

5. The image sensor according to claim 1, in, Based on the conversion gain gate signal being at a high level, charges overflowing from the photodiode are stored in the first sampling capacitor.

6. The image sensor according to claim 5, in, After storing the overflowing charges in the first sampling capacitor for the first illuminance, charges corresponding to the second illuminance are stored in the floating diffusion node based on the conversion gain gate signal being at a low level and the transfer gate signal being at the high level for a predetermined time.

7. The image sensor according to claim 6, in, Based on the transmission gate signal being at the low level and the second switch signal being at the high level, a second sampling operation for storing the charge corresponding to the second illuminance in the second sampling capacitor is performed.

8. The image sensor according to claim 7, in, After performing the second sampling operation, charges corresponding to the first illuminance are stored in the floating diffusion node based on the conversion gain gate signal being at the low level and the transfer gate signal being at the high level for the predetermined time.

9. The image sensor according to claim 8, in, Based on the transmission gate signal being at the low level and the first switch signal being at the high level, a first sampling operation for storing the charge corresponding to the first illuminance in the first sampling capacitor is performed.

10. The image sensor according to claim 1, in, The first illuminance is higher than the second illuminance.

11. An imaging device, include: at least one pixel array having a plurality of pixels connected between a plurality of row lines and a plurality of column lines; a row driver configured to select a row line from the plurality of row lines; a readout circuit configured to receive analog pixel signals from column lines among the plurality of column lines corresponding to pixels among the plurality of pixels connected to the selected row line, and convert the received analog pixel signals into digital signals; a column driver configured to output image data corresponding to the column line based on the digital signal; a timing controller configured to control the operation timing of the at least one pixel array, the row driver, the readout circuit, and the column driver; as well as an image signal processor configured to process the image data output from the column driver, wherein each of the plurality of pixels is configured to perform a first sampling operation corresponding to a first illumination and a second sampling operation corresponding to a second illumination lower than the first illumination, Wherein, each of the plurality of pixels comprises: a first sampling capacitor corresponding to the first illumination and connected to a power supply terminal; a second sampling capacitor corresponding to the second illumination and connected to the power supply terminal; a third sampling capacitor connected between the first sampling node and the second sampling node; a fourth transistor having a drain connected to the power supply terminal, a source connected to the sampling node, and a gate connected to the floating diffusion node; a fifth transistor connected between the sampling node and a ground terminal and configured to be controlled by a pass signal; a sixth transistor connected between the sampling node and the first sampling node and configured to be controlled by a sampling signal; a seventh transistor connected between the first sampling capacitor and the first sampling node and configured to be controlled by a first switching signal; an eighth transistor connected between the second sampling capacitor and the first sampling node and configured to be controlled by a second switching signal; a ninth transistor connected between the power supply terminal and the second sampling node and configured to be controlled by an operation signal; and a tenth transistor having a drain connected to the power supply terminal and a gate connected to the second sampling node.

12. The imaging device according to claim 11, in, Each of the plurality of pixels is configured to perform a conversion gain variation operation.

13. The imaging device according to claim 11, in, Each of the plurality of pixels includes at least two photodiodes.

14. The imaging device according to claim 11, in, Each of the plurality of pixels further comprises: a first transistor connected between the photodiode and the floating diffusion node and configured to be controlled by a transfer gate signal; a second transistor connected between the power supply terminal and the floating diffusion node and configured to be controlled by a reset gate signal; and The eleventh transistor is connected between the source of the tenth transistor and the corresponding column line and is configured to be controlled by the selection signal.

15. The imaging device according to claim 11, in, Each of the plurality of pixels further comprises: a first transistor connected between the photodiode and the floating diffusion node and configured to be controlled by a transfer gate signal; a second transistor connected between the power supply terminal and the expansion node and configured to be controlled by a reset gate signal; a third transistor connected between the extension node and the floating diffusion node and configured to be controlled by a conversion gain gate signal; and The eleventh transistor is connected between the source of the tenth transistor and the corresponding column line and is configured to be controlled by the selection signal.

16. The imaging device according to claim 15, further comprising: include: an extension capacitor connected between the extension node and the ground terminal; as well as A secondary photodiode is connected between the extended node and the ground terminal.

17. An operating method of an image sensor, the operating method include: performing a first sampling operation corresponding to a first illumination in at least one pixel; performing a second sampling operation corresponding to a second illumination in the at least one pixel; as well as In the at least one pixel, a first pixel voltage corresponding to the first sampling operation is output, or a second pixel voltage corresponding to the second sampling operation is output, Wherein, each of the at least one pixel comprises: a first sampling capacitor corresponding to the first illumination and connected to a power supply terminal; a second sampling capacitor corresponding to the second illumination and connected to the power supply terminal; a third sampling capacitor connected between the first sampling node and the second sampling node; a fourth transistor having a drain connected to the power supply terminal, a source connected to the sampling node, and a gate connected to the floating diffusion node; a fifth transistor connected between the sampling node and a ground terminal and configured to be controlled by a pass signal; a sixth transistor connected between the sampling node and the first sampling node and configured to be controlled by a sampling signal; a seventh transistor connected between the first sampling capacitor and the first sampling node and configured to be controlled by a first switching signal; and an eighth transistor connected between the second sampling capacitor and the first sampling node and configured to be controlled by a second switching signal; a ninth transistor connected between the power supply terminal and the second sampling node and configured to be controlled by an operation signal; and a tenth transistor having a drain connected to the power supply terminal and a gate connected to the second sampling node.

18. The method for operating an image sensor according to claim 17, in, The at least one pixel is configured to perform dual conversion gain.

19. The method for operating an image sensor according to claim 17, further comprising: include: Light emitting diode flicker mitigation is performed using a secondary photodiode in the at least one pixel.

20. The method for operating an image sensor according to claim 17, further comprising: include: The overflowed electric charges corresponding to the first illumination are stored in a capacitor.

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