Solid-state image sensor

Abstract

A solid-state imaging element (100) according to the present disclosure is provided with a first semiconductor substrate (200) having a photoelectric conversion element (102) and a second semiconductor substrate (300) facing the first semiconductor substrate (200) via an insulating film (240). The second semiconductor substrate (300) has an amplifying transistor (104) for amplifying an electrical signal output from the photoelectric conversion element (102) on a first main surface (MSa); and a region (302) having a lower resistance than the resistance of the second semiconductor substrate (300) on a second main surface (MSb) opposite to the first main surface (MSa). The second semiconductor substrate (300) is grounded via the region (302).

Description

Technical Field

[0001] The present disclosure relates to a solid-state image sensor. Background Art

[0002] There is a three-dimensional mounting technology for stacking multiple semiconductor substrates. For example, in a solid-state image sensor, it is known to stack a first semiconductor substrate having a pixel region formed thereon and a second semiconductor substrate having a logic circuit formed thereon (for example, see Patent Document 1).

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2010-245506 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] A sufficient space for arranging pixel transistors cannot be ensured in the solid-state image sensor disclosed in Patent Document 1. Therefore, for example, it is conceivable to further separate and stack the substrate in which the photoelectric conversion element is formed and the substrate in which the pixel transistor is formed.

[0008] However, in this configuration, the potential of the substrate in which the pixel transistor is formed is not fixed, and the operation of the pixel transistor becomes unstable.

[0009] Therefore, the present disclosure proposes a solid-state image sensor capable of fixing the potential of stacked substrates while ensuring a space for arranging transistors.

[0010] Solution to the problem

[0011] According to the present disclosure, a solid-state image sensor includes: a first semiconductor substrate having a photoelectric conversion element; and a second semiconductor substrate facing the first semiconductor substrate via an insulating film, wherein the second semiconductor substrate has an amplifying transistor on a first main surface for amplifying an electrical signal output from the photoelectric conversion element, and has a region on a second main surface opposite to the first main surface with a resistance lower than that of the second semiconductor substrate and is grounded via the region. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing an example of a schematic configuration of a solid-state image sensor applicable to each embodiment of the present disclosure.

[0013] Figure 2 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0014] Figure 3 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0015] Figure 4 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0016] Figure 5 It is shown Figure 1 Diagram of an example of a sensor pixel and readout circuitry.

[0017] Figure 6 is a diagram showing an example of a connection pattern of a plurality of readout circuits and a plurality of vertical signal lines.

[0018] Figure 7 It is shown Figure 1 FIG. 1 is a diagram showing an example of a cross-sectional configuration of a solid-state image sensor in the horizontal direction.

[0019] Figure 8 It is shown Figure 1 FIG. 1 is a diagram showing an example of a cross-sectional configuration of a solid-state image sensor in the horizontal direction.

[0020] Fig. 9 It is shown Figure 1 A diagram showing an example of a wiring layout of a solid-state image sensor in a horizontal plane.

[0021] Fig.10 It is shown Figure 1 A diagram showing an example of a wiring layout of a solid-state image sensor in a horizontal plane.

[0022] Fig.11 It is shown Figure 1 A diagram showing an example of a wiring layout of a solid-state image sensor in a horizontal plane.

[0023] Fig.12 It is shown Figure 1 A diagram showing an example of a wiring layout of a solid-state image sensor in a horizontal plane.

[0024] Fig.13 It is shown Figure 1 FIG. 1 is a diagram showing a modified example of a cross-sectional structure of a solid-state image sensor in a horizontal direction.

[0025] Fig.14 It is shown Figure 1 FIG. 1 is a diagram showing a modified example of a cross-sectional structure of a solid-state image sensor in a horizontal direction.

[0026] Fig.15 It is shown Figure 1 FIG. 1 is a diagram showing a modified example of a cross-sectional structure of a solid-state image sensor in a horizontal direction.

[0027] Fig.16 It is shown Figure 1 FIG. 1 is a diagram showing a modified example of a cross-sectional structure of a solid-state image sensor in a horizontal direction.

[0028] Fig.17 It is shown Figure 1 FIG. 1 is a diagram showing a modified example of a cross-sectional structure of a solid-state image sensor in a horizontal direction.

[0029] Fig.18 It is shown Figure 1 FIG. 1 is a diagram showing a modified example of a cross-sectional structure of a solid-state image sensor in a horizontal direction.

[0030] Fig.19 It is shown Figure 1 FIG. 1 is a diagram showing a modified example of a cross-sectional structure of a solid-state image sensor in a horizontal direction.

[0031] Fig. 20 It shows that according to Figure 1 Schematic diagram of a modified example of the circuit configuration of a solid-state image sensor having a configuration and a modified example thereof.

[0032] Fig.21 It shows that Fig. 20 A diagram of an example in which a solid-state image sensor is formed by stacking three substrates.

[0033] Fig. 22 is a diagram showing an example in which a logic circuit is divided between a substrate provided with sensor pixels and a substrate provided with a readout circuit.

[0034] Fig.23 is a diagram showing an example in which a logic circuit is formed on a third substrate.

[0035] Fig.24 is a diagram showing a part of a cross section of a solid-state image sensor according to a first embodiment of the present disclosure.

[0036] Fig.25 : is a schematic diagram showing the vicinity of a bonding position of a substrate of the solid-state image sensor according to the first embodiment of the present disclosure.

[0037] Fig.26 is a flowchart showing an example of a procedure of a manufacturing process of the solid-state image sensor according to the first embodiment of the present disclosure.

[0038] Fig. 27 is a flowchart showing an example of a procedure of a manufacturing process of the solid-state image sensor according to the first embodiment of the present disclosure.

[0039] Fig.28 is a flowchart showing an example of a procedure of a manufacturing process of the solid-state image sensor according to the first embodiment of the present disclosure.

[0040] Fig.29 is a diagram for comparing the solid-state image sensors according to the first embodiment of the present disclosure and Comparative Examples 1 and 2.

[0041] Fig.30 is a diagram showing the configuration of pixel transistors of the solid-state image sensor according to the first embodiment of the present disclosure and Comparative Example 2.

[0042] Fig.31 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a solid-state image sensor according to Modification 1 of the first embodiment of the present disclosure.

[0043] Fig.32 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a solid-state image sensor according to Modification 2 of the first embodiment of the present disclosure.

[0044] Fig.33 : is a diagram showing a part of the cross section of a solid-state image sensor according to Modification 3 of the first embodiment of the present disclosure.

[0045] Fig.34 : is a diagram showing a part of the cross section of a solid-state image sensor according to Modification 4 of the first embodiment of the present disclosure.

[0046] Fig.35 : is a schematic diagram showing the vicinity of a bonding position of a substrate of a solid-state image sensor according to a second embodiment of the present disclosure.

[0047] Fig.36 is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to the second embodiment of the present disclosure.

[0048] Fig.37 is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to the second embodiment of the present disclosure.

[0049] Fig.38 is a diagram for comparing the solid-state image sensors according to the second embodiment of the present disclosure and Comparative Examples 1 and 2.

[0050] Fig.39 is a diagram showing the configuration of pixel transistors of a solid-state image sensor according to the second embodiment of the present disclosure and Comparative Example 2.

[0051] Fig.40 is a diagram showing connections between respective elements of a solid-state image sensor according to a second embodiment of the present disclosure.

[0052] Fig.41 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a solid-state image sensor according to Modification 1 of the second embodiment of the present disclosure.

[0053] Fig.42 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a solid-state image sensor according to Modification 2 of the second embodiment of the present disclosure.

[0054] Fig.43 : is a diagram for comparing the solid-state image sensors according to the second embodiment of the present disclosure, Modification 2 thereof, and Comparative Examples 1 and 2.

[0055] Fig.44 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a solid-state image sensor according to Modification 3 of the second embodiment of the present disclosure.

[0056] Fig.45 is a diagram showing a part of a solid-state image sensor according to a third embodiment of the present disclosure.

[0057] Fig.46 It is a comparison diagram in the case where the configurations of the first and second embodiments of the present disclosure and Comparative Example 2 are applied to the solid-state image sensor according to the third embodiment.

[0058] Fig.47 1 is a schematic diagram showing the vicinity of a bonding position of a substrate in the case where the configuration of the first embodiment of the present disclosure is applied to a semiconductor device according to a fourth embodiment.

[0059] Fig.48 It is a schematic diagram showing the vicinity of a bonding position of a substrate in the case where the configuration of the second embodiment of the present disclosure is applied to a semiconductor device according to a fourth embodiment.

[0060] Fig.49 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a semiconductor device according to Modification 1 of the fourth embodiment of the present disclosure.

[0061] Fig.50 1 is a schematic diagram showing the vicinity of a bonding position of a substrate of a semiconductor device according to Modification 2 of the fourth embodiment of the present disclosure.

[0062] Fig.51 : is a longitudinal sectional view showing the vicinity of a bonding position of a substrate of a solid-state image sensor according to a fifth embodiment of the present disclosure.

[0063] Fig.52 is a cross-sectional view near a bonding position of a substrate including a solid-state image sensor according to a fifth embodiment of the present disclosure.

[0064] Fig.53 is a perspective view showing a part of a solid-state image sensor according to a fifth embodiment of the present disclosure.

[0065] Fig.54is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to a fifth embodiment of the present disclosure.

[0066] Fig.55 is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to a fifth embodiment of the present disclosure.

[0067] Fig.56 is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to a fifth embodiment of the present disclosure.

[0068] Fig.57 is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to a fifth embodiment of the present disclosure.

[0069] Fig.58 : is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to Modification 1 of the fifth embodiment of the present disclosure.

[0070] Fig.59 : is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to Modification 1 of the fifth embodiment of the present disclosure.

[0071] Fig.60 : is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to Modification 2 of the fifth embodiment of the present disclosure.

[0072] Fig.61 is a diagram showing an example of a schematic configuration of an imaging system including the above-described solid-state image sensor.

[0073] Fig.62 It is shown Fig.61 FIG. 1 is a diagram of an example of an imaging process in an imaging system.

[0074] Fig.63 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0075] Fig.64 2 is an explanatory diagram showing an example of installation positions of the vehicle exterior information detection unit and the imaging unit.

[0076] Fig.65 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0077] Fig.66 : is a block diagram showing an example of the functional configuration of a camera and a CCU.

[0078] Fig.67 is a block diagram illustrating an example of a functional configuration of an imaging device according to a seventh embodiment of the present disclosure.

[0079] Fig.68 It is shown Fig.67 A schematic plan view of the schematic structure of the imaging device shown.

[0080] Fig.69 It is shown along Fig.68 The schematic diagram is a cross-section taken along line III-III'.

[0081] Fig.70 yes Fig.67 The equivalent circuit diagram of the pixel sharing unit is shown.

[0082] Fig.71 is a diagram showing an example of a connection pattern of a plurality of pixel sharing units and a plurality of vertical signal lines.

[0083] Fig.72 It is shown Fig.69 Schematic cross-sectional view of an example of a specific configuration of the imaging device shown.

[0084] Fig.73A It is shown Fig.72 A schematic diagram showing an example of a planar configuration of a main portion of the first substrate is shown.

[0085] Fig.73B The pad portion is shown together with Fig.73A A schematic diagram of the plane structure of the main part of the first substrate is shown.

[0086] Fig.74 It is shown Fig.72 Schematic diagram of an example of a planar configuration of the second substrate (semiconductor layer) shown.

[0087] Fig.75 is a diagram showing the main parts of the pixel circuit and the first substrate together with Fig.72 FIG. 1 is a schematic diagram showing an example of a planar configuration of a first wiring layer.

[0088] Fig.76 It is shown Fig.72 Schematic diagram of an example of a planar configuration of a first wiring layer and a second wiring layer shown.

[0089] Fig.77 It is shown Fig.72 Schematic diagram of an example of a planar configuration of a second wiring layer and a third wiring layer shown.

[0090] Fig.78 It is shown Fig.72 Schematic diagram of an example of a planar configuration of a third wiring layer and a fourth wiring layer shown.

[0091] Fig.79 It is used to illustrate Fig.69A schematic diagram of the path of the input signal of the imaging device is shown.

[0092] Fig.80 It is used to illustrate Fig.69 Schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0093] Fig.81 It is shown Fig.74 Schematic diagram of a modification of the planar structure of the second substrate (semiconductor layer) shown.

[0094] Fig.82 is a diagram showing the main part of the first wiring layer and the first substrate together with Fig.81 A schematic diagram of the planar structure of the pixel circuit shown.

[0095] Fig.83 The second wiring layer is shown together with Fig.82 FIG. 1 is a schematic diagram showing an example of a planar configuration of a first wiring layer.

[0096] Fig.84 The third wiring layer is shown together with Fig.83 Schematic diagram of an example of a planar configuration of a second wiring layer shown.

[0097] Fig.85 The fourth wiring layer is shown together with Fig.84 Schematic diagram of an example of a planar configuration of a third wiring layer shown.

[0098] Fig.86 It is shown Fig.73A A schematic diagram of a modified example of the planar structure of the first substrate shown.

[0099] Fig.87 It is shown that the stacking Fig.86 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate is shown.

[0100] Fig.88 It is shown Fig.87 Schematic diagram of an example of a planar configuration of a pixel circuit and a first wiring layer shown.

[0101] Fig.89 The second wiring layer is shown together with Fig.88 FIG. 1 is a schematic diagram showing an example of a planar configuration of a first wiring layer.

[0102] Fig.90 The third wiring layer is shown together with Fig.89 Schematic diagram of an example of a planar configuration of a second wiring layer shown.

[0103] Fig.91 The fourth wiring layer is shown together with Fig.90Schematic diagram of an example of a planar configuration of a third wiring layer shown.

[0104] Fig.92 It is shown Fig.86 Schematic diagrams of other examples of the plane structure of the first substrate shown.

[0105] Fig.93 It is shown that the stacking Fig.92 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate is shown.

[0106] Fig.94 The first wiring layer is shown together with Fig.93 A schematic diagram of an example of a planar configuration of a pixel circuit is shown.

[0107] Fig.95 The second wiring layer is shown together with Fig.94 FIG. 1 is a schematic diagram showing an example of a planar configuration of a first wiring layer.

[0108] Fig.96 The third wiring layer is shown together with Fig.95 Schematic diagram of an example of a planar configuration of a second wiring layer shown.

[0109] Fig.97 The fourth wiring layer is shown together with Fig.96 Schematic diagram of an example of a planar configuration of a third wiring layer shown.

[0110] Fig.98 It is shown Fig.69 Schematic cross-sectional views of other examples of imaging devices are shown.

[0111] Fig.99 It is used to illustrate Fig.98 A schematic diagram of the path of the input signal of the imaging device is shown.

[0112] Fig.100 It is used to illustrate Fig.98 Schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0113] Fig.101 It is shown Fig.72 Schematic cross-sectional views of other examples of imaging devices are shown.

[0114] Fig.102 It is shown Fig.70 Figures showing other examples of equivalent circuits.

[0115] Fig.103 It is shown Fig.73A Schematic plan views of other examples of pixel separation portions in the embodiments of the present invention. DETAILED DESCRIPTION

[0116] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. Note that in the following embodiments, the same parts are denoted by the same reference numerals, and repeated descriptions will be omitted.

[0117] [Schematic Configuration Example of Solid-State Image Sensor]

[0118] Will refer to Figures 1 to 19 A schematic configuration example of a solid-state image sensor will be described.

[0119] (Circuit Configuration Example of Solid-State Image Sensor)

[0120] Figure 1 1 is a diagram showing an example of a schematic configuration of a solid-state image sensor 1 applicable to each embodiment of the present disclosure. The solid-state image sensor 1 converts received light into an electrical signal and outputs it as a pixel signal. In this example, the solid-state image sensor 1 is formed as a complementary metal oxide semiconductor (CMOS) image sensor.

[0121] like Figure 1 As shown, the solid-state image sensor 1 includes three substrates, namely, a first substrate 10, a second substrate 20, and a third substrate 30. The solid-state image sensor 1 is an imaging device of a three-dimensional structure formed by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0122] The first substrate 10 has a plurality of sensor pixels 12 that perform photoelectric conversion on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix in a pixel region 13 of the first substrate 10. The second substrate 20 has a readout circuit 22 for every four sensor pixels 12 on a semiconductor substrate 21 to output a pixel signal based on the charge output from the sensor pixel 12. The second substrate 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has a logic circuit 32 for processing pixel signals on a semiconductor substrate 31. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32, more specifically, the horizontal drive circuit 35 outputs the output voltage Vout of each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low resistance region containing silicide such as CoSi2 or NiSi formed using a silicide process can be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0123] The vertical drive circuit 33 sequentially selects, for example, a plurality of sensor pixels 12 in units of rows. The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on the pixel signal output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts the signal level of the pixel signal by performing, for example, CDS processing, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35 sequentially outputs, for example, the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36 ​​controls, for example, driving of each block of the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35 in the logic circuit 32.

[0124] Figures 2 to 5 is a diagram showing an example of a sensor pixel 12 and a readout circuit 22. The following will describe a case where four sensor pixels 12 share one readout circuit 22. Here, "sharing" means that the outputs of four sensor pixels 12 are input to the shared readout circuit 22. However, as a unit of sharing, the number of pixels is irrelevant. For example, as in the first and second embodiments described later, the output of one sensor pixel 12 can be input to one readout circuit 22. In addition, similar to this example, as in the third embodiment, the outputs of four sensor pixels 12 can be input to one readout circuit 22.

[0125] like Figure 2 As shown, each sensor pixel 12 has components that are common to each other. Figure 2 , identification numbers 1, 2, 3, and 4 are added to the end of the reference numerals of the constituent elements of each sensor pixel 12 to distinguish the constituent elements of each sensor pixel 12 from each other. Hereinafter, in the case where it is necessary to distinguish the constituent elements of each sensor pixel 12 from each other, the identification numbers are added to the end of the reference numerals of the constituent elements of each sensor pixel 12. In the case where it is not necessary to distinguish the constituent elements of each sensor pixel 12 from each other, the identification numbers at the end of the reference numerals of the constituent elements of each sensor pixel 12 are omitted.

[0126] Each sensor pixel 12 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of the "photoelectric conversion element" of the present disclosure. The photodiode PD performs photoelectric conversion to generate a charge corresponding to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line such as a ground line (GND). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23 (refer to Figure 1 ). The transfer transistor TR is, for example, a CMOS transistor.

[0127] The floating diffusions FD of the sensor pixels 12 that share one readout circuit 22 are electrically connected to each other and to the input terminal of the common readout circuit 22. The readout circuit 22 has, for example, a reset transistor RST, a selection transistor SEL, and an amplifier transistor AMP. Note that the selection transistor SEL may be omitted if necessary. The source of the reset transistor RST, which is the input terminal of the readout circuit 22, is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplifier transistor AMP. The gate of the reset transistor RST is electrically connected to the pixel drive line 23 (refer to Figure 1 ). The source of the amplifier transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL as the output terminal of the readout circuit 22 is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (refer to Figure 1 ).

[0128] When the transfer transistor TR is turned on, the charge of the photodiode PD is transferred to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplifier transistor AMP generates a signal having a voltage corresponding to the level of the charge retained in the floating diffusion FD as a pixel signal. The amplifier transistor AMP forms a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated by the photodiode PD. When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are, for example, CMOS transistors.

[0129] Note that Figure 3 As shown, the selection transistor SEL can be arranged between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (refer to Figure 1). The source of the amplifier transistor AMP as the output terminal of the readout circuit 22 is electrically connected to the vertical signal line 24, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST.

[0130] In addition, if Figure 4 and Figure 5 As shown, an FD transfer transistor FDG can be set between the source of the reset transistor RST and the gate of the amplifier transistor AMP. The FD transfer transistor FDG is used to switch the conversion efficiency. Generally, when an image is taken in a dark place, the pixel signal is small. If the FD capacitance C of the floating diffusion FD is large when the charge-voltage conversion is performed based on Q=CV, the voltage V when converted by the amplifier transistor AMP becomes smaller. On the other hand, in a bright place, the pixel signal becomes larger, so unless the FD capacitance C is large, the floating diffusion FD cannot receive the charge of the photodiode PD. In addition, the FD capacitance C needs to be large so that the voltage V when converted by the amplifier transistor AMP does not become too large. Based on these factors, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, so the entire FD capacitance C increases. On the other hand, when the FD transfer transistor FDG is turned off, the entire FD capacitance C decreases. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

[0131] Figure 6 2 is a diagram showing an example of a connection pattern of a plurality of readout circuits 22 and a plurality of vertical signal lines 24. When a plurality of readout circuits 22 are arranged side by side in a column direction which is an extending direction of the vertical signal lines 24, one of the plurality of vertical signal lines 24 may be allocated to each readout circuit 22. Figure 6 As shown in FIG. 1 , when four readout circuits 22 are arranged side by side in the extending direction of the vertical signal lines 24, one of the four vertical signal lines 24 can be allocated to each readout circuit 22. Figure 6 In order to distinguish each vertical signal line 24 , identification numbers 1, 2, 3, 4 are added to the end of the reference numerals of each vertical signal line 24 .

[0132] (Example of Physical Configuration of Solid-State Image Sensor)

[0133] Figure 7 and Figure 8 1 is a diagram showing an example of a cross-sectional configuration of the solid-state image sensor 1 in the horizontal direction. Figure 7 and Figure 8 The figure on the upper side is showing Figure 1 FIG. 2 is a diagram showing an example of a cross-sectional structure of the first substrate 10 in the horizontal direction. Figure 7 and Figure 8The figure on the lower side is shown Figure 1 FIG. 2 is a diagram showing an example of a cross-sectional structure of the second substrate 20 in the horizontal direction. Figure 7 A configuration is illustrated in which two groups of 2×2 of four sensor pixels 12 are arranged in the second direction H, and Figure 8 The configuration is illustrated in which four sets of 2×2 of four sensor pixels 12 are arranged in the first direction V and the second direction H. Note that Figure 7 and Figure 8 In the cross-sectional view on the upper side of the semiconductor substrate 11, a diagram showing an example of the surface structure of the semiconductor substrate 11 is superimposed on the diagram showing Figure 1 The first substrate 10 is formed in a horizontal cross-section. Figure 7 and Figure 8 In the cross-sectional view on the lower side of the semiconductor substrate 21, a diagram showing an example of the surface structure of the semiconductor substrate 21 is superimposed on the diagram showing Figure 1 FIG. 1 is an example of a cross-sectional structure of the second substrate 20 in the horizontal direction.

[0134] like Figure 7 and Figure 8 As shown, a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are formed within the surface of the first substrate 10. Figure 7 The first direction V of the up and down direction or as Figure 8 The second direction H of the left and right direction is arranged in a strip-like manner. Note that Figure 7 and Figure 8 The case where a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are arranged side by side in two columns in the first direction V or the second direction H is illustrated. The first direction V or the second direction H is parallel to one arrangement direction (for example, the column direction) of the row direction and the column direction of the two arrangement directions of the plurality of sensor pixels 12 arranged in a matrix. In the four sensor pixels 12 of the shared readout circuit 22, for example, the four floating diffusions FD are arranged close to each other via the pixel isolation portion 43. In the four sensor pixels 12 of the shared readout circuit 22, the gate electrodes TG of the four transfer transistors TR are arranged to surround the four floating diffusions FD, and the four gate electrodes TG form a ring, for example.

[0135] The insulating layer 53 existing in the portion of the semiconductor substrate 21 penetrated by the plurality of through wirings 54 includes a plurality of blocks extending in the first direction V or the second direction H. The semiconductor substrate 21 includes a plurality of island-shaped blocks 21A extending in the first direction V or the second direction H and arranged side by side in the first direction V or the second direction H orthogonal to each other via the insulating layer 53. Each block 21A is provided with a plurality of groups of, for example, a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 includes, for example, a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL located in a region facing the four sensor pixels 12. One readout circuit 22 shared by four sensor pixels 12 includes, for example, an amplifier transistor AMP in a block 21A adjacent to the left of the insulating layer 53 and a reset transistor RST and a selection transistor SEL in a block 21A adjacent to the right of the insulating layer 53.

[0136] Figures 9 to 12 is a diagram showing an example of a wiring layout of the solid-state image sensor 1 in a horizontal plane. Figures 9 to 12 The case where one readout circuit 22 shared by four sensor pixels 12 is provided in a region facing the four sensor pixels 12 is illustrated. For example, Figures 9 to 12 The wiring described in the above-mentioned pixel transistor is arranged in different layers of the wiring layer not shown. The wiring layer has, for example, a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24, a pad electrode (not shown) exposed on the surface of the wiring layer and used for electrical connection between the second substrate 20 and the third substrate 30, etc.

[0137] For example, Fig. 9 As shown, four mutually adjacent through wirings 54 are electrically connected to the connection wiring 55. The four mutually adjacent through wirings 54 are further electrically connected to the gate of the amplifier transistor AMP included in the block 21A adjacent to the left of the insulating layer 53 and the gate of the reset transistor RST included in the block 21A adjacent to the right of the insulating layer 53 via the connection wiring 55 and the connection portion 59.

[0138] like Fig.10As shown, for example, the power supply line VDD is arranged at a position facing each readout circuit 22 arranged side by side in the second direction H. For example, the power supply line VDD is electrically connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST of each readout circuit 22 arranged side by side in the second direction H via the connection portion 59. For example, two pixel drive lines 23 are arranged at a position facing each readout circuit 22 arranged side by side in the second direction H. For example, one pixel drive line 23 is a wiring RSTG electrically connected to the gate of the reset transistor RST of each readout circuit 22 arranged side by side in the second direction H. For example, the other pixel drive line 23 is a wiring SELG electrically connected to the gate of the selection transistor SEL of each readout circuit 22 arranged side by side in the second direction H. For example, in each readout circuit 22, the source of the amplifier transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via the wiring 25.

[0139] For example, Fig.11 As shown, two power supply lines VSS are arranged at positions facing each readout circuit 22 arranged side by side in the second direction H. For example, each power supply line VSS is electrically connected to a plurality of through wirings 47 at a position facing each sensor pixel 12 arranged side by side in the second direction H. For example, four pixel drive lines 23 are arranged at positions facing each readout circuit 22 arranged side by side in the second direction H. For example, each of the four pixel drive lines 23 is, for example, a wiring TRG electrically connected to a through wiring 48 of one sensor pixel 12 among four sensor pixels 12 corresponding to each readout circuit 22 arranged side by side in the second direction H. That is, the four pixel drive lines 23 used as control lines are electrically connected to the gate electrode TG of the transfer transistor TR of each sensor pixel 12 arranged side by side in the second direction H. Fig.11 In the example, identification numbers 1, 2, 3, and 4 are added to the end of each wiring TRG to distinguish each wiring TRG.

[0140] For example, Fig.12 As shown, the vertical signal line 24 is arranged at a position facing each readout circuit 22 arranged side by side in the first direction V. For example, the vertical signal line 24 used as an output line is electrically connected to the source of the amplifier transistor AMP as the output terminal of each readout circuit 22 arranged side by side in the first direction V.

[0141] (Variant 1)

[0142] Fig.13 and Fig.14 1 is a diagram showing a modified example of the cross-sectional structure of the solid-state image sensor 1 in the horizontal direction. Fig.13 and Fig.14 The figure on the upper side shows Figure 1 A modified example of a cross section of the first substrate 10 in the horizontal direction, Fig.13 The figure below shows Figure 1 The second substrate 20 is a modified example of a cross-section in the horizontal direction. Fig.13 and Fig.14 In the cross-sectional view on the upper side, it is shown Figure 1 The figure showing a modified example of the surface configuration of the semiconductor substrate 11 is superimposed on the Figure 1 In the figure of the modified example of the cross section of the first substrate 10 in the horizontal direction. Fig.13 and Fig.14 In the cross-sectional view on the lower side of the semiconductor substrate 21, a diagram showing a modified example of the surface structure of the semiconductor substrate 21 is superimposed on the diagram showing Figure 1 FIG. 2 is a diagram showing a modified example of a cross-section of the second substrate 20 in the horizontal direction.

[0143] like Fig.13 and Fig.14 As shown, a plurality of through wirings 54, a plurality of through wirings 48, and a plurality of through wirings 47 are formed within the surface of the first substrate 10. Fig.13 and Fig.14 The second direction H of the left and right direction is arranged in a strip-like manner. Note that Fig.13 and Fig.14 The case where the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged side by side in two columns in the second direction H is illustrated. In the four sensor pixels 12 of the shared readout circuit 22, for example, four floating diffusions FD are arranged close to each other via the pixel isolation portion 43. In the four sensor pixels 12 of the shared readout circuit 22, four transfer gates TG1, TG2, TG3, and TG4 are arranged to surround the four floating diffusions FD, and the four transfer gates TG form a ring, for example.

[0144] The insulating layer 53 includes a plurality of blocks extending in the first direction V. The semiconductor substrate 21 includes a plurality of island-shaped blocks 21A extending in the second direction H and arranged side by side in the first direction V orthogonal to the second direction H via the insulating layer 53. Each block 21A is provided with, for example, a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. For example, one readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite to the four sensor pixels 12, but is arranged offset in the first direction V.

[0145] exist Fig.13, one readout circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL in an area in the second substrate 20 that is offset in the first direction V from an area facing the four sensor pixels 12. One readout circuit 22 shared by four sensor pixels 12 includes, for example, the amplifier transistor AMP, the reset transistor RST, and the selection transistor SEL within one block 21A.

[0146] exist Fig.14 , one readout circuit 22 shared by four sensor pixels 12 includes a reset transistor RST, an amplifier transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG in an area in the second substrate 20 that is offset in the first direction V from an area facing the four sensor pixels 12. One readout circuit 22 shared by four sensor pixels 12 includes, for example, the amplifier transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD transfer transistor FDG within one block 21A.

[0147] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite to the four sensor pixels 12, but is, for example, offset from a position directly opposite to the four sensor pixels 12 in the first direction V. In this case, the wiring 25 (see Fig.10 ), or the wiring 25 can be omitted and the source of the amplifier transistor AMP and the drain of the selection transistor SEL can be formed in a common impurity region. As a result, the size of the readout circuit 22 can be reduced, and the size of other parts within the readout circuit 22 can be increased.

[0148] (Variant 2)

[0149] Fig.15 1 is a diagram showing a modified example of the cross-sectional structure of the solid-state image sensor 1 in the horizontal direction. Fig.15 Shows Figure 7 A modified example of the cross-sectional structure.

[0150] In this modification, the semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H via the insulating layer 53. Each block 21A includes, for example, a set of a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and a reduction in the resolution of a reproduced image and degradation of image quality due to color mixing can be suppressed.

[0151] (Variant 3)

[0152] Fig.161 is a diagram showing a modified example of the cross-sectional structure of the solid-state image sensor 1 in the horizontal direction. Fig.16 Shows Fig.15 A modified example of the cross-sectional structure.

[0153] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not arranged directly opposite to the four sensor pixels 12, but is offset in the first direction V. In this modification, similar to Modification 2, the semiconductor substrate 21 includes a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H via an insulating layer 53. Each block 21A is provided with a set of, for example, a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. In this modification, a plurality of through wirings 47 and a plurality of through wirings 54 are also arranged in the second direction H. Specifically, a plurality of through wirings 47 are arranged between four through wirings 54 that share a certain readout circuit 22 and four through wirings 54 that share other readout circuits 22 adjacent to this readout circuit 22 in the second direction H. In this case, crosstalk between the readout circuits 22 adjacent to each other can be suppressed by the insulating layer 53, and a reduction in the resolution of the reproduced image and degradation of the image quality caused by color mixing can be suppressed.

[0154] (Variant 4)

[0155] Fig.17 1 is a diagram showing an example of a cross-sectional configuration of the solid-state image sensor 1 in the horizontal direction. Fig.17 Shows Figure 7 A modified example of the cross-sectional structure.

[0156] In the present modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion FD is shared by every four sensor pixels 12. Therefore, in the present modification, one through wiring 54 is provided for every four sensor pixels 12.

[0157] Among the plurality of sensor pixels 12 arranged in a matrix, four sensor pixels 12 corresponding to an area obtained by shifting a unit area corresponding to four sensor pixels 12 sharing one floating diffusion portion FD by one sensor pixel 12 in the first direction V are conveniently referred to as four sensor pixels 12A. At this time, in the present modification, the first substrate 10 includes a through wiring 47 shared by every four sensor pixels 12A. Therefore, in the present modification, one through wiring 47 is provided for every four sensor pixels 12A.

[0158] In the present modification, the first substrate 10 has an element isolation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the element isolation portion 43 does not completely surround the sensor pixel 12, and has a gap as a non-formed area near the through wiring 54 connected to the floating diffusion portion FD and near the through wiring 47. Thus, the gap allows one through wiring 54 to be shared by four sensor pixels 12 and one through wiring 47 to be shared by four sensor pixels 12A. In the present modification, the second substrate 20 includes a readout circuit 22 for each four sensor pixels 12 that share the floating diffusion portion FD.

[0159] Fig.18 1 is a diagram showing an example of a cross-sectional configuration in the horizontal direction of the solid-state image sensor 1 according to the present modification. Fig.18 Shows Fig.15 In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion portion FD is shared by every four sensor pixels 12. In addition, the first substrate 10 has an element isolation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0160] Fig.19 1 is a diagram showing an example of a cross-sectional configuration in the horizontal direction of the solid-state image sensor 1 according to the present modification. Fig.19 Shows Fig.16 In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and the floating diffusion portion FD is shared by every four sensor pixels 12. In addition, the first substrate 10 has an element isolation portion 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0161] (Variant 5)

[0162] Fig. 20 1 is a diagram showing an example of a circuit configuration of a solid-state image sensor 1 according to a modification. The solid-state image sensor 1 according to the present modification is a CMOS image sensor equipped with a column-parallel ADC.

[0163] like Fig. 20 As shown, in addition to a pixel area 13 formed by two-dimensionally arranging a plurality of sensor pixels 12 including photoelectric conversion elements in a matrix shape, the solid-state image sensor 1 according to the present variation includes a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37 and a system control circuit 36.

[0164] In this system configuration, the system control circuit 36 ​​generates clock signals, control signals, etc. based on the main clock MCK as a reference for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., and supplies the generated signals to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0165] In addition, the vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel area 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0166] Although not shown here, as the sensor pixel 12, for example, a configuration including a transfer transistor TR in addition to the photodiode PD, which transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD can be used. In addition, although not shown here, as the readout circuit 22, for example, a readout circuit including three transistors including a reset transistor RST for controlling the potential of the floating diffusion FD, an amplifier transistor AMP for outputting a signal corresponding to the potential of the floating diffusion FD, and a selection transistor SEL for pixel selection can be used.

[0167] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and each pixel drive line 23 is wired for each row of the pixel configuration of m rows and n columns, and each vertical signal line 24 is wired for each column. Each end of the plurality of pixel drive lines 23 is connected to each output end corresponding to each row of the vertical drive circuit 33. The vertical drive circuit 33 includes a shift register and the like, and performs control of row addressing and row scanning of the pixel region 13 via the plurality of pixel drive lines 23.

[0168] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m, each of which is provided for each pixel column of the pixel area 13, that is, for each vertical signal line 24, and converts the analog signal output from each column of each sensor pixel 12 in the pixel area 13 into a digital signal, and outputs the digital signal.

[0169] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A whose level changes in a slope shape over time as a means for generating a so-called ramp waveform reference voltage Vref. It should be noted that the means for generating a ramp waveform reference voltage Vref is not limited to the DAC 38A.

[0170] The DAC 38A generates a ramp waveform reference voltage Vref based on a clock CK supplied from the system control circuit 36 ​​under the control of a control signal CS1 supplied from the system control circuit 36 ​​, and supplies the reference voltage Vref to the ADCs 34 - 1 to 34 - m of the column processing section.

[0171] Note that each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to respective operation modes, including a normal frame rate mode in which information of all sensor pixels 12 is read out in a row-by-row scanning manner, and a high frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N of that in the normal frame rate mode to increase the frame rate by N times (e.g., increase the frame rate by two times). Such switching of the operation modes is performed by control of control signals CS2 and CS3 supplied from the system control circuit 36. In addition, instruction information for switching between the respective operation modes, i.e., the normal frame rate mode and the high-speed frame rate mode, is supplied from an external system controller (not shown) relative to the system control circuit 36.

[0172] ADC 34-1 to 34-m all have the same configuration, and ADC 34-m is used as an example for description. ADC 34-m includes a comparator 34A, an up / down counter (U / DCNT) 34B serving as a counting means, for example, a transmission switch 34C, and a storage device 34D.

[0173] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 of the n-th column of the pixel area 13 with the reference voltage Vref of the ramp waveform supplied from the reference voltage supply unit 38. For example, when the reference voltage Vref is larger than the signal voltage Vx, the output Vco is changed to an "H" level, and when the reference voltage Vref is equal to or smaller than the signal voltage Vx, the output Vco is changed to an "L" level.

[0174] The up-down counter 34B is an asynchronous counter and, under the control of the control signal CS2 supplied from the system control circuit 36, measures the comparison period from the start to the end of the comparison operation in the comparator 34A by receiving the clock CK from the system control circuit 36 ​​simultaneously with the DAC 38A and performing down-counting or up-counting in synchronization with the clock CK.

[0175] Specifically, in the normal frame rate mode, in the operation of reading out a signal from one sensor pixel 12, the comparison time at the first readout is measured by counting down at the first readout operation, and the comparison time at the second readout is measured by counting up at the second readout operation.

[0176] On the other hand, in the high frame rate mode, the counting result of the sensor pixels 12 in a certain row is kept as it is, and then, for the sensor pixels 12 in the next row, the comparison time at the first readout operation is measured by continuously counting down at the first readout operation from the previous counting result, and the comparison time at the second readout operation is measured by counting up at the second readout operation.

[0177] In the normal frame rate mode, under the control of the control signal CS3 supplied from the system control circuit 36, when the counting operation performed by the up-down counter 34B for a certain row of sensor pixels 12 is completed, the transfer switch 34C is turned on (closed) and the counting result of the up-down counter 34B is transferred to the storage device 34D.

[0178] On the other hand, at a high frame rate N=2, when the counting operation performed by the up-down counter 34B for the sensor pixels 12 in a certain row is completed, the transfer switch 34C remains disconnected (open), and then, when the counting operation performed by the up-down counter 34B for the sensor pixels 12 in the next row is completed, the transfer switch 34C is turned on and the counting results of the two vertical pixels of the up-down counter 34B are transferred to the storage device 34D.

[0179] Therefore, by respective operations of the comparators 34A and the up-down counters 34B in the ADCs 34-1 to 34-m, analog signals supplied column by column from the sensor pixels 12 in the pixel area 13 via the vertical signal lines 24 are converted into N-bit digital signals, and the digital signals are stored in the storage device 34D.

[0180] The horizontal drive circuit 35 includes a shift register and the like, and performs control of column addressing and column scanning on the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of the horizontal drive circuit 35, N-bit digital signals obtained by A / D conversion in the respective ADCs 34-1 to 34-m are sequentially read out to the horizontal output line 37, and are output as imaging data via the horizontal output line 37.

[0181] Note that in addition to the above-described constituent elements, circuits and the like that perform various signal processing on imaging data output via the horizontal output line 37 may be provided; however, these circuits and the like are not shown because they are not directly related to the present disclosure.

[0182] In the solid-state image sensor 1 including the column-parallel ADC having the above-described configuration according to the present variant, the counting result of the up-down counter 34B can be selectively transmitted to the storage device 34D via the transmission switch 34C, which makes it possible to independently control the counting operation of the up-down counter 34B and the operation of reading out the counting result of the up-down counter 34B to the horizontal output line 37.

[0183] Fig.21 The structure is shown in which a substrate is formed by stacking three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). Fig. 20 An example of a solid-state image sensor 1.

[0184] In the present modification, a pixel region 13 including a plurality of sensor pixels 12 is formed in the center of the first substrate 10 , and a vertical drive circuit 33 is formed around the pixel region 13 .

[0185] Furthermore, in the second substrate 20 , a readout circuit region 15 including a plurality of readout circuits 22 is formed in the central portion, and a vertical drive circuit 33 is formed around the readout circuit region 15 .

[0186] Furthermore, in the third substrate 30 , a column signal processing circuit 34 , a horizontal driving circuit 35 , a system control circuit 36 ​​, a horizontal output line 37 , and a reference voltage supply unit 38 are formed.

[0187] Using the above composition, as in Figure 1 As in the configuration and its modified examples, the damage of the increase in chip size and the reduction in area per pixel due to the structure in which the substrates are electrically connected to each other does not occur. As a result, it is possible to provide a solid-state image sensor 1 having a three-layer structure, which has substantially the same chip size as before, without damaging the reduction in area per pixel. Note that the vertical drive circuit 33 may be formed only on the first substrate 10, or may be formed only on the second substrate 20.

[0188] Fig. 22 A modified example of the cross-sectional structure of the solid-state image sensor 1 according to this modified example is shown. Figure 1 In the configuration and its modified example, the solid-state image sensor 1 is formed by stacking three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). Figure 1 In the configuration and its modified example, the solid-state image sensor 1 can be configured by laminating two substrates (the first substrate 10 and the second substrate 20).

[0189] At this time, for example, Fig. 22As shown, a logic circuit 32 is formed by dividing between a first substrate 10 and a second substrate 20. Here, a circuit 32A disposed on the first substrate 10 side in the logic circuit 32 includes a transistor having a gate structure in which a high dielectric constant film formed of a material resistant to high temperature processes (e.g., high-k) and a metal gate electrode are stacked. On the other hand, in a circuit 32B disposed on the second substrate 20 side, a low resistance region containing silicides such as CoSi2 and NiSi formed using a self-aligned silicide (SALICIDE) process is formed on the surface of an impurity diffusion region in contact with a source electrode and a drain electrode. The low resistance region containing silicide contains a compound of a material of the semiconductor substrate and a metal.

[0190] Therefore, when forming the sensor pixel 12, a high temperature process such as thermal oxidation can be used. In addition, in the circuit 32B provided on the second substrate 20 side in the logic circuit 32, in the case where the low resistance region 26 containing silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be improved.

[0191] Fig.23 It shows that according to the above Figure 1 A modified example of the cross-sectional structure of the solid-state image sensor 1 and its modified example. Figure 1 In the logic circuit 32 of the third substrate 30 of the configuration and its modified example, the low resistance region 26 including silicide such as CoSi2 and NiSi formed using the SALICIDE process can be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. Therefore, when forming the sensor pixel 12, a high temperature process such as thermal oxidation can be used. In addition, in the logic circuit 32, in the case where the low resistance region 26 including silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be improved.

[0192] [First embodiment]

[0193] Will refer to Figures 24 to 34 A solid-state image sensor according to a first embodiment is described.

[0194] (Overall Configuration Example of Solid-State Image Sensor)

[0195] Fig.24 1 is a diagram showing a part of a cross section of a solid-state image sensor 100' according to a first embodiment of the present disclosure. Fig.24 As shown, the solid-state image sensor 100 ′ includes a structure in which a substrate 200 , a substrate 300 , and a substrate 400 are attached together. Fig.24The surface 501 shown represents the surface where the substrate 200 and the substrate 300 are bonded together. Fig.24 The surface 502 shown represents the surface where the substrate 300 and the substrate 400 are attached together. These substrates 200 to 400 are electrically connected to each other.

[0196] The substrate 200, which is a semiconductor substrate such as a silicon substrate, includes a plurality of photoelectric conversion elements 102. The photoelectric conversion element 102 converts received light into an electrical signal corresponding to the amount of received light by photoelectric conversion. One photoelectric conversion element 102 corresponds to one pixel. The photoelectric conversion element 102 includes, for example, a PN junction photodiode. One photoelectric conversion element 102 may include a plurality of photodiodes. Fig.24 In the example of FIG. 1 , the photoelectric conversion element 102 includes an N-type semiconductor region 201 of a substrate 200 and a P-type semiconductor region 202 formed to cover the side thereof. Each photoelectric conversion element 102 is electrically separated by a pixel separation unit 203 that separates pixels. The pixel separation unit 203 includes a metal, an insulating film (e.g., SiO2), a combination thereof, or the like.

[0197] The lower end of the photoelectric conversion element 102, that is, the lower side of the substrate 200 is covered by an insulating film 211. The insulating film 211 is formed of, for example, a film having a fixed charge. A planarization film 213 as an insulating film or the like may be further configured at the lower end of the insulating film 211. The insulating film 211 is, for example, a metal oxide film of hafnium oxide, tantalum oxide, aluminum oxide, or the like. The planarization film 213 is, for example, an insulating film of silicon oxide, silicon nitride, or the like. The insulating film 211 and the planarization film 213 may be provided as a multilayer, respectively.

[0198] The color filter 212 is arranged below the insulating film 211 . The on-chip lens 214 is arranged below the color filter 212 . The on-chip lens 214 collects the irradiated light. The collected light is guided to the photoelectric conversion element 102 via the color filter 212 .

[0199] A P-type semiconductor region 204 (P-well) is formed on the photoelectric conversion element 102. Fig.24 In the example of , the P-type semiconductor region 202 constituting the photoelectric conversion element 102 protrudes in a manner covering a portion of the side surface of the semiconductor region 204. However, the P-type semiconductor region 202 may have any depth. For example, the upper surface of the semiconductor region 202 and the lower surface of the semiconductor region 204 may be at the same height.

[0200] The N-type transfer transistor 103 is arranged above the photoelectric conversion element 102. Specifically, an N-type drain region 221 and an N-type source region 222 are formed near the surface of the semiconductor region 204. A gate electrode 223 is formed between the N-type drain region 221 and the N-type source region 222 on the semiconductor region 204. The drain region 221, the source region 222, and the gate electrode 223 form the transfer transistor 103.

[0201] exist Fig.24 In the example of , the gate electrode 223 is connected to the N-type semiconductor region 201 forming the photoelectric conversion element 102. As described above, one transfer transistor 103 is provided for one photoelectric conversion element 102. The transfer transistor 103 transfers an electrical signal output from the photoelectric conversion element 102 to the pixel transistor.

[0202] The source region 222 of the transfer transistor 103 functions as a floating diffusion (FD). The floating diffusion temporarily holds an electrical signal output from the photoelectric conversion element 102. The transfer transistor 103 including the source region 222 as the floating diffusion is covered with an insulating film 240. The substrate 300 is disposed on the insulating film 240.

[0203] The substrate 300, which is a semiconductor substrate such as a P-type silicon substrate, includes a pixel transistor having a plurality of N-type amplifier transistors 104. One pixel transistor such as the amplifier transistor 104 is provided for one transfer transistor 103. The pixel transistor performs a process of reading out an electrical signal corresponding to the amount of light received by the photoelectric conversion element 102. For example, the amplifier transistor 104 amplifies and outputs an electrical signal transmitted from the photoelectric conversion element 102 by the transfer transistor 103.

[0204] The wiring D1 is connected to the gate electrode 313 of the amplifying transistor 104. The wiring D1 is connected to the source region 222 of the transfer transistor 103 as a floating diffusion via a contact Cfd.

[0205] exist Fig.24 In the example of , wirings D1 to D4 are formed across four layers in the substrate 300. Wiring D1 is a wiring formed in the lowermost layer which is the first layer. Wiring D4 is a wiring formed in the uppermost layer which is the fourth layer. Note that the number of wiring layers is not limited to four and can be changed to any number according to design conditions, etc. The amplifier transistor 104 and wirings D1 to D4 are covered by the insulating film 340.

[0206] The substrate 400, which is a semiconductor substrate such as a silicon substrate, is turned upside down and bonded to the wiring D4 of the substrate 300. Fig.24In the example of , the junction 503 between the wiring D4 and the wiring of the substrate 400 overlaps with the pixel region configuring the pixel. A plurality of logic transistors Tr are connected to the wiring of the substrate 400. The wiring of the substrate 400 and the logic transistor Tr are covered by the insulating film 440. A logic circuit as a signal processing circuit is formed by the wiring of the substrate 400 and the logic transistor Tr. The logic circuit corresponds to a peripheral circuit of the solid-state image sensor 100', which processes an electrical signal generated by the photoelectric conversion element 102, etc.

[0207] (Detailed Configuration Example of Solid-State Image Sensor)

[0208] Next, we will refer to Fig.25 A detailed configuration example of the solid-state image sensor 100 ′ according to the first embodiment will be described. Fig.25 1 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300 of the solid-state image sensor 100 ′ according to the first embodiment of the present disclosure. Fig.25 (a) is a cross-sectional view showing the vicinity of the bonding position of the substrates 200 and 300, Fig.25 (b) is a top view of the substrate 300. However, in Fig.25 In (a), the position of the contact portion Cg is offset. Fig.25 In (b), the insulating film 340 and the wiring D1 are omitted. Fig.25 , the amplifier transistor 104 is shown as an example of a pixel transistor.

[0209] like Fig.25 As shown, the solid-state image sensor 100' includes a substrate 200 as a first semiconductor substrate having a photoelectric conversion element 102 and a substrate 300 as a second semiconductor substrate facing the substrate 200 via an insulating film 240. The substrate 200 is grounded. That is, the potential of the substrate 200 is fixed to 0V. The substrate 200 includes a transfer transistor 103 having a gate electrode 223 and an N-type source region 222 as a floating diffusion portion. The transfer transistor 103 is formed as, for example, a metal oxide semiconductor (MOS) type field effect transistor (MOSFET).

[0210] The substrate 300 has an amplifier transistor 104 that amplifies an electrical signal output from the photoelectric conversion element 102 on the main surface MSa as the first main surface. The amplifier transistor 104 is formed as, for example, a MOSFET. The amplifier transistor 104 has an N-type source region 312 and an N-type drain region 311 provided in the substrate 300. The gate electrode 313 of the amplifier transistor 104 is arranged on the substrate 300 between the source region 312 and the drain region 311. The source region 312 is provided with a contact portion Cs connected to an upper layer wiring not shown. The drain region 311 is provided with a contact portion Cd connected to a wiring D1a of Cu or the like. The gate electrode 313 is provided with a contact portion Cg connected to a wiring D1 of Cu or the like. The contact portion Cfd is connected to the wiring D1. The other end of the contact portion Cfd is connected to the source region 222 of the transfer transistor 103.

[0211] The substrate 300 has a substrate contact layer 302 as a region having a lower resistance than the substrate 300 on the main surface MSb which is the second main surface opposite to the main surface MSa. Specifically, the substrate 300 has a certain conductivity type, for example, P type, and the substrate contact layer 302 contains impurities at a higher concentration than other regions 301 of the substrate 300. The N-type source region 312 and the N-type drain region 311 of the amplifier transistor 104 provided on the main surface MSa and the P+ type substrate contact layer 302 provided on the main surface MSb are separated by other regions 301 of the substrate 300. Here, the substrate contact layer 302 does not necessarily have to have a lower resistance as a whole, and does not necessarily have to contain a high concentration of impurities. It is only required that at least a part of the region of the substrate contact layer 302 has a lower resistance and a higher concentration of impurities than other regions 301 of the substrate 300. Therefore, the impurity concentration in the substrate contact layer 302 does not necessarily have to be uniform over the entire substrate contact layer 302.

[0212] The substrate 300 is grounded via the substrate contact layer 302. Specifically, the solid-state image sensor 100' includes a contact portion Csub extending from the substrate contact layer 302 of the substrate 300 toward the substrate 200 side. More specifically, the substrate 300 is arranged on the substrate 200 in such a manner that the main surface MSb side faces the substrate 200, and the solid-state image sensor 100' includes a contact portion Csub connecting the substrate contact layer 302 of the substrate 300 to the substrate 200. Therefore, the substrate 300 is grounded via the substrate contact layer 302 and the substrate 200. That is, the potential of the substrate 300 is fixed to 0V.

[0213] (Example of Manufacturing Process of Solid-State Image Sensor)

[0214] Next, we will refer to Figures 26-28 An example of a manufacturing process of the solid-state image sensor 100 ′ of the first embodiment is described. Figures 26-281 is a flowchart showing an example of a procedure of a manufacturing process of the solid-state image sensor 100 ′ according to the first embodiment of the present disclosure. Note that Figures 26-28 The left figure is a cross-sectional view of the solid-state image sensor 100' during the manufacturing process. Fig.26 Other than (a2) Figures 26-28 The right figure of FIG. 1 is a top view of the solid-state image sensor 100 ′ during the manufacturing process.

[0215] like Fig.26 As shown in (a1), the photoelectric conversion element 102 including the N-type semiconductor region 201, the P-type semiconductor region 204, the gate electrode 223 of the transfer transistor 103, and the source region 222 as the floating diffusion portion are formed on the substrate 200. The gate electrode 223 and the source region 222 are covered by an insulating film 240. The insulating film 240 is penetrated to form a through hole reaching the substrate 200, and a conductive material such as W is buried in the through hole to form a contact portion Csub.

[0216] like Fig.26 As shown in (a2), the substrate contact layer 302 is formed on the main surface MSb of the substrate 300 which is a P-type silicon substrate or the like. The substrate contact layer 302 can be formed by, for example, ion implantation, solid phase diffusion, plasma doping, or the like.

[0217] In the case of using the ion implantation method, for example, about 1×10 16 / cm 3 ~1×10 20 / cm 3 Boron is implanted into the main surface MSb of the substrate 300 at a dose of , and heat-treated at a temperature of about 600° C. to 900° C., thereby forming the substrate contact layer 302 .

[0218] In the case of using the solid phase diffusion method, for example, a silicon oxide film such as a borosilicate glass (BSG) film is deposited on the main surface MSb of the substrate 300 by a low pressure chemical vapor deposition (LP-CVD) method using B2H6 / SiH4 / O2 gas. Then, heat treatment is performed at about 900° C. to diffuse boron on the side of the substrate 300. Thereafter, the BSG film is removed with hydrofluoric acid, thereby forming the substrate contact layer 302.

[0219] When the plasma doping method is used, the B 2 H 6 / He mixed gas is excited by plasma to diffuse boron on the main surface MSb side of the substrate 300 , thereby forming the substrate contact layer 302 .

[0220] like Fig.26 (b1) and Fig.26 As shown in (b2), the substrate 300 on which the substrate contact layer 302 is formed is attached to the substrate 200 in such a manner that the main surface MSb side faces the substrate 200. Fig.26 At this time, a pressure of 0.1 MPa to several MPa is applied, and heat treatment is performed at about 350°C to 600°C. Therefore, the substrate 300 and the substrate 200 are bonded via the insulating film 240. Note that before bonding the substrate 300 and the substrate 200, the bonding surface of the substrate 300 and the bonding surface of the substrate 200 may be subjected to O2 plasma treatment, respectively.

[0221] like Fig. 27 (a1) and Fig. 27 As shown in (a2), the substrate 300 is polished to a thickness of a few tenths of μm to several μm by chemical mechanical polishing (CMP).

[0222] like Fig. 27 (b1) and Fig. 27 As shown in (b2), element isolation is performed on the substrate 300 while retaining the area in which the pixel transistors such as the amplifier transistor 104 are formed. Specifically, a resist pattern is formed on the area in which the pixel transistors are formed by photolithography, and other areas are etched by dry etching. After the resist pattern is ashed, an insulating film 340 such as a silicon oxide film is formed by a CVD method to backfill the etched and removed portion of the substrate 300. The excess insulating film 340 is removed by CMP to expose the surface of the substrate 300.

[0223] like Fig.28 As shown in (a1) of FIG. 28 and (a2) of FIG. 28 , an amplifier transistor 104 is formed on the main surface MSa of the substrate 300. Specifically, a gate oxide film (not shown) is formed on the surface of the substrate 300 by a thermal oxidation method. A polysilicon film or the like is formed by a CVD method, a resist pattern is formed by photolithography, the polysilicon film is etched, and the resist pattern is ashed to form a gate electrode 313. Phosphorus or arsenic is implanted into the substrate 300 on both sides of the gate electrode 313 by ion implantation, and it is heat-treated by a high-temperature rapid thermal annealing (RTA) method to form a source region 312 and a drain region 311.

[0224] like Fig.28 (b1) and Fig.28 As shown in (b2), contact portions Cg, Cs, Cd and Cfd are formed. Specifically, an insulating film 340 covering the amplifying transistor 104 is further formed by a CVD method. Then, the surface of the insulating film 340 is flattened by CMP. A resist pattern is formed on the surface of the insulating film 340 by photolithography, and a through hole reaching the gate electrode 313, the source region 312, the drain region 311 and the substrate 200 is formed by dry etching. After the resist pattern is removed by ashing, a W film or the like is filled in each through hole by a CVD method, and the excess W film is removed by CMP.

[0225] Thereafter, the wirings D1 to D4 are formed, and the substrate 400 on which the logic transistor Tr and the wirings are formed is bonded, thereby completing the manufacturing process of the solid-state image sensor 100 ′.

[0226] (Comparative Example)

[0227] Next, refer to Fig.29 , the configurations of Comparative Examples 1 and 2 are compared with the configuration of the first embodiment. Fig.29 is a diagram for comparing the solid-state image sensor according to the first embodiment of the present disclosure and Comparative Examples 1 and 2.

[0228] In the solid-state image sensor of Patent Document 1, a semiconductor substrate on which a pixel area is formed and a semiconductor substrate on which a logic circuit is formed are joined. That is, a photoelectric conversion element and a pixel transistor are formed on the same semiconductor substrate. However, in this configuration, sufficient space for configuring the pixel transistor cannot be ensured. In the pixel transistor, for example, if the size of the amplifying transistor is small, it is difficult to sufficiently reduce the noise level of random telegraph signal (RTS) noise and the like.

[0229] Therefore, for example, it is conceivable to separate the substrate on which the photoelectric conversion element is formed and the substrate on which the pixel transistor is formed and to join them together. Fig.29 This configuration is shown in FIG. Here, since the substrate on which the pixel transistor is formed is bonded to another substrate via an insulating film, it is a floating substrate in which the substrate potential is not fixed. If the substrate potential is not fixed, the operation of the pixel transistor becomes unstable. In order to improve this, for example, Fig.29 As in the comparative example 2 shown in FIG. 1 , it is conceivable to provide a substrate contact layer 302' separated from the formation region of the amplifier transistor by the element isolation region STI. The substrate potential can be fixed by connecting the substrate contact layer 302' to the ground line of the upper layer. However, in the configuration of the comparative example 2, the size of the amplifier transistor must be reduced by being compressed by the element isolation region STI and the substrate contact layer 302', and the effect of separating the substrate is impaired.

[0230] In the solid-state image sensor 100' of the first embodiment, the substrate contact layer 302 that fixes the potential of the substrate 300 is arranged on the main surface MSb opposite to the side where the amplifier transistor 104 is formed on the substrate 300. Therefore, the area of ​​the main surface MSa side is not reduced by the substrate contact layer 302. In addition, it is not necessary to separately provide an element isolation layer for separating the substrate contact layer 302. Therefore, the potential of the substrate 300 can be fixed while ensuring a space for arranging the amplifier transistor 104.

[0231] When the respective configurations are compared, the size of the amplifying transistor (AMP Tr size) is Comparative Example 1: Comparative Example 2: First Embodiment = 3: 1: 3, and the same size as that of Comparative Example 1 is obtained in the first embodiment. Therefore, the noise level of the RTS noise is Comparative Example 1: Comparative Example 2: First Embodiment = 0.33: 1: 0.33, which is sufficiently reduced in the first embodiment.

[0232] By the above configuration, in the solid-state image sensor 100' of the first embodiment, it is possible to fully utilize the advantage of separating the photoelectric conversion element 102 and the pixel transistor between the separate substrates 200 and 300. That is, compared with the case where the photoelectric conversion element and the pixel transistor are arranged on the same substrate, the area of ​​both the photoelectric conversion element 102 and the pixel transistor can be enlarged. In addition, the number of pixels per unit area can be increased.

[0233] In addition, in the solid-state image sensor 100' of the first embodiment, the substrate 200 and the substrate 300 are connected via the contact portion Cfd. In addition, the substrate 300 and the substrate 400 are connected by the wiring D4 of the substrate 300 and the wiring of the substrate 400. With these configurations, the area required for the connection between the substrates can be reduced compared to the case where the substrates are connected, for example, by through silicon vias (TSVs) provided in the peripheral area of ​​the substrate. Therefore, the chip size of the solid-state image sensor 100' can be reduced. Alternatively, the pixel area can be enlarged with the same chip size.

[0234] In the solid-state image sensor 100' of the first embodiment, the contact Cfd and the junction 503 between the wiring D4 of the substrate 300 and the wiring of the substrate 400 are arranged within the pixel region. Therefore, the chip size can be further reduced or the pixel region can be further expanded.

[0235] here, Fig.30 A more detailed top view of each component is shown.

[0236] Fig.30 is a diagram showing the configuration of pixel transistors of the solid-state image sensor according to the first embodiment of the present disclosure and Comparative Example 2. Fig.30 (a) is a top view of a substrate on which a pixel transistor of Comparative Example 2 is formed, Fig.30 (b) is a top view of the substrate 300 of the first embodiment, Fig.30 (c) is a top view of the substrate 200 of the first embodiment. Fig.30 A portion of the insulating film is omitted.

[0237] like Fig.30As shown in (c), the gate electrode 223 of the transfer transistor 103 is formed into a substantially U-shaped crank shape. By respectively configuring the two ends of the U-shaped gate electrode 223 on the two photoelectric conversion elements 102, the transfer transistor 103 can receive an electrical signal from the photoelectric conversion element 102 and transmit the electrical signal to the amplifier transistor 104. The gate electrode 223 of the transfer transistor 103 is connected to the upper wiring via the contact parts Ctga and Ctgb.

[0238] like Fig.30 As shown in (b), the substrate 300 of the first embodiment includes an amplifying transistor 104, a selecting transistor 106, and a reset transistor 105. So far, only the amplifying transistor 104 has been shown as an example of a pixel transistor, but as described above, the pixel transistor also includes a reset transistor 105, a selecting transistor 106, and the like.

[0239] In order to process the electrical signal amplified by the amplifier transistor 104, the selection transistor 106 selects whether to transmit the electrical signal to the upper wiring D1 to D4. The selection transistor 106 has a gate electrode 323, a source region 322, and a drain region 321. The gate electrode 323 of the selection transistor 106 is arranged in parallel with the gate electrode 313 of the amplifier transistor 104, and is connected to the upper wiring D1 to D4 via a contact portion Csg. The source region 322 of the selection transistor 106 is connected to the upper wiring D1 to D4 via a contact portion Css. The drain region 321 of the selection transistor 106 is connected to the source region 312 of the amplifier transistor 104.

[0240] The reset transistor 105 resets (initializes) the potential of the gate of the amplifier transistor 104 to the power supply potential. The reset transistor 105 is also a transistor that resets the potential of the floating diffusion. The reset transistor 105 has a gate electrode 333, a source region 332, and a drain region 331. The gate electrode 333 of the reset transistor 105 is arranged in series with the gate electrode 323 of the selection transistor 106, and is connected to the upper wiring D1 to D4 via the contact portion Crg. The source region 332 of the reset transistor 105 is connected to the gate electrode 313 of the amplifier transistor 104 via the contacts Crs and Cag and the wiring D1. The drain region 331 of the reset transistor 105 is connected to the upper wiring D1 to D4 via the contact portion Crd.

[0241] The gate electrode 313 of the amplifier transistor 104 is connected to the floating diffusion as the source region 222 of the transfer transistor 103 via contacts Cag and Cfd and the wiring D1. The drain region 311 of the amplifier transistor 104 is connected to upper layer wirings D1 to D4 via contacts Cad.

[0242] like Fig.30As shown in (a), in the structure of Comparative Example 2, the amplifier transistor 104' and the selection transistor 106' are arranged in parallel, and the selection transistor 106' and the reset transistor 105' are arranged in series. However, since a part of the area on the substrate is occupied by the substrate contact layer 302' and the element isolation region STI, the size of the amplifier transistor 104' is limited.

[0243] As described above, even in the detailed diagram showing the pixel transistor other than the amplifying transistor, it is clear that the configuration of the first embodiment has advantages over the configuration of Comparative Example 2.

[0244] (Variant 1)

[0245] Next, we will refer to Fig.31 A solid-state image sensor according to Modification 1 of the first embodiment will be described. Figure 3 1 is a schematic diagram showing the vicinity of the bonding position of substrates 200 and 300 of the solid-state image sensor according to Modification 1 of the first embodiment of the present disclosure.

[0246] like Fig.31 As shown, the solid-state image sensor of Modification 1 includes a contact portion Csub in which at least one or more wirings D0 such as W are inserted. Therefore, the connection position of the substrate 200 and the substrate contact layer 302 of the substrate 300 can be appropriately adjusted. That is, the connection position of the substrate 200 and the substrate contact layer 302 of the substrate 300 does not necessarily overlap in the vertical direction.

[0247] With such a configuration, the degree of freedom in the relative position between the substrate 200 and the substrate 300 , the arrangement of each element in each substrate 200 and 300 , and the like is increased.

[0248] (Variant 2)

[0249] Next, we will refer to Fig.32 A solid-state image sensor according to Modification 2 of the first embodiment will be described. Fig.32 1 is a schematic diagram showing the vicinity of the bonding position of substrates 200 and 300 a of the solid-state image sensor according to Modification 2 of the first embodiment of the present disclosure.

[0250] like Fig.32 As shown, the solid-state image sensor of Modification 2 has a substrate contact layer 302a in a portion of the main surface MSb of the substrate 300a. Therefore, the substrate contact layer 302a does not necessarily have to cover the entire main surface MSb of the substrate 300a. In principle, the substrate contact layer 302a only needs to have an area in which the displacement amount when connecting the contact portion Csub is added to the cross-sectional area required for the contact portion Csub.

[0251] (Variant 3)

[0252] Next, we will refer to Fig.33 A solid-state image sensor 110 according to Modification 3 of the first embodiment will be described. Fig.33 : is a diagram showing a part of a cross section of a solid-state image sensor 110 according to Modification 3 of the first embodiment of the present disclosure.

[0253] like Fig.33 As shown, in the solid-state image sensor 110 of Modification 2, the gate electrode 223 of the transfer transistor 103 is not connected to the photoelectric conversion element 102 but is arranged on the semiconductor region 204. That is, a mode in which the transfer transistor 103 has the gate electrode 223 as a planar transfer gate can be adopted.

[0254] (Variant 4)

[0255] Next, we will refer to Fig.34 A solid-state image sensor 120 ′ according to Modification 4 of the first embodiment will be described. Fig.34 1 is a diagram showing a part of a cross section of a solid-state image sensor 120 ′ according to Modification 4 of the first embodiment of the present disclosure.

[0256] like Fig.34 As shown, in the solid-state image sensor 120' of Modification 4, the substrate 300 and the substrate 400 are electrically connected in the area facing the peripheral area 14 of the substrate 200. The peripheral area 14 corresponds to the frame area of ​​the substrate 200 and is provided at the periphery of the pixel area 13. The substrate 300 has a plurality of pad electrodes 58 in the area facing the peripheral area 14, and the substrate 400 has a plurality of pad electrodes 64 in the area facing the peripheral area 14. The substrate 300 and the substrate 400 are electrically connected to each other by bonding the pad electrodes 58 and 64 provided in the area facing the peripheral area 14.

[0257] Therefore, since substrate 300 and substrate 400 are connected by bonding pad electrodes 58 and 64 to each other, the chip size can be reduced or the pixel area can be expanded compared to the case where the substrates are connected by TSVs provided in the peripheral area of ​​the substrates, for example.

[0258] [Second embodiment]

[0259] Next, we will refer to Figures 35-44 The solid-state image sensor of the second embodiment is described. In the solid-state image sensor of the second embodiment, the shape of the substrate contact layer 302b is different from that of the first embodiment.

[0260] (Detailed Configuration Example of Solid-State Image Sensor)

[0261] Fig.352 is a schematic diagram showing the vicinity of the bonding position of the substrates 200 and 300 b of the solid-state image sensor according to the second embodiment of the present disclosure. Fig.35 (a) is a cross-sectional view showing the vicinity of the bonding position of the substrates 200 and 300b, Fig.35 (b) is a top view of the substrate 300b. Fig.35 In (a), the position of the contact portion Cg is offset. Fig.35 In (b), the insulating film 340 and the wiring D1 are omitted. Fig.35 , the amplifier transistor 104b is shown as an example of a pixel transistor.

[0262] like Fig.35 As shown, the substrate 300b has a substrate contact layer 302b as a region with lower resistance than the substrate 300b on the main surface MSb as the second main surface (opposite to the main surface MSa as the first main surface). Specifically, the substrate 300b has a certain conductivity type, such as P type, and the substrate contact layer 302b contains impurities with a higher concentration than other regions 301b of the substrate 300b. That is, the substrate contact layer 302b is P+ type. Here, it is only required that at least a part of the region of the substrate contact layer 302b has a lower resistance and a higher concentration of impurities than other regions 301b of the substrate 300b.

[0263] The substrate contact layer 302b of the substrate 300b has an extension portion 303 extending toward the outside of the substrate 300b in a direction along the substrate 300b. The direction along the substrate 300b includes a horizontal direction relative to the substrate 300b. That is, the extension portion 303 extends toward the outside of the substrate 300b in a horizontal direction or a substantially horizontal direction relative to the substrate 300b. In other words, the extension portion 303 protrudes from the side of the substrate 300b.

[0264] The substrate 300b is grounded via the substrate contact layer 302b. Specifically, the solid-state image sensor of the second embodiment includes a contact portion Csubb extending from the substrate contact layer 302b of the substrate 300b to the opposite side of the substrate 200. More specifically, the extension portion 303 has a main surface MSc as a third main surface facing the same side as the main surface MSa of the substrate 300b, and a contact portion Csubb is provided with one end connected to the main surface MSc of the extension portion 303 and the other end connected to the ground. Other areas 301b and the like of the substrate 300b do not exist on the main surface MSc of the extension portion 303. Therefore, the contact portion Csubb connected to the main surface MSc of the extension portion 303 can extend to the upper layer and be connected to the wiring D1 and the like. Therefore, the substrate 300b can be grounded by connecting to the ground line via the substrate contact layer 302b, the contact portion Csubb and the wiring D1 to D4. That is, the potential of the substrate 300b is fixed to 0V.

[0265] The substrate 300b has an amplifier transistor 104b on the main surface MSa that amplifies the electrical signal output from the photoelectric conversion element 102. The amplifier transistor 104b is formed as, for example, a MOSFET. The amplifier transistor 104b has an N-type source region 312b and an N-type drain region 311b provided in the substrate 300b. The gate electrode 313b of the amplifier transistor 104b is arranged on the substrate 300b between the source region 312b and the drain region 311b. The area of ​​the main surface MSa of the substrate 300b is reduced by, for example, the area of ​​the extension portion 303 of the substrate contact layer 302b. Therefore, the size of the amplifier transistor 104b is also slightly reduced. The size of the amplifier transistor 104b is smaller than the size of the amplifier transistor 104 of the first embodiment, and larger than the size of the amplifier transistor of Comparative Example 2.

[0266] (Example of Manufacturing Process of Solid-State Image Sensor)

[0267] Next, we will refer to Fig.36 and Fig.37 An example of a manufacturing process of the solid-state image sensor of the second embodiment is described. Fig.36 and Fig.37 : is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to the second embodiment of the present disclosure. Note that Fig.36 and Fig.37 The left figure is a cross-sectional view of a solid-state image sensor during the manufacturing process. Fig.36 and Fig.37 The right figure is a top view of the solid-state image sensor during the manufacturing process.

[0268] The solid-state image sensor of the second embodiment undergoes the same process as the first embodiment described above. Fig.26 and Fig. 27 Here, an example of the subsequent manufacturing process will be described.

[0269] like Fig.36 (a1) and Fig.36 As shown in (a2), the extension portion 303 is formed on the substrate contact layer 302b relative to the substrate 300b on which the element isolation has been performed. Specifically, a resist pattern having an opening at a position corresponding to the extension portion 303 of the substrate 300b is formed by photolithography, the substrate 300b at the opening is etched by dry etching, and the resist pattern is ashed. Therefore, the main surface MSc of the extension portion 303 is exposed.

[0270] like Fig.36 (b1) and Fig.36As shown in (b2), an insulating film 340 such as a silicon oxide film is formed on the main surface MSc of the extension 303 by CVD, and the portion of the substrate 300b removed by etching is backfilled. The excess insulating film 340 is removed by CMP to expose the surface of the substrate 300b.

[0271] like Fig.37 (a1) and Fig.37 As shown in (a2) of FIG. 1 , the amplifier transistor 104b is formed on the main surface MSa of the substrate 300b by a method similar to that of the amplifier transistor 104 of the first embodiment.

[0272] like Fig.37 (b1) and Fig.37 As shown in (b2), the contact portions Cg, Cs, Cd and Cfd are formed as in the first embodiment. In addition, the contact portion Csubb can also be formed by a method similar to that of the other contact portions Cg, Cs, Cd and Cfd.

[0273] Thereafter, the wirings D1 to D4 are formed, and the substrate 400 on which the logic transistor Tr and the wirings are formed is bonded, thereby completing the manufacturing process of the solid-state image sensor of the second embodiment.

[0274] (Comparative Example)

[0275] Next, refer to Fig.38 , the configurations of the above-mentioned comparative examples 1 and 2 are compared with the configuration of the second embodiment. Fig.38 is a diagram for comparing the solid-state image sensor according to the second embodiment of the present disclosure and Comparative Examples 1 and 2.

[0276] In the solid-state image sensor of the second embodiment, the contact portion Csubb is connected to the main surface MSc side of the substrate contact layer 302b arranged on the main surface MSb facing the same side as the main surface MSa. Therefore, although the amplifying transistor 104b reduces the amount of the substrate contact layer 302b having the extension portion 303, it still has an advantage over Comparative Examples 1 and 2.

[0277] The size of the amplifier transistor (AMP Tr size) is Comparative Example 1: Comparative Example 2: Second Embodiment = 3: 1: 2, and in the second embodiment, a size larger than that of Comparative Example 2 is obtained. Therefore, the noise level of the RTS noise is Comparative Example 1: Comparative Example 2: Second Embodiment = 0.33: 1: 0.5, which is also sufficiently reduced in the second embodiment.

[0278] here, Fig.39 A more detailed top view of each component is shown.

[0279] Fig.39is a diagram showing the configuration of pixel transistors of a solid-state image sensor according to the second embodiment of the present disclosure and Comparative Example 2. Fig.39 (a) is a top view of a substrate on which a pixel transistor of Comparative Example 2 is formed, Fig.39 (b) is a top view of the substrate 300b of the second embodiment, Fig.39 (c) is a top view of the substrate 200 of the second embodiment. Fig.39 A portion of the insulating film is omitted.

[0280] like Fig.39 As shown in (c) of FIG. 1 , the solid-state image sensor of the second embodiment further includes a substrate 200 having a configuration similar to that of the first embodiment.

[0281] like Fig.39 As shown in (b), the solid-state image sensor of the second embodiment further includes an amplifying transistor 104b, a selecting transistor 106, and a reset transistor 105, which are basically similar to the configuration in the first embodiment. The solid-state image sensor of the second embodiment is different from the first embodiment in that the extending portion 303 of the substrate contact layer 302b occupies a part of the area of ​​the substrate 300b, and the amplifying transistor 104b is reduced by that amount.

[0282] Fig.40 Shows Fig.39 Cross-sectional diagram of each part.

[0283] Fig.40 is a diagram showing connections between respective elements of a solid-state image sensor according to a second embodiment of the present disclosure. Fig.40 (a) is a top view of the substrate 300b of the second embodiment, Fig.40 (b) is along Fig.40 A cross-sectional view taken along line A-A' of (a), Fig.40 (c) is along Fig.40 A cross-sectional view taken along line BB' of (a), Fig.40 (d) is along Fig.40 A cross-sectional view taken along line CC' in (a).

[0284] like Fig.40 As shown in (b), the substrate contact layer 302b is connected to the upper wiring D1 to D4 via the contact portion Csubb at the extension portion 303 and is grounded. The drain region 311b of the amplifier transistor 104b is connected to the upper wiring D1 to D4 via the contact portion Cad. The source region 322 of the selection transistor 106 is connected to the upper wiring D1 to D4 via the contact portion Css.

[0285] like Fig.40As shown in (c), the source region 222 of the transfer transistor 103 as a floating diffusion is connected to the wiring D1 via the contact Cfd. Although not shown, the wiring D1 is connected to the gate electrode 313b of the amplifying transistor 104b. The gate electrode 223 of the transfer transistor 103 is connected to the wiring D0 of W etc. via the contact Ctga. The wiring D0 is connected to the upper wiring via the contact Ctgb.

[0286] As Fig.40 As shown in (d), the source region 332 of the reset transistor 105 is connected to the wiring D1 via the contact Crs. Although not shown, as described above, the wiring D1 is connected to the gate electrode 313b of the amplifier transistor 104b. The drain region 331 of the reset transistor 105 is connected to the upper wirings D1 to D4 via the contact Crd.

[0287] (Variant 1)

[0288] Next, we will refer to Fig.41 A solid-state image sensor according to Modification 1 of the second embodiment will be described. Fig.41 1 is a schematic diagram showing the vicinity of the bonding position of substrates 200 and 300 c of the solid-state image sensor according to Modification 1 of the second embodiment of the present disclosure.

[0289] like Fig.41 As shown, the solid-state image sensor of Modification 1 includes a through extension portion 303c, a contact portion Csubc connected to the substrate 200 at one end and grounded at the other end. That is, the substrate contact layer 302c of the substrate 300c has an extension portion 303c through which the contact portion Csubc penetrates. The contact portion Csubc is connected to the ground line via the upper wiring D1 to D4. The substrate 200 is grounded via the contact portion Csubc. The substrate 300c is grounded via the extension portion 303c of the substrate contact layer 302c and the contact portion Csubc.

[0290] With such a configuration, the substrate 200 and the substrate 300c can be grounded using a common configuration, and the wiring structure can be made simpler. In addition, the volume occupied by the configuration for grounding can be reduced.

[0291] (Variant 2)

[0292] Next, we will refer to Fig.42 and Fig.43 A solid-state image sensor according to Modification 2 of the second embodiment will be described. Fig.42 1 is a schematic diagram showing the vicinity of the bonding position of substrates 200 and 300 d of the solid-state image sensor according to Modification 2 of the second embodiment of the present disclosure.

[0293] like Fig.42As shown, the solid-state image sensor of the modification example 2 includes a contact portion Csubd having one end connected to the side of the extension portion 303d and the other end connected to the ground. That is, the substrate contact layer 302d of the substrate 300d has an extension portion 303d connected to the contact portion Csubd on the side. The contact portion Csubd is connected to the ground line via the upper layer wiring D1 to D4. The substrate 300d is grounded via the extension portion 303d of the substrate contact layer 302d and the contact portion Csubd.

[0294] The substrate 300d has an amplifier transistor 104d that amplifies an electrical signal output from the photoelectric conversion element 102 on the main surface MSa as the first main surface. The amplifier transistor 104d is formed as, for example, a MOSFET. The amplifier transistor 104d has an N-type source region 312d and an N-type drain region 311d provided in the substrate 300d. The gate electrode 313d of the amplifier transistor 104d is arranged on the substrate 300d between the source region 312d and the drain region 311d.

[0295] With such a configuration, the extension portion 303d of the substrate contact layer 302d does not necessarily have an area in which the displacement amount at the time of connection is added to the cross-sectional area of ​​the contact portion Csubd, and the extension portion 303d can be formed to be smaller than the extension portion 303 in the second embodiment. Along with this, the size of the amplifier transistor 104d can be slightly increased. The size of the amplifier transistor 104d is smaller than the size of the amplifier transistor 104 of the first embodiment, and larger than the size of the amplifier transistor 104b of the second embodiment.

[0296] Fig.43 It is used to compare the structures of the above-mentioned comparative examples 1 and 2 and the structure of the modified example 2. Fig.43 is a diagram for comparing the solid-state image sensor according to the second embodiment of the present disclosure, its modification, and comparative examples 1 and 2.

[0297] In the solid-state image sensor of Modification 2, the contact portion Csubd is connected to the side surface of the substrate contact layer 302d arranged on the main surface MSb. Therefore, compared with Comparative Examples 1 and 2, the solid-state image sensor of the second embodiment has further advantages.

[0298] The size of the amplifier transistor (AMP Tr size) is Comparative Example 1: Comparative Example 2: Second Embodiment: Modified Example 2 = 3: 1: 2: 2.5, and in Modified Example 2, a size larger than that of the second embodiment is obtained. Therefore, the noise level of the RTS noise is Comparative Example 1: Comparative Example 2: Second Embodiment: Modified Example 2 = 0.33: 1: 0.5: 0.4, and Modified Example 2 has a better noise level than the second embodiment.

[0299] (Variant 3)

[0300] Next, we will refer to Fig.44 A solid-state image sensor according to Modification 3 of the second embodiment will be described. Fig.44 1 is a schematic diagram showing the vicinity of a bonding position of substrates 200 e and 300 e of a solid-state image sensor according to Modification 3 of the second embodiment of the present disclosure.

[0301] like Fig.44 (a) The cross-sectional view and Fig.44 As shown in the top view of (b), in the solid-state image sensor of Modification 3, the number of amplification transistors 104e can be increased according to the number of photoelectric conversion elements 102 and corresponding transfer transistors 103.

[0302] Specifically, the substrate 200 e includes a photoelectric conversion element 102 - 1 and a corresponding transfer transistor 103 - 1 , a photoelectric conversion element 102 - 2 and a corresponding transfer transistor 103 - 2 , and a photoelectric conversion element 102 - 3 and a corresponding transfer transistor 103 - 3 .

[0303] The substrate 300e has an amplifier transistor 104e-1 corresponding to the photoelectric conversion element 102-1 and the transfer transistor 103-1. In addition, the substrate 300e has an amplifier transistor 104e-2 corresponding to the photoelectric conversion element 102-2 and the transfer transistor 103-2. In addition, the substrate 300e has an amplifier transistor 104e-3 corresponding to the photoelectric conversion element 102-3 and the transfer transistor 103-3.

[0304] The regions where the amplifier transistors 104e-1 to 104e-3 are provided are connected via a substrate contact layer 302e on the bottom surface of the substrate 300e. The region where the amplifier transistor 104e-1 is provided is connected to the region where the amplifier transistor 104e-2 is provided via an extension 303e-2 of the substrate contact layer 302e. The region where the amplifier transistor 104e-2 is provided is connected to the region where the amplifier transistor 104e-3 is provided via an extension 303e-3 of the substrate contact layer 302e.

[0305] The contact Csube-1 for grounding the substrate 300e is connected to the extension 303e-1 near the amplifying transistor 104e-1. The contact Csube-2 for grounding the substrate 300e is connected to the extension 303e-2 near the amplifying transistor 104e-2. In addition, the extension 303e-2 is provided with a through hole 303th-2 penetrated by Cfd-1 connecting the floating diffusion of the transfer transistor 103-1 and the gate electrode of the amplifying transistor 104e-1. The contact Csube-3 for grounding the substrate 300e is connected to the extension 303e-3 near the amplifying transistor 104e-3. In addition, the extension 303e-3 is provided with a through hole 303th-3 penetrated by Cfd-2 connecting the floating diffusion of the transfer transistor 103-2 and the gate electrode of the amplifying transistor 104e-2.

[0306] With such a configuration, even if the number of photoelectric conversion elements 102 and transfer transistors 103 increases, the number of amplifier transistors 104e can be increased accordingly. Fig.44 In the example of FIG. 1 , three photoelectric conversion elements 102, three transfer transistors 103, and three amplification transistors 104e have a one-to-one correspondence, but the number of these elements is not limited to three. The number of these elements may be two or four or more.

[0307] [Third embodiment]

[0308] Next, we will refer to Fig.45 and Fig.46 A solid-state image sensor 100f of a third embodiment is described. A solid-state image sensor 100f of the third embodiment is different from the first and second embodiments in that a plurality of photoelectric conversion elements 102 are integrated and handled as one.

[0309] Fig.45 is a diagram showing a part of a solid-state image sensor 100 f according to a third embodiment of the present disclosure. Fig.45 (a) is a diagram showing a portion of the upper surface of the substrate 200. Fig.45 (b) is a diagram showing a part of the cross section of the solid-state image sensor 100f.

[0310] like Fig.45 As shown in (a), in the substrate 200, four transfer transistors 103 corresponding to the four photoelectric conversion elements 102 are arranged near the center where the four photoelectric conversion elements 102 are gathered. In addition, the source region 222 as the floating diffusion part of the four transfer transistors 103 is surrounded by the four transfer transistors 103 and arranged close to each other.

[0311] like Fig.45 (a) and Fig.45As shown in (b), the four source regions 222 are combined into one by the wiring Dx above the substrate 200. Specifically, the wiring Dx has four legs Df connected to the respective source regions 222. In addition, a contact portion Cfd is connected to the upper portion of the wiring Dx. The other end of the contact portion Cfd is connected to the wiring D1.

[0312] The substrate 300f has one pixel transistor corresponding to four photoelectric conversion elements 102 and four transfer transistors 103. That is, the substrate 300f has one amplification transistor 104f, one reset transistor 105f and one selection transistor not shown for four photoelectric conversion elements 102 and four transfer transistors 103.

[0313] The wiring D1 connecting the contact portion Cfd is connected to the gate electrode 313f of the amplifier transistor 104f. In addition, the wiring D1 connects the gate electrode 313f of the amplifier transistor 104f and the source region 332f of the reset transistor 105f.

[0314] The configurations of the above-described first and second embodiments and the like can be applied to such a solid-state image sensor 100f. Fig.46 It is a comparison diagram in the case where the configurations of the first and second embodiments of the present disclosure and Comparative Example 2 are applied to the solid-state image sensor 100 f according to the third embodiment.

[0315] like Fig.46 As shown, the size of the amplifier transistor (AMP Tr size) is Comparative Example 2: First Implementation: Second Implementation = 1:2:1.5, and the noise level of the RTS noise is Comparative Example 2: First Implementation: Second Implementation = 1:0.5:0.67.

[0316] As described above, the first embodiment is superior to the third embodiment in terms of the size of the amplifying transistor and the noise level of the RTS noise compared to the application example of Comparative Example 2. The second embodiment is superior to the third embodiment in terms of the size of the amplifying transistor and the noise level of the RTS noise compared to the application example of Comparative Example 2. The first embodiment is superior to the third embodiment in terms of the size of the amplifying transistor and the noise level of the RTS noise compared to the application example of the second embodiment.

[0317] [Fourth embodiment]

[0318] The configurations of the first and second embodiments described above can also be applied to a semiconductor device having a transistor such as a MOSFET. Fig.47 and Fig.48 Each application example is shown.

[0319] Fig.471 is a schematic diagram showing the vicinity of the bonding position of substrates 500 and 600 a in the case where the configuration of the first embodiment of the present disclosure is applied to the semiconductor device according to the fourth embodiment.

[0320] like Fig.47 As shown, the semiconductor device of the fourth embodiment includes a substrate 500 as a first semiconductor substrate, which has a transistor 530' as a first transistor. The substrate 500 as a silicon substrate or the like is grounded. That is, the potential of the substrate 500 is fixed to 0V. The transistor 530' is formed as a MOSFET, for example. The transistor 530' includes a gate electrode 533, an N-type source region 532, and an N-type drain region 531. The gate electrode 533 is provided with a contact portion 533c connected to the upper wiring. The source region 532 is provided with a contact portion 532c connected to the upper wiring. The drain region 531 is provided with a contact portion 531c connected to the upper wiring. In addition, the substrate 500 has a P+ type substrate contact layer 510 separated from the region in which the transistor 530' is configured by the element isolation region 520'.

[0321] Furthermore, the semiconductor device of the fourth embodiment includes a substrate 600a as a second semiconductor substrate facing the substrate 500 via the insulating film 580. That is, the substrate 600a and the substrate 500 are bonded. Fig.47 The illustrated surface 561 represents the surface where the substrate 600a and the substrate 500 are bonded.

[0322] The substrate 600a has a transistor 630 as a second transistor on the main surface MSa as the first main surface. The transistor 630 is formed as, for example, a MOSFET. The transistor 630 includes a gate electrode 633, an N-type source region 632, and an N-type drain region 631. The gate electrode 633 is provided with a contact portion 633c connected to the upper wiring. The source region 632 is provided with a contact portion 632c connected to the upper wiring. The drain region 631 is provided with a contact portion 631c connected to the upper wiring. The transistor 630 is covered by an insulating film 681.

[0323] The substrate 600a has a substrate contact layer 611 as a region having a lower resistance than the substrate 600a on the main surface MSb which is the second main surface opposite to the main surface MSa. Specifically, the substrate 600a has a certain conductivity type, for example, P type, and the substrate contact layer 611 contains impurities at a higher concentration than other regions 634 of the substrate 600a. That is, the N-type source region 632 and the N-type drain region 631 of the transistor 630 provided on the main surface MSa and the P+ type substrate contact layer 611 provided on the main surface MSb are separated by other regions 634 of the substrate 600a. Here, it is only required that at least a portion of the region of the substrate contact layer 611 has a lower resistance and a higher concentration of impurities than other regions 634 of the substrate 600a.

[0324] The substrate 600a is grounded via the substrate contact layer 611. Specifically, the semiconductor device of the fourth embodiment includes a contact portion 611c extending from the substrate contact layer 611 of the substrate 600a to the substrate 500 side. More specifically, the substrate 600a is arranged on the substrate 500 in such a manner that the main surface MSb side faces the substrate 500, and the semiconductor device includes a contact portion 611c connecting the substrate contact layer 611 of the substrate 600a and the substrate contact layer 510 of the substrate 500. Therefore, the substrate 600a is grounded via the substrate contact layer 611 and the substrate 500. That is, the potential of the substrate 600a is fixed to 0V.

[0325] Fig.48 1 is a schematic diagram showing the vicinity of the bonding position of substrates 500 and 600 b in the case where the configuration of the second embodiment of the present disclosure is applied to the semiconductor device according to the fourth embodiment.

[0326] like Fig.48 As shown, the semiconductor device of the fourth embodiment includes a substrate 600b as a second semiconductor substrate facing the substrate 500 via an insulating film 580. That is, the substrate 600b and the substrate 500 are bonded. Fig.48 The illustrated surface 562 represents the surface where the substrate 600b and the substrate 500 are bonded.

[0327] The substrate 600b has a transistor 640 as a second transistor on the main surface MSa as the first main surface. The transistor 640 is formed as, for example, a MOSFET. The transistor 640 includes a gate electrode 643, an N-type source region 642, and an N-type drain region 641. The gate electrode 643 is provided with a contact portion 643c connected to the upper wiring. The source region 642 is provided with a contact portion 642c connected to the upper wiring. The drain region 641 is provided with a contact portion 641c connected to the upper wiring. The transistor 640 is covered by an insulating film 682.

[0328] The substrate 600b has a substrate contact layer 612 as a region having a lower resistance than the substrate 600b on the main surface MSb as the second main surface opposite to the main surface MSa. Specifically, the substrate 600b has a certain conductivity type, for example, P type, and the substrate contact layer 612 contains impurities at a higher concentration than other regions 644 of the substrate 600b. That is, the N-type source region 642 and the N-type drain region 641 of the transistor 640 provided on the main surface MSa and the P+ type substrate contact layer 612 provided on the main surface MSb are separated by other regions 644 of the substrate 600b. Here, it is only required that at least a portion of the substrate contact layer 612 has a lower resistance and a higher concentration of impurities than other regions 644 of the substrate 600b.

[0329] The substrate contact layer 612 of the substrate 600 b has an extension portion 613 extending toward the outside of the substrate 600 b in a direction along the substrate 600 b .

[0330] The substrate 600b is grounded via the substrate contact layer 612. Specifically, the semiconductor device of the fourth embodiment includes a contact portion 612c extending from the substrate contact layer 612 of the substrate 600b to the opposite side of the substrate 500. More specifically, the extension portion 613 has a main surface MSc as a third main surface facing the same side as the main surface MSa of the substrate 600b, and is provided with a contact portion 612c having one end connected to the main surface MSc of the extension portion 613 and the other end grounded. Therefore, the substrate 600b is grounded via the substrate contact layer 612, the contact portion 612c, the upper wiring, etc. That is, the potential of the substrate 600b is fixed to 0V.

[0331] In the semiconductor device of the fourth embodiment, the uses of the transistor 530' of the substrate 500 and the transistors 630 and 640 of the substrates 600a and 600b may be different. The transistor 530' is suitable for applications requiring high-speed processing. The transistors 630 and 640 have a slower operating speed than the transistor 530' of the substrate 500, but are suitable for applications requiring low noise. Therefore, for example, the transistor 530' can be used as a transistor constituting a logic circuit, etc. In addition, the transistors 630 and 640 can be used as transistors constituting an analog circuit, etc.

[0332] (Variant 1)

[0333] Next, we will refer to Fig.49 A semiconductor device according to Modification 1 of the fourth embodiment will be described. Fig.49 1 is a schematic diagram showing the vicinity of the bonding position of substrates 500c and 600c of a semiconductor device according to Modification 1 of the fourth embodiment of the present disclosure. The semiconductor device of Modification 1 is different from the fourth embodiment described above in that N-type transistors 530' and 640 and P-type transistors 540' and 650 are mixed.

[0334] like Fig.49As shown in the cross-sectional view of (a), the semiconductor device of variant example 1 includes a substrate 500c as a first semiconductor substrate having a transistor 530'. The substrate 500c has a transistor 540' as a fourth transistor, which is separated from the transistor 530' by an element isolation region 520' and has a conductivity type different from the conductivity type of the transistor 530', for example, a P-type. The transistor 540' is formed as, for example, a MOSFET. The transistor 540' includes a gate electrode 543', a P-type source region 542', and a P-type drain region 541. The gate electrode 543' is provided with a contact portion 543c connected to the upper wiring. The source region 542' is provided with a contact portion 542c connected to the upper wiring. The drain region 541 is provided with a contact portion 541c connected to the upper wiring.

[0335] The semiconductor device of Modification 1 includes a substrate 600c as a second semiconductor substrate facing the substrate 500c via the insulating film 583. That is, the substrate 600c and the substrate 500c are bonded to each other. Fig.49 The illustrated surface 563 represents the surface where the substrate 600c and the substrate 500c are bonded.

[0336] like Fig.49 (a) The cross-sectional view and Fig.49 As shown in the top view of (b), the substrate 600c has a transistor 640 on the main surface MSa. In addition, the substrate 600c has a transistor 650 as a fifth transistor, which is separated from the transistor 640 by the element isolation regions 602 and 603 and has a conductivity type different from the conductivity type of the transistor 640, such as a P-type. The transistor 650 is formed as, for example, a MOSFET. The transistor 650 includes a gate electrode 653, a P-type source region 652, and a P-type drain region 651. The gate electrode 653 is provided with a contact portion 653c connected to the upper wiring. The source region 652 is provided with a contact portion 652c connected to the upper wiring. The drain region 651 is provided with a contact portion 651c connected to the upper wiring. The element isolation region 602 is also used as a through hole for transferring the contact portions 531c to 533c from the lower substrate 500c to the upper wiring side. The element isolation region 603 also functions as a through hole for passing the contacts 541 c to 543 c from the lower substrate 500 c to the upper wiring side. The entire substrate 600 c including the transistors 640 and 650 is covered with an insulating film 683 .

[0337] The substrate 600c has a substrate contact layer 612 having a lower resistance than a region 644 of the substrate 600c near the transistor 640 at a position corresponding to the main surface MSb. That is, the region 644 of the substrate 600c is, for example, a P type, and the substrate contact layer 612 is a P+ type. The substrate contact layer 612 has an extension portion 613 extending toward the outside of the substrate 600c in a direction along the substrate 600c.

[0338] The substrate 600c has a substrate contact layer 622 having a lower resistance than a region 654 of the substrate 600c near the transistor 650 at a position corresponding to the main surface MSb. That is, the region 654 of the substrate 600c is, for example, N-type, and the substrate contact layer 622 is N+ type. Here, it is only required that at least a portion of the region of the substrate contact layer 622 has a lower resistance and a higher concentration of impurities than other regions 654 of the substrate 600c.

[0339] The substrate contact layer 622 has an extension portion 623 extending toward the outside of the substrate 600c in the direction along the substrate 600c. The extension portion 623 has a main surface MSc as a third main surface facing the same side as the main surface MSa of the substrate 600c, and is provided with a contact portion 622c having one end connected to the main surface MSc of the extension portion 623 and the other end connected to the ground.

[0340] The substrate 600 c is grounded via substrate contact layers 612 and 622 .

[0341] (Variant 2)

[0342] Next, we will refer to Fig.50 A semiconductor device according to Modification 2 of the fourth embodiment will be described. Fig.50 1 is a schematic diagram showing the vicinity of the bonding position of substrates 500c, 700c, and 600c of a semiconductor device according to Modification 2 of the fourth embodiment of the present disclosure. The semiconductor device of Modification 2 is different from Modification 1 described above in that a substrate 700c is sandwiched between substrates 500c and 600c.

[0343] like Fig.50 As shown, in addition to the configuration of Modification 1, the semiconductor device of Modification 2 further includes a substrate 700c as a third semiconductor substrate which is a floating substrate facing the substrate 500c. That is, the substrate 700c as a silicon substrate or the like is bonded to the substrate 500c. Fig.50 The illustrated surface 570 represents the surface where the substrate 500c and the substrate 700c are bonded. In addition, the substrate 600c is bonded to the substrate 700c. Fig.50 The illustrated surface 760 represents the surface where the substrate 700c and the substrate 600c are bonded.

[0344] The substrate 500c is grounded and has a potential fixed to 0 V. The substrate 600c has substrate contact layers 612 and 622, is grounded via contact portions 612c and 622c connected thereto, and has a potential fixed to 0 V. The substrate 700c does not have a substrate contact layer or the like, and is not grounded. That is, the substrate 700c is a floating substrate having an indefinite substrate potential.

[0345] The substrate 700c has transistors 730 and 740 as third transistors. The transistors 730 and 740 are formed as MOSFETs, for example. The transistor 730 has a gate electrode 733, an N-type source region 732, an N-type drain region 731, and a P-type region 734 sandwiched between these regions. The transistor 730 has a fully depleted silicon-on-insulator (FD-SOI) structure, in which the insulating film 583 is configured directly below the body of the NPN structure. The transistor 740 has a gate electrode 743, a P-type source region 742, a P-type drain region 741, and an N-type region 744 sandwiched between these regions. The transistor 740 has a FD-SOI structure, in which the insulating film 583 is configured directly below the body of the PNP structure.

[0346] By forming the transistors 730 and 740 on the substrate 700 c in this manner, the transistors 730 and 740 can be miniaturized, and parasitic capacitance can be suppressed to obtain high-speed transistors 730 and 740 .

[0347] Note that, for the purpose of noise reduction effect, similarly to the substrate 600 c , the substrate 700 c may be provided with a substrate contact layer to fix the potential of the substrate 700 c .

[0348] In addition, in the above-mentioned modification examples 1 and 2, it has been described that the Fig.48 The configuration example of the second embodiment shown in FIG. 1 is shown in FIG. 2 , but in the modification examples 1 and 2, the following configuration example may also be applied: Fig.47 The structure of the first embodiment is shown.

[0349] [Fifth embodiment]

[0350] In a solid-state image sensor including a plurality of types of pixel transistors, how to suppress variations in threshold voltages of the respective pixel transistors is also a problem.

[0351] In a fifth embodiment, a solid-state image sensor capable of adjusting a threshold voltage of a pixel transistor is proposed.

[0352] (Detailed Configuration Example of Solid-State Image Sensor)

[0353] Fig.51 : is a longitudinal sectional view showing the vicinity of the bonding position of substrates 200 and 300 g of the solid-state image sensor 100 g according to the fifth embodiment of the present disclosure. Fig.52 : is a cross-sectional view in the vicinity of a bonding position of substrates 200 and 300 g including a solid-state image sensor 100 g according to a fifth embodiment of the present disclosure. Fig.52 (a) is a cross-sectional view of the substrate 300g, in which the insulating film 340 is omitted. Fig.52 (b) is a cross-sectional view of the insulating film 240. Fig.52(c) is a cross-sectional view of the substrate 200, in which the insulating film 240 is omitted.

[0354] like Fig.51 As shown, the solid-state image sensor 100g of the fifth embodiment has a configuration in which a substrate 200 and a substrate 300g are bonded together.

[0355] The substrate 200 as the first substrate has, for example, a configuration similar to that of the substrate 200 shown in the first embodiment. Fig.51 , a cross section of a different range from that shown in the first embodiment is shown. That is, the substrate 200 includes a plurality of transfer transistors 103 that span the pixel separation portion 203 on the surface portion of the P-type semiconductor region 204. The P-type diffusion region 230 is provided in a region that is a surface portion of the P-type semiconductor region 204 and is separated from a region where the transfer transistor 103 is formed. The diffusion region 230 is connected to, for example, a contact portion C2vs, and the contact portion C2vs is connected to the wiring D1vss. The semiconductor region 204 of the substrate 200 is grounded via the contact portion C2vs, the wiring D1vss, and the like.

[0356] like Fig.51 and Fig.52 As shown in (c), the transfer transistor 103 includes a gate electrode 223 and an N-type source region 222 as a floating diffusion. The gate electrode 223 is connected to a contact Ctg. The source region 222 is connected to a contact Cfd.

[0357] like Fig.51 As shown, the substrate 300g as the second substrate has a P-type semiconductor region 301, which has a main surface MSa as a first main surface and a main surface MSb as a second main surface. The distance between the main surfaces MSa and MSb, that is, the thickness of the semiconductor region 301 is, for example, 100nm or less. The main surface MSb of the substrate 300g is attached to the substrate 200 via an insulating film 240 covering the entire transfer transistor 103 of the substrate 200. The thickness of the insulating film 240 is, for example, about 350nm.

[0358] The substrate 300 g has a pixel transistor on the main surface MSa side. The pixel transistor processes an electrical signal output from the photoelectric conversion element having the N-type semiconductor region 201 included in the substrate 200. Fig.51 A cross section including a selection transistor 106 and a reset transistor 105 as examples of pixel transistors is shown.

[0359] The P-type diffusion region 330 is provided in a region which is a surface layer portion of the P-type semiconductor region 301 and is separated from the formation region of the selection transistor 106, the reset transistor 105, etc. The diffusion region 330 is connected to, for example, the contact C3vs, and the contact C3vs is connected to the wiring D1vss. The semiconductor region 301 of the substrate 300 is grounded via the contact C3vs, the wiring D1vss, etc.

[0360] In the substrate 300g, the entire selection transistor 106, the reset transistor 105, and the like are covered with an insulating film 340. The thickness of the insulating film 340 is, for example, about 350 nm.

[0361] like Fig.51 and 52 As shown in (a), the selection transistor 106 has a gate electrode 323, an N-type source region 322, and an N-type drain region 321. The gate electrode 323 is connected to the contact Csg. The source region 322 is connected to the contact Css, and the contact Css is connected to the source line (not shown) via the wiring D1vs1. The drain region 321 is connected to the contact Csd.

[0362] The reset transistor 105 has a gate electrode 333, an N-type source region 332, and an N-type drain region 331. The gate electrode 333 is connected to the contact Crg. The source region 332 is connected to the contact Crs, and the contact Crs is connected to the source region 222 of the transfer transistor 103 via the wiring D1 and the contact Cfd. The drain region 331 is connected to the contact Crd, and the contact Crd is connected to the power supply (not shown) via the wiring D1vdd.

[0363] like Fig.52 As shown in (a), the amplifier transistor 104 has a gate electrode 313, an N-type source region 312, and an N-type drain region 311. The gate electrode 313 is connected to the contact portion Cag, and the contact portion Cag is connected to the source region 222 of the transfer transistor 103 via the wiring D1 and the contact portion Cfd. The source region 312 is connected to the contact portion Cas. The contact portion Cas is connected to the contact portion Csd, which is connected to the drain region 321 of the selection transistor 106. The drain region 311 of the amplifier transistor 104 is connected to the contact portion Cad.

[0364] like Fig.51 and 52 As shown in (a) of FIG. 1 , the selection transistor 106 , the reset transistor 105 , and the amplifier transistor 104 are separated from each other by an element isolation region STI formed around them.

[0365] like Fig.51 and Fig.52As shown in (b), at positions corresponding to the selection transistor 106, the reset transistor 105 and the amplifier transistor 104, back gate electrodes 251s, 251r, and 251a including polysilicon or the like are arranged near the main surface MSb side of the semiconductor region 301 of the substrate 300g.

[0366] That is, the back gate electrode 251s as the second electrode is arranged on the back side of the selection transistor 106. At this time, in the top view, the back gate electrode 251s is arranged at a position overlapping with at least the gate electrode 323, the source region 322 and the drain region 321 of the selection transistor 106, and preferably, completely covers the gate electrode 323, the source region 322 and the drain region 321.

[0367] In addition, a back gate electrode 251r as a third electrode is disposed on the back side of the reset transistor 105. At this time, in the top view, the back gate electrode 251r is disposed at a position overlapping at least the gate electrode 333, the source region 332, and the drain region 331 of the reset transistor 105, and preferably completely covers the gate electrode 333, the source region 332, and the drain region 331.

[0368] In addition, a back gate electrode 251a as a first electrode is arranged on the back side of the amplifying transistor 104. At this time, in a top view, the back gate electrode 251a is arranged at a position overlapping at least the gate electrode 313, the source region 312, and the drain region 311 of the amplifying transistor 104, and preferably, completely covers the gate electrode 313, the source region 312, and the drain region 311.

[0369] The distance between the back gate electrodes 251s, 251r and 251a and the main surface MSb of the semiconductor region 301 of the substrate 300g is, for example, 10 nm or less. For example, the insulating film 240 is interposed between the back gate electrodes 251s, 251r and 251a and the main surface MSb of the semiconductor region 301 with a thickness of 10 nm or less.

[0370] like Fig.52 As shown in (b), the back gate electrodes 251s, 251r and 251a are connected to the contact parts Cbgs, Cbgr and Cbga, respectively. Fig.52 As shown in (a), the contacts Cbgs, Cbgr and Cbga are respectively connected to the reverse bias line BBL.

[0371] The reverse bias line BBL is configured so that a voltage can be applied to the back gate electrodes 251s, 251r, and 251a via the contacts Cbgs, Cbgr, and Cbga. Therefore, a reverse bias can be applied from the back gate electrodes 251s, 251r, and 251a to the selection transistor 106, the reset transistor 105, and the amplification transistor 104. The reverse bias is a bias generated by the difference between the gate voltage of each back gate electrode 251s, 251r, and 251a and the threshold voltage of each of the selection transistor 106, the reset transistor 105, and the amplification transistor 104.

[0372] (Operation example of solid-state image sensor)

[0373] Next, we will refer to Fig.53 An operation example of the solid-state image sensor 100g according to the fifth embodiment will be described. Fig.53 is a perspective view showing a part of a solid-state image sensor 100g according to a fifth embodiment of the present disclosure. Fig.53 , the insulating films 240 and 340 and the like are omitted.

[0374] The electrical signal from the photoelectric conversion element is transmitted to the amplifier transistor 104 included in the solid-state image sensor 100g by the transfer transistor 103. A voltage corresponding to the magnitude of the electrical signal from the photoelectric conversion element is applied to the gate electrode 313 of the amplifier transistor 104. At this time, a predetermined voltage is also applied to the back gate electrode 251a configured on the back side of the amplifier transistor 104 via the contact portion Cbga, and the threshold voltage of the amplifier transistor 104 is adjusted. Therefore, the amplifier transistor 104 can be turned on at a desired voltage value, and the electrical signal from the photoelectric conversion element is amplified.

[0375] In the selection transistor 106 included in the solid-state image sensor 100g, a voltage is applied to the gate electrode 323 via the contact portion Csg. At this time, a predetermined voltage is also applied to the back gate electrode 251s arranged on the back side of the selection transistor 106 via the contact portion Cbgs, and the threshold voltage of the selection transistor 106 is adjusted. Therefore, the selection transistor 106 can be turned on at a desired voltage value, and the electrical signal from the photoelectric conversion element amplified by the amplifier transistor 104 is transmitted via the wiring D1vs1.

[0376] In addition, in the selection transistor 106, the back gate electrode 251s can reduce the channel resistance of the selection transistor 106, that is, the on-resistance, and can accelerate the timing of turning on the selection transistor 106. Since it takes time for the source line potential VSL to rise due to the resistance of the contact portion Css, the wiring D1vsl, etc., it is possible to shorten the time to wait for the source line potential VSL to rise by advancing the timing of turning on the selection transistor 106.

[0377] In the reset transistor 105 included in the solid-state image sensor 100g, a voltage is applied to the gate electrode 333 via the contact portion Crg. At this time, a predetermined voltage is also applied to the back gate electrode 251r arranged on the back side of the reset transistor 105 via the contact portion Cbgr, and the threshold voltage of the reset transistor 105 is adjusted. Therefore, the reset transistor 105 can be turned on at a desired voltage value, and the potentials of the gate electrode 313 of the amplifier transistor 104 and the source region 222 of the transfer transistor 103 as a floating diffusion portion are reset to the power supply potential VDD.

[0378] Note that Fig.52 and Fig.53 In the example of FIG. 1 , the back gate electrodes 251s and 251r corresponding to the selection transistor 106 and the reset transistor 105 are connected to a common reverse bias line BBL, but may be connected to separate reverse bias lines. Therefore, for example, different voltages may be applied to the back gate electrodes 251s, 251r, and 251a, respectively, to control the respective threshold voltages of the selection transistor 106, the reset transistor 105, and the amplification transistor 104, respectively.

[0379] (Example of Manufacturing Process of Solid-State Image Sensor)

[0380] Next, we will refer to Figures 54-57 An example of a manufacturing process of the solid-state image sensor 100g of the fifth embodiment will be described. Figures 54-57 : is a flowchart showing an example of a procedure of a manufacturing process of the solid-state image sensor 100g according to the fifth embodiment of the present disclosure.

[0381] like Fig.54 As shown in (a), a photoelectric conversion element including an N-type semiconductor region 201, a P-type semiconductor region 204, a gate electrode 223 of a transfer transistor 103, and a source region 222 as a floating diffusion portion are formed on a substrate 200. A P-type diffusion region 230 is formed at a position away from the transfer transistor 103. The semiconductor region 204 including the gate electrode 223 and the source region 222 is covered with an insulating film 240. A polysilicon film 250 is formed on the insulating film 240 by, for example, a CVD method.

[0382] like Fig.54 As shown in (b), N-type impurities are doped into the polysilicon film 250 (ion implantation) to form an N-type polysilicon film 251.

[0383] like Fig.54As shown in (c), a portion of the polysilicon film 251 is etched to form a back gate electrode 251s at a position corresponding to the subsequent selection transistor 106 and a back gate electrode 251r at a position corresponding to the subsequent reset transistor 105. At this time, a back gate electrode 251a (not shown) is also formed at a position corresponding to the subsequent amplifier transistor 104.

[0384] like Fig.54 As shown in (d), the insulating film 240 is further formed so as to cover the back gate electrodes 251s and 251r with a thickness of, for example, 10 nm or less.

[0385] like Fig.55 As shown in (a) of FIG. 2 , the thick film (ie, the substrate 300 g before thinning) is bonded onto the insulating film 240 so that the main surface MSb faces the insulating film 240 .

[0386] like Fig.55 As shown in (b), the substrate 300g is polished by a polisher G or the like to shape the semiconductor region 301, so that the thickness of the semiconductor region 301 is, for example, 100 nm or less.

[0387] like Fig.56 As shown in (a), the semiconductor region 301 of the portion where the contacts Cfd and C2vs connected to the substrate 200 are arranged is removed.

[0388] like Fig.56 As shown in (b), the selection transistor 106 and the reset transistor 105 are formed on the main surface MSa of the semiconductor region 301. Specifically, a gate oxide film (not shown) is formed on the main surface MSa of the semiconductor region 301 by a thermal oxidation method. A polysilicon film or the like is formed by a CVD method, and is partially etched to form gate electrodes 323 and 333 of the selection transistor 106 and the reset transistor 105. N-type impurity ions are implanted into the semiconductor region 301 on both sides of each gate electrode 323 and 333, thereby forming source regions 322 and 332 and drain regions 321 and 331. The amplifier transistor 104 not shown is also similarly formed in parallel therewith.

[0389] Thereafter, an element isolation region STI is formed around the selection transistor 106 , the reset transistor 105 , and the like by a technique such as shallow trench isolation.

[0390] like Fig.57 As shown in (a) of FIG. 1 , an insulating film 340 is formed to cover the selection transistor 106 , the reset transistor 105 , and the like.

[0391] like Fig.57As shown in (b), contact portions Csg, Crg, Css, Crs, Csd, Crd, C3vs, C2vs, and Cfd are formed. Specifically, through holes reaching the gate electrodes 323 and 333, the source regions 322 and 332, the drain regions 321 and 331, and the substrate 200 are formed by dry etching, a W film or the like is added to each through hole by CVD, and an excess W film is removed by CMP. A contact portion connected to the amplifier transistor 104 (not shown) is similarly formed in parallel therewith.

[0392] Thereafter, wirings D1, D1dd, D1vsl, D1vss, etc., to which the respective contacts Csg, Crg, Css, Csd, Crd, C3vs, C2vs, and Cfd are connected, are formed.

[0393] Thereafter, an upper layer wiring not shown is further formed, and the substrate on which the logic transistor and the wiring are formed is bonded, thereby completing the manufacturing process of the solid-state image sensor 100g.

[0394] (Comparative Example)

[0395] The solid-state image sensor includes a plurality of pixel transistors, such as a selection transistor, a reset transistor, and an amplifier transistor. These pixel transistors are manufactured and monolithic in the state of the entire wafer. In the solid-state image sensor of the comparative example, the threshold voltage of each pixel transistor may change due to changes in the processing conditions within the wafer. That is, in some cases, the threshold voltage of the pixel transistor changes between chips or within a chip of the solid-state image sensor.

[0396] In the solid-state image sensor 100g of the fifth embodiment, back gate electrodes 251s, 251r, and 251a for applying a reverse bias voltage are provided on the back side of the selection transistor 106, the reset transistor 105, and the amplifier transistor 104. Therefore, the threshold voltages of the selection transistor 106, the reset transistor 105, and the amplifier transistor 104 can be adjusted to suppress variations in the threshold voltages. Thus, noise is reduced.

[0397] Note that the reverse bias line BBL that applies voltage to each back gate electrode 251s, 251r, and 251a can be separated so that different voltages are applied to the back gate electrodes 251s, 251r, and 251a, respectively. Therefore, the controllability of the threshold voltages of the selection transistor 106, the reset transistor 105, and the amplifier transistor 104 is further improved.

[0398] In the solid-state image sensor 100g of the fifth embodiment, when a voltage is applied to the gate electrodes 323, 333, and 313 of the selection transistor 106, the reset transistor 105, and the amplifier transistor 104, a reverse bias is applied by the back gate electrodes 251s, 251r, and 251a. Therefore, the operation margin of the selection transistor 106, the reset transistor 105, and the amplifier transistor 104 can be widened, and the reliability is improved.

[0399] In the solid-state image sensor 100g of the fifth embodiment, the back gate electrode 251s reduces the on-resistance of the selection transistor 106, thereby advancing the timing of turning on the selection transistor 106. Therefore, the waiting time for the source line potential VSL to rise can be shortened.

[0400] In the solid-state image sensor 100g of the fifth embodiment, the distance between the back gate electrodes 251s, 251r and 251a and the main surface MSb of the substrate 300g is, for example, 10 nm or less. In addition, the thickness of the semiconductor region 301 of the substrate 300g is, for example, 100 nm or less. As described above, since the back gate electrodes 251s, 251r and 251a are at a distance sufficiently close to the selection transistor 106, the reset transistor 105 and the amplifier transistor 104, a reverse bias effect sufficient to adjust the threshold voltage can be obtained.

[0401] (Variant 1)

[0402] Next, we will refer to Fig.58 and Fig.59 A solid-state image sensor according to Modification 1 of the fifth embodiment will be described. The solid-state image sensor according to Modification 1 is different from that of the fifth embodiment described above in that it is manufactured by using an SOI substrate 300h.

[0403] Fig.58 and Fig.59 : is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to Modification 1 of the fifth embodiment of the present disclosure.

[0404] like Fig.58 As shown in (a), a silicon-on-insulator (SOI) substrate 300h is prepared as a second substrate. The SOI substrate 300h includes a support substrate 301hdl such as a P-type silicon substrate, a BOX layer 301box such as a silicon oxide layer on the support substrate 301hdl, and an active layer 301 such as a P-type silicon layer on the BOX layer 301box. The BOX layer 301box and the active layer 301act each have a thickness of, for example, about several tens of μm.

[0405] like Fig.58As shown in (b), the SOI substrate 300h is polished from the supporting substrate 301hdl side using a grinder G or the like so that the BOX layer 301box remains with a thickness of 10 nm or less.

[0406] like Fig.59 As shown in (a), the active layer 301act having a BOX layer 301box with a thickness of 10 nm or less is bonded to the insulating film 240 of the substrate 200 in such a manner that the BOX layer 301box side faces the insulating film 240 side.

[0407] like Fig.59 As shown in (b), the surface of the active layer 301act is polished by a grinder G or the like to a thickness of less than 100 nm.

[0408] Thereafter, by executing the same method as in the fifth embodiment described above Fig.56 and Fig.57 The solid-state image sensor of Modification Example 1 is manufactured by performing processes similar to those in the above-described process.

[0409] In the solid-state image sensor of Modification 1, the SOI substrate 300h is used. Therefore, the distance between the back gate electrodes 251s, 251r, and 251a and the active layer 301act which is a semiconductor region in which various pixel transistors are formed can be accurately controlled.

[0410] (Variant 2)

[0411] Next, we will refer to Fig.60 A solid-state image sensor according to Modification 2 of the fifth embodiment will be described. In the solid-state image sensor according to Modification 2, the back gate electrodes 252s and 252r and the like are formed by using a material different from that of the fifth embodiment described above.

[0412] Fig.60 : is a flowchart showing an example of a procedure of a manufacturing process of a solid-state image sensor according to Modification 2 of the fifth embodiment of the present disclosure.

[0413] like Fig.60 As shown in (a), a trench 252tr is formed in the surface layer of the insulating film 240 covering the semiconductor region 204 by etching or the like.

[0414] like Fig.60 As shown in (b) of FIG. 2 , for example, a metal film 252 such as a Cu film is formed on the insulating film 240 by, for example, a CVD method. At this time, the inside of the trench 252 tr is also filled with the metal film 252 .

[0415] like Fig.60As shown in (c), the metal film 252 on the insulating film 240 is removed by, for example, a CMP method. At this time, by leaving the metal film 252 in the trench 252tr, a back gate electrode 252s is formed at a position corresponding to the subsequent selection transistor, and a back gate electrode 252r is formed at a position corresponding to the subsequent reset transistor. At this time, a back gate electrode not shown is also formed at a position corresponding to the subsequent amplification transistor.

[0416] Thereafter, the solid-state image sensor of Modification 2 is manufactured by performing a process similar to that of the fifth embodiment or Modification 1 of the fifth embodiment described above.

[0417] In the solid-state image sensor of Modification 2, the back gate electrodes 252s, 252r, etc. are formed by using the metal film 252. Therefore, the back gate electrodes 252s, 252r, etc. having low resistance can be obtained.

[0418] [Sixth embodiment]

[0419] Fig.61 1 is a diagram showing an example of a schematic configuration of an imaging system 2 including the solid-state image sensor of the first to third and fifth embodiments and their modified examples. That is, any of the solid-state image sensors of the first to third embodiments and their modified examples described above can be installed in the imaging system 2. In the following description, the imaging system 2 equipped with the solid-state image sensor 100' of the first embodiment will be taken as an example.

[0420] The imaging system 2 is, for example, an imaging device such as a digital still camera or a video camera, or an electronic device such as a mobile terminal device (e.g., a smartphone or a tablet terminal). The imaging system 2 includes, for example, the solid-state image sensor 100' of the first embodiment, a DSP circuit 141, a frame memory 142, a display unit 143, a storage unit 144, an operation unit 145, and a power supply unit 146. In the imaging system 2, the solid-state image sensor 100', the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, the operation unit 145, and the power supply unit 146 are connected to each other via a bus 147.

[0421] The solid-state image sensor 100' outputs image data corresponding to incident light. The DSP circuit 141 is a signal processing circuit that processes image data as a signal output from the solid-state image sensor 100'. The frame memory 142 temporarily holds the image data processed by the DSP circuit 141 in units of frames. The display unit 143 includes, for example, a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays a moving image or a still image captured by the solid-state image sensor 100'. The storage unit 144 records the image data of the moving image or the still image captured by the solid-state image sensor 100' on a recording medium such as a semiconductor memory or a hard disk. The operation unit 145 issues operation instructions for various functions of the imaging system 2 according to the operation of the user. The power supply unit 146 appropriately supplies various power supplies as operation power supplies for the solid-state image sensor 100', the DSP circuit 141, the frame memory 142, the display unit 143, the storage unit 144, and the operation unit 145, and supplies them to these supply objects.

[0422] Next, the imaging process in the imaging system 2 will be described.

[0423] Fig.62 An example of a flowchart showing an imaging operation in the imaging system 2. The imaging system 2 receives the start of imaging by the user's operation of the operation unit 145 or the like (step S101). Then, the operation unit 145 sends an imaging instruction to the solid-state image sensor 100' (step S102). Upon receiving the imaging instruction, the system control circuit (refer to FIG. 103 ) of the solid-state image sensor 100' Figure 1 The system control circuit 36 ​​in the image processing unit 100 performs imaging by a predetermined imaging method (step S103).

[0424] The solid-state image sensor 100' outputs the image data obtained by imaging to the DSP circuit 141. Here, the image data is data for all pixels of the pixel signal generated based on the charge temporarily held in the floating diffusion FD. The DSP circuit 141 performs predetermined signal processing such as noise reduction processing based on the image data input from the solid-state image sensor 100' (step S104). The DSP circuit 141 retains the image data subjected to the predetermined signal processing in the frame memory 142, and the frame memory 142 stores the image data in the storage unit 144 (step S105). Thus, imaging in the imaging system 2 is performed.

[0425] Since the imaging system 2 is equipped with the miniaturized or high-definition solid-state image sensor 100 ′, a compact or high-definition imaging system 2 can be provided.

[0426] (Application Example 1)

[0427] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure is implemented as a device to be installed on any type of mobile body such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, a robot, etc.

[0428] Fig.63 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0429] The vehicle control system 12000 includes a plurality of electronic control units connected together via a communication network 12001. Fig.63 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0430] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a drive force generating device for generating a drive force of the vehicle such as an internal combustion engine or a drive motor, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0431] The main system control unit 12020 controls the operation of various devices installed to the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, or a fog light. In this case, a radio wave or a signal of various switches transmitted from a portable device instead of a key may be input to the main system control unit 12020. The main system control unit 12020 receives the input of the radio wave or the signal and controls the door lock device, the power window device, the light, etc. of the vehicle.

[0432] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. The vehicle exterior information detection unit 12030 can perform object detection processing such as a person, a car, an obstacle, a sign, text on the road, etc. or distance detection processing based on the received image.

[0433] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0434] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera that captures an image of the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver falls asleep in a sitting position.

[0435] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device based on the information inside and outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize the functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of vehicles, tracking driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, lane departure warning of vehicles, etc.

[0436] In addition, the microcomputer 12051 can perform coordinated control by controlling the driving force generating device, steering mechanism, braking device, etc. based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, so as to achieve automatic driving in which the vehicle travels autonomously without relying on the driver's operation.

[0437] In addition, the microcomputer 12051 can output a control instruction to the main system control unit 12020 based on the information outside the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlights according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030 to perform coordinated control to achieve glare prevention such as switching the high beam to the low beam.

[0438] The audio image output unit 12052 transmits at least one of a sound and an image output signal to an output device capable of visually or auditorily notifying the vehicle occupants or information outside the vehicle. Fig.63 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0439] Fig.64 is a diagram of an example of the installation position of the imaging unit 12031.

[0440] exist Fig.64 In the figure, vehicle 12100 includes imaging units 12101, 12102, 12103, 12104 and 12105 as imaging unit 12031.

[0441] Each of the imaging units 12101, 12102, 12103, 12104 and 12105 is disposed at a position such as the front of the vehicle 12100, the side mirror, the rear bumper, the rear door, the upper side of the windshield in the vehicle, etc. The imaging unit 12101 disposed in the front of the vehicle and the imaging unit 12105 disposed on the upper side of the windshield in the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed in the side mirror mainly obtain images on the side of the vehicle 12100. The imaging unit 12104 disposed in the rear bumper or the rear door mainly obtains images on the rear of the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used to detect front vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0442] also, Fig.64An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided in the front of the vehicle, the imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, and the imaging range 12114 represents the imaging range of the imaging unit 12104 provided in the rear bumper or the rear door. For example, the image data captured by the imaging units 12101 to 12104 are overlapped with each other, thereby obtaining a bird's-eye view image of the vehicle 12100 seen from above.

[0443] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of solid-state image sensors, or may be a solid-state image sensor having pixels for phase difference detection.

[0444] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 obtains the distance to each solid object within each imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100), thereby being able to extract, as the front vehicle, a solid object located on the driving route of the vehicle 12100, especially the closest solid object and traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can set the distance between vehicles that is previously ensured in front of the front vehicle, and can perform automatic braking control (including tracking travel stop control), automatic acceleration control (including tracking travel start control), etc. In this way, coordinated control such as automatic driving in which the vehicle travels autonomously without relying on the operation of the driver can be performed.

[0445] For example, based on the distance information obtained from the imaging units 12101 to 12104, by classifying the three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as electric poles, the microcomputer 12051 can extract three-dimensional object data about the three-dimensional objects, and automatically avoid obstacles using the extracted data. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to visually identify. Then, the microcomputer 12051 determines the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 can output a warning to the driver via the audio speaker 12061 and the display unit 12062 or perform forced deceleration or evasive steering via the drive system control unit 12010, thereby enabling driving assistance for collision avoidance.

[0446] At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian exists in the captured images of the imaging units 12101 to 12104. For example, the identification of the pedestrian is performed by extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points indicating the outline of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that the pedestrian exists in the captured images of the imaging units 12101 to 12104 and identifies the pedestrian, the audio image output unit 12052 controls the display unit 12062 to display overlapping quadrilateral contour lines to emphasize the identified pedestrian. In addition, the audio image output unit 12052 may control the display unit 12062 to display an icon indicating the pedestrian at a desired position, etc.

[0447] An example of a mobile vehicle control system to which the technology according to the present disclosure is applicable has been described above. In the above-mentioned configuration, the technology according to the present disclosure can be applied to the imaging unit 12031. Specifically, the solid-state image sensor according to the above-mentioned first to third embodiments and its modified examples can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with less noise can be obtained, and thus high-precision control using the captured image can be performed in the mobile vehicle control system.

[0448] (Application Example 2)

[0449] Fig.65 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology of the present disclosure can be applied.

[0450] Fig.65 The figure shows a state where an operator (doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 supporting the endoscope 11100, and a cart 11200 on which various instruments for endoscopic surgery are mounted.

[0451] The endoscope 11100 includes a lens barrel 11101 in which a region of a predetermined length from a distal end is inserted into a body cavity of a patient 11132, and a camera 11102 connected to a proximal end of the lens barrel 11101. In the example shown in the drawings, the endoscope 11100 formed as a so-called hard scope including a hard lens barrel 11101 is shown, but the endoscope 11100 may be formed as a so-called soft scope including a soft lens barrel.

[0452] The lens barrel 11101 is provided at its distal end with an opening portion into which an objective lens is fitted. The light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the distal end of the lens barrel through a light guide extending to the inside of the lens barrel 11101, and the light is emitted toward the observation object in the body cavity of the patient 11132 via the objective lens. In addition, the endoscope 11100 may be a straight-view mirror, an oblique-view mirror, or a side-view mirror.

[0453] Any of the optical systems and solid-state image sensors of the first to third embodiments and their modified examples is provided inside the camera 11102, and the reflected light (observation light) from the observation object is converged on the solid-state image sensor through the optical system. The observation light is photoelectrically converted by the solid-state image sensor, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image, is generated. The image signal is transmitted to the camera control unit (CCU) 11201 as RAW data.

[0454] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various types of image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0455] The display device 11202 displays an image based on an image signal on which image processing has been performed by the CCU 11201 through the control of the CCU 11201 .

[0456] For example, the light source device 11203 includes a light source such as a light emitting diode (LED) and supplies irradiation light for photographing a surgical site or the like to the endoscope 11100 .

[0457] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs instructions for changing the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100, and the like.

[0458] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for cauterization, incision, sealing of blood vessels, etc. of tissues. The pneumoperitoneum device 11206 injects gas into the body cavity via the pneumoperitoneum tube 11111 to expand the body cavity of the patient 11132 to ensure the field of view of the endoscope 11100 and the working space of the operator. The recorder 11207 is a device capable of recording various types of information related to the operation. The printer 11208 is a device capable of printing various types of information related to the operation in various forms such as text, images, graphics, etc.

[0459] In addition, the light source device 11203 that supplies the irradiation light for photographing the surgical site to the endoscope 11100 may include a white light source such as an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, the output intensity and output timing of each color (wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In addition, in this case, by emitting lasers from each RGB laser light source onto the observed object in a time-division manner and controlling the drive of the solid-state image sensor of the camera 11102 in synchronization with the emission timing, it is also possible to capture images corresponding to RGB in a time-division manner. According to this method, a color image can also be obtained without providing a color filter in the solid-state image sensor.

[0460] In addition, the drive of the light source device 11203 can be controlled so that the intensity of the light to be output is changed at predetermined intervals. By controlling the drive of the solid-state image sensor of the camera 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0461] In addition, the light source device 11203 can supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by using the wavelength dependence of light absorption in body tissue, by emitting light having a narrowband domain compared to the irradiation light (i.e., white light) during ordinary observation, so-called narrowband domain imaging is performed to photograph predetermined tissues such as blood vessels on the surface of the mucosa with high contrast. In addition, in special light observation, fluorescence imaging can be performed to obtain an image by emitting fluorescence generated by excitation light. In fluorescence imaging, for example, excitation light can be irradiated to body tissue to observe fluorescence from the body tissue (autofluorescence imaging), or a reagent such as indocyanine green (ICG) can be locally injected into the body tissue and excitation light corresponding to the fluorescence wavelength of the reagent can be emitted to obtain a fluorescence image. The light source device 11203 can supply narrowband domain light and / or excitation light corresponding to such special light observation.

[0462] Fig.66 It is shown Fig.65 A block diagram showing an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0463] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected by a transmission cable 11400 so that communication can be performed therebetween.

[0464] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light received from the distal end of the lens barrel 11101 is guided to the camera head 11102 and is incident on the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0465] The imaging unit 11402 is composed of a solid-state image sensor. The solid-state image sensor constituting the imaging unit 11402 may be one element (so-called single-board type) or may be a plurality of elements (so-called multi-board type). When the imaging unit 11402 is a multi-board type, for example, image signals corresponding to RGB are generated by each solid-state image sensor, and a color image can be obtained by synthesizing the image signals. In addition, the imaging unit 11402 may include a pair of solid-state image sensors for acquiring image signals for the right eye and the left eye corresponding to a three-dimensional (3D) display. By performing a 3D display, the operator 11131 can more accurately grasp the depth of the body tissue in the surgical site. In addition, when the imaging unit 11402 is a multi-board type, a plurality of lens units 11401 corresponding to each solid-state image sensor may be provided.

[0466] In addition, the imaging unit 11402 does not have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided just behind the objective lens inside the lens barrel 11101.

[0467] The driving unit 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis through the control of the camera control unit 11405. As a result, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0468] The communication unit 11404 includes a communication device for transmitting / receiving various types of information to / from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0469] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control unit 11405. The control signal includes information related to imaging conditions, for example, information specifying a frame rate of a captured image, information specifying an exposure value at the time of imaging, and / or information specifying a magnification and a focus of a captured image, etc.

[0470] In addition, imaging conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set based on the acquired image signal by the control section 11413 of the CCU 11201. In the latter case, a so-called automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated in the endoscope 11100.

[0471] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 11201 received via the communication unit 11404 .

[0472] The communication unit 11411 includes a communication device for transmitting / receiving various types of information to / from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

[0473] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted through electrical communication, optical communication, or the like.

[0474] The image processing unit 11412 performs various types of image processing on the image signal which is RAW data transmitted from the camera 11102 .

[0475] The control unit 11413 performs various types of control related to imaging of a surgical site, etc., by the endoscope 11100 and display of a captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0476] In addition, the control unit 11413 causes the display device 11202 to display a captured image of the surgical site, etc., based on the image signal that has been image-processed by the image processing unit 11412. In this case, the control unit 11413 can recognize various objects within the captured image by using various image recognition technologies. For example, the control unit 11413 detects the edge shape and / or color of an object contained in the captured image, thereby being able to recognize surgical instruments such as forceps, a specific living body part, bleeding, fog when the energy treatment instrument 11112 is used, and the like. When causing the display device 11202 to display the captured image, by using the recognition result, the control unit 11413 can cause the display device 11202 to overlap and display various types of surgical support information related to the image of the surgical site. The surgical support information is overlapped and displayed and presented to the operator 11131, whereby the burden of the operator 11131 can be reduced, and the operator 11131 can reliably perform surgery.

[0477] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 together is an electrical signal cable supporting communication of electrical signals, an optical fiber supporting optical communication, or a composite cable thereof.

[0478] Here, in the example shown in the drawing, wired communication is performed by using the transmission cable 11400 , but wireless communication may be performed between the camera 11102 and the CCU 11201 .

[0479] An example of an endoscopic surgical system to which the technology of the present disclosure is applicable has been described above. In the above configuration, the technology of the present disclosure can be appropriately applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology of the present disclosure to the imaging unit 11402, the imaging unit 11402 can be miniaturized or have high definition, so that a compact or high-definition endoscope 11100 can be provided.

[0480] [Seventh Implementation Plan]

[0481] In describing the seventh embodiment, terms are selected and reference numerals are given again from a different perspective than the above-described embodiments. Therefore, the components referred to by the following terms and reference numerals may be different from the components referred to by similar terms and reference numerals in the above-described embodiments.

[0482] (Functional Configuration of Imaging Device 1)

[0483] Fig.67 : is a block diagram illustrating an example of a functional configuration of an imaging device (imaging device 1 ) according to a seventh embodiment of the present disclosure.

[0484] Fig.67 The imaging device 1 includes, for example, an input unit 510A, a row driving unit 520, a timing control section 530, a pixel array unit 540, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B.

[0485] The pixels 541 are repeatedly arranged in an array in the pixel array unit 540. More specifically, a pixel sharing unit 539 including a plurality of pixels forms a repeating unit, and such a repeating unit is repeatedly arranged in an array in the row direction and the column direction. Note that in the present embodiment, for convenience, the row direction may be referred to as the H direction, and the column direction orthogonal to the row direction may be referred to as the V direction. Fig.67 In the example of FIG. 5 , one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (described later). Fig.72 ). The pixel sharing unit 539 is a pixel sharing circuit (described later). Fig.69210 in the pixel array unit). In other words, each of the four pixels (pixels 541A, 541B, 541C, and 541D) has a pixel circuit (pixel circuit 210 described later). By operating the pixel circuit in a time-division manner, the respective pixel signals of pixels 541A, 541B, 541C, and 541D are read out in sequence. Pixels 541A, 541B, 541C, and 541D are, for example, arranged in two rows × two columns. The pixel array unit 540 is provided with a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 together with the pixels 541A, 541B, 541C, and 541D. The row drive signal line 542 drives the pixel 541 included in each of the plurality of pixel sharing units 539 arranged side by side in the row direction in the pixel array unit 540. In the pixel sharing unit 539, each pixel arranged side by side in the row direction is driven. As will be referred to later Fig.70 As described in detail, the pixel sharing unit 539 is provided with a plurality of transistors. In order to drive each of the plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to a vertical signal line (column readout line) 543. Pixel signals are read out from the respective pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal line (column readout line) 543.

[0486] The row driving unit 520 includes, for example, a row address control section (in other words, a row decoder unit) that determines a row position for pixel driving and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0487] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit with the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539). The column signal processing unit 550 may have an amplifier circuit unit that amplifies a signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may have a noise processing unit. In the noise processing unit, for example, as a result of photoelectric conversion, a system noise level is removed from the signal read out from the pixel sharing unit 539.

[0488] The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read out from the pixel sharing unit 539 or the above-mentioned noise-processed analog signal is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted and the reference signal as the comparison object of the signal are compared. In the counter unit, the time until the comparison result in the comparator unit is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit, which performs control to scan the readout column.

[0489] The timing control section 530 supplies a signal for controlling timing to the row driving unit 520 and the column signal processing unit 550 based on the reference clock signal and the timing control signal input to the device.

[0490] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion (in other words, data obtained as an imaging operation in the imaging device 1). The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may include a processor unit.

[0491] An example of the signal processing performed by the image signal processing unit 560 is a tone curve correction process that increases grayscale in the case where the AD-converted imaging data is data obtained by imaging a dark subject, and reduces grayscale in the case where it is data obtained by imaging a bright subject. In this case, it is desired that the tone curve to be corrected based on the grayscale of the imaging data, and characteristic data of the tone curve regarding the kind of the tone curve is stored in advance in the data holding unit of the image signal processing unit 560.

[0492] The input unit 510A is used to input, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal, etc. The characteristic data is, for example, stored in a data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0493] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is used to acquire the signal input to the input terminal 511 to the inside of the imaging device 1. In the input amplitude changing unit 513, the amplitude of the signal acquired by the input circuit unit 512 is changed to an amplitude that can be easily used inside the imaging device 1. In the input data conversion circuit unit 514, the arrangement of the data string of the input data is changed. The input data conversion circuit unit 514 includes, for example, a serial-to-parallel conversion circuit. In the serial-to-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that in the input unit 510A, the input amplitude changing unit 513 and the input data conversion circuit unit 514 can be omitted. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on the power supplied to the imaging device 1 from the outside.

[0494] When the imaging device 1 is connected to an external storage device, the input unit 510A may be provided with a storage interface circuit for receiving data from the external storage device, such as a flash memory, SRAM, and DRAM.

[0495] The output unit 510B outputs the image data to the outside of the device. The image data is, for example, image data of an image captured by the imaging device 1 and image data signal-processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude changing unit 516, an output circuit unit 517, and an output terminal 518.

[0496] The output data conversion circuit unit 515 includes, for example, a parallel-to-serial conversion circuit, and the output data conversion circuit unit 515 converts a parallel signal used inside the imaging device 1 into a serial signal. The output amplitude changing unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude becomes easy to use for an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from the inside of the imaging device 1 to the outside of the device, and the output circuit unit 517 drives the wiring outside the imaging device 1 connected to the output terminal 518. At the output terminal 518, the data is output from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude changing unit 516 can be omitted.

[0497] When the imaging device 1 is connected to an external storage device, the output unit 510B may be provided with a storage interface circuit for outputting data to the external storage device, such as a flash memory, SRAM, and DRAM.

[0498] (Schematic Configuration of Imaging Device 1)

[0499] Fig.68and Fig.69 An example of a schematic configuration of the imaging device 1 is shown. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Fig.68 The planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300 is schematically shown, and Fig.69 The cross-sectional structure of the first substrate 100 , the second substrate 200 , and the third substrate 300 stacked on each other is schematically shown. Fig.69 Corresponding to along Fig.68 The imaging device 1 is an imaging device having a three-dimensional structure formed by bonding three substrates (a first substrate 100, a second substrate 200, and a third substrate 300) together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film surrounding the substrate is referred to as a wiring layer (100T, 200T, and 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200 and the third substrate 300 are stacked in this order, and along the stacking direction, the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T and the semiconductor layer 300S are sequentially arranged. The specific configuration of the first substrate 100, the second substrate 200 and the third substrate 300 will be described later. Fig.69 The arrow shown in indicates the direction of the light L incident on the imaging device 1. In the present embodiment, for the sake of convenience, in the following cross-sectional views, the light incident side in the imaging device 1 may be referred to as the "bottom", "lower side" and "below" and the side opposite to the light incident side may be referred to as the "top", "upper side" and "above". In addition, in the present embodiment, for the sake of convenience, with respect to the substrate provided with a semiconductor layer and a wiring layer, the surface on the wiring layer side may be referred to as the front side and the surface on the semiconductor layer side may be referred to as the back side. Note that the description of the present specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back side of the first substrate 100 having a photodiode.

[0500] The pixel array unit 540 and the pixel sharing unit 539 included in the pixel array unit 540 are configured by using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C and a pixel 541D included in the pixel sharing unit 539. Each of these pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 described later) included in the pixel sharing unit 539. The pixel circuit reads out the pixel signal transmitted from the photodiode of each pixel 541A, 541B, 541C and 541D via the transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 200 also has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also has a power supply line 544 extending along the row direction. The third substrate 300 has, for example, an input unit 510A, a row driving unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. For example, in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter, simply referred to as the stacking direction), the row driving unit 520 is provided in a region partially overlapping with the pixel array unit 540. More specifically, in the stacking direction, the row driving unit 520 is provided in a region overlapping with the vicinity of the end portion of the pixel array unit 540 in the H direction ( Fig.68 ). In the stacking direction, the column signal processing unit 550 is, for example, disposed in a region partially overlapping with the pixel array unit 540. More specifically, in the stacking direction, the column signal processing unit 550 is disposed in a region overlapping with the vicinity of the end portion in the V direction of the pixel array unit 540 ( Fig.68 ). Although not shown, the input unit 510A and the output unit 510B may be configured in a portion other than the third substrate 300, and may be configured in, for example, the second substrate 200. Alternatively, the input unit 510A and the output unit 510B may be provided on the back side (light incident side) of the first substrate 100. Note that the above-mentioned pixel circuit provided on the second substrate 200 may also be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit as another name. In this embodiment, the term "pixel circuit" is used.

[0501] The first substrate 100 and the second substrate 200 are connected to each other by, for example, through electrodes (described later) Fig.72The through electrodes 120E, 121E) are electrically connected. The second substrate 200 and the third substrate 300 are electrically connected to each other via, for example, contact portions 201, 202, 301 and 302. The second substrate 200 is provided with contact portions 201 and 202, and the third substrate 300 is provided with contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact area 201R provided with a plurality of contact portions 201 and a contact area 202R provided with a plurality of contact portions 202. The third substrate 300 has a contact area 301R provided with a plurality of contact portions 301 and a contact area 302R provided with a plurality of contact portions 302. The contact areas 201R and 301R are provided between the pixel array unit 540 and the row drive unit 520 in the stacking direction ( Fig.69 ). In other words, the contact regions 201R and 301R are provided in, for example, a region where the row drive unit 520 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in the vicinity of the region. The contact regions 201R and 301R are provided, for example, at the ends of the region in the H direction ( Fig.68 In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a part of the row driving unit 520 (specifically, an end portion of the row driving unit 520 in the H direction) ( Fig.68 and Fig.69 ). The contact portions 201 and 301 connect, for example, the row drive unit 520 provided in the third substrate 300 and the row drive line 542 provided in the second substrate 200. The contact portions 201 and 301 can, for example, connect the input unit 510A provided in the third substrate 300 with the power supply line 544 and the reference potential line (reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction ( Fig.69 ). In other words, the contact regions 202R and 302R are provided in a region where, for example, the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in the vicinity of the region. The contact regions 202R and 302R are provided, for example, at the ends of the region in the V direction ( Fig.68 In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a part of the column signal processing unit 550 (specifically, an end portion of the column signal processing unit 550 in the V direction) ( Fig.68 and Fig.69). For example, the contact portions 202 and 302 are used to connect a pixel signal (a signal corresponding to the amount of charge generated as a photoelectric conversion of a photodiode) output from each of the plurality of pixel sharing units 539 included in the pixel array unit 540 to a column signal processing unit 550 provided in the third substrate 300. The pixel signal is transmitted from the second substrate 200 to the third substrate 300.

[0502] Fig.69 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed by electrodes formed from a conductive material. The conductive material is formed, for example, of a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300, for example, by directly bonding wiring formed as electrodes to each other, thereby enabling input and / or output of signals from / to the second substrate 200 and the third substrate 300.

[0503] The electrical connection portion electrically connecting the second substrate 200 and the third substrate 300 may be disposed at a desired position. Fig.69 201R, 202R, 301R, and 302R described in the drawings, they may be provided in a region overlapping in the stacking direction with the pixel array unit 540. In addition, the electrical connection portion may be provided in a region not overlapping in the stacking direction with the pixel array unit 540. Specifically, the electrical connection portion may be provided in a region overlapping in the stacking direction with a peripheral portion arranged outside the pixel array unit 540.

[0504] The first substrate 100 and the second substrate 200 are provided with connection holes H1 and H2, for example. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 ( Fig.69 The connection holes H1 and H2 are arranged outside the pixel array unit 540 (or the portion overlapping with the pixel array unit 540) ( Fig.68). For example, the connection hole H1 is arranged outside the pixel array unit 540 in the H direction, and the connection hole H2 is arranged outside the pixel array unit 540 in the V direction. For example, the connection hole H1 reaches the input unit 510A provided in the third substrate 300, and the connection hole H2 reaches the output unit 510B provided in the third substrate 300. The connection holes H1 and H2 may be hollow, and at least a portion thereof may contain a conductive material. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input unit 510A and / or the output unit 510B. Alternatively, there is a configuration in which an electrode formed as the input unit 510A and / or the output unit 510B is connected to a conductive material provided in the connection holes H1 and H2. The conductive material provided in the connection holes H1 and H2 may be buried in a part or all of the connection holes H1 and H2, or the conductive material may be formed on the side walls of the connection holes H1 and H2.

[0505] Note that Fig.69 In the embodiment, the third substrate 300 is provided with an input unit 510A and an output unit 510B in structure, but is not limited thereto. For example, by sending a signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T, the input unit 510A and / or the output unit 510B may be provided in the second substrate 200. Similarly, by sending a signal of the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T, the input unit 510A and / or the output unit 510B may be provided in the first substrate 100.

[0506] Fig.70 : is an equivalent circuit diagram showing a configuration example of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Fig.70 , four pixels 541 of pixels 541A, 541B, 541C, and 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210 are shown. The pixel circuit 210 includes, for example, four transistors, specifically, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, by operating one pixel circuit 210 in a time-division manner, the pixel sharing unit 539 sequentially outputs the respective pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543. A mode in which one pixel circuit 210 is connected to a plurality of pixels 541 and the pixel signals of the plurality of pixels 541 are output in a time-division manner through the one pixel circuit 210 is described as "a plurality of pixels 541 share one pixel circuit 210."

[0507] Pixels 541A, 541B, 541C, and 541D have components that are common to each other. Hereinafter, in order to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, identification number 1 is added to the end of the reference numeral of the component of pixel 541A, identification number 2 is added to the end of the reference numeral of the component of pixel 541B, identification number 3 is added to the end of the reference numeral of the component of pixel 541C, and identification number 4 is added to the end of the reference numeral of the component of pixel 541D. In the case where it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals of the components of pixels 541A, 541B, 541C, and 541D are omitted.

[0508] The pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiode PD (PD1, PD2, PD3, PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (for example, ground). The photodiode PD performs photoelectric conversion on incident light and generates a charge corresponding to the amount of light received. The transfer transistor TR (transfer transistors TR1, TR2, TR3, TR4) is, for example, an n-type complementary metal oxide semiconductor (CMOS) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. The drive signal line is a plurality of row drive signal lines 542 (refer to Fig.67 ). The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is a charge-voltage conversion means that generates a voltage corresponding to the amount of charge.

[0509] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel sharing unit 539 are electrically connected to each other. And are electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539. The drain of the reset transistor RST is connected to the power line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539. The gate of the amplifier transistor AMP is connected to the floating diffusion FD, the drain of the amplifier transistor AMP is connected to the power line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one pixel sharing unit 539 .

[0510] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and as described later Fig.72 As shown, it is arranged to be Fig.72 The surface of the semiconductor layer 100S in the floating diffusion FD extends to a depth that reaches the PD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a signal having a voltage corresponding to the level of the charge held in the floating diffusion FD as a pixel signal. The amplifier transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplifier transistor AMP is connected to the load circuit unit (refer to Fig.67 ) together form a source follower. When the selection transistor SEL is turned on, the amplifier transistor AMP outputs the voltage of the floating diffusion portion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are, for example, n-type CMOS transistors.

[0511] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD. Generally, when an image is taken in a dark place, the pixel signal is small. If the capacitance (FD capacitance C) of the floating diffusion FD is large when the charge-voltage conversion is performed based on Q=CV, V becomes smaller when it is converted to voltage by the amplifier transistor AMP. On the other hand, in a bright place, the pixel signal becomes larger, so unless the FD capacitance C is large, the floating diffusion FD cannot receive the charge of the photodiode PD. In addition, the FD capacitance C needs to be large so that V does not become too large when it is converted to voltage by the amplifier transistor AMP (in other words, it becomes smaller). Based on these factors, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the entire FD capacitance C increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the entire FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an n-type CMOS transistor.

[0512] Note that a configuration in which the FD conversion gain switching transistor FDG is not provided is also possible. In this case, for example, the pixel circuit 210 includes three transistors, for example, an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one of the pixel transistors such as the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0513] The selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (refer to Fig.67 ). The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Note that although not shown, the number of pixels 541 that share one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0514] Fig.715 shows an example of a connection pattern of a plurality of pixel sharing units 539 and a vertical signal line 543. For example, four pixel sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. Fig.71 An example is shown in which each of the four groups has one pixel sharing unit 539 for the sake of simplicity of explanation, but each of the four groups may include a plurality of pixel sharing units 539. As described above, in the imaging device 1, a plurality of pixel sharing units 539 arranged in the column direction may be divided into groups including one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each of these groups, and pixel signals may be read out from the respective groups at the same time. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 juxtaposed in the column direction. At this time, pixel signals are sequentially read out in a time-division manner from the plurality of pixel sharing units 539 connected to one vertical signal line 543.

[0515] (Specific Configuration of Imaging Device 1)

[0516] Fig.72 An example of a cross-sectional configuration in a direction perpendicular to the main surfaces of the first substrate 100 , the second substrate 200 , and the third substrate 300 of the imaging device 1 is shown. Fig.72 It is an illustration that makes it easy to understand the positional relationship of the constituent elements, and may be different from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200 and the third substrate 300 are stacked in this order. The imaging device 1 also has a light receiving lens 401 on the back side (light incident side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. For example, a light receiving lens 401 is provided for each of the pixels 541A, 541B, 541C and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 has a pixel array unit 540 arranged in the central portion and a peripheral portion 540B arranged on the outside of the pixel array unit 540.

[0517] The first substrate 100 has an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T in order from the light receiving lens 401 side. The semiconductor layer 100S includes, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface (the surface on the wiring layer 100T side) and its vicinity, and has an n-type semiconductor region 114 in other regions (regions deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0518] Fig.73A An example of a planar configuration of the first substrate 100 is shown. Fig.73A The planar structure of the pixel separation unit 117, the photodiode PD, the floating diffusion unit FD, the VSS contact region 118, and the transfer transistor TR is mainly shown. Fig.73A Together with Fig.72 The structure of the first substrate 100 will be described below.

[0519] The floating diffusion FD and the VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD includes an n-type semiconductor region provided in the p-well layer 115. The respective floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other, for example, at the center of the pixel sharing unit 539 ( Fig.73A ). Although the details will be described later, the four floating diffusions (floating diffusions FD1, FD2, FD3, and FD4) included in the shared unit 539 are electrically connected to each other via electrical connection means (pad portion 120 described later) within the first substrate 100 (more specifically, within the wiring layer 100T). In addition, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical means (through electrode 120E described later). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG by electrical means.

[0520] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is arranged to be separated from the floating diffusion portion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion portion FD is arranged at one end in the V direction of each pixel, and the VSS contact region 118 is arranged at the other end ( Fig.73A ). The VSS contact region 118 includes, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Therefore, a reference potential is supplied to the semiconductor layer 100S.

[0521] The first substrate 100 is provided with a transfer transistor TR and a photodiode PD, a floating diffusion FD, and a VSS contact region 118. These photodiodes PD, floating diffusions FD, VSS contact regions 118, and transfer transistors TR are respectively provided in each of pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front side of the semiconductor layer 100S (the side opposite to the light incident surface side, that is, the second substrate 200 side). The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided in the n-type semiconductor region 114. By forming the transfer transistor TR by such a vertical transistor, the occurrence of poor transmission of the pixel signal can be reduced and the readout efficiency of the pixel signal can be improved.

[0522] The horizontal portion TGb of the transfer gate TG extends from a position facing the vertical portion TGa, for example, in the H direction toward the central portion of the pixel sharing unit 539 ( Fig.73A ). Therefore, the position of the through electrode (through electrode TGV described later) reaching the transfer gate TG in the H direction can be made close to the position of the through electrode (through electrodes 120E and 121E described later) connected to the floating diffusion FD and the VSS contact region 118 in the H direction. For example, the plurality of pixel sharing units 539 provided on the first substrate 100 have the same configuration as each other ( Fig.73A ).

[0523] The semiconductor layer 100S is provided with a pixel separation portion 117 that separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the surface of the semiconductor layer 100S). The pixel separation portion 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from each other, and has a planar shape ( Fig.73A and Fig.73B). The pixel separation unit 117, for example, electrically and optically separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation unit 117 includes, for example, a light shielding film 117A and an insulating film 117B. For the light shielding film 117A, for example, tungsten (W) or the like is used. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B contains, for example, silicon oxide (SiO). The pixel separation unit 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation unit 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, it may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S. The pixel separation unit 117 extends in the normal direction of the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0524] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is arranged between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 include, for example, a p-type semiconductor region.

[0525] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. The electric field induced by the fixed charge film 112 forms a first pinning region 113 of a hole accumulation layer on the interface on the light receiving surface (back side) side of the semiconductor layer 100S. Therefore, the generation of dark current due to the interface state on the light receiving surface side of the semiconductor layer 100S is suppressed. The fixed charge film 112 is formed, for example, of an insulating film having a negative fixed charge. Examples of the material of the insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0526] The light shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. The light shielding film 117A may be provided continuously with the light shielding film 117A forming the pixel separation portion 117. The light shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separation portion 117 in the semiconductor layer 100S. The insulating film 111 is provided to cover the light shielding film 117A. The insulating film 111 contains, for example, silicon oxide.

[0527] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in order from the semiconductor layer 100S side. The horizontal portion TGb of the transmission gate TG is provided in the wiring layer 100T, for example. The interlayer insulating film 119 is provided on the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is formed of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above, and is only required to be a configuration having wiring and an insulating film.

[0528] Fig.73B The configuration of the pad portions 120 and 121 and Fig.73A The pad portions 120 and 121 are provided in a selected region on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. For each pixel sharing unit 539, the pad portion 120 is arranged, for example, in the central portion ( Fig.73B The pad portion 120 is provided across the pixel separation portion 117 and is configured to overlap at least a portion of each of the floating diffusion portions FD1, FD2, FD3, and FD4 ( Fig.72 and Fig.73B ). Specifically, the pad portion 120 is formed in a region overlapping with at least a portion of each of the multiple floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of the shared pixel circuit 210 and at least a portion of the pixel separation portion 117 formed between the multiple photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the shared pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is used for connecting vias 120C that electrically connect the pad portion 120 to the floating diffusion portions FD1, FD2, FD3, and FD4. The connecting vias 120C are provided for each of the pixels 541A, 541B, 541C, and 541D. For example, by burying a portion of the pad portion 120 in the connecting via 120C, the pad portion 120 is electrically connected to the floating diffusion portions FD1, FD2, FD3, and FD4.

[0529] The pad portion 121 is used to connect a plurality of VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 adjacent in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of the other pixel sharing unit 539 are electrically connected through the pad portion 121. The pad portion 121 is provided, for example, to cross the pixel separation portion 117, and is configured to overlap at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region overlapping at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection via 121C is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, by burying a portion of the pad portion 121 in the connection via 121C, the pad portion 121 is electrically connected to the VSS contact region 118. For example, the pad portion 120 and the pad portion 121 of each of the plurality of pixel sharing units 539 juxtaposed in the V direction are arranged at substantially the same position in the H direction ( Fig.73B ).

[0530] By providing the pad portion 120, the wiring for connecting each floating diffusion portion FD to the pixel circuit 210 (for example, the gate electrode of the amplifier transistor AMP) can be reduced in the entire chip. Similarly, by providing the pad portion 121, the wiring for supplying the potential to each VSS contact area 118 can be reduced in the entire chip. Therefore, the area of ​​the entire chip can be reduced, electrical interference between wirings in miniaturized pixels can be suppressed, and / or costs can be reduced by reducing the number of components.

[0531] The pad portions 120 and 121 may be disposed at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120 and 121 may be disposed in the insulating region 212 of the wiring layer 100T or the semiconductor layer 200S. In the case of being disposed in the wiring layer 100T, the pad portions 120 and 121 may be directly in contact with the semiconductor layer 100S. Specifically, a configuration may be adopted in which the pad portions 120 and 121 are directly connected to at least a portion of each of the floating diffusion portions FD and / or the VSS contact region 118. In addition, a configuration may be adopted in which connection vias 120C and 121C are provided from each of the floating diffusion portions FD and / or the VSS contact region 118 connected to the pad portions 120 and 121 and the pad portions 120 and 121 are disposed at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0532] In particular, in the case where the pad portions 120 and 121 are provided in the wiring layer 100T, the wiring connected to the floating diffusion portion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S can be reduced. Therefore, in the second substrate 200 for forming the pixel circuit 210, the area of ​​the insulating region 212 for forming the through wiring for connecting the floating diffusion portion FD to the pixel circuit 210 can be reduced. Therefore, a large area of ​​the second substrate 200 for forming the pixel circuit 210 can be ensured. By ensuring the area for the pixel circuit 210, a large pixel transistor can be formed, which can contribute to improving image quality by reducing noise, etc.

[0533] In particular, when the FTI structure is used for the pixel separation portion 117, it is preferable to provide a floating diffusion portion FD and / or a VSS contact region 118 in each pixel 541. Therefore, by using the configuration of the pad portions 120 and 121, the wiring connecting the first substrate 100 and the second substrate 200 can be greatly reduced.

[0534] In addition, if Fig.73B As shown, for example, a pad portion 120 connected to a plurality of floating diffusion portions FD and a pad portion 121 connected to a plurality of VSS contact regions 118 are alternately arranged in a straight line in the V direction. In addition, the pad portions 120 and 121 are formed at a position surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusion portions FD. Therefore, in the first substrate 100 for forming a plurality of elements, elements other than the floating diffusion portions FD and the VSS contact regions 118 can be freely arranged, and the layout efficiency of the entire chip can be improved. In addition, the symmetry of the layout of the elements formed in each pixel sharing unit 539 is ensured, and the variation of the characteristics of each pixel 541 can be suppressed.

[0535] The pad portions 120 and 121 include, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. Preferably, the pad portions 120 and 121 are formed of a conductive material having high heat resistance, such as polysilicon, tungsten (W), titanium (Ti) and titanium nitride (TiN). Therefore, the pixel circuit 210 can be formed after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100. The reason will be described below. Note that in the following description, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 and the second substrate 200 together is referred to as the first manufacturing method.

[0536] Here, it is also conceivable to form the pixel circuit 210 on the second substrate 200 and then attach the second substrate 200 to the first substrate 100 (hereinafter referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are pre-formed on the surface of the first substrate 100 (the surface of the wiring layer 100T) and the surface of the second substrate 200 (the surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are attached together, at the same time, the electrodes for electrical connection formed on each of the surface of the first substrate 100 and the surface of the second substrate 200 are in contact with each other. Therefore, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, the configuration of the imaging device 1 using the second manufacturing method can be manufactured, for example, by using an appropriate process according to the respective configurations of the first substrate 100 and the second substrate 200, so that a high-quality, high-performance imaging device can be manufactured.

[0537] In the second manufacturing method, when the first substrate 100 and the second substrate 200 are attached together, an alignment error may occur due to the manufacturing equipment used for attachment. In addition, the first substrate 100 and the second substrate 200 have a size of, for example, about several tens of centimeters in diameter, and when the first substrate 100 and the second substrate 200 are attached together, expansion and contraction of the substrate may occur in the microscopic area of ​​each part of the first substrate 100 and the second substrate 200. The expansion and contraction of the substrate is caused by a slight shift in the timing of contact between the substrates. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrode for electrical connection formed on each of the surfaces of the first substrate 100 and the second substrate. In the second manufacturing method, it is preferred to take measures so that even if such an error occurs, the respective electrodes of the first substrate 100 and the second substrate 200 are in contact with each other. Specifically, in view of the above-mentioned error, at least one of the electrodes of the first substrate 100 and the second substrate 200 is increased, or preferably, both are increased. Therefore, when the second manufacturing method is used, for example, the size of the electrode formed on the surface of the first substrate 100 or the second substrate 200 (the size in the plane direction of the substrate) becomes larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 200 to the surface in the thickness direction.

[0538] On the other hand, by forming the pad portions 120 and 121 with a heat-resistant conductive material, the above-mentioned first manufacturing method can be used. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD and the transfer transistor TR, etc., the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together. At this time, the second substrate 200 is in a state where the pattern of the active element and wiring layer, etc. constituting the pixel circuit 210 is not formed. Since the second substrate 200 is in a state before patterning, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded, the bonding error does not cause an alignment error between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. Note that when forming a pattern on the second substrate, for example, in an exposure device for pattern formation, the pattern is formed while taking the pattern formed on the first substrate as an alignment object. For the above reasons, in manufacturing the imaging device 1 by the first manufacturing method, the error in the bonding position between the first substrate 100 and the second substrate 200 does not constitute a problem. For similar reasons, the error caused by the expansion and contraction of the substrate caused by the second manufacturing method does not constitute a problem in manufacturing the imaging device 1 by the first manufacturing method.

[0539] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this way, an active element is formed on the second substrate 200. Thereafter, the through electrodes 120E and 121E and the through electrode TGV ( Fig.72 ). When forming the through electrodes 120E, 121E and TGV, for example, by using reduced projection exposure of an exposure device, a pattern of the through electrodes is formed from above the second substrate 200. Because a reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error is only a fraction of the error of the above-mentioned second manufacturing method in the second substrate 200 (the inverse of the reduced exposure projection magnification). Therefore, by forming the imaging device 1 using the first manufacturing method, it is easy to align the various elements formed on the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured.

[0540] The imaging device 1 manufactured by using the first manufacturing method has different characteristics from the imaging device manufactured by the second manufacturing method. Specifically, in the imaging device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, 121E and TGV have a substantially constant thickness (dimension in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E and TGV have a tapered shape, they have a tapered shape with a constant inclination. In the imaging device 1 having such through electrodes 120E, 121E and TGV, the pixel 541 can be easily miniaturized.

[0541] Here, when the imaging device 1 is manufactured by the first manufacturing method, since the active element is formed on the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are attached together, the first substrate 100 is also affected by the heat treatment required to form the active element. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided on the first substrate 100. For example, for the pad portions 120 and 121, it is preferable to use a material having a higher melting point (i.e., higher heat resistance) than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad portions 120 and 121. Therefore, the imaging device 1 can be manufactured by using the above-mentioned first manufacturing method.

[0542] The passivation film 122 is provided on the entire surface of the semiconductor layer 100S to cover, for example, the pad portions 120 and 121 ( Fig.72). The passivation film 122 is formed of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 via the passivation film 122. The interlayer insulating film 123 is, for example, provided on the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is, for example, formed of a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface of the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is provided on the entire main surface of the first substrate 100. The bonding film 124 is, for example, formed of a silicon nitride film.

[0543] The light receiving lens 401 faces the semiconductor layer 100S ( Fig.72 ). The light receiving lens 401 is provided, for example, at a position facing the respective photodiodes PD of the pixels 541A, 541B, 541C, and 541D.

[0544] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in order from the first substrate 100 side. The semiconductor layer 200S is formed of a silicon substrate. In the semiconductor layer 200S, a well region 211 is provided in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210 configured for each pixel sharing unit 539. The pixel circuit 210 is, for example, provided on the front side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is attached to the first substrate 100 in such a manner that the back side (semiconductor layer 200S side) of the second substrate 200 faces the front side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is attached to the first substrate 100 front to back.

[0545] Figures 74-78 An example of a plane configuration of the second substrate 200 is schematically shown. Fig.74 The configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S is shown. Fig.75 The configurations of the wiring layer 200T (specifically, a first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and each portion of the first substrate 100 are schematically shown. Figures 76-78 200T. Figures 74-78 Together with Fig.72 The structure of the second substrate 200 is described together. Fig.74 and Fig.75In the figure, the outer shape of the photodiode PD (the boundary between the pixel separation section 117 and the photodiode PD) is indicated by a dotted line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 212 at the portion overlapping with the gate electrode of each transistor constituting the pixel circuit 210 is indicated by a dotted line. In the portion overlapping with the gate electrode of the amplifier transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213 and the boundary between the element isolation region 213 and the insulating region 212 are set on one side in the channel width direction.

[0546] The second substrate 200 is provided with an insulating region 212 for dividing the semiconductor layer 200S and an element isolation region 213 ( Fig.72 ). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E and 121E connected to the two pixel sharing units 539 of the two pixel circuits 210 and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) are provided ( Fig.75 ).

[0547] The insulating region 212 has a thickness substantially the same as that of the semiconductor layer 200S ( Fig.72 ). The semiconductor layer 200S is divided by an insulating region 212. The through electrodes 120E and 121E and the through electrode TGV are arranged in the insulating region 212. The insulating region 212 contains, for example, silicon oxide.

[0548] The through electrodes 120E and 121E are provided so as to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wirings (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described later) of the wiring layer 200T. The through electrodes 120E and 121E are provided so as to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends thereof are connected to the pad portions 120, 121 ( Fig.72 ). The through electrode 120E is used to electrically connect the pad portion 120 and the pixel circuit 210. That is, the through electrode 120E electrically connects the floating diffusion portion FD of the first substrate 100 to the pixel circuit 210 of the second substrate 200. The through electrode 121E is used to electrically connect the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact area 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0549] The through electrode TGV is provided so as to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring 200T. The through electrode TGV is provided so as to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and the lower end thereof is connected to the transmission gate TG ( Fig.72 Such a through electrode TGV is used to electrically connect the transfer gate TG (transfer gates TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, and 541D to the wiring (part of the row drive signal line 542, specifically, the later-described Fig.77 That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV, and a driving signal is transmitted to each transfer transistor TR (transmission transistors TR1, TR2, TR3 and TR4).

[0550] The insulating region 212 is a region for through-electrodes 120E and 121E and through-electrodes TGV provided to electrically connect the first substrate 100 and the second substrate 200 by being insulated from the semiconductor layer 200S. For example, in the insulating region 212 provided between two pixel circuits 210 (shared unit 539) adjacent to each other in the H direction, through-electrodes 120E, 121E and through-electrodes TGV (through-electrodes TGV1, TGV2, TGV3, and TGV4) connected to the two pixel circuits 210 are provided. The insulating region 212 is provided to extend in the V direction, for example ( Fig.74 and Fig.75 Here, by designing the configuration of the horizontal portion TGb of the transfer gate TG, the position of the through electrode TGV in the H direction is configured to be closer to the positions of the through electrodes 120E and 121E in the H direction than the position of the vertical portion TGa ( Fig.73A and Fig.75). For example, the through electrode TGV is arranged at substantially the same position as the through electrodes 120E and 121E in the H direction. Therefore, the through electrodes 120E and 121E and the through electrode TGV can be arranged together in the insulating region 212 extending along the V direction. As another configuration example, it is conceivable that the horizontal portion TGb is arranged only in the region overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, and, for example, the through electrode TGV is arranged in the approximate center of the H direction and the V direction of each pixel 541. At this time, the position of the through electrode TGV in the H direction deviates greatly from the position of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is arranged around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate them from the adjacent semiconductor layer 200S. In the case where the position of the through electrode TGV in the H direction is greatly separated from the position of the through electrodes 120E and 121E in the H direction, it is necessary to independently provide an insulating region 212 around each of the through electrodes 120E, 121E, and TGV. Therefore, the semiconductor layer 200S is finely divided. On the other hand, in a layout in which the through electrodes 120E and 121E and the through electrode TGV are arranged together in the insulating region 212 extending along the V direction, the size of the semiconductor layer 200S in the H direction can be increased. Therefore, a large area of ​​the semiconductor element formation region in the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased and noise can be suppressed.

[0551] As reference Fig.70 As described, the pixel sharing unit 539 has a structure in which each floating diffusion portion FD provided in a plurality of pixels 541 is electrically connected, and the plurality of pixels 541 share one pixel circuit 210. Then, the electrical connection between the floating diffusion portions FD is performed by the pad portion 120 provided on the first substrate 100 ( Fig.72 and Fig.73B ). The electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected via a through electrode 120E. As another structural example, it is conceivable that the electrical connection portion between the floating diffusion portions FD is provided on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusion portions FD1, FD2, FD3 and FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 insulated around these through electrodes is enlarged. On the other hand, in the structure in which the pad portion 120 is provided on the first substrate 100 ( Fig.72 and Fig.73B), the number of through electrodes can be reduced and the insulating region 212 can be reduced. Therefore, a large area of ​​the semiconductor element formation region in the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased and noise can be suppressed.

[0552] The element isolation region 213 is arranged on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (shallow trench isolation) structure. In the element isolation region 213, the semiconductor layer 200S is excavated in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is buried in the excavated portion. The insulating film contains, for example, silicon oxide. The element isolation region 213 provides element isolation between multiple transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep part of the semiconductor layer 200S).

[0553] Here, refer to Fig.73A , Fig.73B and Fig.74 , the difference between the outer shape of the pixel sharing unit 539 in the first substrate 100 (the outer shape in the plane direction of the substrate) and the outer shape of the pixel sharing unit 539 in the second substrate 200 will be described.

[0554] In the imaging device 1, the pixel sharing unit 539 is provided on both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided on the first substrate 100 and the outer shape of the pixel sharing unit 539 provided on the second substrate 200 are different from each other.

[0555] exist Fig.73A and Fig.73B , the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by alternating dot-dash lines, and the outer shape of the pixel sharing unit 539 is indicated by a bold line. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent thereto in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 includes four pixels 541 of two adjacent rows × two columns, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outer shape. In the pixel array unit 540, such pixel sharing units 539 are arranged adjacent to each other at two pixel pitches in the H direction (each pitch corresponds to two pixels 541) and two pixel pitches in the V direction (each pitch corresponds to two pixels 541).

[0556] exist Fig.74 and Fig.75, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by alternating long and short dashed lines, and the outer shape of the pixel sharing unit 539 is indicated by a bold line. For example, the outer shape of the pixel sharing unit 539 of the second substrate 200 is smaller than the pixel sharing unit 539 of the first substrate 100 in the H direction and larger than the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed with a size (area) corresponding to one pixel in the H direction and a size corresponding to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed with a size corresponding to pixels arranged in adjacent one row×four columns, and the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape.

[0557] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are sequentially arranged side by side in the V direction ( Fig.74 As described above, by setting the outer shape of each pixel circuit 210 to a substantially rectangular shape, the four transistors (select transistor SEL, amplifier transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) can be arranged in one direction ( Fig.74 Therefore, the drain of the amplifier transistor AMP and the drain of the reset transistor RST can be shared by one diffusion region (the diffusion region connected to the power line VDD). For example, the formation region of each pixel circuit 210 can also be set to a substantially square shape (refer to the later described Fig.87 ). In this case, two transistors are arranged in one direction, and it is difficult to share the drain of the amplifier transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by setting the formation area of ​​the pixel circuit 210 to a substantially rectangular shape, it is easy to arrange the four transistors closely to each other, and the formation area of ​​the pixel circuit 210 can be reduced. That is, the pixel can be miniaturized. In addition, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, the formation area of ​​the amplifier transistor AMP can be increased and noise can be suppressed.

[0558] For example, near the surface of the semiconductor layer 200S, in addition to the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided. The VSS contact region 218 is formed, for example, of a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. The VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG via the element isolation region 213 ( Fig.74 ).

[0559] Next, we will refer to Fig.73B and Fig.74 The positional relationship between the pixel sharing unit 539 disposed in the first substrate 100 and the pixel sharing unit 539 disposed in the second substrate 200 is described. For example, one pixel sharing unit 539 (e.g., Fig.73B ) is connected to one pixel sharing unit 539 (for example, Fig.74 For example, the other pixel sharing unit 539 (eg, Fig.73B ) is connected to the other pixel sharing unit 539 (for example, Fig.74 on the right side of the paper).

[0560] For example, in two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (configuration of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout in which the internal layout of the other pixel sharing unit 539 is reversed in the V direction and the H direction. The effect obtained by such a layout will be described below.

[0561] In the two pixel sharing units 539 arranged in the V direction of the first substrate 100, each pad portion 120 is arranged in the central portion of the outer shape of the pixel sharing unit 539, that is, in the central portion of the V direction and the H direction of the pixel sharing unit 539 ( Fig.73B). On the other hand, as described above, since the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape that is long in the V direction, for example, the amplifier transistor AMP connected to the pad portion 120 is arranged at a position shifted upward on the paper from the center of the pixel sharing unit 539 in the V direction. For example, when the internal layouts of two pixel sharing units 539 arranged in the H direction of the second substrate 200 are the same, the amplifier transistor AMP of one pixel sharing unit 539 is connected to the pad portion 120 (for example, Fig.73B The distance between the pad portion 120 of the pixel sharing unit 539 on the upper side of the paper is relatively short. However, the amplifying transistor AMP of another pixel sharing unit 539 and the pad portion 120 (for example, Fig.73B The distance between the pad portion 120 of the pixel sharing unit 539 on the lower side of the paper is long. Therefore, the area of ​​the wiring required to connect the amplifier transistor AMP and the pad portion 120 is large, and the wiring layout of the pixel sharing unit 539 may be complicated. This factor may affect the miniaturization of the imaging device 1.

[0562] On the other hand, in the two pixel sharing units 539 arranged in the H direction of the second substrate 200, by reversing each other's internal layout at least in the V direction, the distance between the amplifier transistor AMP and the pad portion 120 of both of the two pixel sharing units 539 can be shortened. Therefore, compared with a configuration in which the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same, the imaging device 1 can be easily miniaturized. Note that although the planar layout of each of the plurality of pixel sharing units 539 of the second substrate 200 is Fig.74 The range shown is symmetrical, but when including the following Fig.75 When the layout of the first wiring layer W1 is shown, the plane layout is asymmetric.

[0563] In addition, it is preferable that the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are reversed to each other in the H direction. The reason for this will be described below. Fig.75 As shown, two pixel sharing units 539 arranged in the H direction of the second substrate 200 are respectively connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are arranged in the central portion of the H direction of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged in the H direction). Therefore, by making the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 also reverse to each other in the H direction, the distance between each of the plurality of pixel sharing units 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, the imaging device 1 can be more easily miniaturized.

[0564] In addition, the position of the outline of the pixel sharing unit 539 of the second substrate 200 does not necessarily have to be aligned with the position of any outline of the pixel sharing unit 539 of the first substrate 100. For example, one pixel sharing unit 539 of two pixel sharing units 539 arranged in the H direction of the second substrate 200 (e.g., Fig.75 The left side of the paper in the V direction (for example, Fig.75 The outline of the pixel sharing unit 539 (for example, the upper side of the paper in FIG. 1 ) is configured on the first substrate 100 corresponding to the pixel sharing unit 539 (for example, Fig.73B In addition, the other pixel sharing unit 539 of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, Fig.75 on the right side of the paper), the other side in the V direction (for example, Fig.75 The outline of the pixel sharing unit 539 (eg, the lower side of the paper in FIG. 1 ) is configured on the first substrate 100 corresponding to the pixel sharing unit 539 (eg, Fig.73B By arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 side by side in this way, the distance between the amplifier transistor AMP and the pad portion 120 can be shortened. Therefore, the imaging device 1 can be easily miniaturized.

[0565] In addition, the positions of the contours of the plurality of pixel sharing units 539 of the second substrate 200 do not necessarily have to be aligned with each other. For example, two pixel sharing units 539 arranged in the H direction of the second substrate 200 are configured so that the positions of the contours thereof in the V direction are shifted. Therefore, the distance between the amplifier transistor AMP and the pad portion 120 can be shortened. Therefore, the imaging device 1 can be easily miniaturized.

[0566] Reference Fig.73B and Fig.75 The pixel sharing unit 539 in the pixel array unit 540 is described as being repeatedly arranged. The pixel sharing unit 539 of the first substrate 100 has a size of two pixels 541 in the H direction and a size of two pixels 541 in the V direction ( Fig.73B). For example, in the pixel array unit 540 of the first substrate 100, the pixel sharing units 539 having a size corresponding to the four pixels 541 are adjacently and repeatedly arranged at two pixel pitches in the H direction (each pitch corresponds to two pixels 541) and two pixel pitches in the V direction (each pitch corresponds to two pixels 541). Alternatively, the pixel array unit 540 of the first substrate 100 may be provided with pairs of pixel sharing units 539, wherein every two pixel sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array unit 540 of the first substrate 100, for example, the pairs of pixel sharing units 539 are adjacently and repeatedly arranged at two pixel pitches in the H direction (each pitch corresponds to two pixels 541) and four pixel pitches in the V direction (each pitch corresponds to four pixels 541). The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( Fig.75 ). For example, the pixel array unit 540 of the second substrate 200 is provided with a pair of pixel sharing units 539, which include two pixel sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and are arranged shifted in the V direction. In the pixel array unit 540 of the second substrate 200, for example, such a pair of pixel sharing units 539 is arranged adjacently and without gaps at two pixel pitches in the H direction (each pitch corresponds to two pixels 541) and four pixel pitches in the V direction (each pitch corresponds to four pixels 541). Therefore, by such repeated configuration of the pixel sharing units 539, the pixel sharing units 539 can be configured without any gaps. Therefore, the imaging device 1 can be easily miniaturized.

[0567] The amplifier transistor AMP preferably has a three-dimensional structure such as a Fin type ( Fig.72 ). Therefore, the size of the effective gate width becomes larger and noise can be suppressed. The selection transistor SEL, the reset transistor RST and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplifier transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0568] The wiring layer 200T includes, for example, a passivation film 221', an interlayer insulating film 222', and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221', for example, contacts the surface of the semiconductor layer 200S and covers the entire surface of the semiconductor layer 200S. The passivation film 221' covers the respective gate electrodes of the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222' is disposed between the passivation film 221' and the third substrate 300. A plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4) are separated by the interlayer insulating film 222'. The interlayer insulating film 222' contains, for example, silicon oxide.

[0569] The wiring layer 200T is provided with, for example, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202 in sequence from the semiconductor layer 200S side. The interlayer insulating film 222' is provided with a plurality of connection portions for connecting the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to its lower layer. The connection portion is a portion in which a conductive material is buried in a connection hole provided in the interlayer insulating film 222'. For example, the interlayer insulating film 222' is provided with a connection portion 218V connecting the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture of the connection portion that connects the elements of the second substrate 200 to each other is different from the aperture of the through electrodes 120E and 121E and the through electrode TGV. Specifically, it is preferred that the aperture of the connection hole that connects the elements of the second substrate 200 to each other is smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV. The reason will be described below. The depth of the connection portion (connection portion 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E and 121E and the through electrode TGV. Therefore, compared with the through electrodes 120E and 121E and the through electrode TGV, the connection portion allows the connection hole to be easily filled with a conductive material. By making the aperture of the connection portion smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV, the imaging device 1 can be easily miniaturized.

[0570] For example, the first wiring layer W1 connects the through electrode 120E, the gate of the amplifier transistor AMP, and the source of the FD conversion gain switching transistor FDG (specifically, the connection hole reaches the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects, for example, the through electrode 121E and the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S.

[0571] Next, we will refer to Figures 76-78 The planar structure of the wiring layer 200T will be described. Fig.76 An example of a planar configuration of the first wiring layer W1 and the second wiring layer W2 is shown. Fig.77 An example of a planar configuration of the second wiring layer W2 and the third wiring layer W3 is shown. Fig.78 An example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0572] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction). Fig.77 ). These wirings correspond to the reference Fig.70 The multiple row drive signal lines 542 are illustrated. Wiring TRG1, TRG2, TRG3 and TRG4 are used to send drive signals to transmission gates TG1, TG2, TG3 and TG4, respectively. Wiring TRG1, TRG2, TRG3 and TRG4 are connected to transmission gates TG1, TG2, TG3 and TG4 via the second wiring layer W2, the first wiring layer W1 and the through-electrode 120E, respectively. Wiring SELL is used to send a drive signal to the gate of the selection transistor SEL, wiring RSTL is used to send a drive signal to the gate of the reset transistor RST, and wiring FDGL is used to send a drive signal to the gate of the FD conversion gain switching transistor FDG. Wiring SELL, RSTL and FDGL are connected to the gates of the selection transistor SEL, the reset transistor RST and the FD conversion gain switching transistor FDG, respectively, via the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0573] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 ( Fig.78 ). The power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion 218V. In addition, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and the connection portion.

[0574] The contact portions 201 and 202 may be disposed at positions overlapping with the pixel array unit 540 in a plan view (eg, Fig.69), or may be provided on the peripheral portion 540B outside the pixel array unit 540 (for example, Fig.72 ). The contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T side). The contact portions 201 and 202 are formed of, for example, a metal such as Cu (copper) and Al (aluminum). The contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the third substrate 300 side). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for attaching the second substrate 200 and the third substrate 300 to each other.

[0575] Fig.72 2 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. The peripheral circuit may include a portion of the row driving unit 520 or a portion of the column signal processing unit 550, etc. Fig.69 As shown, when the peripheral loop is not disposed in the peripheral portion 540B of the second substrate 200 , the connection holes H1 and H2 may be disposed near the pixel array unit 540 .

[0576] The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in sequence from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is arranged on the second substrate 200 side. The semiconductor layer 300S is formed of a silicon substrate. A circuit is arranged on a part of the front side of the semiconductor layer 300S. Specifically, on a part of the front side of the semiconductor layer 300S, for example, at least a part of the input unit 510A, the row drive unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, or the output unit 510B is arranged. The wiring layer 300T arranged between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. The contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface on the second substrate 200 side), and the contact portion 301 contacts the contact portion 201 of the second substrate 200, and the contact portion 302 contacts the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to the circuit formed in the semiconductor layer 300S (for example, at least one of the input unit 510A, the row driving unit 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, or the output unit 510B). The contact portions 301 and 302 are formed of, for example, a metal such as Cu (copper) and Al (aluminum). For example, the external terminal terminal TA is connected to the input unit 510A via the connection hole H1, and the external terminal TB is connected to the output unit 510B via the connection hole H2.

[0577] Here, features of the imaging device 1 will be described.

[0578] Generally, an imaging device mainly includes a photodiode and a pixel circuit. Here, if the area of ​​the photodiode is increased, the charge generated as a result of photoelectric conversion increases, and therefore, the signal-to-noise ratio (S / N ratio) of the pixel signal improves, and the imaging device can output better image data (image information). On the other hand, if the size of the transistor included in the pixel circuit (particularly the size of the amplifying transistor) is increased, the noise generated in the pixel circuit is reduced, and therefore, the S / N ratio of the imaging signal improves, and the imaging device can output better image data (image information).

[0579] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, it is conceivable that the size of the transistor provided in the pixel circuit becomes smaller. In addition, if the size of the transistor provided in the pixel circuit is increased, it is conceivable that the area of ​​the photodiode becomes smaller.

[0580] In order to solve these problems, for example, the imaging device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is configured by overlapping the photodiode PD. Therefore, it is possible to make the area of ​​the photodiode PD as large as possible and to make the size of the transistor provided in the pixel circuit 210 as large as possible within the limited area of ​​the semiconductor substrate. Therefore, the S / N ratio of the pixel signal can be improved, and the imaging device 1 can output better image data (image information).

[0581] When a structure is implemented in which a plurality of pixels 541 share one pixel circuit 210 and the pixel circuit 210 is configured by overlapping with the photodiode PD, a plurality of wirings extend from the respective floating diffusions FD of the plurality of pixels 541 to be connected to the one pixel circuit 210. In order to ensure a large area of ​​the semiconductor substrate 200 for forming the pixel circuit 210, for example, a connection wiring that interconnects and integrates a plurality of extension wirings into one may be formed. Similarly, for a plurality of wirings extending from the VSS contact region 118, a connection wiring that interconnects and integrates a plurality of extension wirings into one may be formed.

[0582] For example, if a connection wiring interconnecting a plurality of wirings extending from respective floating diffusions FD of a plurality of pixels 541 is formed on the semiconductor substrate 200 on which the pixel circuit 210 is formed, it is conceivable that an area for forming the transistor included in the pixel circuit 210 becomes smaller. Similarly, if a connection wiring interconnecting a plurality of wirings extending from respective VSS contact regions 118 of a plurality of pixels 541 and integrated into one is formed on the semiconductor substrate 200 on which the pixel circuit 210 is formed, it is conceivable that an area for forming the transistor included in the pixel circuit 210 becomes smaller.

[0583] In order to solve these problems, for example, in the imaging device 1 of the present embodiment, the following structure can be set up, in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is configured by overlapping with the photodiode PD, wherein a connection wiring that interconnects and integrates the respective floating diffusion portions FD of the plurality of pixels 541 into one and a connection wiring that interconnects and integrates the respective VSS contact regions 118 provided in the plurality of pixels 541 into one are provided on the first substrate 100.

[0584] Here, if the above-mentioned second manufacturing method is used as a manufacturing method for providing connection wirings that interconnect and integrate the respective floating diffusions FD of a plurality of pixels 541 into one and connection wirings that interconnect and integrate the respective VSS contact regions 118 of a plurality of pixels 541 into one in the first substrate 100, for example, manufacturing can be performed using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured. In addition, the connection wirings of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, in the case of using the above-mentioned second manufacturing method, an electrode connected to the floating diffusion FD and an electrode connected to the VSS contact region 118 are respectively provided on the surface of the first substrate 100 and the surface of the second substrate 200, which become the bonding interface between the first substrate 100 and the second substrate 200. In addition, it is preferable to expand the electrodes formed on the surfaces of the first substrate 100 and the second substrate 200 so that when the two substrates are bonded together, even if the electrodes provided on the surfaces of the two substrates are displaced, the electrodes formed on the surfaces of the two substrates are in contact with each other. In this case, it is conceivable that it may be difficult to arrange the above-mentioned electrodes in the limited area of ​​each pixel provided in the imaging device 1 .

[0585] In order to solve the problem that a large electrode is required at the bonding interface between the first substrate 100 and the second substrate 200, for example, as a manufacturing method of the imaging device 1 of the present embodiment (in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is configured by overlapping with the photodiode PD), the above-mentioned first manufacturing method can be used. Therefore, the elements formed on the first substrate 100 and the second substrate 200 can be easily aligned with each other, and an imaging device with high quality and high performance can be manufactured. In addition, an inherent structure generated by using this manufacturing method can be set. That is, the following structure is set up, in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in sequence. In other words, the first substrate 100 and the second substrate 200 are stacked face to face, and through electrodes 120E and 121E are provided which penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front side of the semiconductor layer 200S of the second substrate 200 to reach the front side of the semiconductor layer 100S of the first substrate 100.

[0586] In a structure in which connecting wirings that interconnect and integrate respective floating diffusion portions FD of a plurality of pixels 541 into one and connecting wirings that interconnect and integrate respective VSS contact areas 118 of a plurality of pixels 541 into one are arranged on a first substrate 100, if such a structure and a second substrate 200 are stacked using a first manufacturing method and a pixel circuit 210 is formed on the second substrate 200, there is a possibility that heat treatment required to form active elements arranged on the pixel circuit 210 affects the above-mentioned connecting wirings formed on the first substrate 100.

[0587] Therefore, in order to solve the above-mentioned problem that the heat treatment when forming the active element affects the connection wiring, in the imaging device 1 of the present embodiment, it is desirable to use a conductive material having high heat resistance for the connection wiring that interconnects and integrates the respective floating diffusion portions FD of the plurality of pixels 541 into one and the connection wiring that interconnects and integrates the respective VSS contact regions 118 of the plurality of pixels 541 into one. Specifically, as the conductive material having high heat resistance, a material having a higher melting point than at least a part of the wiring material contained in the wiring layer 200T of the second substrate 200 can be used.

[0588] As described above, for example, the imaging device 1 of the present embodiment has (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face to face (specifically, the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in sequence), (2) a structure in which through electrodes 120E and 121E are provided which penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front side of the semiconductor layer 200S of the second substrate 200 and reach the front of the semiconductor layer 100S of the first substrate 100, and (3) a structure in which the connecting wiring that interconnects and integrates the respective floating diffusion portions FD provided in the plurality of pixels 541 into one and the connecting wiring that interconnects and integrates the respective VSS contact regions 118 provided in the plurality of pixels 541 into one are formed of a highly heat-resistant conductive material. Therefore, without providing a large electrode at the interface between the first substrate 100 and the second substrate 200, the first substrate 100 can be provided with a connecting wiring that interconnects and integrates the respective floating diffusion portions FD provided in the plurality of pixels 541 into one, and a connecting wiring that interconnects and integrates the respective VSS contact areas 118 provided in the plurality of pixels 541 into one.

[0589] (Operation of Imaging Device 1)

[0590] Next, we will refer to Fig.79 and Fig.80 The operation of the imaging device 1 will be described. Fig.79 and Fig.80 This is done by adding arrows representing the paths of each signal to Fig.69 In Fig.79 In FIG. 1 , the paths of input signals input from the outside to the imaging device 1 and the power supply potential and the reference potential are indicated by arrows. Fig.80, the signal path of the pixel signal output from the imaging device 1 to the outside is indicated by an arrow. For example, the input signal (e.g., pixel clock and synchronization signal) input to the imaging device 1 via the input unit 510A is transmitted to the row driving unit 520 of the third substrate 300, and a row driving signal is created in the row driving unit 520. The row driving signal is sent to the second substrate 200 via the contacts 301 and 201. In addition, the row driving signal reaches the respective pixel sharing units 539 of the pixel array unit 540 via the row driving signal line 542 within the wiring layer 200T. Among the row driving signals that have reached the pixel sharing unit 539 of the second substrate 200, the driving signal other than the transmission gate TG is input to the pixel circuit 210, and the respective transistors included in the pixel circuit 210 are driven. The driving signal for the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and drives the pixels 541A, 541B, 541C, and 541D ( Fig.79 ). In addition, the power supply potential and the reference potential supplied from the outside of the imaging device 1 to the input unit 510A (input terminal 511) of the third substrate 300 are transmitted to the second substrate 200 via the contacts 301 and 201, and are supplied to the respective pixel circuits 210 of the pixel sharing unit 539 via the wiring within the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through-electrode 121E. On the other hand, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 200 in each pixel sharing unit 539 via the through-electrode 120E. A pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contacts 202 and 302. The pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300 and then output to the outside via the output unit 510B.

[0591] [Effect]

[0592] In the present embodiment, pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and pixel circuit 210 are arranged on different substrates (first substrate 100 and second substrate 200). Therefore, compared with the case where pixels 541A, 541B, 541C, 541C, and 541D and pixel circuit 210 are formed on the same substrate, the area of ​​pixels 541A, 541B, 541C, and 541D and pixel circuit 210 can be expanded. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased and the noise of transistors of pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information). In addition, the imaging device 1 can be miniaturized (in other words, the pixel size can be reduced and the size of the imaging device 1 can be reduced). The imaging device 1 can increase the number of pixels per unit area by reducing the pixel size, and can output high-quality images.

[0593] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other by through electrodes 120E and 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes to each other, or a method of connecting by wiring (e.g., through silicon via (TSV)) penetrating the semiconductor layer can also be considered. Compared with this method, by providing the through electrodes 120E and 121E in the insulating region 212, the area for connecting the first substrate 100 and the second substrate 200 can be reduced. Therefore, the pixel size can be reduced, and the size of the imaging device 1 can be further reduced. In addition, the resolution can be further improved by further minimizing the area of ​​each pixel. When it is not necessary to reduce the chip size, the formation area of ​​the pixels 541A, 541B, 541C and 541D and the pixel circuit 210 can be enlarged. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased and the noise of the transistors provided in the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging device 1 can output better pixel data (image information).

[0594] In addition, in the imaging device 1, the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are provided on substrates different from each other (the second substrate 200 and the third substrate 300). Therefore, compared with the case where the pixel circuit 210 and the column signal processing unit 550 and the image signal processing unit 560 are formed on the same substrate, the area of ​​the pixel circuit 210 and the area of ​​the column signal processing unit 550 and the image signal processing unit 560 can be expanded. Therefore, the noise generated in the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be mounted in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0595] In addition, in the imaging device 1, the pixel array unit 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing unit 550 and the image signal processing unit 560 are provided on the third substrate 300. In addition, the contact portions 201, 202, 301 and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array unit 540. Therefore, the contact portions 201, 202, 301 and 302 can be freely laid out without interference of the layout of various wirings provided in the pixel array. Therefore, the contact portions 201, 202, 301 and 302 can be used for electrical connection between the second substrate 200 and the third substrate 300. By using the contact portions 201, 202, 301 and 302, for example, the column signal processing unit 550 and the image signal processing unit 560 have a high degree of freedom in layout. Therefore, the noise generated in the column signal processing unit 550 can be reduced, and an advanced image processing circuit can be carried in the image signal processing unit 560. Therefore, the signal-to-noise ratio of the pixel signal improves, and the imaging device 1 can output better pixel data (image information).

[0596] In addition, in the imaging device 1, the pixel separation section 117 penetrates the semiconductor layer 100S. Therefore, even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is reduced due to the miniaturization of the area of ​​each pixel, color mixing between the pixels 541A, 541B, 541C, and 541D can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0597] In addition, in the imaging device 1, the pixel circuit 210 is provided for each pixel sharing unit 539. Therefore, compared with the case where the pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C, and 541D, the formation area of ​​the transistors (amplifier transistor AMP, reset transistor RST, selection transistor SEL, FD conversion gain switching transistor FDG) constituting the pixel circuit 210 ca...

Claims

1. A solid-state image sensor, comprising: a first semiconductor substrate having a photoelectric conversion element; and a second semiconductor substrate facing the first semiconductor substrate via an insulating film, The second semiconductor substrate has an amplifier transistor on a first main surface for amplifying an electrical signal output from the photoelectric conversion element, and has a low resistance region with a lower resistance than that of the second semiconductor substrate on a second main surface opposite to the first main surface, and is grounded via the low resistance region. In the stacking direction of the first semiconductor substrate and the second semiconductor substrate, the amplifying transistor and the low resistance region are separated by other regions of the second semiconductor substrate.

2. The solid-state image sensor according to claim 1, wherein The second semiconductor substrate has a certain conductivity type, and The low resistance region contains impurities at a higher concentration than other regions of the second semiconductor substrate.

3. The solid-state image sensor according to claim 1 or 2, further comprising A contact portion extending from the low resistance region of the second semiconductor substrate to the first semiconductor substrate side.

4. The solid-state image sensor according to claim 1 or 2, further comprising A contact portion extends from the low resistance region of the second semiconductor substrate to an opposite side of the first semiconductor substrate.

5. The solid-state image sensor according to claim 1 or 2, wherein The second semiconductor substrate is arranged on the first semiconductor substrate such that the second main surface faces the first semiconductor substrate.

6. The solid-state image sensor according to claim 5, further comprising A contact portion connects the low resistance region of the second semiconductor substrate and the first semiconductor substrate.

7. The solid-state image sensor according to claim 5, wherein The region of the second semiconductor substrate has an extension portion extending toward an outer side of the second semiconductor substrate in a direction along the second semiconductor substrate.

8. The solid-state image sensor according to claim 7, wherein The extension portion has a third main surface facing the same side as the first main surface of the second semiconductor substrate, and The solid-state image sensor further includes a contact portion having one end connected to the third main surface of the extending portion and the other end connected to ground.

9. The solid-state image sensor according to claim 7, further comprising A contact portion passes through the extension portion, has one end connected to the first semiconductor substrate and has the other end grounded.

10. The solid-state image sensor according to claim 7, further comprising A contact portion having one end connected to a side surface of the extension portion and the other end connected to ground.

11. A solid-state image sensor comprising: a first semiconductor substrate having a photoelectric conversion element; and a second semiconductor substrate facing the first semiconductor substrate via an insulating film, The second semiconductor substrate comprises: a pixel transistor on the first main surface that processes an electrical signal output from the photoelectric conversion element; and an electrode to which a predetermined voltage is applied, the electrode being provided near a second main surface opposite to the first main surface and at a position corresponding to a gate electrode of the pixel transistor, The distance from the second main surface of the second semiconductor substrate to the electrode is less than 10 nm.

12. The solid-state image sensor according to claim 11, further comprising The predetermined voltage is applied to the wiring of the electrode.

13. The solid-state image sensor according to claim 11 or 12, wherein The electrode is a back gate electrode that applies a reverse bias to the pixel transistor by applying the predetermined voltage.

14. The solid-state image sensor according to claim 11 or 12, wherein The pixel transistor comprises: an amplifying transistor that amplifies an electrical signal output from the photoelectric conversion element; a selection transistor that controls transmission of an electrical signal amplified by the amplification transistor; and a reset transistor that resets the gate potential of the amplifying transistor to a power supply potential, and The electrode comprises: a first electrode disposed at a position corresponding to a gate electrode of the amplifying transistor; a second electrode disposed at a position corresponding to a gate electrode of the selection transistor; and A third electrode is arranged at a position corresponding to the gate electrode of the reset transistor.

15. The solid-state image sensor according to claim 14, wherein The first electrode applies a reverse bias to the amplifying transistor to control the threshold voltage of the amplifying transistor by applying a predetermined voltage different from the threshold voltage of the amplifying transistor, The second electrode applies a reverse bias to the selection transistor to control the threshold voltage of the selection transistor by applying a predetermined voltage different from the threshold voltage of the selection transistor, and The third electrode applies a reverse bias to the reset transistor to control the threshold voltage of the reset transistor by applying a predetermined voltage different from the threshold voltage of the reset transistor.

16. The solid-state image sensor according to claim 15, wherein The first electrode, the second electrode, and the third electrode apply reverse bias voltages of different values ​​to the amplifying transistor, the selecting transistor, and the reset transistor, respectively, to individually control respective threshold voltages of the amplifying transistor, the selecting transistor, and the reset transistor.

17. The solid-state image sensor according to claim 11 or 12, wherein The pixel transistor is a selection transistor.

18. The solid-state image sensor according to claim 17, wherein The electrode applies a reverse bias voltage to the selection transistor so that the on-resistance of the selection transistor is different.

19. The solid-state image sensor according to claim 11 or 12, wherein A distance between the first main surface and the second main surface of the second semiconductor substrate is 100 nm or less.

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