Storage device and data backup method thereof

Abstract

A data backup method for a storage device including a storage controller, a buffer memory, and a plurality of non-volatile memory devices is provided. The method includes detecting a power-off event of external power provided to the storage device, disabling a host interface of the storage controller in response to the detection of the power-off event, moving data stored in the buffer memory to a static random access memory (SRAM) in the storage controller, blocking or disabling power to the buffer memory, setting an interleaving mode of the plurality of non-volatile memory devices to a minimum power mode, and programming the data moved to the SRAM to at least one of the plurality of non-volatile memory devices.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0158696, filed on December 3, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly to a storage device and a data backup method thereof. Background Technology

[0004] Storage devices are devices that store data under the control of host devices such as computers, smartphones, or tablets. Storage devices can be hard disk drives (HDDs), solid-state drives (SSDs), memory cards, etc. Typically, HDDs use disks as storage media, while SSDs use semiconductor memory as storage media.

[0005] Storage devices can be powered by an external power source. When the external power source fails or loses power, the storage device may lose data. Therefore, an auxiliary power supply can be included in the storage device. However, when the external power source is lost, the data on the storage device can be backed up using only the limited energy from the auxiliary power supply.

[0006] In such a scenario, if an unexpected event occurs during the backup operation, it may be impossible to use power from the auxiliary power supply to fully back up the data. This could affect the reliability of the backup data. Furthermore, this situation may be exacerbated if the amount of data to be backed up increases due to an increase in the capacity or performance of the storage device. Therefore, in backup operations on high-capacity and high-performance storage devices, effective backup management strategies may be required to ensure data reliability. Summary of the Invention

[0007] According to an exemplary embodiment of the present invention, a data backup method for a storage device is provided, the storage device including a storage controller, a buffer memory, and a plurality of non-volatile memory devices, the method comprising: detecting a power failure event of external power supplied to the storage device; disabling a host interface of the storage controller in response to the detection of the power failure event; moving data stored in the buffer memory to static random access memory (SRAM) in the storage controller; blocking or disabling power to the buffer memory; setting the interleaving mode of the plurality of non-volatile memory devices to a minimum power mode; and programming the data moved to the SRAM to at least one of the plurality of non-volatile memory devices.

[0008] According to an exemplary embodiment of the present invention, a storage device including an auxiliary power supply is provided, the storage device further comprising: a power loss prevention circuit for monitoring external power to detect a power outage event, generating a power outage detection signal upon detecting the power outage event, and selecting the auxiliary power supply as device power upon detecting the power outage event; a plurality of non-volatile memory devices disposed in the storage device; a buffer memory for temporarily storing data exchanged between the plurality of non-volatile memory devices and a host; and a storage controller, wherein in response to the power outage detection signal, the storage controller moves data stored in the buffer memory, and then programs the data moved from the buffer memory to at least one of the plurality of non-volatile memory devices, and wherein the storage controller disables the host interface, and then blocks or disables power to the buffer memory after the data has been moved from the buffer memory.

[0009] According to an exemplary embodiment of the present invention, a data backup method for a storage device is provided, wherein the storage device performs data backup by using an auxiliary power supply in the event of a power failure. The method includes: disabling a host interface of a storage controller in response to the power failure; configuring a non-volatile memory device to a minimum power consumption interleaving mode among a plurality of interleaving modes for accessing the non-volatile memory device; and programming backup data stored in a buffer memory to the non-volatile memory device, depending on the configured interleaving mode.

[0010] According to an exemplary embodiment of the present invention, a data backup method for a storage device is provided, the storage device including a storage controller, a first memory and a second memory, and a plurality of non-volatile memory devices, the method comprising: powering down a host interface in response to a power failure detection signal; moving data from the first memory to the second memory; powering down the first memory after the data has been moved to the second memory; and programming the data moved to the second memory into the first non-volatile memory device among the plurality of non-volatile memory devices. Attached Figure Description

[0011] The above and other features of the inventive concept will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating an exemplary embodiment of a storage device according to a concept conceived in this invention.

[0013] Figure 2 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 1 A diagram showing the configuration and operation of power loss prevention equipment.

[0014] Figure 3 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 1 A block diagram of the configuration of the storage controller.

[0015] Figure 4 This is a flowchart illustrating an exemplary backup method according to a concept of the present invention. Figure 3 The storage controller executes this backup method.

[0016] Figure 5 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 3 A block diagram of the host interface.

[0017] Figure 6 This is a diagram illustrating how backup data is moved from a buffer memory to static random access memory (SRAM) according to an exemplary embodiment of the present invention.

[0018] Figure 7 This is a block diagram illustrating a non-volatile memory device and a flash memory interface according to an exemplary embodiment of the present invention.

[0019] Figure 8 This is a table illustrating variations in the interlacing pattern according to an exemplary embodiment of the present invention.

[0020] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating an exemplary embodiment of the method for establishing a power connection between a flash memory interface and a non-volatile memory device during backup operations, according to a concept conceived in this invention.

[0021] Figure 10 This is a block diagram illustrating a memory region of a non-volatile memory device storing backup data in an exemplary embodiment of the present invention.

[0022] Figure 11 This is a block diagram illustrating another example of a storage device capable of using a backup method according to an exemplary embodiment of the present invention.

[0023] Figure 12 This is a block diagram illustrating another exemplary embodiment of a memory card according to a concept of the present invention. Detailed Implementation

[0024] In the following description, storage devices using flash memory will be used to illustrate exemplary embodiments of the inventive concept. However, those skilled in the art will understand that the inventive concept is not limited thereto, and that it can be implemented or applied through other embodiments. It should be further understood that, in the accompanying drawings, the same reference numerals may refer to the same or similar elements.

[0025] In the following text, "off" state can refer to a standby state (or idle state) in which power is supplied but functions are disabled, and an off state in which power is essentially disconnected.

[0026] Figure 1 This is a block diagram illustrating an exemplary embodiment of a storage device according to a concept of the present invention. (Reference) Figure 1 The storage device 1000 may include an auxiliary power supply 1100, power loss prevention logic 1200 (e.g., PLP logic), a storage controller 1300, a non-volatile memory device 1400, and a buffer memory 1500.

[0027] When a power outage event occurs that prevents external power from being supplied, the auxiliary power supply 1100 provides stored energy to the storage device 1000. Using the energy from the auxiliary power supply 1100, the storage device 1000 can complete ongoing operations and perform data backup operations. However, as the capacity or performance of the storage device 1000 increases, the energy consumed in backup operations increases. However, by using the inventive techniques described herein to efficiently utilize the limited energy stored in the auxiliary power supply 1100, the reliability of backup operations will be increased.

[0028] Power loss prevention logic 1200 is a component used to prevent power loss supplied to storage device 1000. Power loss prevention logic 1200 can be an integrated circuit (IC), a chip, or a component. Under normal external power supply conditions, power loss prevention logic 1200 provides external power as device power D_PWR for use by storage device 1000. When external power is blocked, power loss prevention logic 1200 provides the output of auxiliary power supply 1100 as device power D_PWR for use by storage device 1000. In other words, power loss prevention logic 1200 can switch from external power to auxiliary power supply 1100.

[0029] Furthermore, the power loss prevention logic 1200 can detect power outage events (PO events), such as the disconnection of external power or a severe voltage drop. When a power outage event (PO event) is detected, the power loss prevention logic 1200 can provide a power outage detection signal PO_DET to the storage controller 1300. The power loss prevention logic 1200 can switch the source of device power D_PWR used to drive the storage device 1000 from external power to auxiliary power device 1100. (See reference...) Figure 2 A more comprehensive description of an exemplary configuration of the power loss prevention logic 1200 is provided.

[0030] The storage controller 1300 can be configured to control the non-volatile memory device 1400 and the buffer memory 1500 in response to commands from or under the control of the host. For example, in response to a request from the host, the storage controller 1300 can write data to the non-volatile memory device 1400, or it can read data stored in the non-volatile memory device 1400 and provide the read data to the host. To access the non-volatile memory device 1400, the storage controller 1300 can provide commands, addresses, data, and control signals to the non-volatile memory device 1400.

[0031] According to an exemplary embodiment of the present invention, the storage controller 1300 can perform a backup operation that efficiently utilizes power. For example, when a power failure detection signal PO_DET from power loss prevention logic 1200 is provided to the storage controller 1300, the storage controller 1300 interrupts the currently executing operation. Next, the storage controller 1300 enters a backup mode and backs up the data stored in the buffer memory 1500 to the non-volatile memory device 1400. In this case, the storage controller 1300 can disable operations associated with intellectual property (or function blocks) or interface circuitry communicating with the host. The storage controller 1300 can move the backup data stored in the buffer memory 1500 to the static random access memory (SRAM) within the storage controller 1300, and then can shut down the buffer memory 1500. In other words, after moving the backup data, the storage controller 1300 can provide a standby command to the buffer memory 1500 or can block power to the buffer memory 1500. The storage controller 1300 may program backup data stored in SRAM to the non-volatile memory device 1400 in a minimum power mode. The minimum power mode can be implemented by partially shutting down the non-volatile memory device 1400. The backup operation of the storage controller 1300 described above can be performed by the backup manager 1345. The backup manager 1345 may be included in the storage controller 1300 in hardware form, or it may be implemented in software or firmware. A detailed configuration or operation of the storage controller 1300 will be described with reference to the accompanying drawings, which will be described later.

[0032] Under the control of the storage controller 1300, the non-volatile memory device 1400 can store data received from the storage controller 1300, or can transfer data stored therein to the storage controller 1300. The non-volatile memory device 1400 is provided as a storage medium for the storage device 1000. For example, the non-volatile memory device 1400 can be a high-capacity NAND flash memory. The non-volatile memory device 1400 may include multiple flash memory devices.

[0033] Typically, multiple flash memory devices are connected to the memory controller 1300 in channels. Multiple flash memory devices communicating with the memory controller 1300 via the same data bus are connected using a single channel. Non-volatile memory devices 1400 may communicate with the memory controller 1300 in a channel / line interleaved manner. Specifically, in the event of a power failure, non-volatile memory device 1400 may operate in an interleaved mode, where it communicates with the memory controller 1300 using minimum power.

[0034] Buffer memory 1500 can be used as a data buffer for data exchange between storage device 1000 and the host. Furthermore, buffer memory 1500 can store a mapping table where logical addresses (or logical bit addresses (LBAs)) provided to storage device 1000 are mapped to addresses in non-volatile memory device 1400. Buffer memory 1500 temporarily stores write data provided from the host or read data provided from non-volatile memory device 1400. When a read operation is requested from the host, if data exists in cached non-volatile memory device 1400, buffer memory 1500 supports a caching function that directly provides cached data to the host. Buffer memory 1500 can be synchronous dynamic random access memory (SDRAM) used to provide sufficient buffering within storage device 1000 when storage device 1000 is used as a high-capacity secondary storage device. However, buffer memory 1500 is not limited to this.

[0035] According to the above embodiments of the present invention, when a power outage occurs, storage device 1000 can block or disable power to execute blocks connected to the host interface of storage controller 1300. For example, storage device 1000 can disable the host interface circuitry. Storage controller 1300 can move data from buffer memory 1500 to SRAM and then shut down buffer memory 1500, which may consume significant standby power during backup operations. Storage controller 1300 may program the backup data moved to SRAM into non-volatile memory device 1400 in a minimum power mode. Minimum power mode may include programming techniques, such as minimizing line crosstalk by programming data to a single-level cell (SLC) region or by partially shutting down non-volatile memory device 1400. According to exemplary embodiments of the present invention, even when the power consumed during backup operations of storage device 1000 is minimized, the reliability of backup data can be increased. Furthermore, it allows for flexibility in responding to increases in the backup data capacity of storage device 1000. It should be understood that storage device 1000 can be a high-capacity and high-performance storage device.

[0036] Figure 2 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 1 A diagram showing the configuration and operation of power loss prevention equipment. Figure 1 The power loss prevention logic 1200 may be referred to as power loss prevention device 1200 in the following text. Reference Figure 2 The power loss prevention device 1200 may include a power failure detector 1220 and a power selection switch (PSSW) 1240.

[0037] The power failure detector 1220 monitors the level of external power and generates a power selection signal SEL and a power failure detection signal PO_DET based on the monitoring results. The power failure detector 1220 can detect when external power is disconnected or when the voltage of external power decreases to a reference value or lower. In either case, the power failure detector 1220 can determine that a power failure event has occurred. In this case, the power failure detector 1220 controls the power selection switch 1240 to select the auxiliary power supply 1100 instead of the external power. In other words, the power selection switch 1240 is connected to the auxiliary power supply 1100. The power failure detector 1220 can transmit the power failure detection signal PO_DET to trigger a backup operation of the storage controller 1300. For example, the power failure detection signal PO_DET can be transmitted via a general purpose input / output interface (GPIO).

[0038] Power selection switch 1240 provides external power or auxiliary power to device 1100 as device power D_PWR in response to a power selection signal SEL provided by power failure detector 1220. Under normal external power supply conditions, power failure detector 1220 allows power selection switch 1240 to provide external power as device power D_PWR. However, if power failure detector 1220 detects a power failure event, power selection switch 1240 can select auxiliary power supply 1100 to provide device power D_PWR.

[0039] The auxiliary power supply 1100 can store energy supplied from an external power source while simultaneously supplying external power. For example, the auxiliary power supply 1100 may include one or more capacitors 1110, 1120, and 1130 for charging. The auxiliary power supply 1100 can store sufficient energy to manage backup operations of the storage device 1000. Therefore, the multiple capacitors 1110, 1120, and 1130 can be capacitive elements with high stability. For example, the multiple capacitors 1110, 1120, and 1130 can be implemented using elements such as electrolytic capacitors, film capacitors, tantalum capacitors, or ceramic capacitors (e.g., multilayer ceramic capacitors (MLCCs)). However, the capacitors 1110, 1120, and 1130 of the auxiliary power supply 1100 are not limited to the examples above.

[0040] Figure 3 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 1 A block diagram illustrating the configuration of the storage controller. (See reference) Figure 3 The storage controller 1300 according to an exemplary embodiment of the present invention may include a general purpose input / output interface (GPIO) 1310, a central processing unit (CPU) 1320, SRAM 1330, code memory 1340, host interface 1350, buffer controller 1360, direct memory access (DMA) engine 1370, flash memory interface 1380 and system bus 1390.

[0041] General Purpose Input / Output Interface 1310 provides an interface for directional communication with the storage controller 1300. Specifically, according to an exemplary embodiment of the present invention, General Purpose Input / Output Interface 1310 can receive a power failure detection signal PO_DET provided from power loss prevention logic 1200. General Purpose Input / Output Interface 1310 can receive the power failure detection signal PO_DET and can transmit the power failure detection signal PO_DET to the central processing unit 1320.

[0042] The central processing unit 1320 may include a processing unit such as a microprocessor. The central processing unit 1320 can manage the overall operation of the storage controller 1300. The central processing unit 1320 is configured to drive firmware for driving the storage controller 1300. The central processing unit 1320 can execute various firmware, for example, loaded into the code memory 1340. Specifically, the central processing unit 1320 can execute a backup manager 1345 according to an exemplary embodiment of the present invention to minimize energy usage during backup. When executing the backup manager 1345, the central processing unit 1320 can transmit various control information required for backup to relevant components.

[0043] For example, when the backup manager 1345 is executed, the central processing unit 1320 detects a power failure event in the storage device 1000. Upon detecting a power failure event, the central processing unit 1320 can disable or deactivate components performing communication with the host, such as the host interface 1350 and the DMA engine 1370. The central processing unit 1320 moves the backup data held in the buffer memory 1500 to the SRAM 1330 located in the storage controller 1300. Next, using command or control signals, the central processing unit 1320 shuts off power to the buffer memory 1500 and the buffer controller 1360, or sets the buffer memory 1500 and the buffer controller 1360 to an inactive mode. Finally, the central processing unit 1320 programs the backup data moved to the SRAM 1330 into the non-volatile memory device 1400. In this case, similarly, under the control of the central processing unit 1320, the flash interface 1380 can control the interleaving mode and may program backup data to the non-volatile memory device 1400 in a minimum power mode.

[0044] SRAM 1330 can be used as a cache memory or working memory for the central processing unit 1320. SRAM 1330 can store code and instructions executed by the central processing unit 1320. SRAM 1330 can store data processed by the central processing unit 1320. For example, data used for connection to the host interface can be stored in SRAM 1330. When a power failure occurs, the functionality of SRAM 1330 may be limited because the function of exchanging data with the host is disabled. In this case, according to an exemplary embodiment of the present invention, pending backup data in the buffer memory 1500 can be moved to SRAM 1330. In other words, when a power failure occurs, SRAM 1330 can buffer backup data instead of the power-consuming buffer memory 1500.

[0045] Code or firmware used to drive or control the storage controller 1300 is loaded into the code memory 1340. For example, firmware used to perform basic functions of the storage controller 1300 manufactured for a specific purpose may be loaded into the code memory 1340. For example, according to an exemplary embodiment of the present invention, a backup manager 1345 is stored in the code memory 1340. When a power failure event is detected, the backup manager 1345 controls the procedures for backing up data from the buffer memory 1500 or SRAM 1330 to the non-volatile memory device 1400. When the backup manager 1345 is executed by the central processing unit 1320, the host interface 1350, DMA engine 1370, buffer memory 1500, buffer controller 1360, and non-volatile memory device 1400 are sequentially shut down by partially blocking power to them in response to the movement of backup data. However, it should be understood that the host interface 1350, DMA engine 1370, buffer memory 1500, buffer controller 1360, and non-volatile memory device 1400 may not be sequentially shut down. For example, the host interface 1350 and the DMA engine 1370 can be shut down simultaneously. Here, the code memory 1340 can be referred to as a "memory" capable of loading firmware or code.

[0046] Host interface 1350 provides an interface between the host and storage controller 1300. In the event of a power outage, overall communication between storage device 1000 and the host will be blocked. Therefore, it is not a problem to disable or deactivate host interface 1350 during a power outage. In this case, for example, power supplied to the physical layer (PHY) of host interface 1350 to enable communication with the host can be blocked. Alternatively, clock signals supplied to the physical layer (PHY) of host interface 1350 can be blocked during a power outage. The host and storage controller 1300 can be connected via one of a variety of standardized interfaces. These standardized interfaces include various interfaces such as Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, external SATA (e-SATA) interface, Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) interface, PCI Express (PCI-E) interface, Universal Serial Bus (USB) interface, IEEE 1394 interface, Universal Flash Storage (UFS) interface, and card interface.

[0047] Buffer controller 1360 controls read and write operations on buffer memory 1500. For example, under the control of central processing unit 1320 or DMA engine 1370, buffer controller 1360 temporarily stores write or read data in buffer memory 1500. For example, under the control of central processing unit 1320, buffer controller 1360 can classify and manage memory regions of buffer memory 1500 through streams. Under the control of central processing unit 1320, buffer controller 1360 can update the head or tail pointer of buffer memory 1500, which is implemented with a ring buffer or circular buffer, and can output the updated pointer externally. For example, when a power failure occurs, buffer controller 1360 controls buffer memory 1500 to move backup data stored in buffer memory 1500 to SRAM 1330. When the backup data stored in buffer memory 1500 has been completely read, backup manager 1345 can shut off the power supplied to buffer memory 1500. The shutdown of buffer memory 1500 can be performed using a physical power gating switch. Alternatively, to shut down the buffer memory 1500, a command to block power can be transmitted to a power management integrated circuit (PMI C) or voltage regulator, which supplies power to the buffer memory 1500 via a control channel such as I2C (e.g., an internal integrated circuit). When the buffer memory 1500 is shut down, under the control of the central processing unit 1320, the power supply to the buffer controller 1360 can be completely or partially blocked, or the clock signal supplied to the buffer controller 1360 can be blocked.

[0048] DMA engine 1370 controls the direct memory access (DMA) operation of storage device 1000. DMA engine 1370 performs data transfers with the host or any other external device under the control of central processing unit 1320. For example, in DMA transfer mode, DMA engine 1370 may stream read data loaded into buffer memory 1500 to the host. Alternatively, in DMA transfer mode, DMA engine 1370 may store streamed data provided from the host into buffer memory 1500. DMA engine 1370 performs DMA operations on buffer memory 1500 together with the host. DMA operations are interrupted when a power failure event occurs. Therefore, as backup data stored in buffer memory 1500 is moved to SRAM 1330, power or clock signals to DMA engine 1370 can be blocked.

[0049] Flash interface 1380 provides an interface connection between storage controller 1300 and non-volatile memory device 1400. For example, data processed by central processing unit 1320 is stored in non-volatile memory device 1400 via flash interface 1380. Specifically, in the event of a power failure, flash interface 1380 communicates with non-volatile memory device 1400 in minimum power mode. Flash interface 1380 may also transmit backup data to non-volatile memory device 1400 connected to corresponding channels CH1, CH2, CH3…CHn in minimum interleaving mode. Flash interface 1380 can control (or change) the interleaving mode associated with non-volatile memory device 1400 under the control of central processing unit 1320. Under the control of central processing unit 1320, flash interface 1380 can minimize the number of line interleaving operations performed on each channel within a specific range.

[0050] The components of the storage controller 1300 have been described above. Due to the functionality of the storage controller 1300 according to an exemplary embodiment of the present invention, in the event of a power outage, power to components unrelated to the backup operation may be blocked or deactivated, supplying power only to the components required for the backup operation. In other words, power is supplied to the minimum number of components required for the backup operation. Therefore, the limited energy of the auxiliary power supply 1100 can be used effectively in the event of a power outage. For example, the energy of the auxiliary power supply 1100 can be effectively controlled so that the backup operation can be completed entirely without data loss.

[0051] Figure 4 This is a flowchart illustrating an exemplary backup method according to a concept of the present invention. Figure 3 The storage controller executes this backup method. (See reference) Figure 4 When a power outage occurs, the storage controller 1300 performs a sequential backup operation to achieve minimum power consumption.

[0052] In operation S110, the storage controller 1300 can monitor for power failure events. The storage controller 1300 monitors the power loss prevention logic 1200 (reference). Figure 1 The power loss prevention logic 1200 provides the power loss detection signal PO_DET. When external power is disconnected or the level of external power decreases to a reference value or less, the power loss prevention logic 1200 can provide the power loss detection signal PO_DET to the storage controller 1300. The power loss prevention logic 1200 uses the power from the auxiliary power supply 1100 as the device power D_PWR. In other words, when external power is disconnected or when the level of external power decreases to a reference value or less, the power loss prevention logic 1200 switches to the auxiliary power supply 1100.

[0053] In operation S120, the storage controller 1300 monitors the power failure detection signal PO_DET from the power loss prevention logic 1200 and detects the occurrence of a power failure event. When the power failure detection signal PO_DET is activated, the procedure proceeds to operation S130 to perform a backup operation according to an example of the concept of the present invention. When the power failure detection signal PO_DET is disabled, the procedure proceeds to operation S110 to continue monitoring for power failure events. It should be understood that under normal operation of the external power supply, the power failure detection signal PO_DET may be disabled.

[0054] In operation S130, the storage controller 1300 can block or disable power to components associated with the storage controller 1300 and communication with the host. For example, the storage controller 1300 can block clock signals supplied to the host interface 1350 connected to the host interface. For example, the storage controller 1300 can disable the phase-locked loop (PLL) used for exchanging data with the host and included in the host interface 1350. Furthermore, power can be blocked to the DMA engine 1370 performing direct memory access (DMA) with the host. Power can be cut off in response to commands provided in the intellectual property (IP) unit or through power gating control performed in the IP unit.

[0055] In operation S140, the data present in the buffer memory 1500 is moved to the SRAM 1330. The buffer memory 1500 may be an SDRAM that requires continuous refresh operations, thereby consuming a large amount of power. Therefore, in order to minimize power consumption, the backup data held in the buffer memory 1500 can be moved to the SRAM 1330, which is a low-power memory.

[0056] In operation S150, the buffer memory 1500 from which backup data has been completely removed is shut down. The buffer memory 1500 can be shut down by controlling a power gating switch present on the power line supplying power to it. Alternatively, commands for controlling the I2C interface of a PMI C or a voltage regulator supplying power to the buffer memory 1500 can be used to shut down the buffer memory 1500.

[0057] In operation S160, the buffer controller 1360 is turned off. After the buffer memory 1500 is turned off, the buffer controller 1360, which is interfaced with the buffer memory 1500, is no longer needed. Therefore, in order to prevent power consumption of the buffer controller 1360 even in the idle state, the power to the buffer controller 1360 can be blocked, or the buffer controller 1360 can be disabled.

[0058] In operation S170, the central processing unit 1320 sets the communication between the flash interface 1380 and the non-volatile memory device 1400 to a minimum power mode. For example, the central processing unit 1320 can change the interleaving mode of the flash interface 1380 to a mode corresponding to minimum bandwidth. For example, when the storage device 1000 is powered by external power, the flash interface 1380 may communicate with the non-volatile memory device 1400 in an interleaving mode that provides maximum performance. In this case, the flash interface 1380 can use an interleaving mode in which all non-volatile memory devices connected to the corresponding channels are used (e.g., 32-line mode). However, when a power failure occurs, the flash interface 1380 may communicate with the non-volatile memory device 1400 in an interleaving mode that uses minimum power instead of maximum performance. In this case, the flash interface 1380 can use an interleaving mode in which minimum bandwidth is provided (e.g., 8-line mode). In this case, the non-volatile memory devices corresponding to unused channels or lines can be set to a disabled mode, or power can be blocked for those non-volatile memory devices.

[0059] In operation S180, backup data stored in SRAM 1330 is programmed into a non-volatile memory device that provides auxiliary power to it. Because the backup data is small in size and only a portion of the non-volatile memory device 1400 is powered, the backup operation can be performed adequately using only the power supplied from auxiliary power supply 1100.

[0060] The above briefly describes a backup method for a storage device 1000 according to an exemplary embodiment of the present invention. When a power outage occurs, the limited energy of the auxiliary power supply 1100 can be used efficiently by blocking power to components not used for backup and then blocking power to components on the backup path after they are used.

[0061] Figure 5 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 3 A block diagram of the host interface. (See reference) Figure 5 The host interface 1350 may include a host interface physical layer 1352, a host interface logic 1354, and a clock generator 1356.

[0062] The host interface physical layer 1352 supports the host's high-speed interface standards. The host interface physical layer 1352 allows the storage device 1000 to communicate according to the host's interface standards (e.g., SATA, SAS, PCIe, or USB). According to the transport protocol used for communicating with the host, the host interface physical layer 1352 can transmit output signals and receive received signals transmitted from the host. For example, the host interface physical layer 1352 may include a MIPI M-PHY that supports high-speed data communication physical layer protocol standards.

[0063] The host interface logic 1354 performs control operations and buffering to support the transport protocol of the host interface physical layer 1352. For example, when data is transferred from the buffer memory 1500 to the host, the host interface logic 1354 can process commands corresponding to the transport protocol used to transfer data, or it can perform control operations such as interrupts.

[0064] Clock generator 1356 generates clock signals CLK0 and CLK1 to drive host interface 1350. For example, clock generator 1356 may be a phase-locked loop (PLL) circuit. Clock generator 1356 can stop generating at least one of clock signals CLK0 and CLK1 in response to a disable signal DIS. The disable signal DIS can be provided from central processing unit 1320. When clock signal CLK1 is disabled, operation of host interface physical layer 1352 is stopped. When clock signal CLK0 is disabled, operation of host interface logic 1354 is stopped.

[0065] When a power outage occurs, no data exchange with the host is required. In this case, the host interface physical layer 1352 and host interface logic 1354, which communicate with the host in the storage controller 1300, are not used. When the backup manager 1345 is activated, the central processing unit 1320 can block power to the host interface 1350, or can disable or deactivate the clock generator 1356. Therefore, idle power consumption in the host interface 1350 can be prevented when a power outage occurs.

[0066] Figure 6 This is a diagram illustrating how backup data is moved from buffer memory to SRAM according to an exemplary embodiment of the present invention. (Reference) Figure 6 The central processing unit 1320 can control the buffer controller 1360 so that backup data stored in the buffer memory 1500 is moved to the SRAM 1330.

[0067] After power or clock signals to the host interface physical layer 1352 and DMA engine 1370 are blocked, the movement of backup data from buffer memory 1500 to SRAM 1330 begins. Because buffer memory 1500 is being accessed, power can be supplied to buffer controller 1360. First, central processing unit 1320 can control buffer controller 1360 to read the backup data held in buffer memory 1500. Buffer controller 1360, under the control of central processing unit 1320, reads the backup data present in buffer memory 1500. Buffer controller 1360, under the control of central processing unit 1320, can transfer the read backup data to SRAM 1330.

[0068] SRAM 1330 can store backup data under the control of central processing unit 1320. In cases where there is insufficient memory to store backup data in SRAM 1330, cache memory or working memory in memory controller 1300 can be utilized. Alternatively, a portion of the backup data can be selectively stored in SRAM 1330 depending on its importance. For example, metadata (such as mapping data) can be preferentially stored in SRAM 1330. In this case, other data can be stored in cache or working memory.

[0069] Figure 7 This is a block diagram illustrating a non-volatile memory device and a flash memory interface according to an exemplary embodiment of the present invention. (Reference) Figure 7 The flash memory interface 1380 can be connected to the non-volatile memory device 1400 through multiple channels CH1, CH2, CH3...CHn.

[0070] The input / output ports of each of the m non-volatile memory devices NVM_11, NVM_12, ​​NVW_13…NVM_1m (where m is a natural number) are connected to the first channel CH1. Multiple non-volatile memory devices NVM_21…NVMnm are connected to each of the second channels CH2 through the nth channel CHn in the same manner. Non-volatile memory devices connected to the same channel share the input / output ports.

[0071] In the event of a power outage, the central processing unit 1320 can set the communication mode between the flash interface 1380 and the non-volatile memory device 1400 to a minimum power mode. For example, the flash interface 1380 can again set the channel / line interleaving mode to a mode corresponding to the minimum power mode (or an interleaved mode). For instance, in normal mode using external power, the flash interface 1380 might communicate with the non-volatile memory device 1400 in a fully interleaved manner using all "n" channels and "m" lines. However, in the event of a power outage, the flash interface 1380 might communicate with the non-volatile memory device 1400 in a partially interleaved manner using a portion of the "n" channels and a portion of the "m" lines.

[0072] The non-volatile memory device 1400 required for programming the backup data has a relatively small memory size. Therefore, in backup operations where the device is powered D_PWR from the auxiliary power supply 1100, a fully interleaved mode that requires high power consumption is not necessary. Thus, the backup data can be programmed even when the interleaving mode is switched to a partially interleaved mode that uses minimal power.

[0073] Figure 8 This is a table illustrating variations in the interlacing pattern according to exemplary embodiments of the present invention. (Reference) Figure 8 The flash interface 1380 may operate in a backup mode set in the event of a power outage, or in a normal mode in which external power is supplied. This is shown in the column under "PW Mode".

[0074] Normal mode corresponds to full-power mode, where all lines are interleaved. For example, in the case of 32 non-volatile memory devices connected to one channel, a 32-line interleaving method can be used, where all non-volatile memory devices connected to the channel are interleaved.

[0075] In backup mode, some of the non-volatile memory devices connected to the channel can be interleaved, and power can be blocked from the remaining non-volatile memory devices, or the remaining non-volatile memory devices can be put into a disabled mode. For example, in Figure 8 In the table, an 8-line interleaving configuration can be used in backup mode. Therefore, the flash interface 1380 and the non-volatile memory device 1400 may operate in minimum power mode.

[0076] The above description of exemplary embodiments of the inventive concept uses an interleaving mode that consumes minimal power in a line-interleaving manner. However, the interleaving mode is merely an example, and it should be understood that various channel / line interleaving methods can be used to minimize power consumption.

[0077] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating an exemplary embodiment of the method for establishing a power connection between a flash memory interface and a non-volatile memory device during backup operations, according to a concept conceived in this invention.

[0078] refer to Figure 9A When a power failure occurs, the flash memory interface 1380 can access the central processing unit 1320 (reference 1320). Figure 3 The flash interface 1380 receives a partial shutdown command PSD_CMD. In this case, the flash interface 1380 can transmit the standby command SB_CMD to the non-volatile memory interfaces NVM9 to NVM32 while maintaining the state of the non-volatile memory devices (e.g., NVM1 to NVM8).

[0079] In contrast, in normal mode where external power is typically supplied to storage device 1000, individual status control commands may not be transmitted to non-volatile memory devices NVM1 through NVM32. In other words, the standby command SB_CMB may not be transmitted to non-volatile memory devices NVM1 through NVM32. Therefore, all non-volatile memory devices NVM1 through NVM32 can perform interleaving normally.

[0080] However, in the event of a power outage, the flash interface 1380 can transmit a standby command SB_CMD to some non-volatile memory devices (e.g., NVM9 to NVM32) in response to a partial shutdown command PSD_CMD provided from the central processing unit 1320. Therefore, non-volatile memory devices NVM1 to NVM8, which are only used for backup, can remain active, while non-volatile memory devices NVM9 to NVM32, which are not used for backup, can enter standby mode.

[0081] Here, non-volatile memory devices NVM1 to NVM8 can be devices that form lines Way 1 to Way 8 in a line-interleaved mode. Non-volatile memory devices NVM9 to NVM32 can be devices that form the remaining lines Way 9 to Way 32 in a line-interleaved mode.

[0082] refer to Figure 9B When a power failure occurs, the flash memory interface 1380 can access the central processing unit 1320 (reference 1320). Figure 3 The flash interface 1380 receives a partial shutdown command PSD_CMD. In this case, the flash interface 1380 can control the components (e.g., voltage regulators) used to supply power to the non-volatile memory devices 1400 so that power is only supplied to some non-volatile memory devices (e.g., NVM1 to NVM8) to be used for backup.

[0083] In normal mode, where external power is typically supplied to storage device 1000, flash interface 1380 can activate all first voltage regulators 1382 and second voltage regulators 1384. Therefore, power can be normally supplied to all non-volatile memory devices NVM1 to NVM32.

[0084] However, in the event of a power outage, in response to the partial shutdown command PSD_CMD provided from the central processing unit 1320, the flash interface 1380 can supply power only to some non-volatile memory devices (e.g., NVM1 to NVM8). In other words, in response to the partial shutdown command PSD_CMD, the flash interface 1380 can activate only the first voltage regulator 1382 and deactivate the second voltage regulator 1384. Therefore, power can be supplied only to some non-volatile memory devices NVM1 to NVM8 intended for backup.

[0085] Here, non-volatile memory devices NVM1 to NVM8 can be devices configured in a line-interleaved mode as lines 1 to 8. Non-volatile memory devices NVM9 to NVM32 can be devices configured in a line-interleaved mode as the remaining lines 9 to 32. In other words, when a power outage occurs, the backup channel or line interleaving method can be changed to a mode using minimum power.

[0086] refer to Figure 9C In the event of a power outage, the flash interface 1380 can partially supply power to the non-volatile memory device 1400. To accomplish this, the flash interface 1380 may include power gating switches SW1 and SW2 for selectively supplying power to some of the non-volatile memory devices.

[0087] In normal mode, where external power is supplied to storage device 1000, flash interface 1380 can keep all power gating switches SW1 and SW2 in the ON state. In this case, external power can be supplied as device power D_PWR.

[0088] In contrast, when a power outage occurs, under the control of the central processing unit 1320, the flash interface 1380 can supply device power D_PWR only to some non-volatile memory devices (e.g., NVM1 to NVM8) intended for backup. To accomplish this, under the control of the central processing unit 1320, the flash interface 1380 can turn on power gating switch SW1, which supplies power to non-volatile memory devices NVM1 to NVM8. The flash interface 1380 can turn off power gating switch SW2, which supplies power to the remaining non-volatile memory devices not used for backup (e.g., NVM9 to NVM32).

[0089] Here, non-volatile memory devices NVM1 to NVM8 can be devices configured in a line-interleaved mode as lines 1 to 8. Non-volatile memory devices NVM9 to NVM32 can be devices configured in a line-interleaved mode as the remaining lines 9 to 32. In other words, when a power outage occurs, the backup channel or line interleaving method can be changed to a mode using minimum power.

[0090] The above description is given as an interleaving mode, in which backup operations are performed using minimum power, reducing the number of lines to be interleaved. However, in exemplary embodiments of the inventive concept, it should be understood that the channel or line interleaving mode is modified to a mode (or condition) for minimum power consumption.

[0091] Figure 10 This is a block diagram illustrating a memory region of a non-volatile memory device storing backup data, according to an exemplary embodiment of the present invention. (Reference) Figure 10 Backup data stored in SRAM 1330 can be provided to a single-level cell (SLC) region of a selected non-volatile memory device 1410.

[0092] Non-volatile memory device 1410 may include multiple regions in which unequal numbers of bits are stored for each cell. For example, non-volatile memory device 1400 may include an SLC region 1412 in which 1 bit of data is stored for each cell and a three-level cell (TLC) region 1414 in which 3 bits of data are stored for each cell. Typically, the operation of programming data to TLC region 1414 requires relatively high power. In contrast, the operation of programming data to SLC region 1412 requires relatively low power. Therefore, in a backup mode in which the operation is performed with limited energy, backup data stored in SRAM 1330 is programmed to SLC region 1412 of non-volatile memory device 1400. Alternatively, backup data stored in SRAM 1330 may be programmed to TLC region 1414.

[0093] Figure 11 This is a block diagram illustrating another example of a storage device capable of using a backup method according to an exemplary embodiment of the present invention. (Reference) Figure 11 The storage device 2000 can operate under the control of a host. For example, the storage device 2000 may include a memory controller 2210 and a non-volatile memory device 2220. The memory controller 2210 can operate in response to commands received from the host. For example, the memory controller 2210 can receive write commands and write data from the host, and can store the received write data into the non-volatile memory device 2220 in response to the received write command.

[0094] Alternatively, the memory controller 2210 may receive a read command from the host and may read data stored in the non-volatile memory device 2220 in response to the received read command. The memory controller 2210 may then transfer the read data to the host. In an exemplary embodiment of the inventive concept, the non-volatile memory device 2220 may be a NAND flash memory device, but the inventive concept is not limited thereto.

[0095] In an exemplary embodiment of the present invention, the host may communicate with the storage device 2000 based on a Universal Flash Storage (UFS) interface defined by the JEDEC standard. For example, the host and storage device 2000 may exchange data packets in the form of UFS Protocol Information Units (UPI U). UPI U may include various information defined by the interface between the host and storage device 2000 (e.g., the UFS interface). However, the present invention is not limited thereto.

[0096] In an exemplary embodiment of the present invention, when a power failure occurs, the storage device 2000 can first cut off power to the host interface and the DMA engine. Next, backup data present in SRAM or DRAM can be programmed into the non-volatile memory device 2220. In this case, the non-volatile memory device 2220 can change mode to an interleaved mode for minimum power consumption.

[0097] Figure 12 This is a block diagram illustrating a memory card according to another exemplary embodiment of the present invention. (Reference) Figure 12 The memory card 3000 includes a memory controller 3210 and a non-volatile memory device 3220. The memory card 3000 includes any storage device, including non-volatile memory such as a Secure Digital (SD) card, a Multimedia Card (MMC) or a removable mobile storage device (e.g., a USB memory).

[0098] The memory controller 3210 may include a central processing unit 3211, SRAM 3213, a host interface 3215, an error correction block 3217, and a flash memory interface 3219. The memory controller 3210 may also include an auxiliary power supply. The auxiliary power supply may be located internally or externally to the memory controller 3210. The auxiliary power supply has the same configuration and operation as described in the above embodiments.

[0099] Memory card 3000 is connected to and used by the host. Memory card 3000 exchanges data with the host device via host interface 3215 and with non-volatile memory 3220 via flash memory interface 3219. Power is supplied from the host to memory card 3000, and the memory card performs internal operations. In the event of a sudden power outage (or interruption) from the host, auxiliary power is provided to perform the operation of backing up data from SRAM 3213 to non-volatile memory 3220. Specifically, memory controller 3210 can first block power to components that do not form a backup path during the data backup operation and can then perform the data backup operation. In other words, when a power outage occurs, memory controller 3210 can block power or clock signals to components other than those in the data backup path. Memory controller 3210 can configure the interleaving mode of non-volatile memory 3220 for minimum power consumption.

[0100] According to an exemplary embodiment of the present invention, when a power failure event occurs in the storage device, the power of the auxiliary power supply can be used effectively and the reliability of the backup data can be increased.

[0101] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept set forth in the appended claims.

Claims

1. A data backup method of a storage device including a storage controller, a buffer memory, and a plurality of nonvolatile memory devices, the method comprising: detecting a power-off event of external power supplied to the storage device; disabling a host interface of the storage controller in response to detecting the power-off event; moving data stored in the buffer memory to a cache memory of the storage controller; blocking or disabling power of the buffer memory after moving the data to the cache memory; changing a full interleaving mode of the plurality of nonvolatile memory devices to a partial interleaving mode to reduce a bandwidth; blocking or disabling power of unselected nonvolatile memory devices among the plurality of nonvolatile memory devices in the partial interleaving mode; and programming the data stored in the cache memory to selected nonvolatile memory devices among the plurality of nonvolatile memory devices in the partial interleaving mode. 2.The method of claim 1, wherein when the power-off event is detected, device power of the storage device is changed from the external power to power of an auxiliary power source. 3.The method of claim 1, wherein when the host interface is disabled, power of a direct memory access (DMA) engine included in the storage controller is blocked. 4.The method of claim 1, further comprising: blocking or disabling power of a buffer controller that controls the buffer memory after blocking or disabling power of the buffer memory. 5.The method of claim 1, wherein disabling the host interface comprises: disabling a clock generator that generates a clock signal for driving the host interface. 6.The method of claim 1, wherein in changing the full interleaving mode of the plurality of nonvolatile memory devices to the partial interleaving mode, a lane or a line interleave unit between the plurality of nonvolatile memory devices and the storage controller is set to a minimum unit of a plurality of interleave units. 7.The method of claim 6, wherein the data is programmed to a single level cell (SLC) region of a nonvolatile memory device selected by an interleave unit. 8.A storage device including an auxiliary power source, comprising: a power loss prevention circuit for monitoring external power to detect a power-off event, generating a power-off detection signal when the power-off event is detected, and selecting the auxiliary power source as device power when the power-off event is detected; a plurality of nonvolatile memory devices provided in the storage device; a buffer memory for temporarily storing data exchanged between the plurality of nonvolatile memory devices and a host; and a storage controller configured to: disable a host interface of the storage controller in response to detecting the power-off event; move data stored in the buffer memory to a cache memory of the storage controller; block or disable power of the buffer memory after moving the data to the cache memory; The fully interleaved mode of the plurality of non-volatile memory devices is changed to a partially interleaved mode to reduce bandwidth; Block or disable power to the unselected non-volatile memory device among the plurality of non-volatile memory devices in the partially interleaved mode; as well as The data stored in the cache memory is programmed into a selected non-volatile memory device among the plurality of non-volatile memory devices in the partially interleaved mode.

9. The storage device of claim 8, wherein the storage controller comprises: Central processing unit, configured to perform backup operation in response to the power failure detection signal; A buffer controller for controlling the buffer memory in response to the central processing unit; as well as The flash memory interface connects to the plurality of non-volatile memory devices via channel units and accesses the plurality of non-volatile memory devices in a channel-interleaved or line-interleaved manner. After the data is moved from the buffer memory, the central processing unit blocks or disables the power to the buffer controller.

10. The storage device of claim 9, wherein the storage controller further comprises: A direct memory access (DMA) engine is used to control DMA operations in conjunction with the host, and The central processing unit together disables the DMA engine and the host interface.

11. The storage device of claim 9, wherein the host interface further comprises: A clock generator is used to provide a clock signal for communication with the host, and The central processing unit disconnects the clock generator and disables the host interface.

12. The storage device of claim 9, wherein in changing the fully interleaved mode of the plurality of non-volatile memory devices to a partially interleaved mode, the flash interface programs the data into the single-level cell (SLC) region of the plurality of non-volatile memory devices.

13. A data backup method for a storage device, wherein the storage device performs data backup by using an auxiliary power supply in the event of a power outage, the method comprising: The host interface of the storage controller is disabled in response to the power failure event; The data stored in the buffer memory of the storage device is moved to the static random access memory (SRAM) of the storage controller; Power to the buffer memory is blocked or disabled after the data is moved to the SRAM; The full interleaving mode of the multiple non-volatile memory devices in the storage device is changed to a partial interleaving mode to reduce bandwidth; Block or disable power to the unselected non-volatile memory device among the plurality of non-volatile memory devices in the partially interleaved mode; as well as The data stored in the SRAM is programmed into a selected non-volatile memory device among the plurality of non-volatile memory devices in the partially interleaved mode.

14. The method of claim 13, wherein when the host interface is disabled, power to the direct memory access (DMA) engine included in the storage controller is blocked.

15. The method of claim 13, wherein, When the host interface is disabled, the clock generator that generates the clock signal used to drive the host interface is also disabled.

16. The method of claim 13, further comprising: After the data has been completely moved to the SRAM of the storage controller, power to the buffer controller used to control the buffer memory is blocked or disabled.

17. The method of claim 13, wherein the data is programmed into a single-level cell (SLC) region of the non-volatile memory device.

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