Array substrate and display device

Abstract

The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scanning line, a data line, a power line, a sensing line, a pixel driving circuit and a light-emitting unit stacked in sequence on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer and a third conductive layer. The first electrode of the storage capacitor is at least arranged on the first conductive layer, and the second electrode of the storage capacitor is at least arranged on the second conductive layer; the data line, the power line and the sensing line are arranged on the third conductive layer. The present disclosure reduces the wiring space pressure, can provide a higher pixel PPI, and can also reduce the resistance of the data line and the IR drop of the power line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display technology is recognized by the industry as the third generation display technology for its advantages such as light weight, self-luminescence, wide viewing angle, fast response speed, low brightness and low power consumption. It has been widely used in the field of high-performance displays.

[0003] As the requirements for the PPI (pixel density) of display panels become higher and higher, the wiring pressure on the panel is also increasing. It is necessary to consider both the tight arrangement of various lines and the minimization of the mutual influence between various lines. Therefore, higher requirements are put forward for wiring design. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide an array substrate and a display device.

[0005] According to one aspect of the present disclosure, an array substrate is provided, comprising a base substrate and a scan line, a data line, a power line, a sensing line, a pixel driving circuit and a light-emitting unit stacked in sequence on the base substrate, the pixel driving circuit comprising a driving transistor and a storage capacitor, the storage capacitor comprising a first electrode and a second electrode, the first stage of the driving transistor being electrically connected to the power line, the second stage being electrically connected to the light-emitting unit, and the gate being electrically connected to the second electrode of the storage capacitor; the array substrate comprising:

[0006] A gate layer, disposed on the base substrate, wherein the scanning line and the gate of the driving transistor are disposed on the gate layer;

[0007] A first conductive layer is provided on a side of the gate layer away from the base substrate, and a first electrode of the storage capacitor is at least provided on the first conductive layer;

[0008] A second conductive layer is provided on a side of the first conductive layer away from the gate layer, and the second electrode of the storage capacitor is at least provided on the second conductive layer;

[0009] The third conductive layer is arranged on a side of the second conductive layer away from the first conductive layer, and the data line, the power line and the sensing line are arranged on the third conductive layer.

[0010] In an exemplary embodiment of the present disclosure, the array substrate further comprises an active layer, and the active layer is provided between the base substrate and the gate layer;

[0011] The first electrode of the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the first conductive layer, the second electrode plate is arranged on the gate layer, the first electrode plate and the second electrode plate are electrically connected through a via hole; the second electrode plate is also electrically connected to the gate of the driving transistor;

[0012] The second electrode of the storage capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate is arranged on the second conductive layer, the fourth electrode plate is arranged at least on a side of the active layer away from the gate layer, the third electrode plate and the fourth electrode plate are electrically connected through a via hole; the third electrode plate is also electrically connected to the light-emitting unit;

[0013] The projections of the first electrode plate and the third electrode plate on the substrate overlap to form a first storage capacitor; the projections of the first electrode plate and the fourth electrode plate on the substrate overlap to form a second storage capacitor; the projections of the second electrode plate and the fourth electrode plate on the substrate overlap to form a third storage capacitor;

[0014] The first storage capacitor, the second storage capacitor and the third storage capacitor are connected in parallel to form the storage capacitor.

[0015] In an exemplary embodiment of the present disclosure, the gate of the driving transistor is reused as the second electrode plate.

[0016] In an exemplary embodiment of the present disclosure, the array substrate further includes a light shielding layer, which is located on a side of the active layer away from the gate layer, and a projection of the light shielding layer on the base substrate overlaps with the gate of the driving transistor.

[0017] In an exemplary embodiment of the present disclosure, the light shielding layer is reused as the fourth electrode plate.

[0018] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0019] A buffer layer is provided between the active layer and the light shielding layer, and a via hole is provided on the buffer layer;

[0020] A first interlayer dielectric layer is provided between the active layer and the first conductive layer, and a via is provided on the first interlayer dielectric layer;

[0021] A second interlayer dielectric layer is provided between the first conductive layer and the second conductive layer, and a via hole is provided on the second interlayer dielectric layer;

[0022] The third electrode plate and the fourth electrode plate are connected through via holes on the buffer layer, the first interlayer dielectric layer and the second interlayer dielectric layer.

[0023] In an exemplary embodiment of the present disclosure, the via holes on the buffer layer and the first interlayer dielectric layer are formed by a one-step patterning process using a half-tone mask.

[0024] In an exemplary embodiment of the present disclosure, the scan line includes a first scan line;

[0025] The array substrate further includes a second transistor, a gate of the second transistor is electrically connected to the first scan line, a first stage of the second transistor is electrically connected to the data line, and a second stage of the second transistor is electrically connected to the gate of the driving transistor.

[0026] In an exemplary embodiment of the present disclosure, the scan line further includes a second scan line;

[0027] The array substrate further includes a third transistor, a gate of the third transistor is electrically connected to the second scan line, a first stage of the third transistor is multiplexed as a second stage of the driving transistor, and a second stage of the third transistor is electrically connected to the sensing line.

[0028] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0029] a sensing connection portion, the sensing connection portion being disposed on the second conductive layer, the sensing connection portion being electrically connected to the second stage of the third transistor through a via hole;

[0030] The sensing connection portion is also electrically connected to the sensing line through a via hole.

[0031] In an exemplary embodiment of the present disclosure, a third interlayer dielectric layer and a first planar layer are arranged between the second conductive layer and the third conductive layer, vias are arranged on the third interlayer dielectric layer and the first planar layer, and the sensing connection part and the sensing line are electrically connected through the vias on the third interlayer dielectric layer and the first planar layer.

[0032] In an exemplary embodiment of the present disclosure, the via holes on the third interlayer dielectric layer and the first planar layer are formed by a one-step patterning process using a half-tone mask.

[0033] In an exemplary embodiment of the present disclosure, the light-emitting unit includes a cathode layer and an anode layer that are arranged opposite to each other, and an organic light-emitting layer arranged between the cathode layer and the anode layer, the anode layer is located on a side of the third conductive layer away from the base substrate, and the cathode layer is located on a side of the anode layer away from the base substrate; the array substrate further includes:

[0034] The auxiliary cathode layer is disposed between the anode layer and the third conductive layer and is electrically connected to the cathode layer.

[0035] In an exemplary embodiment of the present disclosure, the auxiliary cathode layer is provided with a via hole, and the array substrate further includes:

[0036] An insulating layer, disposed between the third conductive layer and the light-emitting unit, wherein a via hole is disposed on the insulating layer;

[0037] A second flat layer is provided between the insulating layer and the light emitting unit, and a via hole is provided on the second flat layer;

[0038] The anode layer is electrically connected to the drain of the driving transistor at least through via holes on the auxiliary cathode layer, the insulating layer, and the second planar layer.

[0039] In an exemplary embodiment of the present disclosure, the via holes on the insulating layer and the second planar layer are formed by a one-step patterning process using a half-tone mask.

[0040] According to another aspect of the present disclosure, a display device is provided, comprising the array substrate described above.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0043] Figure 1 is a schematic structural diagram of an array substrate in this embodiment;

[0044] Figure 2 It is a 3T1C circuit structure of two pixel units;

[0045] Figure 3 It is a 3T1C circuit structure of one sub-pixel;

[0046] Figure 4 is a schematic diagram of the structure of the light-shielding layer;

[0047] Figure 5 is a schematic diagram of the structure of the active layer;

[0048] Figure 6 is a schematic diagram of the structure of the gate layer;

[0049] Figure 7 is a schematic diagram of vias on the first interlayer dielectric layer;

[0050] Figure 8 is a schematic structural diagram of a first conductive layer;

[0051] Fig. 9 is a schematic diagram of vias on the second interlayer dielectric layer;

[0052] Fig.10 is a schematic structural diagram of the second conductive layer;

[0053] Fig.11 A schematic diagram of vias on the third interlayer dielectric layer and the first planar layer;

[0054] Fig.12 is a schematic structural diagram of the third conductive layer;

[0055] Fig.13 is a schematic diagram of vias on the first insulating layer and the second planar layer;

[0056] Fig.14 is a schematic structural diagram of the auxiliary cathode layer;

[0057] Fig.15 is a schematic diagram of the structure of the anode layer;

[0058] Fig.16 A schematic diagram of the structure of the pixel definition layer.

[0059] Description of reference numerals:

[0060] 1. Base substrate; 100. Light shielding layer; 200. Buffer layer; 300. Active layer; 400. Gate insulating layer; 500. Gate layer; 600. First interlayer dielectric layer; 700. First conductive layer; 800. Second interlayer dielectric layer; 900. Second conductive layer; 1000. Third interlayer dielectric layer; 1100. First planar layer; 1200. Third conductive layer; 1300. First insulating layer; 1400. Second planar layer; 1500. Auxiliary cathode layer; 1600. Second insulating layer; 1700. Anode layer; 1800. Organic light emitting layer; 1900. Cathode layer; 2000. Pixel defining layer;

[0061] 11. first scanning line; 12. second scanning line; 20. data line; 30. power line; 40. sensing line; 51. first electrode plate; 52. second electrode plate; 53. third electrode plate; 54. fourth electrode plate; 61. first connecting part; 62. second connecting part; 63. third connecting part; 64. fourth connecting part; 65. fifth connecting part; 66. sixth connecting part; 67. seventh connecting part; 68. sensing connecting part;

[0062] 91, 92, 93, 94, vias. DETAILED DESCRIPTION

[0063] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0064] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0065] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0066] The present disclosure provides an array substrate, referring to Figure 1 , including a base substrate 1 and a data line 20, a power line 30, a sensing line 40, a pixel driving circuit and a light-emitting unit stacked in sequence on the base substrate 1, the pixel driving circuit includes a driving transistor T1 and a storage capacitor, the storage capacitor includes a first electrode and a second electrode, the first stage of the driving transistor T1 is electrically connected to the power line 30, the second stage is electrically connected to the light-emitting unit, and the gate is electrically connected to the second electrode of the storage capacitor.

[0067] The array substrate includes a gate layer 500, a first conductive layer 700, a second conductive layer 900 and a third conductive layer 1200. The gate layer 500 is provided on the base substrate 1, and the gate of the driving transistor is provided on the gate layer 500. The first conductive layer 700 is provided on the side of the gate layer 500 away from the base substrate 1, and the first electrode of the storage capacitor is at least provided on the first conductive layer 700. The second conductive layer 900 is provided on the side of the first conductive layer 700 away from the gate layer 500, and the second electrode of the storage capacitor is at least provided on the second conductive layer 900. The third conductive layer 1200 is provided on the side of the second conductive layer 900 away from the first conductive layer 700, and the data line 20, the power line 30, and the sensing line 40 are provided on the third conductive layer 1200.

[0068] The present disclosure sets three conductive layers on the gate layer 500, and the first conductive layer 700, the second conductive layer 900 and the third conductive layer 1200 can be regarded as the first source-drain layer, the second source-drain layer and the third source-drain layer, respectively. The first conductive layer 700 and the second conductive layer 900 are used to set the storage capacitor, and the third conductive layer 1200 is used to set the data line 20, the power line 30, and the sensing line 40, which provides sufficient wiring space for the signal line, and can reduce the resistance of the data line 20 and the IR drop of the power line 30 while meeting the driving refresh frequency. Compared with setting the above structures in one or two conductive layers, the wiring space pressure is greatly reduced, and for display products with a fixed horizontal size, a higher pixel PPI can be provided, which is particularly suitable for products with ultra-high pixel PPI. In addition, the present disclosure separates the scan line from the data line 20, the power line 30, and the sensing line 40, which reduces the probability of short circuit between layers on the basis of reducing the load, thereby improving the product yield.

[0069] The array substrate according to the embodiment of the present disclosure is described in detail below.

[0070] refer to Figure 2 and Figure 3 ,refer to Figure 2 The 3T1C circuit structure of two pixel units is shown. Figure 3 The 3T1C circuit structure of a sub-pixel is shown. The sub-pixel circuit structure includes a capacitor and three TFT transistors T1 to T9. In this embodiment, all TFTs are N-type TFTs, wherein the first transistor T1 is a driving transistor and the other transistors are switch transistors.

[0071] The capacitor includes a first electrode Cst1 and a second electrode Cst2, the first electrode Cst1 is connected to the node N1, and the second electrode Cst2 is connected to the node N2. The gate 1g of the driving transistor T1 (first transistor) is connected to the node N1, the source 1s is connected to the power line 30 (vdd), and the drain 1d is connected to the node N2. The gate 2g of the second transistor T2 is connected to the first scan line 11 (G1), the source 2s is connected to the data line 20 (data), and the drain 2d is connected to the node N1. The gate 3g of the third transistor T3 is connected to the second scan line 12 (G2), the source 3s is connected to the node N2, and the drain 3d is connected to the sensing line 40 (sense).

[0072] refer to Figure 2 Each pixel unit includes three sub-pixels, corresponding to a red sub-pixel, a green sub-pixel and a blue sub-pixel respectively. The gate electrodes 2g of the six second transistors T2 in the six sub-pixel circuit structure are commonly connected to the same first scan line (G1), the gate electrodes 3g of the six third transistors T3 are commonly connected to the same second scan line (G2), and the drain electrodes 3d of the six third transistors T3 are commonly connected to the same sense line (sense).

[0073] In this embodiment, the sub-pixel driving circuit of each sub-pixel is prepared on a base substrate 1. Figure 1 , an active layer 300, a gate layer 500, a first conductive layer 700, a second conductive layer 900, and a third conductive layer 1200 are sequentially stacked on the substrate 1 from bottom to top, and a light-emitting unit is also arranged on the third conductive layer 1200. In the present disclosure, the light-emitting unit takes an OLED light-emitting device as an example, and includes an anode layer 1700, an organic light-emitting layer 1800, and a cathode layer 1900 stacked from bottom to top. The two film layers are insulated by an insulating material, for example, a gate insulating layer 400 is arranged between the active layer 300 and the gate layer 500, a first interlayer dielectric layer 600 is arranged between the first conductive layer 700 and the second conductive layer 900, a second interlayer dielectric layer 800 is arranged between the first conductive layer 700 and the second conductive layer 900, and a third interlayer dielectric layer 1000 is arranged between the second conductive layer 900 and the third conductive layer 1200. An insulating layer is arranged between the third conductive layer 1200 and the anode layer 1700. A buffer layer 200 is also provided under the active layer 300 to protect the base substrate 1. The array substrate also includes a light shielding layer 100, which is located on the side of the active layer 300 away from the gate layer 500, specifically between the buffer layer 200 and the base substrate 1, and the projection of the light shielding layer 100 on the base substrate 1 overlaps with the gate of the driving transistor T1, so as to prevent the ambient light from the back from affecting the driving transistor T1. The OLED light-emitting devices of each sub-pixel are spaced apart by the pixel defining layer 2000.

[0074] Figure 4-Figure 16 The stacking schematic diagrams of the various film layers are shown in sequence. Figure 1 for Fig.16 Schematic diagram of the cross section along the AA direction.

[0075] Figure 4 is a schematic structural diagram of the light shielding layer 100 . Figure 5 3 is a schematic diagram of the structure of the active layer 300. The active layer 300 is used to set the channel region (1g-3g), the first level (1s-3s) and the second level (1d-3d) of each TFT transistor. Figure 6 Schematic diagram of the structure of the gate layer 500, the gate layer 500 is used to set the gates (such as 1g-3g) of each transistor in the sub-pixel driving circuit, as well as the first scan line 11 and the second scan line 12. The first scan line 11 and the second scan line 12 are arranged in a column direction and extend in a row direction, and are used to provide scan signals to each sub-pixel located in the same row in the row direction. In this embodiment, the first scan line 11 is located below the sub-pixel area, and the second scan line 12 is located above the sub-pixel area. In this embodiment, the gate 1g of the driving transistor T1 is reused as the second plate 52 of the storage capacitor.

[0076] Figure 7 The figure shows a via hole 91 disposed on the first interlayer dielectric layer 600. The first interlayer dielectric layer is a transparent film layer, so only the position of the via hole is shown in the figure. Figure 8 A schematic structural diagram of the first conductive layer 700 is shown.

[0077] A first electrode plate 51 of a storage capacitor is disposed in the first conductive layer 700 . The first electrode plate 51 and the second electrode plate 52 are electrically connected through a via hole to form a first electrode Cst1 of the storage capacitor.

[0078] A first connecting portion 61 is also provided in the first conductive layer 700. One end of the first connecting portion 61 is connected to the gate 1g of the driving transistor T1, and the other end is connected to the drain 2d of the second transistor through a via hole provided on the first interlayer dielectric layer 600, so as to connect the gate 1g of the driving transistor T1 with the drain 2d of the second transistor. The second connecting portion 62 is connected to the source 2s of the second transistor through a via hole provided on the first interlayer dielectric layer 600.

[0079] A third connection portion 63 and a fourth connection portion 64 are also provided in the first conductive layer 700. The third connection portion 63 is connected to the drain 3d of the third transistor through a via hole provided on the first interlayer dielectric layer 600. The fourth connection portion 64 is connected to the source 1s of the driving transistor T1 through a via hole provided on the first interlayer dielectric layer 600.

[0080] A fifth connecting portion 65 is further provided in the first conductive layer 700 . The fifth connecting portion 65 is connected to the drain 1d of the driving transistor T1 through a via hole provided in the first interlayer dielectric layer 600 , and is also connected to the light shielding layer 100 through via holes provided in the first interlayer dielectric layer 600 and the buffer layer 200 .

[0081] Fig. 9 The via hole 92 disposed on the second interlayer dielectric layer 800 is shown. Fig.10 A schematic structural diagram of the second conductive layer 900 is shown.

[0082] The third electrode plate 53 of the storage capacitor is disposed in the second conductive layer 900. In this embodiment, the third electrode plate 53 is connected to the fifth connecting portion 65 through a via hole disposed on the second interlayer dielectric layer 800, so that the light shielding layer 100 is connected to the third electrode plate 53, and the light shielding layer 100 can be reused as the fourth electrode plate 54. The third electrode plate 53 and the fourth electrode plate 54 are electrically connected through the via hole to form the second electrode Cst2 of the storage capacitor. Since the light shielding layer 100 needs to be reused as the fourth electrode plate 54, the light shielding layer 100 needs to be conductive, and it can be made of a conductive material such as metal.

[0083] Among the above-mentioned four plates, the projections of the first plate 51 and the third plate 53 on the substrate 1 overlap, forming a first storage capacitor; the projections of the first plate 51 and the fourth plate 54 on the substrate 1 overlap, forming a second storage capacitor; the projections of the second plate 52 and the fourth plate 54 on the substrate 1 overlap, forming a third storage capacitor; the first storage capacitor, the second storage capacitor and the third storage capacitor are connected in parallel to form a storage capacitor, which can improve the capacitor storage effect.

[0084] A sensing connection portion 68 is also provided in the second conductive layer 900. The sensing connection portion 68 is electrically connected to the second stage 3d of the third transistor T3 through a via hole provided on the second interlayer dielectric layer 800. In this embodiment, the sensing connection portions 68 of the six sub-pixels in every two pixel units are connected as a whole and extend in the row direction as a whole.

[0085] A sixth connection portion 66 and a seventh connection portion 67 are also provided in the second conductive layer 900 . The sixth connection portion 66 is connected to the second connection portion 62 through a via hole provided on the second interlayer dielectric layer 800 . The seventh connection portion 67 is connected to the fourth connection portion 64 through a via hole provided on the second interlayer dielectric layer 800 .

[0086] Fig.11 The via holes 93 provided on the third interlayer dielectric layer 1000 and the first planar layer 1100 are shown. Fig.12 A schematic structural diagram of the third conductive layer 1200 is shown.

[0087] The third conductive layer 1200 is provided with a data line 20, a power line 30 and a sensing line 40. The sensing line 40 is electrically connected to the sensing connection part 68 through a via hole provided on the third interlayer dielectric layer 1000, so that the second stage of the third transistor is connected to the sensing line 40. The sensing connection part 68 in every two pixel units is connected to the sensing line 40 through a via hole provided on the third interlayer dielectric layer 1000. In this embodiment, the via hole is located between the two pixel units. The data line 20 is connected to the sixth connection part 66 through a via hole provided on the third interlayer dielectric layer 1000, and then connected to the source 2s of the second transistor through the second connection part 62, so as to apply a data voltage to the second transistor. The power line 30 is connected to the seventh connection part 67 through a via hole provided on the third interlayer dielectric layer 1000, and then connected to the source 1s of the driving transistor T1 through the fourth connection part, so as to apply a power supply voltage to the driving transistor T1. In this embodiment, three sub-pixels in each pixel unit share a power line 30 , and each sub-pixel corresponds to its own data line 20 .

[0088] Furthermore, a first flat layer 1100 is disposed between the second conductive layer 900 and the third conductive layer 1200, and a via is also disposed on the first flat layer 1100. The structures in the second conductive layer 900 and the third conductive layer 1200 are electrically connected through the vias in the third interlayer dielectric layer 1000 and the vias in the first flat layer 1100. The first flat layer 1100 can increase the thickness between the third conductive layer 1200 and the gate layer 500, reduce the overlap capacitance, and reduce the risk of short circuit, thereby improving the yield.

[0089] It should be noted that, since the positions of the via holes on the third interlayer dielectric layer 1000 and the first planar layer 1100 overlap, Fig.11 The via holes indicated by 93 include hexagonal via holes on the third interlayer dielectric layer 1000 and triangular via holes on the first flat layer 1100. The via holes on the third interlayer dielectric layer 1000 and the via holes on the first flat layer 1100 can be formed by etching in two steps, or by a one-step patterning process using a half-tone mask, thereby reducing the number of photolithography steps.

[0090] Fig.13 The via holes 94 disposed on the first insulating layer 1300 and the second planarizing layer 1400 are shown. Fig.14 A schematic structural diagram of the auxiliary cathode layer 1500 is shown. Fig.15 A schematic structural diagram of the anode layer 1700 is shown. Fig.16 A schematic structural diagram of a pixel defining layer 2000 is shown.

[0091] The array substrate further includes an auxiliary cathode layer 1500 , which is disposed between the anode layer 1700 and the third conductive layer 1200 and electrically connected to the cathode layer 1900 , thereby reducing the resistance of the cathode layer 1900 and thereby reducing the IRDrop of vss.

[0092] A second insulating layer 1600 is provided between the auxiliary cathode layer 1500 and the anode layer 1700. A first insulating layer 1300 and a second flat layer 1400 are provided between the auxiliary cathode layer 1500 and the third conductive layer 1200. Vias 94 are provided on the first insulating layer 1300 and the second flat layer 1400. Vias are also provided on the auxiliary cathode layer 1500. The anode layer 1700 is connected to the third electrode plate 53 through the vias on the auxiliary cathode layer 1500, the first insulating layer 1300 and the second flat layer 1400, and then connected to the drain 1d of the driving transistor T1 via the fifth connecting portion 65, so that the anode layer 1700 is connected to the drain 1d of the driving transistor T1. The design of the second flat layer 1400 can also reduce the overlap capacitance between the auxiliary cathode layer 1500 and the third conductive layer 1200, and can also reduce the risk of short circuit and thus improve the yield.

[0093] In another embodiment, the auxiliary cathode layer may not be provided, and the anode layer 1700 is connected to the third electrode plate 53 through a via provided on the insulating layer, and further connected to the drain 1d of the driving transistor T1 via the fifth connecting portion 65, so that the anode layer 1700 is connected to the drain 1d of the driving transistor T1.

[0094] The Disclosure Figure 1 The array substrate shown has an impedance load reduced by about 40%, and the overlap capacitance between Gate and SD3 is also reduced accordingly (the impedance load is reduced by about 15%). While effectively reducing the impedance load, the VDD IR Drop is also reduced accordingly, providing technical support for large-size ultra-high PPI.

[0095] The following is an explanation of the method for preparing the array substrate disclosed in the present invention. Figure 1 The array substrate shown in the figure, the preparation method comprises:

[0096] In step S100 , a base substrate 1 is provided, and a light shielding layer 100 and a buffer layer 200 covering the light shielding layer 100 are formed on the base substrate 1 .

[0097] Step S200, forming an active layer 300, a gate insulating layer 400 and a gate layer 500 on the buffer layer 200 to form a driving transistor T1, a second transistor and a third transistor. The gate 1g of the driving transistor T1 is reused as the second electrode 52 of the storage capacitor.

[0098] Step S300, forming a first interlayer dielectric layer 600 and a first conductive layer 700 above the gate layer 500, so that the first conductive layer 700 includes a first plate 51 of the storage capacitor, and the first plate 51 and the second plate are connected through a via hole on the first interlayer dielectric layer 600. The first conductive layer 700 also includes a fifth connecting portion 65, and the fifth connecting portion 65 is connected to the light shielding layer 100 through a via hole on the first interlayer dielectric layer 600.

[0099] The first conductive layer 700 also includes a first connection portion 61 to a fifth connection portion 65. The first connection portion 61 is used to connect the gate 1g of the driving transistor T1 to the drain 2d of the second transistor. The second connection portion 62 is connected to the source 2s of the second transistor through a via hole provided on the first interlayer dielectric layer 600. The third connection portion 63 is connected to the drain 3d of the third transistor through a via hole provided on the first interlayer dielectric layer 600. The fourth connection portion is connected to the source 1s of the driving transistor T1 through a via hole provided on the first interlayer dielectric layer 600. The fifth connection portion 65 is connected to the drain 1d of the driving transistor T1 through a via hole provided on the first interlayer dielectric layer 600, and is also connected to the light shielding layer 100 through a via hole provided on the first interlayer dielectric layer 600 and the buffer layer 200.

[0100] In step S400, a second interlayer dielectric layer 800 and a second conductive layer 900 are formed above the first conductive layer 700, so that the second conductive layer 900 includes a third electrode 53 of the storage capacitor, and the third electrode 53 is connected to the fifth connecting portion 65 through a via hole on the second interlayer dielectric layer 800, and then connected to the shading layer 100, and the shading layer 100 is reused as the fourth electrode 54 of the storage capacitor.

[0101] The first electrode plate 51 and the third electrode plate 53 form a first storage capacitor, the first electrode plate 51 and the fourth electrode plate 54 form a second storage capacitor, the second electrode plate 52 and the fourth electrode plate 54 form a third storage capacitor, and the first storage capacitor, the second storage capacitor and the third storage capacitor are connected in parallel to form a storage capacitor.

[0102] The second conductive layer 900 further includes a sensing connection portion 68, a sixth connection portion 66, and a seventh connection portion 67. The sensing connection portion 68 is electrically connected to the second stage of the third transistor through a via hole on the first interlayer dielectric layer 600. The sixth connection portion 66 is connected to the second connection portion 62 through a via hole provided on the second interlayer dielectric layer 800, and the seventh connection portion 67 is connected to the fourth connection portion through a via hole provided on the second interlayer dielectric layer 800.

[0103] Step S500, forming a third interlayer dielectric layer 1000, a first flat layer 1100 and a third conductive layer 1200 on the second conductive layer 900, so that the third conductive layer 1200 includes a data line 20, a power line 30 and a sensing line 40. The sensing line 40 is connected to the sensing connection part 68 through the via holes on the third interlayer dielectric layer 1000 and the first flat layer 1100, and is further connected to the second stage of the third transistor. The data line 20 is connected to the sixth connection part 66 through the via holes set on the third interlayer dielectric layer 1000 and the first flat layer 1100, and is further connected to the source 2s of the second transistor through the second connection part 62. The power line 30 is connected to the seventh connection part 67 through the via holes set on the third interlayer dielectric layer 1000 and the first flat layer 1100, and is further connected to the source 1s of the driving transistor T1 through the fourth connection part.

[0104] Step S600, a first insulating layer 1300, a second flat layer 1400, an auxiliary cathode layer 1500, and a second insulating layer 1600 are sequentially formed on the third conductive layer 1200, and via holes are formed on these film layers. Then, a light-emitting unit is formed on the second insulating layer 1600, wherein the anode layer 1700 is connected to the third electrode plate 53 through the via holes on the auxiliary cathode layer 1500, the first insulating layer 1300, the second flat layer 1400, and the second insulating layer 1600, and then connected to the drain 1d of the driving transistor T1 via the fifth connecting portion 65, so that the anode layer 1700 is connected to the drain 1d of the driving transistor T1.

[0105] Then, a pixel defining layer 2000 having an opening area is formed, the opening area exposes the anode layer 1700, and an organic light emitting layer 1800 is formed in the opening area. Finally, a cathode layer 1900 is formed and connected to the auxiliary cathode layer 1500.

[0106] Follow the above steps to gradually form Figure 1 In the structure process shown, a total of 16 mask processes are required. In order to reduce the process steps, in step S300, when forming via holes on the first interlayer dielectric layer 600 and the buffer layer 200, a half-tone mask can be used to form via holes through a one-step etching process. In step S500, when forming via holes on the third interlayer dielectric layer 1000 and the first flat layer 1100, a half-tone mask can be used to form via holes through a one-step etching process. In step S600, when forming via holes on the first insulating layer 1300 and the second flat layer 1400, a half-tone mask can be used to form via holes through a one-step etching process.

[0107] Taking step S500 as an example, when etching is performed using a halftone mask, a third interlayer dielectric layer 1000 is first formed on the entire surface through deposition and other processes, and then a first flat layer 1100 is formed on the entire surface through printing and other processes. Finally, a halftone mask is used to form vias of different depths at the locations where vias are required using a photolithography process.

[0108] The use of this etching method allows the entire process to be performed with only 14 mask processes, thereby improving preparation efficiency, saving the number of mask plates, and reducing processing costs. Of course, the vias on the two film layers can also be formed by etching in two steps.

[0109] It should be noted that, although the steps of the disclosed method are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0110] The present disclosure also provides a display device, comprising the array substrate in the above embodiment. Since the display device comprises the above array substrate, it has the same beneficial effects, and the present disclosure will not repeat them here.

[0111] The present disclosure does not impose any specific restrictions on the applicability of display devices, which can be any product or component with flexible display function, such as televisions, laptops, tablet computers, wearable display devices, mobile phones, car displays, navigation, e-books, digital photo frames, advertising light boxes, etc.

[0112] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, comprising a base substrate and a scanning line, a data line, a power line, a sensing line, a pixel driving circuit and a light-emitting unit stacked in sequence on the base substrate, wherein the pixel driving circuit comprises a driving transistor and a storage capacitor, the storage capacitor comprises a first electrode and a second electrode, the first stage of the driving transistor is electrically connected to the power line, the second stage is electrically connected to the light-emitting unit, and the gate is electrically connected to the second electrode of the storage capacitor; characterized in that: The array substrate comprises: A gate layer, disposed on the base substrate, wherein the scanning line and the gate of the driving transistor are disposed on the gate layer; A first conductive layer is provided on a side of the gate layer away from the base substrate, and a first electrode of the storage capacitor is at least provided on the first conductive layer; A second conductive layer is provided on a side of the first conductive layer away from the gate layer, and the second electrode of the storage capacitor is at least provided on the second conductive layer; A third conductive layer is provided on a side of the second conductive layer away from the first conductive layer, and the data line, the power line, and the sensing line are provided on the third conductive layer; The array substrate further includes a third interlayer dielectric layer and a first flat layer located between the second conductive layer and the third conductive layer, the third interlayer dielectric layer and the first flat layer are both full-surface structures with vias, the second electrode of the storage capacitor is located on a side of the first flat layer away from the third conductive layer, and the first flat layer and the second electrode of the storage capacitor have an overlapping area in the thickness direction of the array substrate; The scan line includes a first scan line and a second scan line, the pixel driving circuit also includes a second transistor and a third transistor, the gate of the second transistor is electrically connected to the first scan line, the first level of the second transistor is electrically connected to the data line, the second level of the second transistor is electrically connected to the gate of the driving transistor, the gate of the third transistor is electrically connected to the second scan line, the first level of the third transistor is multiplexed as the second level of the driving transistor, and the second level of the third transistor is electrically connected to the sensing line; The array substrate also includes a sensing connection portion, which is arranged on the second conductive layer and is electrically connected to the second level of the third transistor through a via hole. The sensing connection portions of six sub-pixels in every two pixel units are connected as a whole. The sensing connection portion is also electrically connected to the sensing line through a via hole, and the via hole connecting the sensing connection portion and the sensing line is located between the two pixel units.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises an active layer, wherein the active layer is arranged between the base substrate and the gate layer; The first electrode of the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the first conductive layer, the second electrode plate is arranged on the gate layer, the first electrode plate and the second electrode plate are electrically connected through a via hole; the second electrode plate is also electrically connected to the gate of the driving transistor; The second electrode of the storage capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate is arranged on the second conductive layer, the fourth electrode plate is arranged at least on a side of the active layer away from the gate layer, the third electrode plate and the fourth electrode plate are electrically connected through a via hole; the third electrode plate is also electrically connected to the light-emitting unit; The projections of the first electrode plate and the third electrode plate on the substrate overlap to form a first storage capacitor; the projections of the first electrode plate and the fourth electrode plate on the substrate overlap to form a second storage capacitor; the projections of the second electrode plate and the fourth electrode plate on the substrate overlap to form a third storage capacitor; The first storage capacitor, the second storage capacitor and the third storage capacitor are connected in parallel to form the storage capacitor.

3. The array substrate according to claim 2, characterized in that: The gate of the driving transistor is reused as the second electrode plate.

4. The array substrate according to claim 3, characterized in that: The array substrate further includes a light shielding layer, which is located on a side of the active layer away from the gate layer, and a projection of the light shielding layer on the base substrate overlaps with the gate of the driving transistor.

5. The array substrate according to claim 4, characterized in that: The light shielding layer is reused as the fourth electrode plate.

6. The array substrate according to claim 5, characterized in that: The array substrate further includes: A buffer layer is provided between the active layer and the light shielding layer, and a via hole is provided on the buffer layer; A first interlayer dielectric layer is provided between the active layer and the first conductive layer, and a via is provided on the first interlayer dielectric layer; A second interlayer dielectric layer is provided between the first conductive layer and the second conductive layer, and a via hole is provided on the second interlayer dielectric layer; The third electrode plate and the fourth electrode plate are connected through via holes on the buffer layer, the first interlayer dielectric layer and the second interlayer dielectric layer.

7. The array substrate according to claim 6, characterized in that: The via holes on the buffer layer and the first interlayer dielectric layer are formed by a one-step patterning process using a half-tone mask.

8. The array substrate according to claim 1, characterized in that: The sensing connection portion and the sensing line are electrically connected through via holes on the third interlayer dielectric layer and the first planar layer.

9. The array substrate according to claim 8, characterized in that: The via holes on the third interlayer dielectric layer and the first flat layer are formed by a one-step patterning process using a half-tone mask.

10. The array substrate according to claim 5, characterized in that: The light-emitting unit includes a cathode layer and an anode layer that are arranged opposite to each other, and an organic light-emitting layer arranged between the cathode layer and the anode layer, the anode layer is located on a side of the third conductive layer away from the base substrate, and the cathode layer is located on a side of the anode layer away from the base substrate; the array substrate also includes: The auxiliary cathode layer is disposed between the anode layer and the third conductive layer and is electrically connected to the cathode layer.

11. The array substrate according to claim 10, characterized in that: The auxiliary cathode layer is provided with a via hole, and the array substrate further comprises: An insulating layer, disposed between the third conductive layer and the light-emitting unit, wherein a via hole is disposed on the insulating layer; A second flat layer is provided between the insulating layer and the light emitting unit, and a via hole is provided on the second flat layer; The anode layer is electrically connected to the drain of the driving transistor at least through via holes on the auxiliary cathode layer, the insulating layer, and the second planar layer.

12. The array substrate according to claim 11, characterized in that: The via holes on the insulating layer and the second planar layer are formed by a one-step patterning process using a half-tone mask.

13. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 12.

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