Transmitter with equalization function

Abstract

A transmitter with low power and robust equalization functionality is provided. The transmitter includes a transmitter driver and a driver bias circuit. The transmitter driver receives data and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to increase the level of a bias signal of the transmitter driver in response to a transition in the data.

Description

Technical Field

[0001] The present invention relates to a transmitter with an equalization function. Background Art

[0002] In telecommunications and data transmission, the demand for serial communications continues to grow. Serial links need to achieve large data throughput and low power consumption per bit.

[0003] However, high-speed serial links can incur considerable insertion loss. Equalization refers to the reversal of the distortion induced by the signal transmitted through the channel, which flattens the frequency response from one end to the other. The power of the equalizer is proportional to the number of equalization nodes (N), the signal frequency at the equalization node (F), the capacitance of the equalization node (C), and the voltage level at the equalization node (V). For example, the equalization power can be expressed as N*F*C*V 2 Conventional equalizers can result in considerable power consumption.

[0004] In conventional designs, the equalizer is placed at the output of the transmitter's driver. Figure 1A A transmitter 100 is depicted, which includes a pre-cursor driver slice 102, a main-cursor driver slice 104, and a post-cursor driver slice 106. By summing the outputs of the pre-cursor driver slice 102, the main-cursor driver slice 104, and the post-cursor driver slice 106, the strength of the high-frequency portion of the signal is enhanced, wherein a 64-bit input Din is input to the TX data path.

[0005] Figure 1B The waveforms of the transmitter 100 are depicted. The output of the master driver slice 104 is 112.

[0006] In the absence of a timing shift, the output of the post-marker driver slice 106 is 114, and the final waveform 116 is generated by subtracting 114 from 112. As shown, the frequent transitions in the main mark output 112 are reflected in the output 114 of the post-marker driver slice 106 at the appropriate time, and the strength of the high-frequency portion of the signal in the final waveform 116 is successfully enhanced to compensate for the transmission loss of the channel.

[0007] With the time offset, the output of the post-script driver slice 106 is 118, and the final waveform 120 is produced by subtracting 118 from 112. The final waveform 120 shows poor equalization.

[0008] The shortcomings of the transmitter 100 are discussed in this section. All networks (including the front-end driver slice 102, the main-end driver slice 104, the rear-end driver slice 106 and the positive differential output terminal TX P and negative differential output TX N ) all run at high speed, which consumes significant power. Timing skew can result in poor equalization (see final waveform 120). When a direct-current (DC) signal with a high output from the primary driver slice 104 and a low output from the secondary driver slice 106 is transmitted, additional power consumption may occur due to short-circuit current between the primary driver slice 104 and the secondary driver slice 106.

[0009] There is a need for a transmitter with low power and robust equalization capabilities. Summary of the Invention

[0010] A transmitter according to an exemplary embodiment of the present invention includes a transmitter driver and a bias circuit for the driver. The transmitter driver receives data and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver and is configured to increase the level of a bias signal of the transmitter driver in response to data conversion. In one embodiment, an increased bias voltage or bias current is provided to the transmitter driver during the period when the data is converted at the highest frequency. The data is differential data.

[0011] The present invention configures the bias circuit of the driver to increase the level of the bias signal of the transmitter driver in response to the conversion of the data, so that the transmitter has a more robust equalization function.

[0012] The bias circuit of the driver may be coupled to the common node of the transmitter's driver.In the present invention it is proposed to perform equalization on the common node of the transmitter's driver rather than on the output of the transmitter's driver.

[0013] In an exemplary embodiment, the driver of the transmitter is a voltage-mode driver. The bias circuit of the driver is configured to increase a voltage level of a common node of the voltage-mode driver in response to a transition of data.

[0014] In another exemplary embodiment, the driver of the transmitter is a current mode driver. The bias circuit of the driver is configured to increase a current level of a common node of the current mode driver in response to a transition of data.

[0015] In the following embodiments, a detailed description is given with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention may be more fully understood by reading the following detailed description and examples with reference to the accompanying drawings, in which:

[0017] Figure 1A A transmitter 100 is depicted, which includes a front-end driver slice 102 , a main-end driver slice 104 , and a rear-end driver slice 106 ;

[0018] Figure 1B The waveform of the transmitter 100 is shown;

[0019] Figure 2A shows a block diagram of a transmitter 200 according to an exemplary embodiment of the present invention;

[0020] Figure 2B The waveform of the transmitter 200 is shown;

[0021] Figure 3 depicts a detailed circuit for an equalization design for a voltage-mode transmitter according to an exemplary embodiment of the present invention;

[0022] Figure 4 depicts a detailed circuit for an equalization design for a voltage-mode transmitter according to another exemplary embodiment of the present invention;

[0023] Figure 5 depicts a detailed circuit for an equalization design for a current mode transmitter according to an exemplary embodiment of the present invention; and

[0024] Figure 6 Depicted is a detailed circuit for a balanced design of a current mode transmitter according to another exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following description shows an exemplary embodiment of the present invention. This description is for the purpose of illustrating the general principles of the present invention and should not be considered as limiting the present invention. The scope of the present invention is determined by the appended claims.

[0026] Figure 2A is a block diagram depicting a transmitter 200 according to an exemplary embodiment of the present invention.

[0027] The transmitter 200 includes a transmitter data path 202, a transmitter driver 204, and a driver bias circuit 206. The transmitter data path 202 outputs data (the positive portion of the data P and negative part data N Driver 204 receives data (indicated by data P and data N ), and thus generates a positive differential output TX to be transmitted by the transmitter 200P and negative differential output TX N The driver bias circuit 206 is coupled to the transmitter driver 204 to bias the transmitter driver 204 and is configured to increase the level of the bias signal of the transmitter driver 204 in response to the transition of the data. EQ The driver bias circuit 206 is activated to increase the level of the bias signal of the transmitter driver 204. The transmitter data path 202 generates the control signal data EQ To indicate the conversion of data.

[0028] exist Figure 2A In the example, the main driver slice 208 is based on the positive portion of the data P Generates positive differential output TX P , and the master driver slice 210 is based on the negative portion of the data data N Generates negative differential output TX N The bias circuit 206 of the driver is coupled to the common net between the plurality of master driver slices 208 and the plurality of master driver slices 210. The common net of the transmitter driver 204 is not coupled to the differential output terminals (output TX) of the transmitter driver 204. P and TX N ) performs balancing. The common node may be a common mode node.

[0029] Figure 2B Waveforms are shown for transmitter 200. Waveform 212 shows the data to be transmitted.

[0030] In the absence of a time offset, waveform 214 shows the change in the level of the bias signal (wherein the bias signal includes a bias current or a bias voltage, and in this embodiment, may be a bias voltage LDO) of the transmitter driver 204, generating a final waveform 216 actually transmitted by the transmitter 200. As shown in the figure, in response to the frequent data transitions shown in waveform 212, the level of bias signal (LDO) 214 increases at the appropriate time, and in the final waveform 216, the strength of the high-frequency portion of the signal is successfully enhanced to compensate for the transmission loss of the channel. In other words, during the frequent data transition intervals, the signal strength in the final waveform 216 is successfully enhanced.

[0031] Waveform 218 shows that, with time offset, the change in the level of the bias signal (LDO) of transmitter driver 204 is delayed, resulting in the final waveform 220 actually transmitted by transmitter 200. As shown, final waveform 220 is not significantly affected by the time delay, and the equalization effect is very good. Simple error correction techniques are sufficient to address the imperfect equalization that appears in final waveform 220.

[0032] The advantages of the transmitter 200 are described in this paragraph. Referring to the LDO waveforms 214 and 218, there is no transition in the level of the bias signal (LDO) during the frequent data conversion intervals, thereby saving a lot of power. As shown in the final waveform 220, the equalization at the common node of the transmitter's driver 204 is insensitive to time offset. In addition, when transmitting a direct current (DC) signal, there is no need to increase the level of the bias signal (LDO). The driving current is at a preset level, which also saves power. Specifically, the equalization strength is clearly defined by the level of the bias signal and the termination resistor. As for the number of equalization nodes, the transmitter 200 uses only one equalization node (e.g., the common node), which is less than the equalization node (TX 100) used in the transmitter 100. P and TX N Because the balancing power is proportional to the number of balancing nodes, the balancing power consumed by the transmitter 200 is lower than the balancing power consumed by the transmitter 100. The balancing power is the power consumed in performing the balancing operation.

[0033] Figure 3 Depicted is a detailed circuit for an equalization design for a voltage-mode transmitter according to an exemplary embodiment of the present invention.

[0034] The transmitter driver (204) is implemented by a voltage mode driver 302. The voltage mode driver 302 includes four switches 304, 306, 308 and 310 and two output terminals 312 and 314. The two output terminals 312 and 314 output positive differential outputs TX P and negative differential output TX N Based on the positive part of the data (data P ) switch 304 is closed to couple the output terminal 312 to the common node 316. Based on the negative portion of the data (data N ) switch 306 is closed to couple the output terminal 312 to ground. N ) switch 308 is closed to couple the output terminal 314 to the common node 316. Based on the positive portion of the data (data P )Switch 310 is closed to couple output terminal 314 to ground.

[0035] The bias circuit 318 of the driver includes two transistors 320 and 322 and a switch 324. The transistors 320 and 322 are referenced to a voltage V LDO Bias. Transistor 320 is coupled between the supply voltage and the common node 316. When switch 324 is closed, transistor 322 is coupled between the supply voltage and the common node 316 and is biased according to the control signal data. EQ , close switch 324. Figure 3 In the example, there is a transition detection circuit 326, which is configured to detect data (by data P and data N In response to the conversion of the data, a control signal data is generated. EQ To close the switch 324. The transition detection circuit 326 includes a delay unit 321 and an XOR gate 330. The delay unit 321 delays the positive portion of the data data P The XOR gate 330 is based on the positive part of the data. P and delayed data P Output control signal data EQ In response to the data conversion, the control signal data EQ is high, and switch 324 is closed. Therefore, during frequent data conversion, the control signal data EQ is high, switch 324 is closed. Figure 3 In the embodiment, transistors 320 and 322 are n-type metal oxide semiconductor (NMOS) transistors. When switch 324 is closed, the size of the conductive transistor increases, so that the voltage difference V between transistors 320 and 322 GS decreases, and the voltage level of the common node 316 (V LDO -V GS ) increases. Successfully enhances the power from TX during frequent data conversion intervals P and TX N The strength of the transmitted differential signal.

[0036] Figure 4 FIG4 depicts a detailed circuit diagram of a balanced design for a voltage-mode transmitter according to another exemplary embodiment of the present invention. The bias circuit of the driver includes a transistor 402 coupled between a supply voltage and a common node 404 of the voltage-mode driver. Optionally, the structure of the transition detection circuit in FIG4 can be similar to that of FIG4. Figure 3 The structure of the conversion detection circuit 326 is the same as that in FIG. 1 , and will not be described in detail here. EQ When no data conversion is indicated, the reference voltage V LDOBias transistor 402. Otherwise, by the reference voltage V LDO The boosted value biases transistor 402. For example, in response to the conversion of data, the control signal data EQ is high, at this time, the reference voltage V LDO The boosted value biases transistor 402. Figure 4 In the example, transistor 402 is an NMOS transistor. Due to the increase in V LDO , the voltage level of the common node 404 (V LDO -V GS ) has been improved. Successfully enhanced the TX P and TX N The strength of the transmitted differential signal.

[0037] Figure 5 Depicted is a detailed circuit for an equalization design for a current mode transmitter according to an exemplary embodiment of the present invention.

[0038] The transmitter driver (204) is implemented by a current mode driver 502. The current mode driver 502 includes two output transistors 504 and 506, two resistors 508 and 510, and two output terminals 512 and 514. The two output terminals 512 and 514 output positive differential outputs TX P and negative differential output TX N The output transistor 504 is coupled between the common node 516 of the current mode driver 502 and the output terminal 512 and is configured to output the current mode driver 502 in accordance with the negative portion of the data. N ) to control the output transistor 504. The resistor 508 is coupled between the output terminal 512 and the ground. The output transistor 506 is coupled between the common node 516 and the output terminal 514 and is connected to the output terminal 514 according to the positive part of the data (data P ) to control the output transistor 506. A resistor 510 is coupled between an output terminal 514 and ground. The output transistors 504 and 506 are p-type metal oxide semiconductor (PMOS) transistors.

[0039] The driver bias circuit 518 includes two transistors 520 and 522 and a switch 524. Transistors 520 and 522 are biased by a voltage V B Bias. Transistor 520 is coupled between the supply voltage and the common node 516. When switch 524 is closed, transistor 522 is coupled between the supply voltage and the common node 516 and is biased according to the control signal data. EQ , the switch 524 is closed. In response to the conversion of the data, the control signal data EQ is high, and switch 524 is closed. Figure 5 In FIG, transistors 520 and 522 are PMOS transistors. When switch 524 is closed, transistor 522 provides additional current to increase the current level of common node 516. This successfully enhances the current from TX during frequent data transition intervals. P and TX N The strength of the transmitted differential signal.

[0040] Figure 6 FIG6 depicts a detailed circuit diagram of a balanced design for a current mode transmitter according to another exemplary embodiment of the present invention. The bias circuit of the driver includes a transistor 602 coupled between a supply voltage and a common node 604 of the current mode driver. Optionally, the structure of the transition detection circuit in FIG6 can be the same as Figure 5 The structure of the conversion detection circuit 326 is the same as that in FIG. 1 , and will not be described in detail here. EQ When no data conversion is indicated, the bias voltage V B Bias transistor 602. Otherwise, the bias voltage V B For example, in response to the transition of data, the control signal data EQ is high, at this time, the bias voltage V B The suppression value biases transistor 602. Figure 6 In the example, transistor 602 is a PMOS transistor. Since V B , so the current level of the common node 604 is increased. Successfully enhances the current from TX during the frequent data conversion intervals P and TX N The strength of the transmitted differential signal.

[0041] There are many designs for the aforementioned voltage mode driver, current mode driver, driver bias circuit and transition detection circuit. Any transmitter having an equalization function on the common node of the transmitter driver should be considered within the scope of protection of the present invention.

[0042] Although the present invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (which will be obvious to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation so as to cover all such modifications and similar arrangements.

Claims

1. A transmitter, characterized in that: include: a transmitter driver that receives data and generates positive and negative differential outputs to be transmitted by the transmitter; as well as A driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to increase a level of a bias signal of the transmitter driver in response to a transition of the data; wherein the level of the bias signal is constant during frequent data transition intervals.

2. The transmitter according to claim 1, wherein The bias circuit of the driver is coupled to a common node of the driver of the transmitter, wherein the common node is a common mode node.

3. The transmitter according to claim 2, characterized in that The transmitter's driver is a voltage mode driver; and The bias circuit of the driver is configured to increase a voltage level of a common node of the voltage-mode driver in response to a transition of the data.

4. The transmitter according to claim 3, characterized in that The driver bias circuit comprises: a first transistor biased by a reference voltage and coupled between a supply voltage and the common node; and A second transistor is biased by the reference voltage and a switch, wherein when the switch is closed, the second transistor is coupled between the supply voltage and the common node, and the switch is closed in response to the transition of the data.

5. The transmitter according to claim 4, characterized in that The transition detection circuit is configured to detect a transition of the data and generate a control signal to close the switch in response to the transition of the data.

6. The transmitter according to claim 4, characterized in that The first transistor and the second transistor are n-type metal oxide semiconductor transistors.

7. The transmitter according to claim 3, characterized in that The bias circuit of the driver includes: a transistor biased by a reference voltage and coupled between a supply voltage and a common node, The reference voltage is increased in response to the conversion of the data.

8. The transmitter according to claim 7, characterized in that The transistor is an n-type metal oxide semiconductor transistor.

9. The transmitter according to claim 3, characterized in that The voltage mode driver comprises: a first switch, a second switch, a third switch, and a fourth switch; and a first output terminal for outputting the positive differential output, and a second output terminal for outputting the negative differential output, in: In response to a positive portion of the data, the first switch is closed to couple the first output terminal to the common node; According to a negative portion of the data, the second switch is closed to ground the first output terminal; According to a negative portion of the data, the third switch is closed to couple the second output terminal to the common node; and According to a positive portion of the data, the fourth switch is closed to couple the second output terminal to ground.

10. The transmitter according to claim 2, characterized in that The driver of the transmitter is a current mode driver; as well as The bias circuit of the driver is configured to increase a current level of a common node of the current mode driver in response to a transition of the data; The current mode driver comprises: a first output transistor, a second output transistor, a first resistor, and a second resistor; and The first output terminal is used to output a positive differential output, and the second output terminal is used to output a negative differential output, wherein: The first output transistor is coupled between the common node and the first output terminal, and is controlled according to a negative portion of the data; The first resistor is coupled between the first output terminal and ground; The second output transistor is coupled between the common node and the second output terminal, and is controlled according to a positive portion of the data; and The second resistor is coupled between the second output terminal and the ground.

11. The transmitter according to claim 10, characterized in that The bias circuit of the driver includes: a first transistor biased by a bias voltage and coupled between a supply voltage and the common node; A second transistor is biased by the bias voltage and a switch, wherein when the switch is closed, the second transistor is coupled between the supply voltage and the common node, and the switch is closed in response to the transition of the data.

12. The transmitter according to claim 11, characterized in that Further including: The transition detection circuit is configured to detect a transition of the data and generate a control signal to close the switch in response to the transition of the data.

13. The transmitter according to claim 5 or 12, characterized in that The conversion detection circuit comprises: a delay unit that delays a positive portion of the data; and The XOR gate outputs the control signal according to the positive part of the data and the positive part of the delayed data.

14. The transmitter according to claim 11, characterized in that The first transistor and the second transistor are p-type metal oxide semiconductor transistors.

15. The transmitter according to claim 10, characterized in that The bias circuit of the driver includes: A transistor is biased by a bias voltage and coupled between a supply voltage and the common node, wherein the bias voltage is suppressed in response to the transition of the data.

16. The transmitter according to claim 15, characterized in that The transistor is a p-type metal oxide semiconductor transistor.

17. The transmitter according to claim 10, characterized in that The first output transistor and the second output transistor are p-type metal oxide semiconductor transistors.

18. A transmitter, characterized in that: include: a transmitter driver that receives data and generates positive and negative differential outputs to be transmitted by the transmitter; as well as a driver bias circuit coupled to the transmitter driver to bias the transmitter driver; wherein the driver of the transmitter is a current mode driver; and The bias circuit of the driver is configured to increase a current level of a common node of the current mode driver in response to a transition of the data; The current mode driver comprises: a first output transistor, a second output transistor, a first resistor, and a second resistor; and The first output terminal is used to output a positive differential output, and the second output terminal is used to output a negative differential output, wherein: The first output transistor is coupled between the common node and the first output terminal, and is controlled according to a negative portion of the data; The first resistor is coupled between the first output terminal and ground; The second output transistor is coupled between the common node and the second output terminal, and is controlled according to a positive portion of the data; and The second resistor is coupled between the second output terminal and the ground.

19. The transmitter according to claim 18, characterized in that The bias circuit of the driver includes: a first transistor biased by a bias voltage and coupled between a supply voltage and the common node; A second transistor is biased by the bias voltage and a switch, wherein when the switch is closed, the second transistor is coupled between the supply voltage and the common node, and the switch is closed in response to the transition of the data.

20. The transmitter according to claim 19, wherein Further including: The transition detection circuit is configured to detect a transition of the data and generate a control signal to close the switch in response to the transition of the data.

21. The transmitter according to claim 20, characterized in that The conversion detection circuit comprises: a delay unit that delays a positive portion of the data; and The XOR gate outputs the control signal according to the positive part of the data and the positive part of the delayed data.

22. The transmitter according to claim 19, wherein The first transistor and the second transistor are p-type metal oxide semiconductor transistors.

23. The transmitter according to claim 18, wherein The bias circuit of the driver includes: A transistor is biased by a bias voltage and coupled between a supply voltage and the common node, wherein the bias voltage is suppressed in response to the transition of the data.

24. The transmitter according to claim 23, characterized in that The transistor is a p-type metal oxide semiconductor transistor.

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