Storage devices using decorated address space

Abstract

This application discloses a storage device using a decorated address space, relating to the field of memory, and resolving the conflict between the need to annotate the unevenness of the address space and the large size of the FTL table. The storage device of this application includes an interface, a control component, one or more NVM chips, and a DRAM. The control component is coupled to the interface, the NVM chip, and the DRAM, respectively. The DRAM includes multiple FTL tables, each of which includes multiple FTL entries. Each FTL entry records a normal physical address space corresponding to a first logical address, and can access a decorated address space through the FTL entry.

Description

Technical Field

[0001] The present application relates to storage technology, and in particular, to a storage device using a decorated address space. Background Art

[0002] Figure 1 A block diagram of a solid-state storage device is shown. A solid-state storage device 102 is coupled to a host to provide storage capabilities for the host. The host and solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and solid-state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication networks, and the like. The host can be an information processing device capable of communicating with the storage device in the above manner, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, and the like. The storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, or the like.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit) or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data in the DRAM 110. The FTL table and / or cached IO command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash memory interface controller (also known as a media interface controller or a flash memory lane controller). The flash memory interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle" and "ONFI".

[0007] In storage devices, the Flash Translation Layer (FTL) is used to maintain mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of solid-state storage devices as perceived by upper-layer software such as the operating system. Physical addresses are addresses used to access physical storage units in solid-state storage devices. In related technologies, address mapping can also be implemented using intermediate address forms. For example, logical addresses can be mapped to intermediate addresses, which are then further mapped to physical addresses. In these cases, the read / write commands received by the storage device indicate logical addresses.

[0008] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is important metadata in solid-state storage devices. Typically, an FTL table entry records the address mapping relationship in units of data pages in the storage device.

[0009] In some storage devices, the FTL is provided by the host to which the storage device is coupled. The host's memory stores the FTL table, and the host's CPU executes software to provide the FTL. In other cases, the FTL is provided by a storage management device located between the host and the storage device. In these cases, the read / write commands received by the storage device specify physical addresses.

[0010] The host may provide commands to the storage device that access the logical address space corresponding to one or more entries in the FTL table. Furthermore, the control component may modify the form of the command received from interface 103 (for example, by splitting the command according to the size of the logical address space corresponding to the FTL entry) and process the modified command. For clarity, this document describes a read / write command received by the storage device that accesses a single FTL entry as an example.

[0011] Chinese patent application number 201811154190.7 provides an FTL and utilizes the FTL to provide data cache for a storage device.

[0012] Figure 2A FIG. 1 is a schematic diagram of a logical address (LBA) space of the background art. As an example, the logical address space is a continuous address space. The FTL maintains the logical address space. Figure 2A The logical address space increases from top to bottom. The logical address space consists of multiple regions of equal size, each of which is called a small block. Each entry in the FTL table (called an FTL entry) records the mapping of a small block of the logical address space to a physical address. Figure 2A FIGURE 1 shows multiple entries of an FTL table, including FTL entry 0, FTL entry 1, ..., and FTL entry 5. For example, the size of the logical address space corresponding to each FTL entry can be 512 bytes, 1 KB, or 4 KB. The FTL entries are indexed based on the address of the logical address space. For example, the address of the logical address space is divided by the size of the logical address space corresponding to the FTL entry, and the resulting quotient is the index of the FTL entry.

[0013] Figure 2B An FTL table showing background technology.

[0014] The FTL table includes multiple FTL entries, each corresponding to one of the small chunks. The value of the FTL entry records the NVM data frame address or cache container index that provides storage space for the small chunk. Optionally, based on the value of the FTL entry, it is determined whether the value indicates an NVM data frame address or a cache container index. For example, FTL entry values ​​greater than a threshold are mapped to NVM data frame addresses, while FTL entry values ​​less than the threshold are mapped to cache container indexes. As another example, a flag bit is recorded in the FTL entry to indicate whether the FTL entry value indicates an NVM data frame address or a cache container index.

[0015] The FTL table is stored in, for example, DRAM 110 (see also Figure 1 ) or SRAM. The FTL calculates the index of the corresponding FTL entry based on the accessed logical address, and obtains the NVM data frame or cache container that provides storage space for the small block from the FTL entry.

[0016] An NVM data frame address is, for example, a physical address for accessing a physical page of an NVM chip, a physical address for accessing a combination of multiple physical pages of an NVM chip (a combined physical page is, for example, a physical page with the same physical page number located on multiple planes of the same logical unit (LUN)), or a physical address for accessing a portion of a data unit within a physical page of an NVM chip. A cache container index is, for example, the address of a cache unit in DRAM or the address of a cache unit descriptor. A cache unit is a section of storage space in DRAM or SRAM, for example. A cache unit descriptor is used to describe a cache unit. A cache container is used to record cache unit descriptors.

[0017] NVM chips such as NAND flash memory are unreliable storage media, and the data stored therein may contain erroneous bits. In order to identify and correct erroneous bits, ECC (Error Correction Code) encoding is performed on the data written to the NVM chip, and the encoded check data is written into the NVM chip together with the data. When data is read from the NVM chip, ECC decoding is performed on the read data (together with the check data) to obtain the correct data. When there are many erroneous bits in the data, ECC decoding cannot obtain the correct data. Optionally, the control component of the storage device also takes other data correction measures (for example, read-retry, RAID data reconstruction, etc.) to try to recover the correct data. There are still some cases where correct data cannot be obtained even after using multiple or all data verification measures. This situation is called the data read is UECC (Uncorrectable Error Correction Code).

[0018] Data errors may also occur in the storage system's data transmission channels or other components. The NVMe standard defines end-to-end data protection (End-to-End Data Protection). Protection information (PI) is carried in the transmitted data and is associated with the transmitted data to identify errors. The DIF / DIX (Data Integrity Field / Data Integrity Extension) defined by the T10 subcommittee of the ICITS (International Committee for Information Standards) (available at http: / / www.t10.org / ftp / t10 / document.03 / 03-111r0.pdf) is also used to verify data integrity.

[0019] Some storage devices support encryption, such as data encryption / decryption using the Advanced Encryption Standard (AES). AES encrypts, for example, 256-bit data units and groups the encrypted data into 512-byte blocks. The storage device's control unit also appends metadata to the AES-encrypted data blocks, which may not be AES-encrypted. Consequently, some data (e.g., metadata) stored in NVM data frames is not AES-encrypted. Summary of the Invention

[0020] The FTL provides a mapping from the logical address space to the physical address space. As the logical address space provided by storage devices increases, the size of the FTL table also increases. Common storage devices have FTL tables that are several or even tens of GB in size. For embedded devices, accommodating such large FTL tables in DRAM becomes difficult.

[0021] The evolution of storage protocols such as NVMe has placed additional demands on storage devices for features such as data encryption and de-allocation. The development of NVM storage media has also expanded its operational capabilities, such as soft decoding, read redo, and adjustable read thresholds. These characteristics can lead to inconsistencies between the logical and physical address spaces of storage devices. For example, data in certain locations of the address space may contain uncorrectable error correction codes (UECCs), require soft decoding for error correction, have been de-allocated, and / or cached, while data in other locations should be accessed using standard methods. These inconsistencies in the address space elements need to be marked, allowing for different access methods to optimize storage device performance. However, marking the elements of the storage space requires further increases in the FTL table capacity, which is unacceptable in some storage devices. A method for effectively marking the address space of storage devices is needed.

[0022] According to the first aspect of the present application, a first storage device according to the first aspect of the present application is provided, the storage device including an interface, a control component, one or more NVM chips and a DRAM, the control component being coupled to the interface, the NVM chip and the DRAM respectively; the DRAM including multiple FTL tables, each FTL table including multiple FTL entries, each FTL entry recording a normal physical address space corresponding to a first logical address, and a modified address space that can be accessed through the FTL entry.

[0023] According to the first storage device of the first aspect of the present application, a second storage device according to the first aspect of the present application is provided, and the modified address space accessed through the FTL entry is one or more of the special physical address space corresponding to the first logical address recorded by the FTL entry, and the address space indicated by the first label attached to the FTL entry.

[0024] According to the second storage device of the first aspect of the present application, a third storage device according to the first aspect of the present application is provided. When the modified address space accessed through the FTL entry includes a special physical address space corresponding to the first logical address recorded by the FTL entry, the physical address space element is recorded in the FTL entry, and the ordinary physical address space and the special physical address space are distinguished based on the physical address space element obtained from the FTL table.

[0025] According to the third storage device of the first aspect of the present application, a fourth storage device according to the first aspect of the present application is provided, the physical address space includes ordinary physical address space and special physical address space, the ordinary physical address space and the special physical address space are exclusive, and the physical address space elements recorded in the FTL entry cannot indicate the ordinary physical address space and the special physical address space at the same time.

[0026] According to the third or fourth storage device of the first aspect of the present application, a fifth storage device according to the first aspect of the present application is provided, which accesses the NVM storage medium according to the normal physical address space element if the normal physical address space element is obtained from the FTL table.

[0027] According to the third or fourth storage device of the first aspect of the present application, a sixth storage device according to the first aspect of the present application is provided. If a special physical address space element is obtained from the FTL table, its meaning is determined based on the value of the special physical address space element, and then the corresponding operation is performed.

[0028] According to the sixth storage device of the first aspect of the present application, a seventh storage device according to the first aspect of the present application is provided, and if the special physical address space element obtained from the FTL table indicates a cache, the indicated cache is accessed to process the IO command.

[0029] According to the sixth storage device of the first aspect of the present application, an eighth storage device according to the first aspect of the present application is provided. If the special physical address space element obtained from the FTL table indicates that the cache is de-allocated, there is no need to actually read the data from the storage medium, and the de-allocated data can be read to the command requester indicator.

[0030] According to the sixth storage device of the first aspect of the present application, a ninth storage device according to the first aspect of the present application is provided, which directly indicates to the command requester that UECC has occurred if the special physical address space element obtained from the FTL table indicates UECC.

[0031] According to the sixth storage device of the first aspect of the present application, a tenth storage device according to the first aspect of the present application is provided, which marks the special physical address space element as "reserved" if the special physical address space element obtained from the FTL table is not used.

[0032] According to one of the second to tenth storage devices of the first aspect of the present application, an eleventh storage device according to the first aspect of the present application is provided. When the modified address space accessed through the FTL entry includes the address space indicated by the first label attached to the FTL entry, the first label increases the size of the FTL entry, and the first label increases the logical address space, and can simultaneously indicate the ordinary physical address space and the particularity of the address space.

[0033] According to the second or eleventh storage device of the first aspect of the present application, a twelfth storage device according to the first aspect of the present application is provided, and the first tag attached to the FTL entry indicates the use of soft decoding, the use of specified read redo, whether the data carries protection information, and / or whether the data is encrypted data.

[0034] According to the twelfth storage device of the first aspect of the present application, a thirteenth storage device according to the first aspect of the present application is provided. In response to the first tag indicating the use of soft decoding, when reading data from the NVM data frame, the process of issuing a normal read command is omitted, and a read command for reading the soft bit is directly issued.

[0035] According to the twelfth storage device of the first aspect of the present application, a fourteenth storage device according to the first aspect of the present application is provided, which responds to the first tag indication to use the specified read redo, omits the process of issuing a normal read command, and directly issues a read redo command according to the read redo parameters specified by the tag.

[0036] According to the twelfth storage device of the first aspect of the present application, a fifteenth storage device according to the first aspect of the present application is provided, which determines whether to check the protection information of the read data based on whether it carries the protection information in response to the first tag indicating whether the data carries the protection information.

[0037] According to the twelfth storage device of the first aspect of the present application, a sixteenth storage device according to the first aspect of the present application is provided, which determines whether to perform a decryption operation on the read data based on whether the data is encrypted data in response to the first tag indicating whether the data is encrypted data.

[0038] According to one of the first to tenth storage devices of the first aspect of the present application, a seventeenth storage device according to the first aspect of the present application is provided, wherein the modified address space accessed through the FTL entry is the address space indicated by the second label obtained in the NVM data frame accessed by the ordinary physical address space element recorded by the FTL entry, the second label increases the logical address space, and the second label can indicate the particularity of the address space.

[0039] According to the seventeenth storage device of the first aspect of the present application, there is provided the eighteenth storage device according to the first aspect of the present application, wherein the NVM data frame includes user data, metadata, and a second tag.

[0040] According to the seventeenth or eighteenth storage device of the first aspect of the present application, a nineteenth storage device according to the first aspect of the present application is provided, and the second tag in the NVM data frame indicates whether the data carries protection information and / or whether the data is encrypted data.

[0041] According to the nineteenth storage device of the first aspect of the present application, a twentieth storage device according to the first aspect of the present application is provided, which determines whether to check the protection information of the read data based on whether the protection information is carried by the second tag indicating whether the data carries the protection information.

[0042] According to the twentieth storage device of the first aspect of the present application, a twenty-first storage device according to the first aspect of the present application is provided, which determines whether to perform a decryption operation on the read data based on whether the data is encrypted data in response to the second tag indicating whether the data is encrypted data.

[0043] According to one of the eighteenth to twenty-first storage devices of the first aspect of the present application, a twenty-second storage device according to the first aspect of the present application is provided, and the metadata of the NVM data frame includes a logical address, error checking information, a first randomization seed and / or first protection information, second protection information and / or a second randomization seed.

[0044] According to the twenty-second storage device of the first aspect of the present application, a twenty-third storage device according to the first aspect of the present application is provided, and second protection information is intentionally written into the metadata to indicate that a UECC exists in the NVM data frame where the metadata is located.

[0045] According to the twenty-second storage device of the first aspect of the present application, a twenty-fourth storage device according to the first aspect of the present application is provided, wherein a first randomization seed generated by a special process is written in a first position of the metadata, and a second randomization seed generated by a regular process is written in a second position of the metadata.

[0046] According to the twenty-fourth storage device of the first aspect of the present application, a twenty-fifth storage device according to the first aspect of the present application is provided, which, when the user data of the NVM data frame is encrypted data, records the first randomization seed generated by a special process only at the first position of the metadata of the NVM data frame.

[0047] According to the twenty-fourth storage device of the first aspect of the present application, a twenty-sixth storage device according to the first aspect of the present application is provided, which, when the user data of the NVM data frame is non-encrypted data, records a first randomization seed generated by a special process at a first position of the metadata of the NVM data frame, and records a second randomization seed generated by a conventional process at a second position of the metadata.

[0048] According to the twenty-sixth storage device of the first aspect of the present application, there is provided a twenty-seventh storage device according to the first aspect of the present application, which, when reading out the NVM data frame, if it is detected that the first randomization seed is wrong and the second randomization seed is correct, determines that the user data of the read NVM data frame is unencrypted data.

[0049] According to the twenty-sixth storage device of the first aspect of the present application, a twenty-eighth storage device according to the first aspect of the present application is provided. If it is detected that the first randomization seed is wrong and the second randomization seed is also wrong, it means that there is an error in the NVM data frame itself.

[0050] According to the twenty-fifth storage device of the first aspect of the present application, a twenty-ninth storage device according to the first aspect of the present application is provided, which, for a normal NVM data frame that stores encrypted data, only detects the first randomization seed, and when the first randomization seed is correct, identifies the metadata of the NVM data frame as encrypted data by default and decrypts it.

[0051] According to one of the first to twenty-ninth storage devices of the first aspect of the present application, there is provided a thirtieth storage device according to the first aspect of the present application, wherein the control component executes the method described in any one of the second aspect of the present application.

[0052] According to the second aspect of the present application, a method for processing a first read command according to the second aspect of the present application is provided, including: obtaining a read command indicating to read data from a first logical address; querying the FTL table with the first logical address to obtain a first physical address corresponding to the first logical address; identifying whether the first physical address belongs to a modified address space; in response to the first physical address belonging to the modified address space, further identifying the meaning of the modified address space to which the first physical address belongs.

[0053] According to the processing method of the first read command of the second aspect of the present application, a processing method of the second read command according to the second aspect of the present application is provided. In response to the fact that the modified address space to which the first physical address belongs is a special physical address space corresponding to the first logical address recorded by the FTL entry, the physical address space element is recorded in the FTL entry, and the ordinary physical address space and the special physical address space are distinguished according to the physical address space element obtained from the FTL table.

[0054] According to the processing method of the second read command of the second aspect of the present application, a processing method of the third read command according to the second aspect of the present application is provided, the physical address space includes ordinary physical address space and special physical address space, the ordinary physical address space and the special physical address space are exclusive, and the physical address space elements recorded in the FTL entry cannot indicate the ordinary physical address space and the special physical address space at the same time.

[0055] According to the processing method of the second or third read command of the second aspect of the present application, a processing method of the fourth read command according to the second aspect of the present application is provided. If the special physical address space representative to which the first physical address belongs is de-allocated, the data indicating the de-allocation is transmitted to the host as a response to the read command.

[0056] According to one of the processing methods of the second to fourth read commands of the second aspect of the present application, a processing method of the fifth read command according to the second aspect of the present application is provided, and if the special physical address space to which the first physical address belongs represents the UECC, a data error is used as a response to the read command.

[0057] According to one of the processing methods of the second to fifth read commands of the second aspect of the present application, a processing method of the sixth read command according to the second aspect of the present application is provided. If the special physical address space to which the first physical address belongs represents a cache, data is read from the cache according to the first physical address, and the read data is transmitted to the host as a response to the read command.

[0058] According to one of the processing methods of the second to sixth read commands of the second aspect of the present application, a processing method of the seventh read command according to the second aspect of the present application is provided. In response to identifying that the first physical address does not belong to the modified address space, the value of the first physical address is the ordinary physical address space, and data is read from the NVM data frame indicated by the first physical address.

[0059] According to the processing method of the seventh read command of the second aspect of the present application, a processing method of the eighth read command according to the second aspect of the present application is provided, error correction decoding is performed on the read data, if the read data contains UECC, a second physical address indicating UECC is allocated from the special physical address space, the FTL table is updated to record the first logical address associated with the allocated second physical address, and the data error is used as a response to the read command.

[0060] According to the processing method of the seventh or eighth read command of the second aspect of the present application, a processing method of the ninth read command according to the second aspect of the present application is provided. If the read data does not exist in the UECC, the result of the error correction of the read data is transmitted to the host as a response to the read command.

[0061] According to one of the processing methods of the first to ninth read commands of the second aspect of the present application, a processing method of the tenth read command according to the second aspect of the present application is provided. In response to the modified address space to which the first physical address belongs being the address space indicated by the first label attached to the FTL entry, the first label increases the size of the FTL entry, and the first label increases the logical address space, which can simultaneously indicate the ordinary physical address space and the particularity of the address space.

[0062] According to the processing method of the tenth read command of the second aspect of the present application, a processing method of the eleventh read command according to the second aspect of the present application is provided, and the first tag indicates the use of soft decoding, the use of specified read redo, whether the data carries protection information, and / or whether the data is encrypted data.

[0063] According to the processing method of the eleventh read command of the second aspect of the present application, a processing method of the twelfth read command according to the second aspect of the present application is provided. If the first tag indicates the use of soft decoding, a read command for reading the soft bit is directly issued to the first physical address, and soft decoding is performed on the read soft bit data.

[0064] According to one of the processing methods of the tenth to twelfth read commands of the second aspect of the present application, a processing method of the thirteenth read command according to the second aspect of the present application is provided. If the first tag indicates the use of specified read redo, a read redo command is directly issued to the first physical address according to the read redo parameters specified by the first tag.

[0065] According to one of the processing methods of the tenth to thirteenth read commands of the second aspect of the present application, a processing method of the fourteenth read command according to the second aspect of the present application is provided. If the first tag indicates that the data does not carry protection information, the step of checking the protection information of the read data is omitted.

[0066] According to one of the processing methods of the tenth to fourteenth read commands of the second aspect of the present application, a processing method of the fifteenth read command according to the second aspect of the present application is provided. If the first tag indicates that the data is unencrypted data, the decryption operation is omitted for the read data.

[0067] According to one of the processing methods of the tenth to fifteenth read commands of the second aspect of the present application, a processing method of the sixteenth read command according to the second aspect of the present application is provided, in response to the FTL entry to which the first physical address belongs not indicating the first tag, reading data from the NVM data frame indicated by the first physical address.

[0068] According to one of the processing methods of the first to tenth read commands of the second aspect of the present application, a processing method of the seventeenth read command according to the second aspect of the present application is provided, and error correction decoding is performed on the data read from the NVM data frame indicated by the first physical address. If the error correction decoding fails, the data is read out of the first physical address through soft decoding; and a third label indicating the use of soft decoding is generated, and the generated third label is used to update the FTL entry associated with the first logical address, so that the FTL entry indicates both the first physical address and the third label.

[0069] According to the processing method of the sixteenth or seventeenth read command of the second aspect of the present application, a processing method of the eighteenth read command according to the second aspect of the present application is provided, and error correction decoding is performed on the read data. If the error correction decoding is successful, the result of the error correction of the read data is transmitted to the host as a response to the read command.

[0070] According to one of the processing methods of the first and sixteenth to eighteenth read commands of the second aspect of the present application, a processing method of the nineteenth read command according to the second aspect of the present application is provided, in response to the modified address space being the address space indicated by the second label obtained in the NVM data frame accessed by the physical address space recorded by the FTL entry, the second label increases the logical address space, and the second label can indicate the particularity of the address space.

[0071] According to the processing method of the nineteenth read command of the second aspect of the present application, a processing method of the twentieth read command according to the second aspect of the present application is provided. If the second tag indicates the use of soft decoding, a read command for reading the soft bit is directly issued to the first physical address, and soft decoding is performed on the read soft bit data.

[0072] According to the processing method of the nineteenth or twentieth read command of the second aspect of the present application, a processing method of the twenty-first read command according to the second aspect of the present application is provided. If the second tag indicates the use of soft decoding, then in response to the failure of error correction decoding of the data read from the NVM data frame accessed from the ordinary physical address space recorded by the FTL entry, a read command for reading the soft bits is directly issued to the first physical address, and soft decoding is performed on the read soft bit data.

[0073] According to one of the processing methods of the nineteenth to twenty-first read commands of the second aspect of the present application, a processing method of the twenty-second read command of the second aspect of the present application is provided. If the second tag indicates the use of specified read redo, a read redo command is issued to the first physical address according to the read redo parameters specified by the second tag.

[0074] According to one of the processing methods of the nineteenth to twenty-second read commands of the second aspect of the present application, a processing method of the twenty-third read command of the second aspect of the present application is provided, wherein if the second tag indicates the use of specified read redo, then in response to the failure of error correction decoding of data read from the NVM data frame accessed from the ordinary physical address space recorded by the FTL entry, a read redo command is issued to the first physical address according to the read redo parameters specified by the second tag.

[0075] According to one of the processing methods of the nineteenth to twenty-third read commands of the second aspect of the present application, a processing method of the twenty-fourth read command of the second aspect of the present application is provided. If the second tag indicates that the data does not carry protection information, the step of checking the protection information of the read data is omitted.

[0076] According to one of the processing methods of the nineteenth to twenty-fourth read commands of the second aspect of the present application, a processing method of the twenty-fifth read command of the second aspect of the present application is provided. If the second tag indicates that the data is unencrypted data, the decryption operation is omitted for the read data.

[0077] According to a third aspect of the present application, a program comprising program code is provided. When loaded into a storage device and executed on the storage device, the program code causes the storage device to execute the method for processing a read command according to the second aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0079] Figure 1 A block diagram of a solid-state storage device in the prior art is shown;

[0080] Figure 2A is a schematic diagram of a logical address (LBA) space of the background art;

[0081] Figure 2B FTL table showing background technology;

[0082] Figure 3A shows a schematic diagram of an FTL table according to the first embodiment of the present application;

[0083] Figure 3B A schematic diagram of a physical address space according to a first embodiment of the present application is shown;

[0084] Figure 4 The following describes a read command processing flow according to the first embodiment of the present application;

[0085] Figure 5 shows a schematic diagram of an FTL table according to a second embodiment of the present application;

[0086] Figure 6 The following describes a read command processing flow according to the second embodiment of the present application;

[0087] Figure 7A shows a schematic diagram of an FTL table according to a third embodiment of the present application;

[0088] Figure 7B A schematic diagram of an NVM data frame according to a third embodiment of the present application is shown;

[0089] Figure 7C shows a metadata schematic diagram of another NVM data frame according to the third embodiment of the present application;

[0090] Figure 8A is a flowchart of processing a write command according to the third embodiment of the present application;

[0091] Figure 8B is a flowchart of processing a read command according to the third embodiment of the present application;

[0092] Figure 9A is a flowchart of another method for processing a write command according to the third embodiment of the present application;

[0093] Figure 9B This is a flowchart of another method of processing a read command according to the third embodiment of the present application. DETAILED DESCRIPTION

[0094] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0095] According to the first embodiment of the present application, the physical address space is divided into a common physical address space and a special physical address space. The common physical address space is used to index NVM data frames, while the special physical address space is assigned a flag related to the inconsistency of the logical address space.

[0096] Figure 3A A schematic diagram of an FTL table according to the first embodiment of the present application is shown. Figure 3B A schematic diagram of a physical address space according to the first embodiment of the present application is shown.

[0097] The FTL table includes multiple FTL entries, and the value of the FTL entry records the physical address corresponding to the logical address ( Figure 3A denoted as PBA) space element.

[0098] The possible values ​​of the physical address space element depend on the size of the FTL entry. See also Figure 3B For example, if the size of an FTL entry is 32 bits, the value range of the physical address space element is from 0X0000 0000 to 0XFFFFFFFF. For example, the physical address space 0X0000 0000 to 0XFFFEFFFF is used as the normal physical address space, and the physical address space 0XFFFF 0000 to 0XFFFF FFFF is used as the special physical address space.

[0099] Different areas of the special physical address space represent different meanings. For example, some areas of the special physical address space represent cache container indexes or cache unit indexes, some areas represent the presence of a UECC, and some areas represent de-allocation. Therefore, the value of a special physical address space element indicates the special meaning it represents, and the special meaning represented by the value of the special physical address space element can be identified.

[0100] The physical address space element is recorded in the FTL entry. Depending on whether the physical address space element obtained from the FTL table belongs to the normal physical address space or the special physical address space, different operations are determined for the accessed physical address. For example, if the normal physical address space element is obtained from the FTL table, the NVM storage medium is accessed based on the normal physical address space element. If the special physical address space element is obtained from the FTL table, its meaning is determined based on the value of the special physical address space element and the corresponding operation is then performed.

[0101] For example, if the special physical address space element obtained from the FTL table indicates a cache (cache unit index or cache descriptor index), the indicated cache is accessed to process the IO command; if the special physical address space element obtained from the FTL table indicates that the cache is de-allocated, there is no need to actually read data from the storage medium and the command requester is informed that all 0 data or de-allocated data is read; if the special physical address space element obtained from the FTL table indicates UECC, the command requester is directly informed that UECC has occurred, although no data is actually read and no error correction is performed. There are also some special physical address space elements that are not used. Figure 3B Mark it as "Retain" in the

[0102] It should be noted that according to the first embodiment of the present application, the special physical address space and the normal physical address space are distinguished based on the value of the FTL entry. Therefore, the special physical address space and the normal physical address space are mutually exclusive. The FTL entry cannot provide both normal physical address space elements and special physical address space elements at the same time. Therefore, it is impossible to mark the normal physical address space elements as inconsistent. For example, if a certain NVM data frame needs to be accessed, but it needs to be accessed preferentially using soft decoding or designated read redo, this situation cannot be described according to the method of the first embodiment.

[0103] Figure 4 The read command processing flow according to the first embodiment of the present application is shown.

[0104] The storage device receives a read command indicating that data is to be read from a first logical address (410). The control unit of the storage device uses the first logical address to query the FTL table and obtain a first physical address corresponding to the first logical address (420). The control unit identifies whether the first physical address belongs to the normal physical address space or the special physical address space based on the value of the first physical address. If the first physical address does not belong to the special physical address space (i.e., belongs to the normal physical address space) (430), data is read from the NVM data frame indicated by the first physical address (440).

[0105] Error correction decoding is performed on the read data. If the read data contains a UECC (450), a second physical address indicating the UECC is allocated from the special physical address space (460), an FTL table is updated to record the association of the first logical address with the allocated second physical address (470), and a data error is used as a response to the read command (480). If the read data does not contain a UECC, a result of the error correction of the read data is transmitted to the host as a response to the read command.

[0106] In step 430, if the first physical address belongs to a special physical address space, the meaning represented by the first physical address is further identified (432), and corresponding processing is performed according to the meaning represented by the first physical address. For example, if the first physical address represents de-allocation, data such as all 0s is transmitted to the host (434) as a response to the read command. If the first physical address represents UECC, a data error is used as a response to the read command (480). If the first physical address represents a cache, data is read from the cache according to the first physical address, and the read data is transmitted to the host ( Figure 4 not shown).

[0107] According to the second embodiment of the present application, a tag is added to the FTL entry to indicate the specificity of the physical address space. Unlike the first embodiment, each FTL entry can include a tag, so that the common physical address space and the specificity can be indicated at the same time, but at the cost of increasing the size of the FTL table.

[0108] Figure 5 A schematic diagram of an FTL table according to the second embodiment of the present application is shown.

[0109] The FTL table includes multiple FTL entries. The value of the FTL entry records the common physical address corresponding to the logical address ( Figure 5 The FTL entry is also labeled as a PBA space element. The tag of the FTL entry indicates its specificity. For example, the tag indicates whether soft decoding is used, whether specified read redo is used, whether the data carries protection information, and / or whether the data is encrypted.

[0110] Thus, the NVM data frame can be accessed based on the normal physical address space elements obtained by accessing the FTL, and the specificity of the address space indicated by the tag can be understood based on the tag obtained by accessing the FTL. For example, if the tag indicates the use of soft decoding, then when reading data from the NVM data frame, the process of issuing a normal read command is omitted, and a read command for reading soft bits is directly issued. If the tag indicates the use of a specified read redo, the process of issuing a normal read command is also omitted, and a read redo command is directly issued according to the read redo parameters specified by the tag. If the tag indicates whether the data carries protection information, then the protection information is checked for the read data based on whether it carries protection information. If the tag indicates whether the data is encrypted, then the decryption operation is determined based on whether the read data is encrypted.

[0111] Furthermore, the second embodiment combines the solution of the first embodiment, and the FTL entry may also be a special physical address space element. After obtaining the FTL entry, processing is performed based on both the normal physical address space element or the special physical address space element indicated by the FTL entry and the tag of the FTL entry.

[0112] Optionally, since the special physical address space element corresponds one-to-one with the logical address space element in the FTL table or multiple elements of the logical address space correspond to the same special physical address space element, the special physical address space element can be used to indicate the particularity of the logical address space element. However, the special physical address space element cannot correspond one-to-one with the entire physical address space element, but a label can be attached to each element of the physical address space, so that the physical address space element and the label can correspond one-to-one or multiple elements of the physical address space correspond to the same label. Therefore, the label can be used to indicate the particularity of the physical address space element. When it is necessary to indicate the particularity of the logical address label, either the label or the special physical address space element can be used, and when it is necessary to indicate the particularity of the physical address space element, the label can be used.

[0113] The specificity of logical address space elements includes, for example, whether the data corresponding to the logical address space element is deallocated, UECC occurs, whether the data is cached, whether the data is encrypted, and / or whether the data carries protection information. The specificity of physical address space elements includes, for example, whether soft decoding is used, whether specified read redo is used, whether the data carries protection information, and / or whether the data is encrypted.

[0114] Figure 6 The read command processing flow according to the second embodiment of the present application is shown.

[0115] A storage device receives a read command that indicates reading data from a first logical address (610). The control unit of the storage device queries an FTL table using the first logical address and obtains a first physical address corresponding to the first logical address from the obtained FTL entry (620). The control unit identifies whether the FTL entry obtained from the FTL table indicates a tag (630). If the FTL entry does not indicate a tag, data is read from the NVM data frame indicated by the first physical address (640). Error correction decoding is performed on the read data. If the error correction decoding fails (650), data is read from the first physical address using soft decoding (660). A tag indicating the use of soft decoding is generated (670), and the generated tag is used to update the FTL entry associated with the first logical address (680), so that the FTL entry indicates both the first physical address and the tag.

[0116] In step 650, if the error correction decoding is successful, the error-corrected result of the read data is transmitted to the host as a response to the read command (652).

[0117] In step 630, if the FTL entry indicates a tag, the meaning of the tag is obtained (632). For example, if the tag indicates the use of soft decoding, a read command for reading soft bits is directly issued to the first physical address, and soft decoding is performed on the read soft bit data, thereby eliminating the need to issue a normal read command to the first physical address and speeding up the processing of the read command. This is because the tag indicates that a normal read command for the first physical address is likely to fail to obtain correct data. If the tag indicates the use of a specified read redo, the process of issuing a normal read command is also eliminated, and a read redo command is directly issued to the first physical address according to the read redo parameters specified by the tag. This is because the tag indicates that a normal read command for the first physical address is likely to fail to obtain correct data. If the tag indicates that the data does not carry protection information, the step of checking the protection information is omitted for the read data. If the tag indicates that the data is unencrypted data, the decryption operation is omitted for the read data.

[0118] According to the third embodiment of the present application, a tag is added to the NVM data frame, and the tag is used to indicate the particularity of the physical address space. The meaning indicated by the tag of the third embodiment is the same as that of the tag of the second embodiment, but it is recorded in the NVM data frame instead of in the FTL entry. Thus, the tag is used without increasing the size of the FTL table. The NVM data frame is recorded in the NVM chip. The NVM chip of the storage device, like DRAM, usually has a larger storage space. Recording the tag in the NVM data frame will not significantly increase the cost of the storage device. Optionally, in addition to adding a tag to the NVM data frame, the metadata of the NVM data frame is also used to indicate the particularity of the physical address space. The metadata of the NVM data frame usually stores the logical address, error checking information, randomization seed, protection information, etc. associated with the NVM data frame.

[0119] Figure 7A A schematic diagram of an FTL table according to the third embodiment of the present application is shown.

[0120] The FTL table includes multiple FTL entries. The value of the FTL entry records the common physical address corresponding to the logical address ( Figure 7A denoted as PBA) space element.

[0121] The storage device further includes a plurality of NVM chips. The common physical address space element recorded in the FTL entry indicates the NVM data frame. Thus, the NVM data frame indicated by the common physical address space element recorded in the FTL entry can be accessed.

[0122] Thus, the NVM data frame can be accessed by accessing the normal physical address space elements obtained from the FTL, and the specificity of the address space indicated by the tag can be understood based on the tag obtained from the NVM data frame. The meaning of the tag and the way of using the tag are consistent with the meaning and usage of the tag in the second embodiment of this application.

[0123] Figure 7B A schematic diagram of an NVM data frame according to a third embodiment of the present application is shown.

[0124] Figure 7B In the NVM data frame, the NVM data frame includes user data, metadata and tags ( Figure 7B indicated by “Tag” in the diagram).

[0125] Figure 7C A metadata diagram of another NVM data frame according to the third embodiment of the present application is shown.

[0126] Figure 7C In the NVM data frame, the metadata includes the usual logical address, error checking information ( Figure 7C Indicated by "ECC check"), random seed ( Figure 7C ) and / or protection information ( Figure 7C PI), and also includes, for example, second protection information ( Figure 7C ) and / or a second randomization seed ( Figure 7C indicated by “SS2” in the example).

[0127] The second protection information and / or the randomization seed in the metadata partially replaces the role of the tag in indicating the uniqueness of the address space element.

[0128] Typically, the metadata is generated and used by the hardware of the control component, so that the second protection information and / or randomization seed in the metadata is also detected and processed by the hardware of the control component without increasing the burden on the processor or firmware (software) of the control component.

[0129] For example, NVM data frames can be accessed based on the normal physical address space elements obtained by accessing the FTL. The tag obtained from the accessed NVM data frame can then be used to determine the specificity of the address space indicated by the tag. For example, if the tag indicates whether the data carries protection information, then the read data is checked for protection information based on whether it carries protection information. If the tag indicates whether the data is encrypted, then the read data is decrypted based on whether it is encrypted.

[0130] Still as an example, the hardware detection metadata of the control component. For example, see Figure 7C Incorrect protection information (PI') is intentionally written into the metadata to indicate the presence of a UECC in the NVM data frame containing the metadata. The control component's hardware detects the protection information (PI'), identifies that the protection information is incorrect, and reports an error based on the incorrect protection information. In some scenarios, this replaces the operation of identifying and reporting the UECC.

[0131] In another example, two randomization seeds (SS and SS2) are intentionally written into the metadata. In the metadata, randomization seed SS2 is generated using a conventional process, while randomization seed SS is generated using a special process. Typically, hardware only checks the randomization seeds using the conventional process. When encountering randomization seed SS generated using the special process, it will detect an error, but when encountering randomization seed SS2, it will detect a correct result. In this case, for example, when the user data of an NVM data frame is encrypted, only the randomization seed generated using the conventional process is recorded in the metadata of the NVM data frame. When the user data of an NVM data frame is unencrypted, the randomization seed generated using the special process is recorded in the metadata of the NVM data frame at the SS position, and the randomization seed generated using the conventional process is recorded in the SS2 position. Consequently, when reading the NVM data frame, the hardware uses conventional procedures to check the correctness of the randomization seed in the metadata at the SS position. Based on the fact that the randomization seed in the metadata at the SS position is incorrect and the randomization seed in the metadata at the SS2 position is correct, the hardware determines that the user data of the read NVM data frame is unencrypted data. If the metadata's randomization seed at the SS position is detected to be incorrect and the metadata's randomization seed at the SS2 position is also detected to be incorrect, this indicates an error in the NVM data frame itself. For NVM data frames that typically store encrypted data, the typical data read process only checks the metadata's randomization seed at the SS position. If the check passes, the NVM data frame's metadata is identified as encrypted data by default and decrypted. Therefore, if unencrypted and encrypted data coexist, and the majority of the data is encrypted, there is no need to label or identify each read NVM data frame as encrypted data. Instead, only when an error occurs in the randomization seed SS check is the result of the randomization seed SS2 check determined to determine whether the data is unencrypted or erroneous. This identification of whether the data is encrypted has minimal impact on the read command processing process and eliminates the need to add a tag indicating whether the data is encrypted to the FTL entry.

[0132] Figure 8A is a flowchart of processing a write command according to the third embodiment of the present application.

[0133] A storage device receives a write command that instructs writing data to a first logical address (801). A control component of the storage device allocates a first physical address to the write command (802). The control component also identifies whether the data to be written is encrypted data (803).

[0134] In step 803, if the data to be written is encrypted data, the data to be written is randomized using a first randomization seed generated in a first manner (804), and the randomized data to be written and the first randomization seed are written to the first physical address (805).

[0135] In step 830, if the data to be written is unencrypted data, the data to be written is randomized using a first randomization seed generated in a first manner (832), and a second randomization seed generated in a second manner different from the first manner is generated. The randomized data to be written, the second randomization seed, and the first randomization seed are written to the first physical address (834). Preferably, the second randomization seed is written to the location where the first randomization seed was stored in the NVM data frame in step 805.

[0136] Figure 8B is a flowchart of processing a read command according to the third embodiment of the present application.

[0137] The storage device receives a read command that instructs the user to read data from a first logical address (810). The control unit of the storage device queries the FTL table using the first logical address and obtains a first physical address corresponding to the first logical address from the obtained FTL entry (820). The data is then read from the first physical address (830).

[0138] The first random seed of the read data is verified. For example, a random seed is generated in a first manner according to the read data, and the generated random seed is compared with the first random seed to verify whether they are the same (840).

[0139] If the verification of the first random seed succeeds, it means that the data read from the first physical address is encrypted according to the specified encryption method, and the read data is decrypted (850). If the verification of the first random seed fails, a second random seed is obtained from the read data and the second random seed is verified (842). For example, a random seed is generated according to the read data using the second method, and the generated random seed is compared with the second random seed to verify whether it is the same.

[0140] If the second random seed is successfully verified, it means that the data read from the first physical address is unencrypted data, and the decryption operation on the read data is skipped (844). If the second random seed is unverified, it means that the read data has an error, and error handling is required (846).

[0141] Figure 9A This is a flowchart of another method of processing a write command according to the third embodiment of the present application.

[0142] The storage device receives a write command and a read command indicating that data is to be written to a first logical address (901). The control component of the storage device allocates a first physical address to the write command (902). The control component also identifies whether the data to be written is encrypted data (903).

[0143] In step 903, if the written data is encrypted data, a tag indicating encrypted data is generated (904), and if the written data is unencrypted data, a tag indicating unencrypted data is generated (932).

[0144] The first physical address associated with the first logical address recorded in the FTL table is updated with the generated tag (905), so that the generated tag is also obtained when the first physical address is obtained from the FTL entry next time. And the data to be written is written to the first physical address (906).

[0145] Figure 9B This is a flowchart of another method of processing a read command according to the third embodiment of the present application.

[0146] A storage device receives a read command that indicates reading data from a first logical address (910). A control unit of the storage device queries an FTL table using the first logical address and obtains a first physical address corresponding to the first logical address from the obtained FTL entry (920). The control unit identifies whether the FTL entry obtained from the FTL table indicates a tag (930). If the FTL entry does not indicate a tag, data is read from the NVM data frame indicated by the first physical address (940). Error correction decoding is performed on the read data (950). If the error correction decoding fails, data is read from the first physical address using soft decoding (960). A tag indicating the use of soft decoding is generated (970), and the generated tag is used to update the FTL entry associated with the first logical address (980), so that the FTL entry indicates both the first physical address and the tag.

[0147] In step 950, if the error correction decoding is successful, the error-corrected result of the read data is decrypted (952), and the decrypted data is transmitted to the host as a response to the read command (954).

[0148] At step 930, if the FTL entry indicates a tag, the meaning of the tag is obtained (934). For example, if the tag indicates the use of soft decoding, a read command for reading the soft bits is directly issued to the first physical address, and soft decoding is performed on the read soft bit data, thereby eliminating the need to issue a normal read command to the first physical address. If the tag indicates the use of a specified read redo, the process of issuing a normal read command is also eliminated, and a read redo command is directly issued to the first physical address according to the read redo parameters specified by the tag. If the tag indicates that the data is unencrypted data, the decryption operation is omitted for the read data, and the undecrypted data is transmitted to the host as a response to the read command (954). If the tag indicates that the data contains a UECC, information indicating a data error is transmitted to the host as a response to the read command (936), eliminating the need to correct the data error. If the tag indicates that the data does not carry protection information, the step of checking the protection information is omitted for the read data.

[0149] Although preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this application. Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if such changes and modifications fall within the scope of the claims of this application and their equivalents, then this application is intended to include such changes and modifications.

Claims

1. A method for processing a read command, characterized in that: include: Obtaining a read command instructing to read data from a first logical address; Using the first logical address to query the FTL table, obtaining a first physical address corresponding to the first logical address; Identifying whether the value of the first physical address belongs to the modified address space; The physical address space is divided into an undecorated address space and a decorated address space. The decorated address space is divided into different regions representing different meanings. The different meanings correspond to different operations related to the specificity of the logical address space elements. The particularities of the logical address space element include: whether the data corresponding to the logical address space element is de-allocated, whether UECC occurs, whether the data is cached, whether the data is encrypted, and / or whether the data carries protection information; In response to the value of the first physical address belonging to the modified address space, the meaning of the area of ​​the modified address space to which the first physical address belongs is further identified based on the value of the first physical address, and corresponding operations are performed based on the meaning of the area of ​​the modified address space to which the first physical address belongs.

2. A storage device, characterized in that: The storage device includes an interface, a control component, one or more NVM chips, and a DRAM, wherein the control component is coupled to the interface, the NVM chip, and the DRAM respectively; the DRAM includes a plurality of FTL tables, each of the FTL tables includes a plurality of FTL entries, each FTL entry records a first physical address corresponding to a first logical address, and can identify whether the first physical address in the FTL entry belongs to a modified address space; The physical address space is divided into an undecorated address space and a decorated address space. The decorated address space is divided into different regions representing different meanings. The different meanings correspond to different operations related to the specificity of the logical address space elements. The particularities of the logical address space element include: whether the data corresponding to the logical address space element is de-allocated, whether UECC occurs, whether the data is cached, whether the data is encrypted, and / or whether the data carries protection information; The meaning of the region of the modified address space to which the first physical address belongs is identified according to the value of the first physical address, and corresponding operations are performed according to the meaning of the region of the modified address space to which the first physical address belongs.

3. The storage device according to claim 2, wherein: The modified address space accessed through the FTL entry is one or more of a special physical address space corresponding to the first logical address recorded in the FTL entry and an address space indicated by the first tag attached to the FTL entry.

4. The storage device according to claim 3, wherein: When the modified address space accessed through the FTL entry includes a special physical address space corresponding to the first logical address recorded by the FTL entry, the physical address space element is recorded in the FTL entry, and the ordinary physical address space and the special physical address space are distinguished based on the physical address space element obtained from the FTL table.

5. The storage device according to claim 4, wherein: The physical address space includes the common physical address space and the special physical address space. The common physical address space and the special physical address space are mutually exclusive. The physical address space element recorded in the FTL entry cannot indicate both the common physical address space and the special physical address space at the same time.

6. The storage device according to claim 4, wherein: If the normal physical address space element is obtained from the FTL table, the NVM storage medium is accessed according to the normal physical address space element.

7. The storage device according to claim 4, wherein: If a special physical address space element is obtained from the FTL table, its meaning is determined according to the value of the special physical address space element, and then the corresponding operation is performed.

8. The storage device according to claim 7, wherein: If the special physical address space element obtained from the FTL table indicates a cache, the indicated cache is accessed to process the IO command.

9. The storage device according to claim 7, wherein: If the special physical address space element obtained from the FTL table indicates that the cache is deallocated, the deallocated data can be read to the command requester without actually reading the data from the storage medium.

10. The storage device according to claim 7, wherein: If the special physical address space element obtained from the FTL table indicates UECC, it directly indicates to the command requester that UECC has occurred.

11. The storage device according to claim 7, wherein: If the special physical address space element obtained from the FTL table is not used, the special physical address space element is marked as "reserved".

12. The storage device according to any one of claims 3 to 11, wherein: When the decorated address space accessed through the FTL entry includes the address space indicated by the first tag attached to the FTL entry, the first tag increases the logical address space and can indicate both the normal physical address space and the special address space.

13. The storage device according to claim 3, wherein: The first tag attached to the FTL entry indicates whether soft decoding is used, whether designated read redo is used, whether the data carries protection information, and / or whether the data is encrypted data.

14. The storage device according to claim 13, wherein: In response to the first tag indicating the use of soft decoding, when reading data from the NVM data frame, the process of issuing a normal read command is omitted, and a read command for reading soft bits is directly issued.

15. The storage device according to claim 13, wherein: In response to the first tag indicating the use of the specified read redo, the process of issuing a normal read command is omitted, and the read redo command is directly issued according to the read redo parameters specified by the tag.

16. The storage device according to claim 13, wherein: In response to the first tag indicating whether the data carries protection information, it is determined whether to check the protection information of the read data according to whether the data carries the protection information.

17. The storage device according to claim 13, wherein: In response to whether the first tag indicates whether the data is encrypted data, it is determined whether to perform a decryption operation on the read data according to whether the data is encrypted data.

18. The storage device according to any one of claims 2 to 11, wherein: The modified address space accessed through the FTL entry is the address space indicated by the second tag obtained in the NVM data frame accessed through the ordinary physical address space element recorded by the FTL entry. The second tag increases the logical address space and can indicate the particularity of the physical address space.

19. The storage device according to claim 18, wherein: The NVM data frame includes user data, metadata and a second tag. A first randomization seed generated by a special process is written in a first position of the metadata, and a second randomization seed generated by a conventional process is written in a second position of the metadata. When the user data of the NVM data frame is encrypted data, the first randomization seed generated by the special process is recorded only in the first position of the metadata of the NVM data frame. When the user data of the NVM data frame is non-encrypted data, the first randomization seed generated by the special process is recorded in the first position of the metadata of the NVM data frame, and the second randomization seed generated by the conventional process is recorded in the second position of the metadata.

20. The storage device according to claim 18, wherein The second tag in the NVM data frame indicates whether the data carries protection information and / or whether the data is encrypted data.

21. The storage device according to claim 20, wherein: In response to the second tag indicating whether the data carries protection information, it is determined whether to check the protection information of the read data according to whether the data carries the protection information.

22. The storage device according to claim 21, wherein In response to whether the second tag indicates whether the data is encrypted data, it is determined whether to perform a decryption operation on the read data according to whether the data is encrypted data.

23. The storage device according to claim 20, wherein: The metadata of the NVM data frame includes a logical address, error checking information, a first randomization seed and / or first protection information, second protection information and / or a second randomization seed.

24. The storage device according to claim 23, wherein: The second protection information is intentionally written into the metadata to indicate that the NVM data frame where the metadata is located has a UECC.

25. The storage device according to claim 19, wherein When reading the NVM data frame, if it is detected that the first randomization seed is wrong and the second randomization seed is correct, it is determined that the user data of the read NVM data frame is unencrypted data.

26. The storage device according to claim 19, wherein If it is detected that the first randomization seed is wrong and the second randomization seed is also wrong, it means that there is an error in the NVM data frame itself.

27. The storage device according to claim 19, wherein For a typical NVM data frame storing encrypted data, only the first randomization seed is detected, and when the first randomization seed is correct, the metadata of the NVM data frame is recognized as encrypted data by default and decrypted.

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