Shift register, gate drive circuit, display panel and device

Abstract

Embodiments of the present invention relate to a shift register, a gate driving circuit, a display panel and a device. The shift register comprises: a pull-up control module, a first pull-up module, a first pull-down module, a second pull-down module, a third pull-down module, a fourth pull-down module, a fifth pull-down module and an output module. By connecting the shift register to three level signal terminals and controlling the voltage change of the second pull-up node through the first pull-up module, the problem of display abnormality is reduced when the display panel switches between the display stage and the touch stage.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to a shift register, a gate driving circuit, a display panel and a device. Background Art

[0002] The gate drive on array (GOA) technology integrates the scan line driving circuit on the array substrate of the liquid crystal panel, thereby reducing the product cost in terms of material cost and manufacturing process.

[0003] At present, embedded (in-cell) touch display panels are mainly concentrated in small and medium sizes. For medium and large sizes, the corresponding driving load is higher due to the large panel size, and the driving capability of the circuit is required to be higher. The existing large-size in-cell touch display panels are driven by external ICs, which are expensive. In addition, the GOA circuit has a large leakage current because the corresponding driving voltage of the large-size in-cell touch display panel is too high, and the voltage holding capability of the overall circuit is poor, resulting in display abnormalities. Summary of the invention

[0004] In view of this, in order to solve the above technical problems or part of the technical problems, the embodiments of the present invention provide a shift register, a gate driving circuit, a display panel and a device.

[0005] In a first aspect, an embodiment of the present invention provides a shift register, comprising:

[0006] A pull-up control module, a first pull-up module, a first pull-down module, a second pull-down module, a third pull-down module, a fourth pull-down module, a fifth pull-down module and an output module;

[0007] The pull-up control module is connected to the start signal input terminal and the first pull-up node;

[0008] The first pull-up module is connected to the enable signal input terminal, the voltage signal input terminal, the first pull-up node and the second pull-up node;

[0009] The first pull-down module is connected to the first level signal terminal, the first output terminal of the reset signal, the first pull-up node and the first pull-down node;

[0010] The second pull-down module is connected to the voltage signal input terminal, the second level signal terminal, the first pull-up node and the first pull-down node;

[0011] The third pull-down module is connected to the second level signal terminal, the first pull-down node, the second pull-up node and the second pull-down node;

[0012] The fourth pull-down module is connected to the voltage signal input terminal, the enable signal input terminal, the second level signal terminal, and the second pull-down node;

[0013] The fifth pull-down module is connected to the first pull-down node, the first output terminal and the third level signal terminal;

[0014] The output module is connected to the clock signal input terminal, the second pull-up node and the first output terminal.

[0015] In a possible implementation, the pull-up control module includes: a first thin film transistor;

[0016] The drain of the first thin film transistor is connected to the start signal input terminal, the gate is connected to the drain, and the source is connected to the first pull-up node;

[0017] or,

[0018] The pull-up control module includes: a first thin film transistor and a fourteenth thin film transistor;

[0019] The drain of the first thin film transistor is connected to the start signal input terminal, the gate is connected to the drain, and the source is connected to the first pull-up node;

[0020] The gate of the fourteenth thin film transistor is connected to the start signal input terminal, the drain is connected to the first pull-down node, and the source is connected to the second level signal terminal.

[0021] In a possible implementation, the first pull-down module includes: a second thin film transistor and a third thin film transistor;

[0022] The gate of the second thin film transistor is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal;

[0023] The gate of the third thin film transistor is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal;

[0024] or,

[0025] The first pull-down module includes: a second thin film transistor, a third thin film transistor and a fifteenth thin film transistor;

[0026] The gate of the second thin film transistor is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal;

[0027] The gate of the third thin film transistor is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal;

[0028] The gate of the fifteenth thin film transistor is connected to the reset control terminal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal.

[0029] In a possible implementation, the second pull-down module includes: a fourth thin film transistor and a fifth thin film transistor;

[0030] The gate of the fourth thin film transistor is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor;

[0031] The gate of the fifth thin film transistor is connected to the first pull-up node, and the source is connected to the second level signal terminal;

[0032] or,

[0033] The second pull-down module includes: a fourth thin film transistor, a fifth thin film transistor, a seventeenth thin film transistor and an eighteenth thin film transistor;

[0034] The gate of the seventeenth thin film transistor is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the eighteenth thin film transistor and the gate of the fourth thin film transistor;

[0035] The gate of the eighteenth thin film transistor is connected to the first pull-up node, the drain is connected to the source of the seventeenth thin film transistor and the gate of the fourth thin film transistor, and the source is connected to the second level signal terminal;

[0036] The gate of the fourth thin film transistor is connected to the drain of the eighteenth thin film transistor and the source of the seventeenth thin film transistor, the drain is connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor;

[0037] The gate of the fifth thin film transistor is connected to the first pull-up node, and the source is connected to the second level signal terminal.

[0038] In a possible implementation, the first pull-up module includes: a sixth thin film transistor and a seventh thin film transistor;

[0039] The sixth thin film transistor has a gate connected to the first pull-up node, a drain connected to the voltage signal input terminal, and a source connected to the second pull-up node;

[0040] The seventh thin film transistor has a gate connected to the enable signal input terminal, a drain connected to the voltage signal input terminal, and a source connected to the second pull-up node.

[0041] In a possible implementation, the third pull-down module includes: an eighth thin film transistor and a ninth thin film transistor;

[0042] The gate of the eighth thin film transistor is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal;

[0043] The gate of the ninth thin film transistor is connected to the second pull-down node, and the drain is connected to the second pull-up node;

[0044] or,

[0045] The third pull-down module includes: an eighth thin film transistor, a ninth thin film transistor and a sixteenth thin film transistor;

[0046] The gate of the eighth thin film transistor is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal;

[0047] The gate of the ninth thin film transistor is connected to the second pull-down node, and the drain is connected to the second pull-up node;

[0048] The gate of the sixteenth thin film transistor is connected to the first output terminal of the reset signal, the drain is connected to the second pull-up node, and the source is connected to the second level signal terminal.

[0049] In a possible implementation, the fourth pull-down module includes: a tenth thin film transistor and an eleventh thin film transistor;

[0050] The gate of the tenth thin film transistor is connected to the voltage signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-down node;

[0051] The gate of the eleventh thin film transistor is connected to the enable signal input terminal, the drain is connected to the second pull-down node, and the source is connected to the second level signal terminal.

[0052] In a possible implementation, the output module includes: a twelfth thin film transistor;

[0053] The gate of the twelfth thin film transistor is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal;

[0054] or,

[0055] The output module includes: a twelfth thin film transistor and a nineteenth thin film transistor;

[0056] The gate of the nineteenth thin film transistor is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the second output terminal;

[0057] The gate of the twelfth thin film transistor is connected to the gate of the nineteenth thin film transistor, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal.

[0058] In a possible implementation, the fifth pull-down module includes: a thirteenth thin film transistor;

[0059] The gate of the thirteenth thin film transistor is connected to the first pull-down node, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal;

[0060] or,

[0061] The fifth pull-down module includes: a thirteenth thin film transistor;

[0062] The gate of the thirteenth thin film transistor is connected to the first pull-down node, the drain is connected to the second output terminal of the reset signal, and the source is connected to the third level signal terminal;

[0063] or,

[0064] The fifth pull-down module includes: a thirteenth thin film transistor and a twentieth thin film transistor;

[0065] The gate of the twentieth thin film transistor is connected to the first pull-down node, the drain is connected to the second output terminal, and the source is connected to the second level signal terminal;

[0066] The gate of the thirteenth thin film transistor is connected to the first pull-down node, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal.

[0067] In a possible implementation, the shift register further includes: a bootstrap capacitor;

[0068] One end of the bootstrap capacitor is connected to the second pull-up node, and the other end is connected to the first output terminal.

[0069] In a second aspect, an embodiment of the present invention provides a gate driving circuit, comprising: a plurality of cascaded shift registers according to any one of the first aspects above; wherein:

[0070] The first row shift register is connected to the start signal input terminal, the first clock signal input terminal, the first level signal terminal, the second level signal terminal, the third level signal terminal, the output terminal, and the start signal input terminal of the second row shift register;

[0071] The n+1th row shift register is connected to the output terminal of the nth row shift register, the second clock signal input terminal, the first level signal terminal, the second level signal terminal, the third level signal terminal, the output terminal, and the reset signal first output terminal of the nth row shift register, where n is an integer greater than 1.

[0072] In a third aspect, an embodiment of the present invention provides a display panel, characterized in that it includes: a pixel array and the gate driving circuit in the above second aspect.

[0073] In a fourth aspect, an embodiment of the present invention provides a display device, comprising: the display panel in the third aspect.

[0074] The solution provided by the embodiment of the present invention reduces the problem of display abnormality when the display panel switches between the display stage and the touch stage by connecting the shift register to three level signal terminals and controlling the voltage change of the second pull-up node through the first pull-up module. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1A schematic diagram of the structure of a first shift register provided by an embodiment of the present invention;

[0076] Figure 2 A schematic diagram of the structure of a second shift register provided by an embodiment of the present invention;

[0077] Figure 3 A schematic diagram of the structure of a third shift register provided by an embodiment of the present invention;

[0078] Figure 4 A schematic diagram of the structure of a fourth shift register provided by an embodiment of the present invention;

[0079] Figure 5 A schematic diagram of the structure of a fifth shift register provided by an embodiment of the present invention;

[0080] Figure 6 A schematic diagram of the structure of a sixth shift register provided by an embodiment of the present invention;

[0081] Figure 7 A schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present invention;

[0082] Figure 8 A schematic diagram of the timing sequence of circuit control signals provided by an embodiment of the present invention;

[0083] Fig. 9 A schematic diagram of the working state of the gate drive circuit switching in the display / touch stage is provided for an embodiment of the present invention;

[0084] Fig.10 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0085] Fig.11 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0086] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0087] To facilitate understanding of the embodiments of the present invention, specific embodiments will be further explained below in conjunction with the accompanying drawings. The embodiments do not constitute a limitation on the embodiments of the present invention.

[0088] Figure 1A schematic diagram of the structure of a first shift register provided in an embodiment of the present invention, wherein the shift register is applied to a gate drive circuit, and the shift register specifically comprises:

[0089] The pull-up control module 10 , the first pull-down module 20 , the second pull-down module 30 , the first pull-up module 40 , the third pull-down module 50 , the fourth pull-down module 60 , the output module 70 and the fifth pull-down module 80 .

[0090] Furthermore, the shift register also includes a first pull-up node (hereinafter collectively referred to as P1), a second pull-up node (hereinafter collectively referred to as P3), a first pull-down node (hereinafter collectively referred to as P2) and a second pull-down node (hereinafter collectively referred to as P4). The above-mentioned nodes can be understood as connection points formed by connecting two modules or three modules.

[0091] Among them, the circuit structure inside the shift register includes:

[0092] The pull-up control module 10 is connected to the start signal input terminal (hereinafter collectively referred to as Input) and the first pull-up node P1;

[0093] The first pull-up module 40 is connected to an enable signal input terminal (hereinafter collectively referred to as Touch-EN), a voltage signal input terminal (hereinafter collectively referred to as VDD), a first pull-up node P1 and a second pull-up node P3;

[0094] The first pull-down module 20 is connected to the first level signal terminal (hereinafter collectively referred to as VGL2), the first reset signal output terminal (hereinafter collectively referred to as RST-PU), the first pull-up node P1 and the first pull-down node P2;

[0095] The second pull-down module 30 is connected to the voltage signal input terminal VDD, the second level signal terminal (hereinafter collectively referred to as LVGL), the first pull-up node P1 and the first pull-down node P2;

[0096] The third pull-down module 50 is connected to the second level signal terminal LVGL, the first pull-down node P2, the second pull-up node P3 and the second pull-down node P4;

[0097] The fourth pull-down module 60 is connected to the voltage signal input terminal VDD and the enable signal input terminal Touch - EN, a second level signal terminal LVGL, and a second pull-down node P4;

[0098] The fifth pull-down module 80 is connected to the first pull-down node P2, the first output terminal (hereinafter collectively referred to as Gout) and the third level signal terminal (hereinafter collectively referred to as VGL);

[0099] The output module 70 is connected to a clock signal input terminal (hereinafter collectively referred to as CLK), a second pull-up node P3 and a first output terminal Gout.

[0100] The shift register of this embodiment is applied to a gate driving circuit in a display panel. The gate driving circuit is provided with a pixel array correspondingly. Each pixel in the display panel is provided with a shift register correspondingly. The display panel includes: a display stage and a touch stage.

[0101] Furthermore, when the display panel is in the display stage, the enable signal input terminal Touch-EN is connected to a low-level signal, and the start signal input terminal (Input) inputs a high-level start signal (STV signal), the voltage of the first pull-up node P1 is increased through the pull-up control module 10, and the voltage of the first pull-down node P2 is reduced to a fixed level corresponding to the second level signal terminal LVGL through the first pull-down module 20. Because Touch-EN is connected to a low-level signal, the voltage of the second pull-up node P3 is increased from the voltage of the first pull-up node P1 to a high level through the first pull-up module 40 through the third pull-down module 50, and the CLK signal input from the control clock signal input terminal is output by the output module 70 to the first output terminal Gout.

[0102] The first output terminal of the reset signal (hereinafter collectively referred to as RST-PU) is connected to the first output terminal or the second output terminal of the next shift register. When a high level is output at the first output terminal or the second output terminal, the voltage of the first pull-up node P1 is pulled down to VGL2 through the first pull-down module 20, the voltage of the second pull-up node P3 is pulled down to LVGL, the voltage of the first pull-down node P2 is pulled up to VDD, and the voltage of the first pull-up node P1 is maintained at VGL2, and the output voltage of the first output terminal Gout is maintained at VGL until the start signal input terminal (Input) inputs a high level again.

[0103] When the display panel is in the touch stage, the enable signal input terminal Touch-EN is connected to a high-level signal, and the voltage of the second pull-up node P3 is raised to a high level via the first pull-up module 40 and the fourth pull-down module 60 (at this stage, the voltage of the second pull-up node P3 is no longer affected by the voltage of the first pull-up node P1), and the CLK signal inputted by the control clock signal input terminal is outputted by the output module 70 to the first output terminal Gout.

[0104] VGL, LVGL, and VGL2 maintain fixed low-level signals to maintain the voltage stability of the first pull-down module 20, the second pull-down module 30, the third pull-down module 50, the fourth pull-down module 60, and the fifth pull-down module 80; when the display panel is in the touch stage, VGL2 is increased to ΔV higher than LVGL, so that the voltage of the first pull-down module 20 on the P1 leakage path moves from 0 to -ΔV, thereby reducing the leakage current and improving the voltage holding ability of the first pull-up node P1, so as to avoid abnormal display when switching to the display stage due to the drop of the voltage of the first pull-up node P1 due to leakage in the touch stage.

[0105] After the display panel switches from the touch stage to the display stage, the enable signal input terminal Touch-EN changes from a high level to a low level, and the voltage of the second pull-up node P3 is controlled by the voltage of the first pull-up node P1 through the first pull-up module 40, thereby reducing the influence of the voltage of the first pull-up node P1 on the voltage of the second pull-up node P3, thereby reducing the change in the voltage of the second pull-up node P3 before and after the switching between the two stages, and reducing the risk of display horizontal stripes after switching.

[0106] In this embodiment, by connecting the shift register to three level signal terminals and controlling the voltage change of the second pull-up node through the first pull-up module 40, the problem of display abnormality is reduced when the display panel switches between the display stage and the touch stage.

[0107] In an optional scheme of an embodiment of the present invention, in the touch stage, the clock signal input terminal (CLK) can receive the same touch modulation signal superimposed by the CLK signal, the Data signal, and the VCOM signal, and the enable signal input terminal Touch-EN inputs a high level, so that the clock signal input terminal (CLK) outputs the touch modulation signal to the corresponding pixel area through the output module 70, thereby realizing zero-load driving (Zero-load-drving, ZLD), without having to rely on external IC driving, reducing costs, and further reducing the border area.

[0108] In an optional solution of the embodiment of the present invention, the pull-up control module includes (hereinafter referred to as A1): a first thin film transistor, or the pull-up control module includes (hereinafter referred to as A2): a first thin film transistor and a fourteenth thin film transistor.

[0109] In an optional scheme of the embodiment of the present invention, the first pull-down module includes (hereinafter referred to as B1): a second thin film transistor and a third thin film transistor, or the first pull-down module includes (hereinafter referred to as B2): a second thin film transistor, a third thin film transistor and a fifteenth thin film transistor.

[0110] In an optional scheme of an embodiment of the present invention, the second pull-down module includes (hereinafter referred to as C1): a fourth thin film transistor and a fifth thin film transistor, or the second pull-down module includes (hereinafter referred to as C2): a fourth thin film transistor, a fifth thin film transistor, a seventeenth thin film transistor and an eighteenth thin film transistor.

[0111] In an optional solution of the embodiment of the present invention, the first pull-up module includes (hereinafter referred to as D1): a sixth thin film transistor and a seventh thin film transistor.

[0112] In an optional scheme of the embodiment of the present invention, the third pull-down module includes (hereinafter referred to as E1): an eighth thin film transistor and a ninth thin film transistor, or the third pull-down module includes (hereinafter referred to as E2): an eighth thin film transistor, a ninth thin film transistor and a sixteenth thin film transistor.

[0113] In an optional solution of the embodiment of the present invention, the fourth pull-down module (hereinafter referred to as F1) includes: a tenth thin film transistor and an eleventh thin film transistor.

[0114] In an optional solution of the embodiment of the present invention, the output module includes (hereinafter referred to as G1): a twelfth thin film transistor, or the output module includes (hereinafter referred to as G2): a twelfth thin film transistor and a nineteenth thin film transistor.

[0115] In an optional solution of the embodiment of the present invention, the fifth pull-down module includes (hereinafter referred to as H1): a thirteenth thin film transistor, or the fifth pull-down module includes (hereinafter referred to as H2): a thirteenth thin film transistor and a twentieth thin film transistor.

[0116] The internal circuit structure of the shift register provided in this embodiment can be formed by combining any one of (A1, A2), any one of (B1, B2), any one of (C1, C2), any one of D1, (E1, E2), any one of F1, (G1, G2), and any one of (H1, H2).

[0117] There are 64 structural designs of the internal circuit structure of the shift register. The specific structural design can be set according to actual needs, and this embodiment does not make any specific limitation on this.

[0118] The following will take the combination of (A1, B1, C1, D1, E1, F1, G1 and H1), the combination of (A2, B2, C1, D1, E2, F1, G1 and H1), the combination of (A2, B2, C2, D1, E2, F1, G1 and H1), and the combination of (A2, B2, C2, D1, E2, F1, G2 and H2) as examples for introduction.

[0119] Reference Figure 2 FIG. 4 shows a schematic diagram of the structure of a second shift register provided by an embodiment of the present invention. Figure 2 As shown, the structure adopts a combination design of A1, B1, C1, D1, E1, F1, G1 and H1, specifically including:

[0120] The pull-up control module 10 , the first pull-down module 20 , the second pull-down module 30 , the first pull-up module 40 , the third pull-down module 50 , the fourth pull-down module 60 , the output module 70 and the fifth pull-down module 80 .

[0121] The pull-up control module 10 includes: a first thin film transistor M1; a drain of the first thin film transistor M1 is connected to the start signal input terminal, a gate is connected to the drain, and a source is connected to the first pull-up node.

[0122] The first pull-down module 20 includes: a second thin film transistor M2 and a third thin film transistor M3; the gate of the second thin film transistor M2 is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the third thin film transistor M3 is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal;

[0123] The second pull-down module 30 includes: a fourth thin film transistor M4 and a fifth thin film transistor M5; the gate of the fourth thin film transistor M4 is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor; the gate of the fifth thin film transistor M5 is connected to the first pull-up node, and the source is connected to the second level signal terminal;

[0124] The first pull-up module 40 includes: a sixth thin film transistor M6 and a seventh thin film transistor M7; the gate of the sixth thin film transistor is connected to the first pull-up node, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node; the gate of the seventh thin film transistor is connected to the enable signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node.

[0125] The third pull-down module 50 includes: an eighth thin film transistor M8 and a ninth thin film transistor M9; the gate of the eighth thin film transistor M8 is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal;

[0126] The ninth thin film transistor M9 has a gate connected to the second pull-down node, and a drain connected to the second pull-up node.

[0127] The fourth pull-down module 60 includes: a tenth thin film transistor M10 and an eleventh thin film transistor M11; the gate of the tenth thin film transistor M10 is connected to the voltage signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-down node; the gate of the eleventh thin film transistor M11 is connected to the enable signal input terminal, the drain is connected to the second pull-down node, and the source is connected to the second level signal terminal.

[0128] The output module 70 includes: a twelfth thin film transistor M12; the gate of the twelfth thin film transistor M12 is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal.

[0129] The fifth pull-down module 80 includes: a thirteenth thin film transistor M13; the gate of the thirteenth thin film transistor M13 is connected to the first pull-down node, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal.

[0130] The shift register further includes: a bootstrap capacitor C1; one end of the bootstrap capacitor C1 is connected to the second pull-up node, and the other end is connected to the first output end.

[0131] Reference Figure 3 FIG. 4 shows a schematic diagram of the structure of a third shift register provided by an embodiment of the present invention. Figure 3 As shown, the structure adopts a combination design of A1, B1, C1, D1, E1, F1, G1 and H1, specifically including:

[0132] The pull-up control module 10 , the first pull-down module 20 , the second pull-down module 30 , the first pull-up module 40 , the third pull-down module 50 , the fourth pull-down module 60 , the output module 70 and the fifth pull-down module 80 .

[0133] The pull-up control module 10 includes: a first thin film transistor M1; a drain of the first thin film transistor M1 is connected to the start signal input terminal, a gate is connected to the drain, and a source is connected to the first pull-up node.

[0134] The first pull-down module 20 includes: a second thin film transistor M2 and a third thin film transistor M3; the gate of the second thin film transistor M2 is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the third thin film transistor M3 is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal;

[0135] The second pull-down module 30 includes: a fourth thin film transistor M4 and a fifth thin film transistor M5; the gate of the fourth thin film transistor M4 is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor; the gate of the fifth thin film transistor M5 is connected to the first pull-up node, and the source is connected to the second level signal terminal;

[0136] The first pull-up module 40 includes: a sixth thin film transistor M6 and a seventh thin film transistor M7; the gate of the sixth thin film transistor is connected to the first pull-up node, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node; the gate of the seventh thin film transistor is connected to the enable signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node.

[0137] The third pull-down module 50 includes: an eighth thin film transistor M8 and a ninth thin film transistor M9; the gate of the eighth thin film transistor M8 is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal;

[0138] The ninth thin film transistor M9 has a gate connected to the second pull-down node, and a drain connected to the second pull-up node.

[0139] The fourth pull-down module 60 includes: a tenth thin film transistor M10 and an eleventh thin film transistor M11; the gate of the tenth thin film transistor M10 is connected to the voltage signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-down node; the gate of the eleventh thin film transistor M11 is connected to the enable signal input terminal, the drain is connected to the second pull-down node, and the source is connected to the second level signal terminal.

[0140] The output module 70 includes: a twelfth thin film transistor M12; the gate of the twelfth thin film transistor M12 is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal.

[0141] The fifth pull-down module 80 includes: a thirteenth thin film transistor M13; the gate of the thirteenth thin film transistor M13 is connected to the first pull-down node, the drain is connected to the second output terminal of the reset signal (Rst-Gout), and the source is connected to the third level signal terminal.

[0142] The shift register further includes: a bootstrap capacitor C1; one end of the bootstrap capacitor C1 is connected to the second pull-up node, and the other end is connected to the first output end.

[0143] Reference Figure 4 FIG. 4 shows a schematic diagram of the structure of a fourth shift register provided by an embodiment of the present invention. Figure 4 As shown, the structure adopts a combination design of A2, B2, C1, D1, E2, F1, G1 and H1, specifically including:

[0144] The pull-up control module 10 , the first pull-down module 20 , the second pull-down module 30 , the first pull-up module 40 , the third pull-down module 50 , the fourth pull-down module 60 , the output module 70 and the fifth pull-down module 80 .

[0145] in,

[0146] The pull-up control module 10 includes: a first thin film transistor M1 and a fourteenth thin film transistor M14; the drain of the first thin film transistor M1 is connected to the start signal input terminal, the gate is connected to the drain, and the source is connected to the first pull-up node; the gate of the fourteenth thin film transistor M14 is connected to the start signal input terminal, the drain is connected to the first pull-down node, and the source is connected to the second level signal terminal.

[0147] The first pull-down module 20 includes: a second thin film transistor M2, a third thin film transistor M3 and a fifteenth thin film transistor M15; the gate of the second thin film transistor M2 is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the third thin film transistor M3 is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the fifteenth thin film transistor M15 is connected to the reset control terminal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal.

[0148] The second pull-down module 30 includes: a fourth thin film transistor M4 and a fifth thin film transistor M5; the gate of the fourth thin film transistor M4 is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor; the gate of the fifth thin film transistor M5 is connected to the first pull-up node, and the source is connected to the second level signal terminal;

[0149] The first pull-up module 40 includes: a sixth thin film transistor M6 and a seventh thin film transistor M7; the gate of the sixth thin film transistor is connected to the first pull-up node, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node; the gate of the seventh thin film transistor is connected to the enable signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node.

[0150] The third pull-down module 50 includes: an eighth thin film transistor M8, a ninth thin film transistor M9 and a sixteenth thin film transistor M16; the gate of the eighth thin film transistor M8 is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal; the gate of the ninth thin film transistor M9 is connected to the second pull-down node, and the drain is connected to the second pull-up node; the gate of the sixteenth thin film transistor M16 is connected to the first output terminal of the reset signal, the drain is connected to the second pull-up node, and the source is connected to the second level signal terminal.

[0151] The fourth pull-down module 60 includes: a tenth thin film transistor M10 and an eleventh thin film transistor M11; the gate of the tenth thin film transistor M10 is connected to the voltage signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-down node; the gate of the eleventh thin film transistor M11 is connected to the enable signal input terminal, the drain is connected to the second pull-down node, and the source is connected to the second level signal terminal.

[0152] The output module 70 includes: a twelfth thin film transistor M12; the gate of the twelfth thin film transistor M12 is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal.

[0153] The fifth pull-down module 80 includes: a thirteenth thin film transistor M13; the gate of the thirteenth thin film transistor M13 is connected to the first pull-down node, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal.

[0154] The shift register further includes: a bootstrap capacitor C1; one end of the bootstrap capacitor C1 is connected to the second pull-up node, and the other end is connected to the first output end.

[0155] Reference Figure 5 FIG. 4 shows a schematic diagram of the structure of a fifth shift register provided by an embodiment of the present invention. Figure 5As shown, the structure adopts a combination design of A2, B2, C2, D1, E2, F1, G1 and H1, specifically including:

[0156] The pull-up control module 10 , the first pull-down module 20 , the second pull-down module 30 , the first pull-up module 40 , the third pull-down module 50 , the fourth pull-down module 60 , the output module 70 and the fifth pull-down module 80 .

[0157] The pull-up control module 10 includes: a first thin film transistor M1 and a fourteenth thin film transistor M14; the drain of the first thin film transistor M1 is connected to the start signal input terminal, the gate is connected to the drain, and the source is connected to the first pull-up node; the gate of the fourteenth thin film transistor M14 is connected to the start signal input terminal, the drain is connected to the first pull-down node, and the source is connected to the second level signal terminal.

[0158] The first pull-down module 20 includes: a second thin film transistor M2, a third thin film transistor M3 and a fifteenth thin film transistor M15; the gate of the second thin film transistor M2 is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the third thin film transistor M3 is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the fifteenth thin film transistor M15 is connected to the reset control terminal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal.

[0159] The second pull-down module 30 includes: a fourth thin film transistor M4, a fifth thin film transistor M5, a seventeenth thin film transistor M17 and an eighteenth thin film transistor M18; the gate of the seventeenth thin film transistor M17 is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the eighteenth thin film transistor and the gate of the fourth thin film transistor; the gate of the eighteenth thin film transistor M18 is connected to the first pull-up node, the drain is connected to the source of the seventeenth thin film transistor and the gate of the fourth thin film transistor, and the source is connected to the second level signal terminal; the gate of the fourth thin film transistor M4 is connected to the drain of the eighteenth thin film transistor and the source of the seventeenth thin film transistor, the drain is connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor; the gate of the fifth thin film transistor M15 is connected to the first pull-up node, and the source is connected to the second level signal terminal.

[0160] The first pull-up module 40 includes: a sixth thin film transistor M6 and a seventh thin film transistor M7; the gate of the sixth thin film transistor is connected to the first pull-up node, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node; the gate of the seventh thin film transistor is connected to the enable signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node.

[0161] The third pull-down module 50 includes: an eighth thin film transistor M8, a ninth thin film transistor M9 and a sixteenth thin film transistor M16; the gate of the eighth thin film transistor M8 is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal; the gate of the ninth thin film transistor M9 is connected to the second pull-down node, and the drain is connected to the second pull-up node; the gate of the sixteenth thin film transistor M16 is connected to the first output terminal of the reset signal, the drain is connected to the second pull-up node, and the source is connected to the second level signal terminal.

[0162] The fourth pull-down module 60 includes: a tenth thin film transistor M10 and an eleventh thin film transistor M11; the gate of the tenth thin film transistor M10 is connected to the voltage signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-down node; the gate of the eleventh thin film transistor M11 is connected to the enable signal input terminal, the drain is connected to the second pull-down node, and the source is connected to the second level signal terminal.

[0163] The output module 70 includes: a twelfth thin film transistor M12; the gate of the twelfth thin film transistor M12 is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal.

[0164] The fifth pull-down module 80 includes: a thirteenth thin film transistor M13; the gate of the thirteenth thin film transistor M13 is connected to the first pull-down node, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal.

[0165] The shift register further includes: a bootstrap capacitor C1; one end of the bootstrap capacitor C1 is connected to the second pull-up node, and the other end is connected to the first output end.

[0166] Reference Figure 6 FIG. 4 shows a schematic diagram of the structure of a sixth shift register provided by an embodiment of the present invention. Figure 6 As shown, the structure adopts a combination design of A2, B2, C2, D1, E2, F1, G2 and H2, specifically including:

[0167] The pull-up control module 10 , the first pull-down module 20 , the second pull-down module 30 , the first pull-up module 40 , the third pull-down module 50 , the fourth pull-down module 60 , the output module 70 and the fifth pull-down module 80 .

[0168] in,

[0169] The pull-up control module 10 includes: a first thin film transistor M1 and a fourteenth thin film transistor M14; the drain of the first thin film transistor M1 is connected to the start signal input terminal, the gate is connected to the drain, and the source is connected to the first pull-up node; the gate of the fourteenth thin film transistor M14 is connected to the start signal input terminal, the drain is connected to the first pull-down node, and the source is connected to the second level signal terminal.

[0170] The first pull-down module 20 includes: a second thin film transistor M2, a third thin film transistor M3 and a fifteenth thin film transistor M15; the gate of the second thin film transistor M2 is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the third thin film transistor M3 is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; the gate of the fifteenth thin film transistor M15 is connected to the reset control terminal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal.

[0171] The second pull-down module 30 includes: a fourth thin film transistor M4 and a fifth thin film transistor M5; the gate of the fourth thin film transistor M4 is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor; the gate of the fifth thin film transistor M5 is connected to the first pull-up node, and the source is connected to the second level signal terminal;

[0172] The first pull-up module 40 includes: a sixth thin film transistor M6 and a seventh thin film transistor M7; the gate of the sixth thin film transistor is connected to the first pull-up node, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node; the gate of the seventh thin film transistor is connected to the enable signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node.

[0173] The third pull-down module 50 includes: an eighth thin film transistor M8, a ninth thin film transistor M9 and a sixteenth thin film transistor M16; the gate of the eighth thin film transistor M8 is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal; the gate of the ninth thin film transistor M9 is connected to the second pull-down node, and the drain is connected to the second pull-up node; the gate of the sixteenth thin film transistor M16 is connected to the first output terminal of the reset signal, the drain is connected to the second pull-up node, and the source is connected to the second level signal terminal.

[0174] The fourth pull-down module 60 includes: a tenth thin film transistor M10 and an eleventh thin film transistor M11; the gate of the tenth thin film transistor M10 is connected to the voltage signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-down node; the gate of the eleventh thin film transistor M11 is connected to the enable signal input terminal, the drain is connected to the second pull-down node, and the source is connected to the second level signal terminal.

[0175] The output module 70 includes: a twelfth thin film transistor M12 and a nineteenth thin film transistor M19; the gate of the nineteenth thin film transistor M19 is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the second output terminal (OUT.C); the gate of the twelfth thin film transistor M12 is connected to the gate of the nineteenth thin film transistor, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal.

[0176] The fifth pull-down module 80 includes: a thirteenth thin film transistor M13 and a twentieth thin film transistor M20; the gate of the twentieth thin film transistor M13 is connected to the first pull-down node, the drain is connected to the second output terminal, and the source is connected to the second level signal terminal; the gate of the thirteenth thin film transistor M20 is connected to the first pull-down node, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal.

[0177] The shift register further includes: a bootstrap capacitor C1; one end of the bootstrap capacitor C1 is connected to the second pull-up node, and the other end is connected to the first output end.

[0178] Figure 7 A schematic diagram of a gate drive circuit is provided for an embodiment of the present invention. Figure 7 The circuit shown specifically includes:

[0179] A plurality of shift registers according to any one of the first aspects described above are cascaded; wherein,

[0180] The first row shift register 1 is connected to a start signal input terminal (Input, for receiving an STV signal), a first clock signal input terminal (for receiving a CLK1 signal), a first level signal terminal (VGL2), a second level signal terminal (LVGL), a third level signal terminal (LVGL), an output terminal (Gout), and a start signal input terminal (Input) of the second row shift register;

[0181] The shift register n of the n+1th row is connected to the output terminal (Gout or OUT.C) of the shift register of the nth row, the second clock signal input terminal (for receiving the CLK2 signal), the first level signal terminal (VGL2), the second level signal terminal (LVGL), the third level signal terminal (LVGL), the output terminal (Gout), and the reset signal first output terminal (Rst) of the shift register of the nth row, where n is an integer greater than 1.

[0182] The following will use the shift register as Figure 6 The gate drive circuit is introduced by taking the shift register shown in the figure as an example.

[0183] The Input of the first row of shift register 1 is connected to the STV signal, which controls the shift register to output the Gout signal in sequence. The Input of the n+1th row of shift register n+1 is connected to the Gout output of the nth row of shift register n. The Gout output of the n+1th row is connected to the Rst input of the nth row of shift register n and the Input of the n+2th row of shift register n+2, which reset the Gout output of the nth row of shift register n and open the input of the n+2th row of shift register n+2.

[0184] When the display panel is in the display stage, the enable signal input terminal Touch-EN is connected to a low-level signal, and the start signal input terminal (Input) inputs a high-level start signal (STV signal), M1 is turned on, the voltage at point P1 rises, M5 and M18 are turned on, and the voltage at point P2 drops to LVGL, so that M3, M13, M20, and M8 are turned off. Because Touch_EN is at a low level, M7 and M11 are turned off, and M9 is turned on. The voltage at point P3 is increased to a high level by turning on M6 from the voltage at point P2, and M12 and M19 are turned on, so that the CLK signal can be output to Gout through M12 and to Out_C through M19.

[0185] Out_C is connected to the next row of Input. When Out_C outputs a high level, M1 of the next row is turned on. After the same process as above, Out_C of the next row is output to Rst_PU of this row, so that M2 and M16 are turned on, the voltage at point P1 is pulled down to VGL2, the voltage at point P3 is pulled down to LVGL, M5 and M18 are turned off, and the voltage at point P2 is pulled up to VDD by M4. M12, M19, M9, and M18 are turned on, so that the voltage at point P2 is maintained at the VGL2 voltage, and Gout is maintained at the VGL voltage until the Input inputs a high level again, so that the above process is repeated. At this stage, the circuit realizes the row-by-row output of the shift register and completes the row-by-row writing of the display data of the display panel.

[0186] When the display panel is in the touch stage, Touch_EN maintains a high level, M7 and M11 are turned on, and M9 is turned off. The voltage at point P4 of all display panels is pulled up to a high level by turning on M7. M12 and M19 are turned on so that the CLK signal can be output to Gout through M12. The voltage at point P4 is no longer controlled by the voltage at point P1.

[0187] VGL, LVGL, and VGL2 maintain fixed low-level signals to maintain the voltage stability of the first pull-down module 20, the second pull-down module 30, the third pull-down module 50, the fourth pull-down module 60, and the fifth pull-down module 80; when the display panel is in the touch stage, VGL2 is increased to ΔV higher than LVGL, so that the voltage of the first pull-down module 20 on the leakage path of point P1 moves from 0 to -ΔV, thereby reducing the leakage current and improving the voltage holding capacity of point P1, so as to avoid abnormal display when switching to the display stage due to the drop of the voltage of the first pull-up node P1 due to leakage in the touch stage.

[0188] After the display panel switches from the touch stage to the display stage, the enable signal input terminal Touch-EN changes from a high level to a low level, and the voltage at point P3 is controlled by the voltage at point P1 through the first pull-up module 40, thereby reducing the influence of the voltage at point P1 on the voltage at point P3, thereby reducing the change in the voltage at point P3 before and after the switching between the two stages, and reducing the risk of display horizontal stripes after switching.

[0189] In this embodiment, the shift register is connected to three level signal terminals, and the voltage change of the second pull-up node is controlled by the first pull-up module 40 to reduce the problem of display abnormality when the display panel switches between the display stage and the touch stage.

[0190] In an optional solution of the embodiment of the present invention, the gate driving circuit can be applied to an in-cell touch display panel in LHB (Long-Horizontal-Blanking) mode and support ZLD touch driving at the same time. The following is an introduction taking two CLK signals as an example:

[0191] Reference Figure 8 , is a schematic diagram of the timing of the circuit control signal provided by the embodiment of the present invention. At the start of a frame display, STV gives a high-level pulse signal to the Input of the first row shift register 1, so that the shift register starts scanning row by row, and sequentially outputs the Gout signal corresponding to the CLK signal to the display pixel area, turns on the pixels of the corresponding row, writes the Data signal to the corresponding pixel, and completes the pixel charging row by row. In this stage, Touch_EN is at a low level; the CLK signal is a normal display signal, the low level is VGL, and the high level is VGH; VGL, LVGL, and VGL2 are all fixed voltage values, which can be the same or different; VCOM is a fixed voltage Vcom; Data input is the voltage corresponding to the display screen.

[0192] After the predetermined n-row scan, the display panel switches from the display stage to the touch stage, Touch_EN becomes high, and the CLK signal, VCOM signal, and Data signal are all superimposed with the same touch modulation signal to achieve ZLD touch drive. In this stage, the P1 point voltage of the nth and n+1th rows is high, and the P1 point voltage of other rows is low. When the touch stage ends, it switches to the display stage, the CLK signal returns to the state at the beginning of the touch stage, the n+1th row Gout outputs a high level, and the gate drive circuit continues to scan row by row from the n+1th row, such as Fig. 9 As shown, after completing n-line scanning, the process switches to the touch control stage again, and the cycle continues.

[0193] In a touch control phase, the voltage at point P1 of the n+1th row is kept at a high level. After the touch control phase ends, the gate driving circuit can continue to scan row by row in the same state as at the beginning of the touch control.

[0194] Figure 6The voltage at point P1 will gradually decrease due to leakage of M2, M15 and M3. VGL2 remains at LVGL during the display phase, and the voltage is increased to LVGL+ΔV during the touch phase, where ΔV is 2 to 10V. LVGL remains at LVGL, and VGL remains at VGL. Due to the increase in VGL2, Figure 6 The gate voltage of M2, M15 and M3 is LVGL, the source voltage is LVGL+ΔV, and the drain voltage is P1 voltage, so the gate-source voltage difference Vgs becomes -ΔV, its operating point shifts to the left, and the leakage current is reduced. Therefore, the ability to maintain the voltage at point P2 can be improved, avoiding the black screen abnormality caused by the failure of the gate drive circuit to restore normal scanning in the subsequent display stage due to the decrease in the voltage leakage at point P1 in the touch stage.

[0195] Furthermore, the gate drive circuit in the embodiment of the present invention directly controls the Gout output by P3, and the P1 point affects the P3 point voltage by controlling the M17 switch. The P3 point voltage is less affected by the change of the P1 point voltage, thereby reducing the risk of display horizontal stripes caused by the P1 voltage difference during touch-display switching.

[0196] In an embodiment of the present invention, ZLD driving can be supported in the touch stage, and the same touch modulation signal is superimposed on the CLK signal, the Data signal, and the VCOM signal, wherein the CLK signal is superimposed on the basis of the VGL level, and the Data and VCOM are superimposed on the basis of the Vcom level, and the amplitude of the modulation signal is 2 to 5 V. In the touch stage, Touch_EN is at a high level, and M7 of all gate drive circuits is turned on, so that the P3 point of all shift registers is at a high level, and the signal on CLK can be output to all Gate lines through M12, so that the gate lines of all pixel rows of the entire panel are all equipped with touch modulation signals. At the same time, combined with the touch modulation signals on the Data and VCOM electrodes, ZLD touch drive of touch can be realized, and the touch effect is improved, and it is no longer necessary to rely on external IC drivers, which reduces costs and further reduces the border area.

[0197] Fig.10 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Fig.10 As shown, the display panel 1000 includes:

[0198] Gate driving circuit 100 and pixel array 200;

[0199] The gate drive circuit is used to drive the pixel array.

[0200] The gate drive circuit can be Figure 7 The gate drive circuit is shown.

[0201] The display panel according to the embodiment of the present invention adopts the gate driving circuit in the above embodiment. When the display panel switches between the display stage and the touch stage, the problem of display abnormality is reduced, and the ZLD touch driving of touch is realized, thereby improving the touch effect. It is no longer necessary to rely on an external IC driver, which reduces costs and further reduces the border area.

[0202] Fig.11 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.11 As shown, the display device 10000 includes:

[0203] Display panel 1000;

[0204] The display panel may be Fig.10 The display panel shown.

[0205] The display device according to the embodiment of the present invention adopts the display panel in the above embodiment. When the display device switches between the display stage and the touch stage, the problem of display abnormality is reduced, and the ZLD touch drive of touch is realized, thereby improving the touch effect. It is no longer necessary to rely on an external IC driver, which reduces costs and further reduces the border area.

[0206] The professionals should further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0207] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0208] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A shift register, characterized in that: The shift register is applied to a gate drive circuit in a display panel, the gate drive circuit is correspondingly provided with a pixel array, each pixel in the display panel is correspondingly provided with a shift register, the display panel includes: a display stage and a touch stage, and the shift register includes: A pull-up control module, a first pull-up module, a first pull-down module, a second pull-down module, a third pull-down module, a fourth pull-down module, a fifth pull-down module and an output module; The pull-up control module is connected to the start signal input terminal and the first pull-up node; The first pull-up module is connected to the enable signal input terminal, the voltage signal input terminal, the first pull-up node and the second pull-up node; The first pull-down module is connected to the first level signal terminal, the first output terminal of the reset signal, the first pull-up node and the first pull-down node; The second pull-down module is connected to the voltage signal input terminal, the second level signal terminal, the first pull-up node and the first pull-down node; The third pull-down module is connected to the second level signal end, the first pull-down node, the second pull-up node and the second pull-down node; The fourth pull-down module is connected to the voltage signal input terminal, the enable signal input terminal, the second level signal terminal, and the second pull-down node; The fifth pull-down module is connected to the second pull-up node, the first output terminal and the third level signal terminal; The output module is connected to the clock signal input terminal, the second pull-up node and the first output terminal.

2. The shift register according to claim 1, characterized in that: The pull-up control module includes: a first thin film transistor; The drain of the first thin film transistor is connected to the start signal input terminal, the gate is connected to the drain, and the source is connected to the first pull-up node; or, The pull-up control module includes: a first thin film transistor and a fourteenth thin film transistor; The drain of the first thin film transistor is connected to the start signal input terminal, the gate is connected to the drain, and the source is connected to the first pull-up node; The gate of the fourteenth thin film transistor is connected to the start signal input terminal, the drain is connected to the first pull-down node, and the source is connected to the second level signal terminal.

3. The shift register according to claim 1, wherein: The first pull-down module includes: a second thin film transistor and a third thin film transistor; The gate of the second thin film transistor is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; The gate of the third thin film transistor is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; or, The first pull-down module includes: a second thin film transistor, a third thin film transistor and a fifteenth thin film transistor; The gate of the second thin film transistor is connected to the first output terminal of the reset signal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; The gate of the third thin film transistor is connected to the first pull-down node, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal; The gate of the fifteenth thin film transistor is connected to the reset control terminal, the drain is connected to the first pull-up node, and the source is connected to the first level signal terminal.

4. The shift register according to claim 1, wherein: The second pull-down module includes: a fourth thin film transistor and a fifth thin film transistor; The gate of the fourth thin film transistor is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor; The gate of the fifth thin film transistor is connected to the first pull-up node, and the source is connected to the second level signal terminal; or, The second pull-down module includes: a fourth thin film transistor, a fifth thin film transistor, a seventeenth thin film transistor and an eighteenth thin film transistor; The gate of the seventeenth thin film transistor is connected to the drain, the gate and the drain are connected to the voltage signal input terminal, and the source is connected to the drain of the eighteenth thin film transistor and the gate of the fourth thin film transistor; The gate of the eighteenth thin film transistor is connected to the first pull-up node, the drain is connected to the source of the seventeenth thin film transistor and the gate of the fourth thin film transistor, and the source is connected to the second level signal terminal; The gate of the fourth thin film transistor is connected to the drain of the eighteenth thin film transistor and the source of the seventeenth thin film transistor, the drain is connected to the voltage signal input terminal, and the source is connected to the drain of the fifth thin film transistor; The gate of the fifth thin film transistor is connected to the first pull-up node, and the source is connected to the second level signal terminal.

5. The shift register according to claim 1, characterized in that: The first pull-up module includes: a sixth thin film transistor and a seventh thin film transistor; The gate of the sixth thin film transistor is connected to the first pull-up node, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-up node; The seventh thin film transistor has a gate connected to the enable signal input terminal, a drain connected to the voltage signal input terminal, and a source connected to the second pull-up node.

6. The shift register according to claim 1, characterized in that: The third pull-down module includes: an eighth thin film transistor and a ninth thin film transistor; The gate of the eighth thin film transistor is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal; The gate electrode of the ninth thin film transistor is connected to the second pull-down node, and the drain electrode is connected to the second pull-up node; or, The third pull-down module includes: an eighth thin film transistor, a ninth thin film transistor and a sixteenth thin film transistor; The gate of the eighth thin film transistor is connected to the first pull-down node, the drain is connected to the source of the ninth thin film transistor, and the source is connected to the second level signal terminal; The gate electrode of the ninth thin film transistor is connected to the second pull-down node, and the drain electrode is connected to the second pull-up node; The gate of the sixteenth thin film transistor is connected to the first output terminal of the reset signal, the drain is connected to the second pull-up node, and the source is connected to the second level signal terminal.

7. The shift register according to claim 1, characterized in that: The fourth pull-down module comprises: a tenth thin film transistor and an eleventh thin film transistor; The gate of the tenth thin film transistor is connected to the voltage signal input terminal, the drain is connected to the voltage signal input terminal, and the source is connected to the second pull-down node; The gate of the eleventh thin film transistor is connected to the enable signal input terminal, the drain is connected to the second pull-down node, and the source is connected to the second level signal terminal.

8. The shift register according to claim 1, characterized in that: The output module includes: a twelfth thin film transistor; The gate of the twelfth thin film transistor is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal; or, The output module includes: a twelfth thin film transistor and a nineteenth thin film transistor; The gate of the nineteenth thin film transistor is connected to the second pull-up node, the drain is connected to the clock signal input terminal, and the source is connected to the second output terminal; The gate of the twelfth thin film transistor is connected to the gate of the nineteenth thin film transistor, the drain is connected to the clock signal input terminal, and the source is connected to the first output terminal.

9. The shift register according to claim 1, characterized in that: The fifth pull-down module includes: a thirteenth thin film transistor; The gate of the thirteenth thin film transistor is connected to the first pull-down node, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal; or, The fifth pull-down module includes: a thirteenth thin film transistor; The gate of the thirteenth thin film transistor is connected to the second output terminal of the reset signal, the drain is connected to the first output terminal, and the source is connected to the third level signal terminal; or, The fifth pull-down module includes: a thirteenth thin film transistor and a twentieth thin film transistor; The gate of the twentieth thin film transistor is connected to the first pull-down node, the drain is connected to the second output terminal, and the source is connected to the second level signal terminal; The thirteenth thin film transistor has a gate connected to the first pull-down node, a drain connected to the first output terminal, and a source connected to the third level signal terminal.

10. The shift register according to any one of claims 1 to 9, characterized in that: The shift register further includes: a bootstrap capacitor; One end of the bootstrap capacitor is connected to the second pull-up node, and the other end is connected to the first output end.

11. A gate drive circuit, characterized in that: include: A plurality of cascaded shift registers as claimed in any one of claims 1 to 10; wherein: The shift registers in the first row are connected to a start signal input terminal, a first clock signal input terminal, a first level signal terminal, a second level signal terminal, a third level signal terminal, an output terminal, and a start signal input terminal of the shift registers in the second row; The shift register in the n+1th row is connected to the output end of the shift register in the nth row, the second clock signal input end, the first level signal end, the second level signal end, the third level signal end, the output end, and the reset signal first output end of the shift register in the nth row, where n is an integer greater than 1.

12. A display panel, characterized in that: include: A pixel array and a gate driving circuit as claimed in claim 11.

13. A display device, characterized in that: include: The display panel as claimed in claim 12.

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