Display device

Abstract

A display device is provided. The display device includes: a substrate; a first electrode base layer and a second electrode base layer, spaced apart from each other on the substrate; a first electrode and a second electrode, the first electrode being on the first electrode base layer and the second electrode being on the second electrode base layer; a first inner bank and a second inner bank, the first inner bank being between the first electrode base layer and the first electrode, and the second inner bank being between the second electrode base layer and the second electrode; and a light-emitting element, between the first electrode and the second electrode, at least one end of the light-emitting element being electrically connected to the first electrode or the second electrode, wherein side surfaces of at least one end of each of the first electrode base layer and the second electrode base layer are in the same line as side surfaces of corresponding ends of one of the first electrode and the second electrode.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0153363, filed with the Korean Intellectual Property Office on November 26, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] With the development of multimedia, display devices have become increasingly important. Accordingly, various types of display devices, such as organic light-emitting displays and liquid crystal displays, are being used.

[0004] A display device is a device for displaying an image and includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element such as a light-emitting diode (LED). For example, the LED may be an organic light-emitting diode (OLED) using an organic material as a fluorescent material, or may be an inorganic LED using an inorganic material as a fluorescent material. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device in which an area where a light-emitting element is disposed is separated from an area where a circuit element is disposed.

[0006] Aspects of the present disclosure also provide a display device that can be manufactured by reducing the number of processes because an electrode and a circuit element or wiring electrically connected to the light-emitting element are formed in the same process.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0008] According to some example embodiments of the present disclosure, a display device includes: a substrate; a first electrode substrate layer and a second electrode substrate layer spaced apart from each other on the substrate; a first electrode on the first electrode substrate layer and a second electrode on the second electrode substrate layer; a first inner dike between the first electrode substrate layer and the first electrode and a second inner dike between the second electrode substrate layer and the second electrode; and a light-emitting element between the first electrode and the second electrode, at least one end of the light-emitting element being electrically connected to the first electrode or the second electrode, wherein side surfaces of at least one end of each of the first electrode substrate layer and the second electrode substrate layer are in the same line as side surfaces of an end of a corresponding one of the first electrode and the second electrode.

[0009] In some exemplary embodiments, the first electrode may cover the outer surface of the first inner embankment, and the second electrode may cover the outer surface of the second inner embankment.

[0010] In some exemplary embodiments, at least a portion of the lower surface of the first electrode may directly contact the upper surface of the first electrode base layer, and at least a portion of the lower surface of the second electrode may directly contact the upper surface of the second electrode base layer.

[0011] In some exemplary embodiments, at least one side surface of each of the first electrode base layer and the second electrode base layer may not contact the corresponding one of the first electrode and the second electrode.

[0012] In some exemplary embodiments, the first electrode and the second electrode may not directly contact the substrate.

[0013] In some exemplary embodiments, the first inner embankment and the second inner embankment may be directly on the first electrode base layer and the second electrode base layer, respectively.

[0014] In some exemplary embodiments, the distance between the first electrode and the second electrode may be less than the distance between the first inner embankment and the second inner embankment.

[0015] In some exemplary embodiments, at least one end of the light-emitting element may be on the first electrode or the second electrode.

[0016] In some exemplary embodiments, the display device may further include a first insulating layer between the first electrode and the second electrode and covering at least a portion of each of the first electrode and the second electrode, wherein the light-emitting element may be on the first insulating layer.

[0017] In some exemplary embodiments, the first electrode base layer and the second electrode base layer may directly contact the first insulating layer.

[0018] In some exemplary embodiments, the display device may further include a first contact electrode contacting an end of the light-emitting element and the first electrode and a second contact electrode contacting the other end of the light-emitting element and the second electrode.

[0019] In some exemplary embodiments, the substrate includes an emission region and a non-emission region, and the first electrode, the second electrode, and the light-emitting element may be in the emission region, and the display device may further include a first data conductive layer in the non-emission region.

[0020] In some exemplary embodiments, the display device may further include a first interlayer insulating layer on the substrate, wherein the first data conductive layer and the first electrode base layer may be directly on the first interlayer insulating layer.

[0021] In some exemplary embodiments, the first electrode may be electrically connected to the first data conductive layer.

[0022] In some exemplary embodiments, the substrate further includes a non-display area, and the display device may further include a pad substrate layer in the non-display area and a pad electrode on the pad substrate layer.

[0023] In some exemplary embodiments, the pad substrate layer may be at the same layer as the first electrode substrate layer, and the pad electrode may be at the same layer as the first electrode.

[0024] In some exemplary embodiments, the display device may further include a first planarization layer on the first data conductive layer in the non-emission area and an outer bank surrounding the first electrode and the second electrode in the emission area, wherein the first planarization layer, the outer bank, and the first inner bank may be at the same layer.

[0025] In some exemplary embodiments, the first planarization layer, the outer bank, and the first inner bank may have different heights.

[0026] In some exemplary embodiments, the display device may further include a data line between the outer bank and the substrate, wherein at least one side surface of the data line may not contact the outer bank.

[0027] According to some exemplary embodiments of the present disclosure, a display device includes: a substrate having an emission area and a non-emission area; a first interlayer insulating layer on the substrate; a first data conductive layer on the first interlayer insulating layer and including source / drain electrodes of driving transistors and a plurality of electrode substrate layers in the emission area; a via layer on the first data conductive layer and including a first planarization layer in the non-emission area and an inner bank on the plurality of electrode substrate layers; a plurality of electrodes respectively on the plurality of electrode substrate layers; and a plurality of light-emitting elements between the plurality of electrodes, wherein the plurality of electrode substrate layers include a first electrode substrate layer and a second electrode substrate layer spaced apart from the first electrode substrate layer, the plurality of electrodes include a first electrode on the first electrode substrate layer and a second electrode on the second electrode substrate layer, and the plurality of light-emitting elements are between the first electrode and the second electrode.

[0028] In some exemplary embodiments, the inner bank may include a first inner bank between the first electrode substrate layer and the first electrode and a second inner bank between the second electrode substrate layer and the second electrode, and the first electrode and the second electrode may respectively cover outer surfaces of the first inner bank and the second inner bank.

[0029] In some exemplary embodiments, a width of the first inner bank measured in one direction may be less than a width of the first electrode substrate layer measured in the same direction.

[0030] In some exemplary embodiments, at least a part of a lower surface of the first electrode may directly contact the first electrode substrate layer.

[0031] In some example embodiments, the height of the first planarization layer may be greater than the height of the inner dike.

[0032] In some example embodiments, the via layer may further include an outer dike at the periphery of the emission region, wherein the height of the outer dike may be greater than the height of the inner dike but less than the height of the first planarization layer.

[0033] In some example embodiments, the substrate further includes a non-display region, the first data conductive layer may further include a pad base layer in the non-display region, and there may be a pad electrode on the pad base layer.

[0034] In some example embodiments, the pad electrode may be at the same layer as the first electrode.

[0035] In some example embodiments, the width of the pad base layer measured in one direction may be substantially the same as the width of the pad electrode measured in the same direction.

[0036] In some example embodiments, the display device may further include: a semiconductor layer, in the non-emission region of the substrate and including a first active material layer of a driving transistor; a first gate insulating layer, on the semiconductor layer; and a first gate electrode of the driving transistor, on the first gate insulating layer, wherein the source / drain electrodes of the driving transistor may contact the first active material layer through contact holes penetrating the first interlayer insulating layer and the first gate insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] By describing the example embodiments of the present disclosure in detail with reference to the drawings, the above and other aspects and features of the present disclosure will become more apparent, in the drawings:

[0038] Figure 1 is a plan view of a display device according to some embodiments of the present disclosure;

[0039] Figure 2 is a schematic plan view showing the arrangement of wirings included in a display device according to some embodiments of the present disclosure;

[0040] Figure 3 is an equivalent circuit diagram of a pixel included in a display device according to some embodiments of the present disclosure;

[0041] Figure 4 is a layout diagram of a pixel of a display device according to some embodiments of the present disclosure;

[0042] Figure 5 is according to some embodiments of the present disclosure Figure 4 is a layout diagram of a sub-pixel of;

[0043] Figure 6 is according to some embodiments of the present disclosure along Figure 5A cross-sectional view taken along line I-I' and a part of the non-display area;

[0044] Figure 7 It is according to some embodiments of the present disclosure Figure 6 A schematic enlarged view of part QL1;

[0045] Figure 8 A partial cross-sectional view of a display device according to some embodiments of the present disclosure;

[0046] Figure 9 A schematic diagram of a light-emitting element according to some embodiments of the present disclosure;

[0047] Figures 10 to 18 A cross-sectional view showing nine parts of a process for manufacturing a display device according to some embodiments of the present disclosure;

[0048] Figure 19 A layout diagram of sub-pixels of a display device according to some embodiments of the present disclosure;

[0049] Figure 20 It is according to some embodiments of the present disclosure along Figure 19 A cross-sectional view taken along line II-II' and a part of the non-display area;

[0050] Figure 21 A layout diagram of sub-pixels of a display device according to some embodiments of the present disclosure;

[0051] Figure 22 It is according to some embodiments of the present disclosure along Figure 21 A cross-sectional view taken along line III-III' and a part of the non-display area;

[0052] Figure 23 A cross-sectional view of sub-pixels of a display device according to some embodiments of the present disclosure; and

[0053] Figure 24 It is according to some embodiments of the present disclosure Figure 23 A schematic enlarged view of part QL2. Detailed Description

[0054] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0055] It will also be understood that when a layer is referred to as being “on” another layer or a substrate, the layer can be directly on the other layer or substrate, or there can also be an intermediate layer. Throughout the specification, like reference numerals indicate like components.

[0056] It will be understood that although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0057] For ease of description, spatial relative terms such as “beneath”, “below”, “lower”, “underneath”, “above” and “on” may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. It will be understood that such spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, the element described as “beneath” or “below” or “underneath” other elements or features will then be oriented “above” the other elements or features. Thus, the example terms “beneath” and “below” can include both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as being “between” two layers, the layer can be the only layer between the two layers, or there can also be one or more intermediate layers.

[0058] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the inventive concept. As used herein, the terms “substantially”, “about” and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0059] As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms. It will also be understood that when the terms "comprises" and / or its variants are used in this specification, it is specified that there are the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. When an expression such as "at least one of..." is after a list of elements, it modifies the entire list of elements, rather than individual elements in the list. In addition, when describing embodiments of the inventive concept, the use of "may" refers to "one or more embodiments of the present invention". Additionally, the term "exemplary" is intended to indicate an example or illustration. As used herein, the terms "use" and its variants may be considered to be synonymous with the terms "utilize" and its variants, respectively.

[0060] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "adjacent to" another element or layer, the element or layer may be directly on, directly connected to, directly coupled to or adjacent to the other element or layer, or there may be one or more intervening elements or layers. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", "directly coupled to" another element or layer or "directly adjacent to" another element or layer, there are no intervening elements or layers.

[0061] Any numerical range recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, the range "1.0 to 10.0" is intended to include all sub-ranges between the recited minimum value 1.0 and the recited maximum value 10.0 (and including the recited minimum value 1.0 and the recited maximum value 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as by way of example 2.4 to 7.6. Any maximum numerical limit recited herein is intended to include all lower numerical limits subsumed therein, and any minimum numerical limit recited in this specification is intended to include all higher numerical limits subsumed therein. In an exemplary embodiment, the expression "source / drain electrode" may refer to "source electrode and drain electrode" according to the actual situation, or may refer to "source electrode or drain electrode" according to the context description. The specific semantics of "source / drain electrode" will be apparent to those skilled in the art.

[0062] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0063] Figure 1is a schematic plan view of a display device 10 according to some embodiments of the present disclosure.

[0064] Referring to Figure 1 , the display device 10 displays moving images or still images. The display device 10 may refer to any electronic device including a display screen. Non-limiting examples of the display device 10 may include a television, a notebook computer, a monitor, a billboard, the Internet of Things (IoT), a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a gaming machine, a digital camera, and a portable video camera, all of which provide a display screen.

[0065] The display device 10 includes a display panel providing a display screen. Non-limiting examples of the display panel include a light-emitting diode (LED) display panel, an organic light-emitting display panel, a quantum dot light-emitting display panel, a plasma display panel, and a field emission display panel. The case where an LED display panel is applied as an example of the display panel will be described below, but the embodiments are not limited to this case, and other display panels may also be applied as long as the same technical spirit is applicable.

[0066] Various modifications can be made to the shape of the display device 10. For example, the display device 10 may have various shapes (such as a horizontally long rectangle, a vertically long rectangle, a square, a quadrilateral with rounded corners (vertices), other polygons, and a circle). The shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10. In Figure 1 , each of the display device 10 and the display area DPA is shaped like a horizontally long rectangle.

[0067] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an area where an image can be displayed, and the non-display area NDA may be an area where an image is not displayed. The display area DPA may also be referred to as an effective area, and the non-display area NDA may also be referred to as an ineffective area. The display area DPA generally may occupy the central part of the display device 10.

[0068] The display area DPA may include a plurality of pixels PX. The pixels PX may be arranged along a matrix direction (e.g., the pixels PX may be arranged in a matrix form). Each of the pixels PX may be rectangular or square in a plan view. However, the shape of each of the pixels PX is not limited to these examples and may also be in a rhombus shape with each side inclined with respect to a direction. The pixels PX may be alternately arranged in a stripe or pentile pattern. In some embodiments, each of the pixels PX may include one or more light-emitting elements 300 that emit light of a specific wavelength band to display a specific color (see Figure 4 ).

[0069] The non-display area NDA may be provided around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may be rectangular, and the non-display area NDA may be provided adjacent to the four sides of the display area DPA. The non-display area NDA may form a border of the display device 10.

[0070] Figure 2 is a schematic plan view showing the arrangement of wirings SCL, SSL, DTL, VDL, and RVL included in the display device 10 according to some embodiments of the present disclosure.

[0071] Referring to Figure 2 , the display device 10 may include a plurality of wirings. The wirings may include scan lines SCL, sense lines SSL, data lines DTL, reference voltage lines RVL, and first voltage wirings VDL. In some embodiments, although not shown in the drawings, the wirings may further include second voltage wirings VSL (see Figure 3 ).

[0072] The scan lines SCL and the sense lines SSL may extend along a first direction DR1. The scan lines SCL and the sense lines SSL may be connected to a scan driver SDR. The scan driver SDR may include a driving circuit. The scan driver SDR may be provided in the non-display area NDA on one side of the display area DPA in the first direction DR1 (e.g., on the left side of the display area DPA), but the embodiment is not limited to this case. The scan driver SDR may be connected to a signal connection wiring CWL, and at least one end of the signal connection wiring CWL may form a pad (also referred to as a "pad" or "bond pad") WPD_CW in the non-display area NDA and may thus be connected to an external device.

[0073] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 that intersects the first direction DR1. The first voltage wiring VDL may include a portion extending in the second direction DR2. In some embodiments, the first voltage wiring VDL may further include a portion extending in the first direction DR1. Thus, the first voltage wiring VDL may have a mesh structure, but the embodiments are not limited to this case. Although not shown in the drawings, the second voltage wiring VSL, like the first voltage wiring VDL, may include a portion extending in the second direction DR2 and a portion extending in the first direction DR1.

[0074] The wiring pads WPD may be provided at at least one end of each of the data line DTL, the reference voltage line RVL, and the first voltage wiring VDL. Each wiring pad WPD may be provided in the non-display area NDA. In some embodiments, the wiring pad WPD_DT (hereinafter referred to as the "data pad") of the data line DTL may be provided in the non-display area NDA located on the second side (i.e., the lower side) in the second direction DR2 of the display area DPA, and the wiring pad WPD_RV (hereinafter referred to as the "reference voltage pad") of the reference voltage line RVL and the wiring pad WPD_VDD (hereinafter referred to as the "first power supply pad") of the first voltage wiring VDL may be provided in the non-display area NDA located on the first side (i.e., the upper side) in the second direction DR2 of the display area DPA. In another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power supply pad WPD_VDD may all be provided in the same area, for example, in the non-display area NDA located on the upper side of the display area DPA. The external device may be mounted on the wiring pad WPD as described above. The external device may be mounted on the wiring pad WPD by an anisotropic conductive film or ultrasonic bonding, etc.

[0075] Each pixel PX of the display device 10 includes a pixel driving circuit. The wirings SCL, SSL, DTL, VDL, and RVL described above may transmit driving signals to each pixel driving circuit while passing through or around each pixel PX. The pixel driving circuit may include transistors and capacitors. Various modifications may be made to the number of transistors and capacitors included in each pixel driving circuit. The pixel driving circuit will be described below as having a 3T1C structure including three transistors and one capacitor. However, the pixel driving circuit may also have various modified pixel structures such as a 2T1C structure, a 7T1C structure, or a 6T1C structure.

[0076] Figure 3 is an equivalent circuit diagram of the pixel PX included in the display device 10 according to some embodiments of the present disclosure.

[0077] Refer toFigure 3 , except for the LED EL, each pixel PX of the display device 10 according to some embodiments includes three transistors DT, SCT, and SST and a storage capacitor Cst.

[0078] The LED EL emits light according to the current supplied through the driving transistor DT. The LED EL may include a light-emitting element 300 that generates light (see Figure 4 ) and a first electrode 210 (see Figure 4 ) and a second electrode 220 (see Figure 4 ) that are electrically connected to both ends of each of the light-emitting elements 300 (see Figure 4 ). This will be described in detail later.

[0079] The LED EL may have one end connected to the second source / drain electrode of the driving transistor DT and the other end connected to the second voltage wiring VSL, and a low-potential voltage (e.g., the second power supply voltage VSS) lower than the high-potential voltage (e.g., the first power supply voltage VDD) of the first voltage wiring VDL is supplied to the second voltage wiring VSL.

[0080] The driving transistor DT adjusts the current flowing from the first voltage wiring VDL supplied with the first power supply voltage VDD to the LED EL according to the voltage difference between the gate electrode and the source electrode of the driving transistor DT. The driving transistor DT may have a gate electrode connected to the second source / drain electrode of the scanning transistor SCT, a second source / drain electrode connected to the first electrode of the LED EL, and a first source / drain electrode connected to the first voltage wiring VDL to which the first power supply voltage VDD is applied.

[0081] The scanning transistor SCT is turned on by the scanning signal of the scanning line SCL to connect the data line DTL to the gate electrode of the driving transistor DT. The scanning transistor SCT may have a gate electrode connected to the scanning line SCL, a second source / drain electrode connected to the gate electrode of the driving transistor DT, and a first source / drain electrode connected to the data line DTL.

[0082] The sensing transistor SST is turned on by the sensing signal of the sensing line SSL to connect the reference voltage line RVL to the second source / drain electrode of the driving transistor DT. The sensing transistor SST may have a gate electrode connected to the sensing line SSL, a first source / drain electrode connected to the reference voltage line RVL, and a second source / drain electrode connected to the second source / drain electrode of the driving transistor DT.

[0083] In some embodiments, the first source / drain electrode of each of the transistors DT, SCT, and SST may be the source electrode, and the second source / drain electrode may be the drain electrode. However, the opposite may also be true.

[0084] A storage capacitor Cst is formed between the gate electrode of a driving transistor DT and a second source / drain electrode. The storage capacitor Cst stores a voltage difference between the gate voltage of the driving transistor DT and the second source / drain voltage.

[0085] Each of the transistors DT, SCT, and SST may be formed as a thin-film transistor. In some embodiments, although each of the transistors DT, SCT, and SST is described as an N-type metal-oxide semiconductor field-effect transistor (MOSFET) in Figure 3 , the embodiments are not limited to this case. For example, each of the transistors DT, SCT, and SST may also be formed as a P-type MOSFET. In some embodiments, some of the transistors DT, SCT, and SST may be formed as N-type MOSFETs, and others may be formed as P-type MOSFETs.

[0086] The structure of a pixel PX of a display device 10 according to an exemplary embodiment will now be described in further detail with reference to another drawing.

[0087] Figure 4 is a layout diagram of a pixel PX of a display device 10 according to some embodiments of the present disclosure.

[0088] Referring to Figure 4 , each of the pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The sub-pixel PXn may refer to the first sub-pixel PX1, the second sub-pixel PX2, or the third sub-pixel PX3. Each sub-pixel PXn may include one or more light-emitting elements 300 to display light of a specific wavelength band. The light-emitting elements 300 provided in each sub-pixel PXn may include a material different from that of the light-emitting elements 300 provided in other sub-pixels PXn to emit light of different wavelength bands. For example, the first sub-pixel PX1 may include a light-emitting element 300 that emits light of a first color, the second sub-pixel PX2 may include a light-emitting element 300 that emits light of a second color, and the third sub-pixel PX3 may include a light-emitting element 300 that emits light of a third color. Accordingly, light of the first color may be output from the first sub-pixel PX1, light of the second color may be output from the second sub-pixel PX2, and light of the third color may be output from the third sub-pixel PX3. In some embodiments, the light of the first color may be blue light whose central wavelength band is in the range of 450 nm to 495 nm, the light of the second color may be green light whose central wavelength band is in the range of 495 nm to 570 nm, and the light of the third color may be red light whose central wavelength band is in the range of 620 nm to 752 nm.

[0089] In some cases, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include the same type of light-emitting element 300 to emit light of substantially the same color. Although in Figure 4 one pixel PX includes three sub-pixels PXn, the embodiment is not limited to this case, and the pixel PX may also include more sub-pixels PXn.

[0090] In some embodiments, each pixel PX of the display device 10 may include an emission area EMA and a non-emission area NEA. The first sub-pixel PX1 may include a first emission area EMA1 and a first non-emission area NEA1, the second sub-pixel PX2 may include a second emission area EMA2 and a second non-emission area NEA2, and the third sub-pixel PX3 may include a third emission area EMA3 and a third non-emission area NEA3. The emission area EMA may be defined as an area where the light emitted from the light-emitting element 300 provided in each pixel PX is output. As described above, the light-emitting element 300 may emit light of a specific wavelength band in any direction. The light emitted from each light-emitting element 300 may not only radiate toward both ends of the light-emitting element 300, but also radiate in the lateral direction of the light-emitting element 300. Therefore, the emission area EMA of each sub-pixel PXn may include an area where the light-emitting element 300 is provided and an area adjacent to the light-emitting element 300 where the light emitted from the light-emitting element 300 is output thereto. However, the embodiment is not limited to this case, and the emission area EMA may also include an area where the light emitted from the light-emitting element 300 is output after being reflected or refracted by other components.

[0091] Each pixel PX or sub-pixel PXn may include a pixel driving circuit, and the pixel driving circuit may be disposed in a non-emission area NEA of each pixel PX or sub-pixel PXn. For example, the non-emission area NEA may be an area in which circuit elements or a plurality of wirings constituting the pixel driving circuit of each pixel PX or sub-pixel PXn are disposed. In some embodiments, since the light emitted from the light-emitting element 300 does not reach (or arrive at) the non-emission area NEA, the non-emission area NEA may be an area other than the emission area EMA and an area from which no light is emitted. In the display device 10 according to some embodiments, the light-emitting element 300 that emits light and the circuit elements for driving the light-emitting element 300 may be disposed in different areas (e.g., in the emission area EMA and the non-emission area NEA), and may not overlap each other in the thickness direction. Therefore, the display device 10 may output light through the upper surface or the rear surface of the area in which the light-emitting element 300 is disposed. In addition, as will be described later, the electrodes 210 and 220 and the electrode base layers 230 and 240 electrically connected to the light-emitting element 300 may be formed in the same process as the circuit elements or wirings of the non-emission area NEA. Therefore, the number of manufacturing processes of the display device 10 can be reduced.

[0092] The arrangement of elements included in each pixel PX or sub-pixel PXn will now be further described with reference to other drawings.

[0093] Figure 5 is according to some embodiments of the present disclosure Figure 4 layout diagram of the sub-pixel PXn. Figure 6 is according to some embodiments of the present disclosure along Figure 5 cross-sectional view taken along line I-I' and a part of the non-display area NDA.

[0094] For ease of description, the outer bank 450 (see Figure 5 ) and the first planarization layer 480 (see Figure 4 ) provided in each sub-pixel PXn are not shown in Figure 4 . Figure 6 The part taken along line I-I' of Figure 5 is a partial cross-section of the non-emission area NEA and the emission area EMA of each sub-pixel PXn, and a cross-section across two opposite ends of the light-emitting element 300 is shown in Figure 6 . In some embodiments, Figure 6 shows a pad area PDA in which a plurality of wiring pads WPD are provided in the non-display area NDA.

[0095] Except for Figure 4 , referring to Figure 5 and Figure 6, each pixel PX or sub - pixel PXn of the display device 10 may include a first substrate 101, and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate 101. The conductive layers may include a first gate conductive layer, a first data conductive layer, an electrode, and a contact electrode, and the insulating layers may include a buffer layer 102, a first gate insulating layer 103, a first protective layer 105, a first interlayer insulating layer 107, a first planarization layer 480, a first insulating layer 510, a second insulating layer 520, a third insulating layer 530, and a fourth insulating layer 550. The conductive layers and the semiconductor layer may constitute the transistors DT, SCT, and SST, the storage capacitor Cst, and multiple signal lines or voltage lines of each pixel PX described above with reference to Figure 3 The circuit elements described above. Figure 6 FIG. shows a cross - section of only the driving transistor DT among the circuit elements disposed in the non - emission region NEA. Since those of ordinary skill in the art will be able to describe such elements through the details provided in other parts of the present disclosure, the description of the other transistors (e.g., the scanning transistor SCT and the sensing transistor SST) of each sub - pixel PXn will not be provided in detail.

[0096] First, the first substrate 101 may be an insulating substrate. The first substrate 101 may be made of an insulating material such as glass, quartz, or a polymer resin. In some embodiments, the first substrate 101 may be a rigid substrate, but may also be a flexible substrate that can be bent, folded, and / or curled. The emission region EMA and the non - emission region NEA may be defined in the first substrate 101. The light - emitting element 300 may be disposed in the emission region EMA of the first substrate 101, and the driving transistor DT, etc., may be disposed as circuit elements in the non - emission region NEA.

[0097] The first light - blocking layer BML1 may be disposed on the first substrate 101. The first light - blocking layer BML1 may be disposed in the non - emission region NEA of the first substrate 101 and may be overlapped by a part of the first active material layer ACT1 of the driving transistor DT to be described later. The first light - blocking layer BML1 may include a light - blocking material to prevent light from entering the first active material layer ACT1 (or reduce the amount of light entering the first active material layer ACT1). For example, the first light - blocking layer BML1 may be made of an opaque metal material that blocks the transmission of light. In some cases, the first light - blocking layer BML1 may be omitted.

[0098] The buffer layer 102 is disposed on the first substrate 101 having the first light-blocking layer BML1. The buffer layer 102 may be entirely disposed in the non-emission area NEA, the emission area EMA, and the non-display area NDA of the first substrate 101. The buffer layer 102 may be formed on the first substrate 101 to protect the transistors DT, SCT, and SST of each sub-pixel PXn from moisture introduced through the first substrate 101 that may be vulnerable to moisture penetration and may also perform a surface flattening function. The buffer layer 102 may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer 102 may be formed as a multi-layer in which one or more inorganic layers selected from a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, and a silicon oxynitride (SiON) layer are stacked alternately.

[0099] The semiconductor layer is disposed on the buffer layer 102. The semiconductor layer may be disposed in the non-emission area NEA of each pixel PX or sub-pixel PXn and may include the active material layers of each transistor DT, SCT, or SST. The semiconductor layer may include a first active material layer ACT1 for driving the transistor DT, a second active material layer ACT2 for the scan transistor SCT, and a third active material layer ACT3 for the sense transistor SST.

[0100] The semiconductor layer may be partially overlapped by the gate electrodes GE1 to GE3 of the first gate conductive layer to be described later. In the drawings, the second active material layer ACT2 may be disposed on the first side (i.e., the upper side) in the second direction DR2 at the center of the non-emission area NEA of each sub-pixel PXn, and the first active material layer ACT1 and the third active material layer ACT3 may be disposed on the second side (i.e., the lower side) in the second direction DR2 at the center of the non-emission area NEA. As shown in the drawings, the first active material layer ACT1 of the driving transistor DT and the third active material layer ACT3 of the sense transistor SST may be integrated into one semiconductor layer. A part of the semiconductor layer may be the first active material layer ACT1, and another part of the semiconductor layer may be the third active material layer ACT3.

[0101] In some example embodiments, the semiconductor layer may include polysilicon, single-crystalline silicon, or an oxide semiconductor, etc. When the semiconductor layer includes polysilicon, the first active material layer ACT1 may include a first doped region ACT1a, a second doped region ACT1b, and a first channel region ACT1c. The first doped region ACT1a and the second doped region ACT1b may be regions doped with impurities. The first channel region ACT1c may be disposed between the first doped region ACT1a and the second doped region ACT1b. The polysilicon may be formed by crystallizing amorphous silicon. Non-limiting examples of the crystallization method include rapid thermal annealing (RTA), solid-phase crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), and sequential lateral solidification (SLS). In some embodiments, the first active material layer ACT1 may include single-crystalline silicon, low-temperature polysilicon, or amorphous silicon, etc.

[0102] The first active material layer ACT1 is not limited to the above examples. In some example embodiments, the first active material layer ACT1 may include an oxide semiconductor. In some embodiments, the doped region may be a conductive region. When the first active material layer ACT1 includes an oxide semiconductor, the oxide semiconductor may be an oxide semiconductor containing indium (In). In some embodiments, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO).

[0103] The first gate insulating layer 103 is disposed on the semiconductor layer and the buffer layer 102. The first gate insulating layer 103 may be disposed on the buffer layer 102 having a semiconductor layer (e.g., the first active material layer ACT1 to the third active material layer ACT3). For example, the first gate insulating layer 103 may be entirely disposed in the non-emission region NEA, the emission region EMA, and the non-display region NDA. The first gate insulating layer 103 may be used as a gate insulating film for each transistor DT, SCT, or SST. The first gate insulating layer 103 may be made of an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ) or a stack thereof.

[0104] The first gate conductive layer is disposed on the first gate insulating layer 103. The first gate conductive layer may include corresponding gate electrodes GE1, GE2, and GE3 of transistors DT, SCT, and SST disposed in the non-emission region NEA, a scan line SCL, a sense line SSL, a second voltage wiring VSL, a reference voltage distribution line RVT, and a first capacitive electrode CSE1 of a storage capacitor Cst.

[0105] First, the respective gate electrodes GE1, GE2, and GE3 of the transistors DT, SCT, and SST can be stacked with the first active material layer ACT1, the second active material layer ACT2, and the third active material layer ACT3, respectively. The first gate electrode GE1 can be stacked with at least a part of the first active material layer ACT1, the second gate electrode GE2 can be stacked with at least a part of the second active material layer ACT2, and the third gate electrode GE3 can be stacked with at least a part of the third active material layer ACT3. The first gate electrode GE1 can be electrically connected to the first capacitive electrode CSE1 of a storage capacitor Cst to be described later. The second gate electrode GE2 can be electrically connected to a scan line SCL to be described later, and the third gate electrode GE3 can be electrically connected to a sense line SSL to be described later.

[0106] The scan line SCL can extend in a first direction DR1 beyond the boundary of an adjacent sub-pixel PXn. For example, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the first direction DR1 can share a scan line SCL. The scan line SCL can be disposed on a first side (i.e., the upper side) in a second direction DR2 at the center of a non-emission area NEA of each sub-pixel PXn. The scan line SCL can be electrically connected to the second gate electrode GE2 of the scan transistor SCT through a part of a first data conductive layer to be described later and can transmit a scan signal to the scan transistor SCT.

[0107] The sense line SSL can also extend in the first direction DR1 beyond the boundary of an adjacent sub-pixel PXn. For example, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the first direction DR1 can share a sense line SSL. The sense line SSL can be disposed on a second side (i.e., the lower side) in the second direction DR2 at the center of the non-emission area NEA of each sub-pixel PXn. The sense line SSL can be electrically connected to the third gate electrode GE3 of the sense transistor SST through a part of the first data conductive layer to be described later and can transmit a sense signal to the sense transistor SST.

[0108] A reference voltage distribution line RVT can be disposed on a second side of the sense line SSL in the second direction DR2 and can extend in the first direction DR1. The reference voltage distribution line RVT can extend from a first sub-pixel PX1 to a third sub-pixel PX3, and each pixel PX (e.g., three sub-pixels PXn) can share a reference voltage distribution line RVT. The reference voltage distribution line RVT can be electrically connected to a reference voltage line RVL to be described later and a first source / drain electrode of the sense transistor SST of each sub-pixel PXn. Therefore, the reference voltage distribution line RVT can transmit a reference voltage received from the reference voltage line RVL to the sense transistor SST.

[0109] The second voltage wiring VSL may be disposed on one side of the emission area EMA and may extend in the first direction DR1. For example, the second voltage wiring VSL may be disposed on the second side (i.e., the lower side) of the emission area EMA in the second direction DR2 and may be positioned opposite to the non-emission area NEA with respect to the center of each sub-pixel PXn. However, since a plurality of pixels PX or sub-pixels PXn may be arranged along the first direction DR1 and the second direction DR2, the second voltage wiring VSL may be positioned at the boundary between sub-pixels PXn adjacent to each other in the second direction DR2. In some embodiments, the second voltage wiring VSL may further include a portion disposed in the non-display area NDA of the display device 10 and extending in the second direction DR2. The portion of the second voltage wiring VSL extending in the second direction DR2 may be connected to the wiring pad WPD described above and thus receive the second supply voltage VSS. The second voltage wiring VSL may be electrically connected to the second electrode 220 described later and apply the second supply voltage VSS to the light-emitting element 300. In Figure 5 this case, the second voltage wiring VSL and the second electrode 220 are connected in each sub-pixel PXn. However, the embodiments are not limited to this case. In some cases, the second electrodes 220 of a plurality of sub-pixels PXn may be connected to form a single electrode and then electrically connected to the second voltage wiring VSL positioned in the non-display area NDA.

[0110] The first capacitive electrode CSE1 of the storage capacitor Cst is disposed between the scan line SCL and the sense line SSL. The first capacitive electrode CSE1 of the storage capacitor Cst may be electrically connected to the first gate electrode GE1 of the driving transistor DT and the second source / drain electrode SDE4 of the scan transistor SCT.

[0111] The second source / drain electrode SDE4 of the scan transistor SCT may contact one side of the second active material layer ACT2 through a third contact hole CT3 in a region overlapping with one side of the second active material layer ACT2. The second source / drain electrode SDE4 may be connected to the first capacitive electrode CSE1 of the storage capacitor Cst.

[0112] The first gate conductive layer may be, but is not limited to, a single layer or a multi-layer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0113] The first protective layer 105 is disposed on the first gate conductive layer. The first protective layer 105 may be entirely disposed in the non-emission area NEA, the emission area EMA, and the non-display area NDA to cover the active material layers ACT1, ACT2, and ACT3 of the transistors DT, SCT, and SST and the plurality of signal lines. The first protective layer 105 may be made of an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or a stack thereof.

[0114] The first interlayer insulating layer 107 is disposed on the first protective layer 105. The first interlayer insulating layer 107 may compensate for the step formed by the conductive layer disposed below the first interlayer insulating layer 107 and at the same time serve as an insulating film between the first gate conductive layer and other layers disposed on the first gate conductive layer. The first interlayer insulating layer 107 may be made of an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or a stack thereof.

[0115] Although only one first interlayer insulating layer 107 is disposed between the first gate conductive layer and the first data conductive layer in the drawings, the embodiments are not limited to this case. According to some embodiments, another conductive layer may be further disposed between the first gate conductive layer and the first data conductive layer, and more interlayer insulating layers may be disposed to insulate the conductive layers. This will be described with reference to some exemplary embodiments.

[0116] The first data conductive layer is disposed on the first interlayer insulating layer 107. The first data conductive layer may include data lines DTL disposed in the non-emission area NEA, a first voltage wiring VDL, a reference voltage line RVL, corresponding first source / drain electrodes SDE1, SDE3, and SDE5 of the transistors DT, SCT, and SST, second source / drain electrodes SDE2 and SDE4, a plurality of conductive patterns DP1 and DP2, and a second capacitance electrode CSE2 of the storage capacitor Cst. In some embodiments, the first data conductive layer may include electrode substrate layers 230 and 240 disposed in the emission area EMA and a pad substrate layer 710 disposed in the pad area PDA.

[0117] As described above, in the display device 10 according to some embodiments, the emission area EMA and the non-emission area NEA of each pixel PX or sub-pixel PXn may be separated, and the components provided in the emission area EMA and the components provided in the non-emission area NEA may not overlap in the thickness direction. Accordingly, the conductive layers or insulating layers provided in the emission area EMA, the non-emission area NEA, and also the non-display area NDA may be concurrently (e.g., simultaneously) formed in the same process, and the number of manufacturing processes of the display device 10 may be reduced. According to some embodiments, in the display device 10, the electrode base layers 230 and 240 of the emission area EMA, the source / drain electrodes SDE1 to SDE5 of the transistors DT, SCT, and SST provided in the non-emission area NEA, and the pad base layer 710 provided in the non-display area NDA may be provided at the same layer.

[0118] In some embodiments, the data line DTL may extend in the second direction DR2 beyond the boundary of an adjacent sub-pixel PXn. For example, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the second direction DR2 may share one data line DTL. The data line DTL may be provided on a first side (e.g., the right side) in the first direction DR1 of the center of the non-emission area NEA of each sub-pixel PXn. The data line DTL may contact one side of the second active material layer ACT2 of the scan transistor SCT through the fourth contact hole CT4. For example, a part of the data line DTL may be the first source / drain electrode SDE3 of the scan transistor SCT. Accordingly, the data signal transmitted to the data line DTL may be transmitted to the scan transistor SCT.

[0119] The first voltage wiring VDL may also extend in the second direction DR2 beyond the boundary of an adjacent sub-pixel PXn. For example, a plurality of pixels PX or sub-pixels PXn adjacent to each other in the second direction DR2 may share one first voltage wiring VDL. The first voltage wiring VDL may be provided on a second side (i.e., the left side) in the first direction DR1 of the center of the non-emission area NEA of each sub-pixel PXn. The first voltage wiring VDL may contact one side of the first active material layer ACT1 of the driving transistor DT through the first contact hole CT1. For example, a part of the first voltage wiring VDL may be the first source / drain electrode SDE1 of the driving transistor DT. Accordingly, the first supply voltage VDD applied to the first voltage wiring VDL may be transmitted to the driving transistor DT.

[0120] The first voltage wiring VDL and the data line DTL can be provided in each sub-pixel PXn. As shown in the drawings, the first voltage wiring VDL and the data line DTL can be respectively provided on the left and right sides of the center of each sub-pixel PXn, and can extend in the second direction DR2 in the non-emission area NEA and the emission area EMA. The first voltage wiring VDL and the data line DTL provided in the emission area EMA can be provided under the outer dike 450 which will be described later.

[0121] A reference voltage line RVL can be provided in each pixel PX (for example, every three sub-pixels PXn). For example, the reference voltage line RVL can be provided on the first side (i.e., the left side) of the data line DTL of each sub-pixel PXn in the first direction DR1, and can extend in the second direction DR2. A plurality of pixels PX adjacent to each other in the second direction DR2 can share a reference voltage line RVL. The reference voltage line RVL can be electrically connected to the reference voltage distribution line RVT described above, and the reference voltage applied through the reference voltage line RVL can be transmitted to the sensing transistor SST of each sub-pixel PXn through the reference voltage distribution line RVT.

[0122] The second capacitance electrode CSE2 of the storage capacitor Cst is provided between the first voltage wiring VDL and the data line DTL. The second capacitance electrode CSE2 of the storage capacitor Cst can be stacked with the first capacitance electrode CSE1, and the storage capacitor Cst can be formed between the first capacitance electrode CSE1 and the second capacitance electrode CSE2. The second capacitance electrode CSE2 of the storage capacitor Cst can be connected to the second source / drain electrode SDE2 of the driving transistor DT. The second source / drain electrode SDE2 of the driving transistor DT can contact a part of the first active material layer ACT1 through the second contact hole CT2. In some embodiments, the second source / drain electrode SDE2 of the driving transistor DT can contact one side of the third active material layer ACT3 of the sensing transistor SST to form the second source / drain electrode of the sensing transistor SST.

[0123] The first source / drain electrode SDE5 of the sensing transistor SST can contact one side of the third active material layer ACT3 and the reference voltage distribution line RVT. The first source / drain electrode SDE5 of the sensing transistor SST can receive the reference voltage from the reference voltage distribution line RVT.

[0124] The first conductive pattern DP1 and the second conductive pattern DP2 of the first data conductive layer may be connected to a portion of the first gate conductive layer. The first conductive pattern DP1 may be connected to the scan line SCL and the second gate electrode GE2 of the scan transistor SCT and transmit the scan signal received from the scan line SCL to the second gate electrode GE2 of the scan transistor SCT. The second conductive pattern DP2 may be connected to the sense line SSL and the third gate electrode GE3 of the sense transistor SST and transmit the sense signal received from the sense line SSL to the third gate electrode GE3 of the sense transistor SST.

[0125] The display device 10 according to an exemplary embodiment may include a plurality of substrate layers. The substrate layers may include electrode substrate layers 230 and 240 disposed in the emission area EMA and a pad substrate layer 710 disposed in the non-display area NDA. The substrate layers may be included in the first data conductive layer. For example, the electrode substrate layers 230 and 240 and the pad substrate layer 710 according to some embodiments may be disposed on the first interlayer insulating layer 107 at the same layer as the source / drain electrodes SDE1 and SDE2 of the driving transistor DT.

[0126] In some embodiments, the electrode substrate layers 230 and 240 are disposed on the first interlayer insulating layer 107 in the emission area EMA. The electrode substrate layers 230 and 240 may include a first electrode substrate layer 230 and a second electrode substrate layer 240. The first electrode substrate layer 230 and the second electrode substrate layer 240 may extend in one direction in the emission area EMA and may be spaced apart to face each other. For example, the first electrode substrate layer 230 and the second electrode substrate layer 240 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1 with respect to the center of the emission area EMA. The first electrode substrate layer 230 and the second electrode substrate layer 240 may be spaced apart from each other, and the inner dams 410 and 420 and the electrodes 210 and 220 may be disposed on the first electrode substrate layer 230 and the second electrode substrate layer 240, respectively, thereby providing a space in which the light-emitting element 300 is disposed.

[0127] In some embodiments, the first electrode substrate layer 230 and the second electrode substrate layer 240 may extend in the second direction DR2, but may end at a position spaced apart from at least the boundary of each sub-pixel PXn so as not to be disposed in another adjacent sub-pixel PXn in the second direction DR2. Accordingly, the first electrode substrate layer 230 and the second electrode substrate layer 240 may be disposed in each sub-pixel PXn to form a linear pattern on the entire surface of the display device 10.

[0128] However, the first electrode base layer 230 and the second electrode base layer 240 may extend different lengths along the second direction DR2. The first electrode base layer 230 may extend from the emission area EMA along the second direction DR2 such that at least a portion of the first electrode base layer 230 is disposed in the non-emission area NEA. The second electrode base layer 240 may be spaced apart from the non-emission area NEA, and at least a portion of the second electrode base layer 240 may be disposed under the outer bank 450. Although one first electrode base layer 230 and one second electrode base layer 240 are shown in the drawings disposed in each sub-pixel PXn, the embodiments are not limited to this case. In some embodiments, more than one first electrode base layer 230 and more than one second electrode base layer 240 may be provided, and some of them may be connected to each other.

[0129] The first electrode base layer 230 and the second electrode base layer 240 may be disposed at the same layer as circuit elements or wirings disposed in each sub-pixel PXn and may be electrically connected to the circuit elements or wirings. As described above, the electrode base layers 230 and 240 may be directly disposed on the first interlayer insulating layer 107 and may be included in the first data conductive layer. The light-emitting element 300 that emits light and the circuit elements (e.g., the driving transistor DT for driving the light-emitting element 300) may be disposed such that they do not overlap each other in the thickness direction, and the layers disposed in the emission area EMA and the non-emission area NEA of the display device 10 may be formed in the same process. Thus, the number of manufacturing processes may be reduced. In some embodiments, since the light-emitting element 300 does not overlap the circuit elements in the thickness direction, the light emitted from the light-emitting element 300 may be output above or below the first substrate 101.

[0130] The first electrode base layer 230 and the second electrode base layer 240 may be electrically connected to the first electrode 210 and the second electrode 220, respectively, and the first electrode 210 and the second electrode 220 may receive electrical signals through the electrode base layers 230 and 240, respectively.

[0131] According to some embodiments, the first electrode base layer 230 may be directly connected to the source / drain electrode of the driving transistor DT. For example, the first electrode base layer 230 may extend along the second direction DR2 and may be connected to the second source / drain electrode SDE2 of the driving transistor DT. For example, the first electrode base layer 230 may form a pattern substantially integral with the second source / drain electrode SDE2 of the driving transistor DT. While the display device 10 is being driven, the electrical signal transmitted from the driving transistor DT may be transmitted to the first electrode 210, which will be described later, through the first electrode base layer 230.

[0132] The second electrode base layer 240 may be electrically connected to a second voltage wiring VSL, which is disposed in a region overlapping with an outer bank 450 to be described later and is disposed under the outer bank 450. For example, the second electrode base layer 240 may be connected to the second voltage wiring VSL through a fifth contact hole CT5 that penetrates the first interlayer insulating layer 107 in a region overlapping with the outer bank 450. While the display device 10 is being driven, a second supply voltage VSS applied to the second voltage wiring VSL may be applied to the second electrode 220 through the second electrode base layer 240.

[0133] However, the embodiments are not limited to this example. The first electrode base layer 230 and the second electrode base layer 240 do not have to be connected to the driving transistor DT or the second voltage wiring VSL as shown in Figure 5 and Figure 6 . In some embodiments, the electrode base layers 230 and 240 may be electrically connected to circuit elements or wirings through bridge patterns, and in some cases, the first electrode 210 and the second electrode 220 may be directly electrically connected to circuit elements or wirings.

[0134] A plurality of wiring pads WPD may be disposed in a pad region PDA of a non-display region NDA, and each of the wiring pads WPD may include a pad base layer 710 included in a first data conductive layer. The pad base layer 710 may be directly disposed on the first interlayer insulating layer 107 in the pad region PDA. In the display device 10, since the electrode base layers 230 and 240 of the emission region EMA, the source / drain electrodes and voltage wirings of the non-emission region NEA, and the pad base layer 710 of the pad region PDA are formed in the same process, the number of manufacturing processes can be reduced. The electrode base layers 230 and 240 and the pad base layer 710 included in the first data conductive layer may be formed by placing a conductive layer on the entire surface of the first interlayer insulating layer 107 and then concurrently (e.g., simultaneously) patterning the conductive layer together with the members disposed on the conductive layer. In some exemplary embodiments, a part of the first data conductive layer may be formed with substantially the same pattern as the elements disposed on that part. This will be described later.

[0135] A via layer is disposed on the first data conductive layer. The via layer may include a first planarization layer 480 disposed in the non-emission region NEA and inner banks 410 and 420 and an outer bank 450 disposed in the emission region EMA. In the display device 10 according to the exemplary embodiments, since the elements of the via layer disposed on the first data conductive layer are formed together in the same process, the number of manufacturing processes can be reduced. However, the elements of the via layer may be formed to have different heights as shown in the drawings.

[0136] In some embodiments, the first planarization layer 480 may cover the entire non-emission area NEA of the first data conductive layer including the non-emission area NEA. The first planarization layer 480 may protect the first data conductive layer while planarizing the steps formed by the circuit elements disposed in the non-emission area NEA.

[0137] The outer bank 450 may be disposed in a part of the emission area EMA and may be formed in the same process as the first planarization layer 480 of the non-emission area NEA. However, as Figure 4 shown, the first planarization layer 480 may cover the entire non-emission area NEA, but the outer bank 450 may expose a part of the emission area EMA.

[0138] For example, the outer bank 450 (e.g., see Figure 4 ) may be disposed at the boundary between the sub-pixels PXn. The outer bank 450 may extend along the first direction DR1 and the second direction DR2, and surround the electrode substrate layers 230 and 240, the inner banks 410 and 420, and also the electrodes 210 and 220, and the area where the light-emitting element 300 is disposed between the electrode substrate layers 230 and 240 and between the inner banks 410 and 420. For example, the outer bank 450 may form a grid pattern on the entire surface of the display area DPA.

[0139] The portion of the outer bank 450 extending along the first direction DR1 may be disposed on the second voltage wiring VSL, and the portion of the outer bank 450 extending along the second direction DR2 may be disposed on the first voltage wiring VDL and the data line DTL of the first data conductive layer. In some embodiments, the outer bank 450 may be directly disposed on the first data conductive layer, and a part of the outer bank 450 may be directly disposed on the data line DTL or the first voltage wiring VDL.

[0140] During the manufacturing process of the display device 10, the first data conductive layer disposed in the emission area EMA may be patterned in the same process as the electrodes 210 and 220. Here, the first data conductive layer on which the electrodes 210 and 220 are not disposed may be patterned along the shape of the via layer (e.g., the outer bank 450 disposed on the first data conductive layer). As Figure 6 shown, the data line DTL disposed under the outer bank 450 may be patterned along the shape of the outer bank 450, and the side surface of the data line DTL may be in the same plane as the side surface of the outer bank 450. For example, according to some embodiments, at least one side surface of the data line DTL may not contact the outer bank 450. Therefore, the side surface of the data line DTL may be exposed and may directly contact the first insulating layer 510 to be described later.

[0141] In some embodiments, the outer bank 450 may be formed to be higher than the inner banks 410 and 420 to separate adjacent sub-pixels PXn. In some embodiments, during the manufacturing process of the display device 10, as will be described later, the outer bank 450 may prevent ink from overflowing into adjacent sub-pixels PXn (or reduce the chance of ink overflowing into adjacent sub-pixels PXn) in the inkjet process for placing the light-emitting elements 300.

[0142] The inner banks 410 and 420 are respectively disposed on the electrode substrate layers 230 and 240 provided in the emission area EMA. For example, the inner banks 410 and 420 may include a first inner bank 410 and a second inner bank 420. The first inner bank 410 may be directly disposed on the first electrode substrate layer 230, and the second inner bank 420 may be directly disposed on the second electrode substrate layer 240. The first inner bank 410 and the second inner bank 420 may extend along the second direction DR2 in the emission area EMA of each sub-pixel PXn, and may be spaced apart in the first direction DR1 to face each other. The inner banks 410 and 420 may be spaced apart from the boundaries of each sub-pixel PXn so as not to extend into adjacent sub-pixels PXn, and may be patterned on the entire surface of the display device 10. In some embodiments, the inner banks 410 and 420 may be spaced apart from each other, and an area in which the light-emitting elements 300 are disposed may be formed between the inner banks 410 and 420.

[0143] The inner banks 410 and 420 may be formed to have dimensions smaller than those of the electrode substrate layers 230 and 240. In some embodiments, the width of the inner banks 410 and 420 measured in one direction (e.g., in the first direction DR1) may be smaller than the width of the electrode substrate layers 230 and 240 measured in that direction. As Figure 6 shown, the two side surfaces of the inner banks 410 and 420 may be recessed from the two side surfaces of the electrode substrate layers 230 and 240 to partially expose the upper surfaces of the electrode substrate layers 230 and 240. The electrodes 210 and 220 are respectively disposed on the exposed upper surfaces of the electrode substrate layers 230 and 240. In some embodiments, the length of the inner banks 410 and 420 extending along the second direction DR2 may be smaller than the length of the electrode substrate layers 230 and 240 extending along the second direction DR2. For example, the inner banks 410 and 420 may be disposed only on the electrode substrate layers 230 and 240.

[0144] Although one first inner bank 410 and one second inner bank 420 are shown in the drawings, the embodiments are not limited to this case. In some cases, more inner banks 410 and 420 may be provided according to the number of the electrodes 210 and 220 to be described later.

[0145] In some embodiments, at least a portion of each of the first inner dam 410 and the second inner dam 420 may protrude from the upper surface of the electrode substrate layer 230 or 240. The protruding portions of the first inner dam 410 and the second inner dam 420 may have inclined side surfaces, and light emitted from the light-emitting element 300 disposed between the first inner dam 410 and the second inner dam 420 may be emitted to the inclined side surfaces of the inner dams 410 and 420. As will be described later, the electrodes 210 and 220 disposed on the inner dams 410 and 420 may include a material having a high reflectivity, and the light emitted from the light-emitting element 300 may be reflected by the side surfaces of the inner dams 410 and 420 to travel in an upward direction with respect to the first substrate 101. For example, the inner dams 410 and 420 may provide an area in which the light-emitting element 300 is disposed, and at the same time, serve as a reflection stopper for reflecting the light emitted from the light-emitting element 300 in the upward direction.

[0146] As described above, in the display device 10 according to the exemplary embodiment, the first planarization layer 480, the inner dams 410 and 420, and the outer dam 450 in the via layer may have different heights. The first planarization layer 480, the inner dams 410 and 420, and the outer dam 450 may be concurrently (e.g., simultaneously) formed in the same process during the manufacturing process of the display device 10, but may be formed to have different heights according to their positions and functions. This will be described in detail later with reference to other drawings.

[0147] A plurality of electrodes 210 and 220 may be disposed on the first data conductive layer of the emission area EMA. In some embodiments, the pad electrode 720 may be disposed on the first data conductive layer (e.g., the pad substrate layer 710 of the non-display area NDA or the pad area PDA). The display device 10 according to the exemplary embodiment may include a first electrode 210 disposed on the first electrode substrate layer 230 and a second electrode 220 disposed on the second electrode substrate layer 240, and may further include a pad electrode 720 disposed on the pad substrate layer 710.

[0148] The first electrode 210 is disposed on the first electrode substrate layer 230. As Figure 5 shown, the first electrode 210 may extend in the second direction DR2 in the emission area EMA of each sub-pixel PXn. The first electrode 210 may not extend to another adjacent sub-pixel PXn in the second direction DR2, and may be spaced apart from the outer dam 450 surrounding the emission area EMA of each sub-pixel PXn. The first electrode 210 may partially contact the first planarization layer 480 of the non-emission area NEA, but the embodiment is not limited to this example.

[0149] The first electrode 210 may be formed to have a pattern substantially the same as that of the first electrode base layer 230. According to some embodiments, the side surface of at least one end of the first electrode base layer 230 may be in the same line as the side surface of the end of the first electrode 210. For example, the side surface of the end of the first electrode base layer 230 in the first direction DR1 and the side surface of the end of the first electrode 210 in the first direction DR1 may be in the same line, forming a flat surface therewith.

[0150] The first electrode 210 and the first electrode base layer 230 may be formed by patterning a part of a conductive layer provided on the entire surface of the first interlayer insulating layer 107 in the same process during the manufacturing process of the display device 10. Accordingly, the first electrode 210 may have a pattern similar to that of the first electrode base layer 230. In some embodiments, the width of the first electrode 210 measured in one direction (e.g., in the first direction DR1) may be substantially the same as the width of the first electrode base layer 230 measured in the first direction DR1. However, a part of the first electrode base layer 230 may be disposed in the non-emission area NEA, and the first electrode 210 may not be disposed on that part.

[0151] The first electrode 210 may be electrically connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT. For example, as shown in the drawings, the first electrode base layer 230 may be directly connected to the second source / drain electrode SDE2 of the driving transistor DT, and the first electrode 210 may be electrically connected to the driving transistor DT through the first electrode base layer 230. However, the embodiments are not limited to this example. In some embodiments, the first electrode 210 may be directly connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT.

[0152] The second electrode 220 is disposed on the second electrode base layer 240. As Figure 5 shown, the second electrode 220 may extend in the second direction DR2 in the emission area EMA of each sub-pixel PXn. The second electrode 220 may not extend to another adjacent sub-pixel PXn in the second direction DR2 and may be spaced apart from the outer bank 450 surrounding the emission area EMA of each sub-pixel PXn. However, the second electrode 220 may partially contact the outer bank 450 extending in the first direction DR1, but the embodiments are not limited to this example.

[0153] The second electrode 220 may be electrically connected to the second voltage wiring VSL. For example, the second electrode base layer 240 may be connected to the second voltage wiring VSL through a fifth contact hole CT5 at a position overlapping with the outer embankment 450 extending in the first direction DR1, and the second electrode 220 may be electrically connected to the second voltage wiring VSL through the second electrode base layer 240. The second electrode 220 may be electrically connected to the second voltage wiring VSL in each pixel PX or sub-pixel PXn. However, the embodiments are not limited to this example. In some embodiments, the wiring of the second electrode 220 extending in one direction and connected to a plurality of pixels PX or sub-pixels PXn may be electrically connected to the second voltage wiring VSL on the periphery of the display area DPA, and the second electrode 220 may be electrically connected to the second voltage wiring VSL through the wiring.

[0154] The second electrode 220 may be formed in a pattern substantially the same as that of the second electrode base layer 240. Similar to the first electrode 210 and the first electrode base layer 230, according to some embodiments, the side surfaces of at least one end of the second electrode base layer 240 may be in the same line as the side surfaces of the ends of the second electrode 220. For example, the side surfaces of the ends of the second electrode base layer 240 in the first direction DR1 and the side surfaces of the ends of the second electrode 220 in the first direction DR1 may be in the same line, forming a flat surface. In some embodiments, the width of the second electrode 220 measured in the first direction DR1 may be substantially the same as the width of the second electrode base layer 240 measured in the first direction DR1. However, a part of the second electrode base layer 240 may be disposed under the outer embankment 450, and the second electrode 220 may not be disposed on this part.

[0155] The first electrode 210 and the second electrode 220 may be disposed adjacent to the center of the emission region EMA and may be spaced apart from each other. A plurality of light-emitting elements 300 may be disposed between the first electrode 210 and the second electrode 220, and the electrodes 210 and 220 may be electrically connected to the light-emitting elements 300 and may receive a predetermined (e.g., set) voltage so that the light-emitting elements 300 can emit light. For example, the electrodes 210 and 220 may be electrically connected to the light-emitting elements 300 through contact electrodes 261 and 262 to be described later, and the received electrical signals may be transmitted to the light-emitting elements 300 through the contact electrodes 261 and 262. In some embodiments, at least a part of each of the electrodes 210 and 220 may be used to form an electric field in each sub-pixel PXn to align the light-emitting elements 300.

[0156] In some example embodiments, the first electrode 210 may be separated in each sub-pixel PXn, and the second electrode 220 may be connected along each sub-pixel PXn. Any one of the first electrode 210 and the second electrode 220 may be electrically connected to the anode of the light-emitting element 300, and the other may be electrically connected to the cathode of the light-emitting element 300. However, the embodiments are not limited to this case, and the opposite case may also hold.

[0157] Each of the electrodes 210 and 220 may include a transparent conductive material. For example, each of the electrodes 210 and 220 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). In some embodiments, each of the electrodes 210 and 220 may include a conductive material having a high reflectivity. For example, each of the electrodes 210 and 220 may include a metal such as silver (Ag), copper (Cu), or aluminum (Al) as a material having a high reflectivity. In some embodiments, each of the electrodes 210 and 220 may reflect incident light in the upward direction in each sub-pixel PXn.

[0158] In some embodiments, each of the electrodes 210 and 220 may have a structure in which a transparent conductive material and a metal layer having a high reflectivity are stacked in one or more layers, or may be formed as a single layer including a transparent conductive material and a metal layer. In some example embodiments, each of the electrodes 210 and 220 may have a stacked structure of ITO / Ag / ITO / IZO or may be an alloy containing aluminum (Al), nickel (Ni), or lanthanum (La), etc.

[0159] Although one first electrode 210 and one second electrode 220 are provided in each sub-pixel PXn in the drawings, the embodiments are not limited to this case. Similar to the electrode substrate layers 230 and 240 and the inner dams 410 and 420, more first electrodes 210 and more second electrodes 220 may be placed. In some embodiments, the first electrode 210 and the second electrode 220 may not have to extend in one direction but may be arranged in various structures. For example, the first electrode 210 and the second electrode 220 may be partially bent or folded, or any one of the first electrode 210 and the second electrode 220 may surround the other electrode. The structure or shape in which the first electrode 210 and the second electrode 220 are provided is not particularly limited as long as the first electrode 210 and the second electrode 220 are at least partially spaced apart from each other to face each other such that a region in which the light-emitting element 300 is to be provided can be formed between the first electrode 210 and the second electrode 220.

[0160] As described above, according to some embodiments, the first inner embankment 410 may be disposed between the first electrode base layer 230 and the first electrode 210, and the second inner embankment 420 may be disposed between the second electrode base layer 240 and the second electrode 220. The electrode base layers 230 and 240 and the electrodes 210 and 220 may be patterned in the same process during the manufacturing process, and the inner embankments 410 and 420 may be disposed between the electrode base layers 230 and 240 and the electrodes 210 and 220.

[0161] Figure 7 is according to some embodiments of the present disclosure Figure 6 schematic enlarged view of a partial QL1.

[0162] Figure 7 More specifically shows the arrangement of the electrode base layers 230 and 240, the inner embankments 410 and 420, and the electrodes 210 and 220. Referring to Figure 7 , the first electrode base layer 230 and the second electrode base layer 240 may be disposed on the first interlayer insulating layer 107 to be spaced apart from each other, the first electrode 210 may be disposed on the first electrode base layer 230, and the second electrode 220 may be disposed on the second electrode base layer 240. The first electrode 210 and the second electrode 220 may be spaced apart from each other, and the light-emitting element 300 may be disposed between the first electrode 210 and the second electrode 220.

[0163] The inner embankments 410 and 420 may be disposed between the electrode base layers 230 and 240 and the electrodes 210 and 220. For example, the first inner embankment 410 may be disposed between the first electrode base layer 230 and the first electrode 210, and the second inner embankment 420 may be disposed between the second electrode base layer 240 and the second electrode 220. According to some embodiments, the first inner embankment 410 and the second inner embankment 420 may be directly disposed on the first electrode base layer 230 and the second electrode base layer 240 respectively, and the lower surfaces of the inner embankments 410 and 420 may contact the upper surfaces of the electrode base layers 230 and 240. During the manufacturing process of the display device 10, the layer constituting the via layer is disposed on the first data conductive layer and may be directly disposed on the first data conductive layer.

[0164] In the display device 10 according to the exemplary embodiment, the width WC measured in one direction of each of the inner dams 410 and 420 may be less than the width WA measured in the same direction of each of the electrode substrate layers 230 and 240. During the manufacturing process of the display device 10, the first inner dam 410 and the second inner dam 420 may be patterned in processes different from the processes of the electrode substrate layers 230 and 240, respectively. The inner dams 410 and 420 may be directly disposed on the electrode substrate layers 230 and 240, and may be formed to have a width WC smaller than the width WA of the electrode substrate layers 230 and 240. Accordingly, the lower surfaces of the inner dams 410 and 420 may directly contact the upper surfaces of the electrode substrate layers 230 and 240, but may not contact the first interlayer insulating layer 107 disposed under the electrode substrate layers 230 and 240.

[0165] Since the inner dams 410 and 420 are formed to have a width WC smaller than the width WA of the electrode substrate layers 230 and 240, the electrodes 210 and 220 disposed on the inner dams 410 and 420 may be formed to cover the inner dams 410 and 420. In some embodiments, since the electrodes 210 and 220 are patterned and formed in the same process as the electrode substrate layers 230 and 240, they may have a width substantially the same as the width WA of the electrode substrate layers 230 and 240. According to some embodiments, the first electrode 210 may cover the outer surface of the first inner dam 410, and the second electrode 220 may cover the outer surface of the second inner dam 420. The widths of the first electrode 210 and the second electrode 220 may be greater than the width WC of the inner dams 410 and 420. Accordingly, a part of the lower surface of the first electrode 210 may directly contact a part of the upper surface of the first electrode substrate layer 230, and a part of the lower surface of the second electrode 220 may directly contact a part of the upper surface of the second electrode substrate layer 240.

[0166] The width WA of each of the electrode substrate layers 230 and 240 may be greater than the width WC of each of the inner dams 410 and 420, and a part of the upper surface of each of the electrode substrate layers 230 and 240 may be exposed. The electrodes 210 and 220 disposed on the electrode substrate layers 230 and 240 may have a width greater than the width WC of the inner dams 410 and 420 to cover the outer surfaces of the inner dams 410 and 420. According to some embodiments, a part of the lower surface of each of the electrodes 210 and 220 of the display device 10 may directly contact a part of the upper surface of the corresponding one of the electrode substrate layers 230 and 240.

[0167] In some embodiments, as shown in the accompanying drawings, according to some embodiments, a first distance DW1 between electrode base layers 230 and 240 may be less than a second distance DW2 between inner dikes 410 and 420. Portions of electrodes 210 and 220 that directly contact electrode base layers 230 and 240 may protrude further than the side surfaces of inner dikes 410 and 420, and at least one end of each of light-emitting elements 300 disposed between inner dikes 410 and 420 may be on the first electrode 210 or the second electrode 220. As will be described later, light-emitting elements 300 may be disposed on a first insulating layer 510, and the first insulating layer 510 may cover at least one end of each of electrodes 210 and 220. The length of each of light-emitting elements 300 may be greater than the first distance DW1 between electrode base layers 230 and 240, and at least one end of each of light-emitting elements 300 disposed between electrodes 210 and 220 may be on electrodes 210 and 220. However, the embodiments are not limited to this example.

[0168] Electrodes 210 and 220 and electrode base layers 230 and 240 may be patterned and formed concurrently (e.g., simultaneously) in the same process during the manufacturing process of the display device 10. The conductive layers for forming electrode base layers 230 and 240 and electrodes 210 and 220 on the first interlayer insulating layer 107 may be patterned together, and electrode base layers 230 and 240 and electrodes 210 and 220 may be formed to have substantially the same width. According to some embodiments, side surfaces of at least one end of each of the first electrode base layer 230 and the second electrode base layer 240 may be in the same line as side surfaces of ends of the corresponding one of the first electrode 210 and the second electrode 220.

[0169] In the accompanying drawings, side surfaces of electrodes 210 and 220 and side surfaces of electrode base layers 230 and 240 are inclined, and electrode base layers 230 and 240 have a width greater than the width of electrodes 210 and 220. However, this is only a structural feature that may occur in the patterning process, and electrodes 210 and 220 and electrode base layers 230 and 240 may also have substantially the same width.

[0170] During the manufacturing process of the display device 10, the conductive layer for forming electrodes 210 and 220 is disposed on the conductive layer for forming electrode base layers 230 and 240. Thus, according to some embodiments, the first electrode 210 and the second electrode 220 may not directly contact the first interlayer insulating layer 107. In some embodiments, at least one side surface of each of electrode base layers 230 and 240 may not contact electrode 210 or 220, and corresponding side surfaces of electrode base layers 230 and 240 and electrodes 210 and 220 may be in the same plane.

[0171] The first electrode 210 and the second electrode 220 may cover the inner dikes 410 and 420, and at least a portion of each of the first electrode 210 and the second electrode 220 may be disposed on the inclined side surfaces of the inner dikes 410 or 420. Light generated by each of the light-emitting elements 300 may be emitted through both ends of the light-emitting element 300 and may travel toward the first electrode 210 and the second electrode 220 disposed on the inclined side surfaces of the inner dikes 410 and 420. As described above, the first electrode 210 and the second electrode 220 may include a material having a high reflectivity to reflect incident light upward above the first substrate 101 ( Figure 7 the "L" in). (For example, reflect incident light from the first substrate 101 toward the upward direction ( Figure 7 the "L" in).

[0172] Referring again to Figure 5 and Figure 6 , the first insulating layer 510 may be disposed in the entire emission area EMA, but may expose a portion of each of the electrodes 210 and 220. For example, the first insulating layer 510 may be disposed in the entire emission area EMA including the electrodes 210 and 220, but may expose a portion of each of the electrodes 210 and 220 positioned on the inner dikes 410 and 420. Openings may be formed in the first insulating layer 510 to partially expose the upper surfaces of the first electrode 210 and the second electrode 220. The openings of the first insulating layer 510 may be formed between portions where the first electrode 210 and the second electrode 220 are stacked with the inner dikes 410 and 420 in the thickness direction. For example, the first insulating layer 510 may be disposed not only in the area between the electrodes 210 and 220, but also on the opposite side of each of the inner dikes 410 and 420 to this area. The first insulating layer 510 may be disposed between the first electrode 210 and the second electrode 220 to cover at least a portion of each of the first electrode 210 and the second electrode 220.

[0173] As described above, the side surfaces of the ends of each of the first electrode 210 and the second electrode 220 may be in the same line as the side surfaces of the ends of the corresponding one of the first electrode base layer 230 and the second electrode base layer 240. According to some embodiments, both side surfaces of each of the first electrode base layer 230 and the second electrode base layer 240 may directly contact the first insulating layer 510. During the manufacturing process of the display device 10, the electrodes 210 and 220 and the electrode base layers 230 and 240 may be patterned and formed in the same process, and both side surfaces of the electrodes 210 and 220 and the electrode base layers 230 and 240 may be aligned with each other. For example, as Figure 7As shown, the side surfaces of the ends of the first electrode 210 and the side surfaces of the ends of the first electrode base layer 230 may be in the same plane (e.g., an inclined side plane), and the side surfaces of the ends of the first electrode base layer 230 may contact the first insulating layer 510.

[0174] The first insulating layer 510 may protect the first electrode 210 and the second electrode 220 while insulating them from each other. In some embodiments, the first insulating layer 510 may reduce the chance that the light-emitting elements 300 disposed on the first insulating layer 510 directly contact other components and are thus damaged. However, the shape and structure of the first insulating layer 510 are not limited to the above examples.

[0175] In some embodiments, the first insulating layer 510 may extend beyond the emission area EMA to be disposed on a portion of the first planarization layer 480 in the non-emission area NEA and a portion of the pad electrode 720 in the pad area PDA. The first insulating layer 510 disposed in the pad area PDA may expose a portion of the upper surface of the pad electrode 720, and the exposed upper surface of the pad electrode 720 may contact a pad cover layer 760 to be described later (see Figure 6 ). However, the embodiments are not limited to this example, and the first insulating layer 510 may also be disposed only in the emission area EMA.

[0176] The light-emitting elements 300 may be disposed between the first electrode 210 and the second electrode 220. Each end of each of the light-emitting elements 300 may be electrically connected to the first electrode 210, and the other end of each of the light-emitting elements 300 may be electrically connected to the second electrode 220. Both ends of each of the light-emitting elements 300 may contact contact electrodes 261 and 262 to be described later and may thus be electrically connected to the first electrode 210 and the second electrode 220 through the contact electrodes 261 and 262, respectively.

[0177] The light-emitting elements 300 may be spaced apart from each other and aligned substantially parallel to each other. The distance between the light-emitting elements 300 is not specifically limited. In some cases, a plurality of light-emitting elements 300 may be disposed adjacent to each other to form a cluster, and a plurality of other light-emitting elements 300 may be disposed at regular intervals to form a cluster. In some embodiments, the light-emitting elements 300 may have an uneven density, but may be positioned and aligned in one direction. In some embodiments, the light-emitting elements 300 may extend in one direction, and the direction along which each electrode (e.g., the first electrode 210 and the second electrode 220) extends may be substantially perpendicular to the direction along which the light-emitting elements 300 extend. In some embodiments, the light-emitting elements 300 may not be perpendicular to but may be inclined to the direction along which each electrode extends.

[0178] The light-emitting element 300 according to some embodiments may include an active layer 330 including different materials (e.g., see Figure 9 ) to emit light of different wavelength bands. The display device 10 according to an exemplary embodiment may include the light-emitting element 300 that emits light of different wavelength bands. Each light-emitting element 300 of the first sub-pixel PX1 may include an active layer 330 that emits light of a first color whose center wavelength band is a first wavelength, each light-emitting element 300 of the second sub-pixel PX2 may include an active layer 330 that emits light of a second color whose center wavelength band is a second wavelength, and each light-emitting element 300 of the third sub-pixel PX3 may include an active layer 330 that emits light of a third color whose center wavelength band is a third wavelength.

[0179] Accordingly, light of the first color may be output from the first sub-pixel PX1, light of the second color may be output from the second sub-pixel PX2, and light of the third color may be output from the third sub-pixel PX3. However, the embodiments are not limited to this case. In some cases, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include the same type of light-emitting element 300 to emit light of substantially the same color.

[0180] The light-emitting element 300 may be disposed on the first insulating layer 510 between the electrodes 210 and 220. However, the embodiments of the present disclosure are not limited to this example. In some embodiments, at least some of the light-emitting elements 300 disposed in each sub-pixel PXn may be disposed in a region other than the region between the first electrode 210 and the second electrode 220. For example, they may be disposed between each of the electrodes 210 and 220 and the outer bank 450. In some embodiments, a part of each of the light-emitting elements 300 may be stacked with each of the electrodes 210 or 220 in the thickness direction. For example, an end portion of each of the light-emitting elements 300 may be disposed on the first electrode 210, and the other end portion of each of the light-emitting elements 300 may be disposed on the second electrode 220.

[0181] In some embodiments, each of the light-emitting elements 300 may include a plurality of layers disposed in a direction parallel to the upper surface of the first substrate 101 or the first insulating layer 510. Each of the light-emitting elements 300 of the display device 10 according to some embodiments may extend in one direction and have a structure in which a plurality of semiconductor layers are sequentially disposed along that direction. The direction along which the light-emitting element 300 extends may be parallel to the first insulating layer 510, and the semiconductor layers included in each of the light-emitting elements 300 may be sequentially disposed in a direction parallel to the upper surface of the first insulating layer 510. However, the embodiments are not limited to this case. In some cases, when each of the light-emitting elements 300 has a different structure, the layers may be disposed in a direction perpendicular to the first insulating layer 510. The structure of each of the light-emitting elements 300 will be described in more detail with reference to other drawings later.

[0182] The second insulating layer 520 may be disposed on the light-emitting elements 300. The second insulating layer 520 may expose both ends of each of the light-emitting elements 300 and a part of the upper surface of each of the first electrode 210 and the second electrode 220. For example, a part of the second insulating layer 520 disposed on each of the light-emitting elements 300 may extend in the second direction DR2 between the first electrode 210 and the second electrode 220 in the emission region EMA. A part of the second insulating layer 520 may form a stripe pattern or an island pattern in the emission region EMA of each sub-pixel PXn. The second insulating layer 520 may also partially cover the outer surfaces of each of the light-emitting elements 300 to protect the light-emitting elements 300 while fixing the light-emitting elements 300 during the manufacturing process of the display device 10. Here, the second insulating layer 520 may expose both ends of each of the light-emitting elements 300, and the exposed ends of each of the light-emitting elements 300 may contact the contact electrodes 261 and 262 to be described later.

[0183] The width of the second insulating layer 520 may be smaller than the length of each of the light-emitting elements 300. Accordingly, one end of each of the light-emitting elements 300 may have an exposed end surface and a part of the exposed side surface, and the other end of each of the light-emitting elements 300 may have an exposed end surface and a covered side surface. For example, one side surface of the second insulating layer 520 may be spaced apart from the end surface of one end of each of the light-emitting elements 300, and the other side surface may be in the same plane (e.g., the same plane along the side surface) as the end surface of the other end of each of the light-emitting elements 300. However, the embodiments are not limited to this example, and both side surfaces of the second insulating layer 520 may also be recessed from both ends of each of the light-emitting elements 300.

[0184] The contact electrodes 261 and 262 and the third insulating layer 530 may be disposed on the second insulating layer 520 in the emission region EMA.

[0185] As Figure 5 shown, the contact electrodes 261 and 262 may extend in one direction. The contact electrodes 261 and 262 may contact the light-emitting element 300 and the electrodes 210 and 220, and the light-emitting element 300 may receive an electrical signal from the first electrode 210 and the second electrode 220 through the contact electrodes 261 and 262.

[0186] The contact electrodes 261 and 262 may include a first contact electrode 261 and a second contact electrode 262. The first contact electrode 261 and the second contact electrode 262 may be respectively disposed on the first electrode 210 and the second electrode 220. The first contact electrode 261 may be disposed on the first electrode 210 and extend in a second direction DR2, and the second contact electrode 262 may be disposed on the second electrode 220 and extend in the second direction DR2. The first contact electrode 261 and the second contact electrode 262 may be spaced apart in a first direction DR1 to face each other, and may form a stripe pattern in the emission region EMA of each sub-pixel PXn.

[0187] In some embodiments, the width of each of the first contact electrode 261 and the second contact electrode 262 measured in one direction may be equal to or greater than the width of each of the first electrode 210 and the second electrode 220 measured in this direction. The first contact electrode 261 and the second contact electrode 262 may respectively contact both ends of each light-emitting element 300 and cover the upper surfaces of the first electrode 210 and the second electrode 220. However, the embodiments are not limited to this example. In some cases, the first contact electrode 261 and the second contact electrode 262 may only partially cover the first electrode 210 and the second electrode 220.

[0188] According to some embodiments, the semiconductor layer may be exposed at the end surfaces of each light-emitting element 300 in the direction along which each light-emitting element 300 extends, and the first contact electrode 261 and the second contact electrode 262 may contact each light-emitting element 300 at the end surfaces where the semiconductor layer is exposed. In some embodiments, the side surfaces of both ends of each light-emitting element 300 may be partially exposed. During the manufacturing process of the display device 10, the insulating film 380 (see Figure 9 ) surrounding the outer surface of the semiconductor layer of each light-emitting element 300 may be partially removed in the process of forming the second insulating layer 520 covering the outer surface of each light-emitting element 300, and the exposed side surfaces of each light-emitting element 300 may contact the first contact electrode 261 and the second contact electrode 262.

[0189] Although a first contact electrode 261 and a second contact electrode 262 are provided in one sub-pixel PXn in the drawings, the embodiments are not limited to this example. The number of the first contact electrode 261 and the second contact electrode 262 may vary according to the number of the first electrode 210 and the second electrode 220 provided in each sub-pixel PXn.

[0190] In some embodiments, as Figure 6 shown, the first contact electrode 261 is provided on the first electrode 210 and the second insulating layer 520. The first contact electrode 261 may contact the end of each light-emitting element 300 and the exposed upper surface of the first electrode 210. The end of each light-emitting element 300 may be electrically connected to the first electrode 210 through the first contact electrode 261.

[0191] A third insulating layer 530 is provided on the first contact electrode 261. The third insulating layer 530 may electrically insulate the first contact electrode 261 and the second contact electrode 262 from each other. The third insulating layer 530 may be provided to cover the first contact electrode 261, but may not be provided on the other end of each light-emitting element 300, so that the light-emitting element 300 can contact the second contact electrode 262. The third insulating layer 530 may partially contact the first contact electrode 261 and the second insulating layer 520 on the upper surface of the second insulating layer 520. The side surface of the third insulating layer 530 in the direction along which the second electrode 220 is provided may be aligned with the side surface of the second insulating layer 520. In some embodiments, the third insulating layer 530 may be provided in the non-emitting area NEA, for example, on the first insulating layer 510 provided on the first planarization layer 480. However, the embodiments are not limited to this example.

[0192] The second contact electrode 262 is provided on the second electrode 220, the second insulating layer 520, and the third insulating layer 530. The second contact electrode 262 may contact the other end of each light-emitting element 300 and the exposed upper surface of the second electrode 220. The other end of each light-emitting element 300 may be electrically connected to the second electrode 220 through the second contact electrode 262.

[0193] For example, the first contact electrode 261 may be disposed between the first electrode 210 and the third insulating layer 530, and the second contact electrode 262 may be disposed on the third insulating layer 530. The second contact electrode 262 may partially contact the second insulating layer 520, the third insulating layer 530, the second electrode 220, and the light-emitting element 300. An end portion of the second contact electrode 262 in the direction along which the first electrode 210 is disposed may be disposed on the third insulating layer 530. The first contact electrode 261 and the second contact electrode 262 may not contact each other due to the second insulating layer 520 and the third insulating layer 530. However, the embodiments are not limited to this example. In some cases, the third insulating layer 530 may be omitted.

[0194] The contact electrodes 261 and 262 may include a conductive material such as ITO, IZO, ITZO, or aluminum (Al). For example, the contact electrodes 261 and 262 may include a transparent conductive material, and light emitted from each light-emitting element 300 may pass through the contact electrodes 261 and 262 and travel toward the electrodes 210 and 220. As Figure 7 shown, each of the electrodes 210 or 220 may include a material having a high reflectivity, and the electrodes 210 and 220 disposed on the inclined side surfaces of the inner dams 410 and 420 may reflect incident light L upward above the first substrate 101 (e.g., reflect incident light L from the first substrate 101 in the upward direction).

[0195] However, the embodiments of the present disclosure are not limited to this example. In some embodiments, the contact electrodes 261 and 262 may include a material having a high reflectivity to reflect light emitted from the light-emitting element 300. In the display device 10, an emission area EMA where the light-emitting element 300 is disposed and a non-emission area NEA where circuit elements and wirings are disposed may be separated, and the light-emitting element 300 may not overlap with the circuit elements or wirings in the thickness direction. When the contact electrodes 261 and 262 include a material having a high reflectivity, light emitted from the light-emitting element 300 may be reflected by the contact electrodes 261 and 262 downward toward the first substrate 101. For example, the display device 10 may have a bottom emission structure. This will be described with reference to some embodiments.

[0196] A pad cover layer 760 disposed on the same layer as the contact electrodes 261 and 262 may be disposed on the pad electrode 720 in the non-display area NDA. The pad cover layer 760 may contact an exposed portion of the upper surface of the pad electrode 720 where the first insulating layer 510 is not provided. The pad cover layer 760 may include the same material as that of the contact electrodes 261 and 262, and may be electrically connected to the pad electrode 720 while covering the pad electrode 720 to protect the pad electrode 720. Although the first insulating layer 510 is disposed on the pad electrode 720 and the pad cover layer 760 only covers a part of the pad electrode 720 in the drawings, the embodiments are not limited to this example. In some embodiments, the first insulating layer 510 may not be disposed in the non-display area NDA, and the pad cover layer 760 may be disposed to cover the outer surfaces of the pad electrode 720 and the pad substrate layer 710.

[0197] The fourth insulating layer 550 may be disposed on the entire surface of the first substrate 101 in the emission area EMA, the non-emission area NEA, and the non-display area NDA. The fourth insulating layer 550 may serve to protect the components disposed on the first substrate 101 from the external environment.

[0198] Each of the first insulating layer 510, the second insulating layer 520, the third insulating layer 530, and the fourth insulating layer 550 described above may include an inorganic insulating material or an organic insulating material. In some exemplary embodiments, each of the first insulating layer 510, the second insulating layer 520, the third insulating layer 530, and the fourth insulating layer 550 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), or aluminum nitride (AlN). In some embodiments, each of the first insulating layer 510, the second insulating layer 520, the third insulating layer 530, and the fourth insulating layer 550 may include an organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, silicone resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, or polymethyl methacrylate-polycarbonate synthetic resin).

[0199] Figure 8 is a partial cross-sectional view of a display device 10 according to some embodiments of the present disclosure.

[0200] Refer to Figure 8, in the display device 10 according to the exemplary embodiment, the third insulating layer 530 may be omitted, and a part of the second contact electrode 262 may be directly disposed on the second insulating layer 520. The first contact electrode 261 and the second contact electrode 262 may be spaced apart from each other on the second insulating layer 520. The second insulating layer 520 may include an organic insulating material, and the first contact electrode 261 and the second contact electrode 262 may be formed together in the same process. Here, the width of the second insulating layer 520 may be smaller than the length of the light-emitting element 300, and two side surfaces of the second insulating layer 520 may be spaced apart from two end surfaces of the light-emitting element 300. For example, the second insulating layer 520 may expose the end surfaces and side surfaces of both ends of the light-emitting element 300.

[0201] The facing side surfaces of the first contact electrode 261 and the second contact electrode 262 may be disposed on the second insulating layer 520 and spaced apart from each other. The first contact electrode 261 may contact the end of the light-emitting element 300, the first electrode 210, and the second insulating layer 520, and the second contact electrode 262 may contact the other end of the light-emitting element 300, the second electrode 220, and the second insulating layer 520. Other details are the same as the details described above, because those of ordinary skill in the art will be able to describe such elements through the details provided in other parts of the present disclosure, and thus their detailed descriptions will not be provided in detail.

[0202] According to some embodiments, the electrode substrate layers 230 and 240 positioned in the emission area EMA of the display device 10 to provide the area where the light-emitting element 300 is disposed may be disposed on the same layer as the circuit elements positioned in the non-emission area NEA to drive the light-emitting element 300. In some embodiments, the electrode substrate layers 230 and 240 may be patterned in the same process as the electrodes 210 and 220 disposed on the electrode substrate layers 230 and 240. Therefore, the number of manufacturing processes of the display device 10 according to the exemplary embodiment can be reduced.

[0203] The light-emitting element 300 may be an LED. In some embodiments, each of the light-emitting elements 300 may be an inorganic LED having a micron size or a nano size and made of an inorganic material. When an electric field is formed in a specific direction between two facing electrodes, the inorganic LED may be aligned between the two electrodes where polarity is formed. The light-emitting element 300 may be aligned between the two electrodes by the electric field formed between the electrodes.

[0204] The light-emitting element 300 according to some embodiments may extend in one direction. Each of the light-emitting elements 300 may be shaped like a rod, a wire, a tube, or the like. In some exemplary embodiments, each of the light-emitting elements 300 may be shaped like a cylinder or a rod. In some embodiments, each of the light-emitting elements 300 may have various shapes including polygonal prisms such as a cube, a cuboid, and a hexagonal prism, and a shape that extends in one direction and has a partially inclined outer surface. A plurality of semiconductors included in each of the light-emitting elements 300 described later may be sequentially arranged or stacked along the above direction.

[0205] Each of the light-emitting elements 300 may include a semiconductor layer doped with impurities of any conductive type (e.g., p-type or n-type). The semiconductor layer may receive an electrical signal from an external power source and emit the electrical signal as light in a specific wavelength band.

[0206] Figure 9 is a schematic diagram of the light-emitting element 300 according to some embodiments of the present disclosure.

[0207] Referring to Figure 9 , the light-emitting element 300 may include a first semiconductor layer 310, a second semiconductor layer 320, an active layer 330, an electrode layer 370, and an insulating film 380.

[0208] The first semiconductor layer 310 may be an n-type semiconductor. In some exemplary embodiments, if the light-emitting element 300 emits light in the blue wavelength band, the first semiconductor layer 310 may include a semiconductor material having the chemical formula Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). For example, the first semiconductor layer 310 may be any one or more of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer 310 may be doped with an n-type dopant, and the n-type dopant may be, for example, Si, Ge, or Sn. In some exemplary embodiments, the first semiconductor layer 310 may be n-GaN doped with n-type Si. The length of the first semiconductor layer 310 may be in the range of 1.5 μm to 5 μm, but is not limited thereto.

[0209] The second semiconductor layer 320 is disposed on the active layer 330 described later. The second semiconductor layer 320 may be a p-type semiconductor. In some exemplary embodiments, if the light-emitting element 300 emits light in the blue or green wavelength band, the second semiconductor layer 320 may include a semiconductor material having the chemical formula Al x Ga y In 1-x-yA semiconductor material of N(0≤x≤1, 0≤y≤1, 0≤x + y≤1). For example, the second semiconductor layer 320 can be any one or more of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer 320 can be doped with a p-type dopant, and the p-type dopant can be, for example, Mg, Zn, Ca, Se, or Ba. In some exemplary embodiments, the second semiconductor layer 320 can be p-GaN doped with p-type Mg. The length of the second semiconductor layer 320 can be in the range of 0.05 μm to 0.10 μm, but is not limited thereto.

[0210] Although in the drawings each of the first semiconductor layer 310 and the second semiconductor layer 320 is constituted by one layer, the embodiments are not limited to this case. In some embodiments, each of the first semiconductor layer 310 and the second semiconductor layer 320 can include more layers according to the material of the active layer 330. For example, a cladding layer or a tensile strain barrier reduction (TSBR) layer can be further included. This will be described later with reference to other drawings.

[0211] The active layer 330 is disposed between the first semiconductor layer 310 and the second semiconductor layer 320. The active layer 330 can include a material having a single quantum well structure or a multi-quantum well structure. When the active layer 330 includes a material having a multi-quantum well structure, the active layer 330 can have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The active layer 330 can emit light through the combination of electron-hole pairs according to the electrical signals received through the first semiconductor layer 310 and the second semiconductor layer 320. For example, when the active layer 330 emits light in the blue wavelength band, the active layer 330 can include a material such as AlGaN or AlGaInN. Specifically, when the active layer 330 has a multi-quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layers can include a material such as AlGaN or AlGaInN, and the well layers can include a material such as GaN or AlInN. In some exemplary embodiments, the active layer 330 can include AlGaInN as the quantum layer and AlInN as the well layer, and can emit blue light with a central wavelength band in the range of 450 nm to 495 nm.

[0212] In some embodiments, the active layer 330 can have a structure in which a semiconductor material having a large bandgap energy and a semiconductor material having a small bandgap energy are alternately stacked, or can include different group 3 to group 5 semiconductor materials according to the wavelength band of the emitted light. The light emitted from the active layer 330 is not limited to light in the blue wavelength band. In some cases, the active layer 330 can emit light in the red or green wavelength band. The length of the active layer 330 can be in the range of 0.05 μm to 0.10 μm, but is not limited thereto.

[0213] The light emitted from the active layer 330 can be radiated not only through the outer surface of the light-emitting element 300 in the longitudinal direction, but also through the two side surfaces. The direction of the light emitted from the active layer 330 is not limited to one direction.

[0214] The electrode layer 370 may be an ohmic contact electrode. However, the electrode layer 370 is not limited to an ohmic contact electrode and may also be a Schottky contact electrode. The light-emitting element 300 may include at least one electrode layer 370. Although Figure 9 the light-emitting element 300 includes one electrode layer 370 in [the description], the embodiments are not limited to this example. In some cases, the light-emitting element 300 may include more electrode layers 370, or the electrode layer 370 may be omitted. Even when the light-emitting element 300 includes a different number of electrode layers 370 or also includes another structure, the following description of the light-emitting element 300 may equally apply.

[0215] When the light-emitting element 300 is electrically connected to the electrodes 210 and 220 or in contact with the contact electrodes 261 and 262, the electrode layer 370 can reduce the resistance between the light-emitting element 300 and the electrodes 210 and 220 or the contact electrodes 261 and 262. The electrode layer 370 may include a conductive metal. For example, the electrode layer 370 may include at least any one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). In some embodiments, the electrode layer 370 may include an n-type or p-type doped semiconductor material. The electrode layer 370 may include the same material or different materials, but the embodiments are not limited to this case.

[0216] The insulating film 380 surrounds the outer surfaces of the semiconductor layers 310 and 320 and the electrode layer 370 described above. In some exemplary embodiments, the insulating film 380 may surround at least the outer surface of the active layer 330 and extend in the direction in which the light-emitting element 300 extends. The insulating film 380 can protect the above components (e.g., 310, 320, 330, 370). For example, the insulating film 380 may surround the side surfaces of the above components, but may expose both ends of the light-emitting element 300 in the longitudinal direction.

[0217] In the drawings, the insulating film 380 extends in the longitudinal direction of the light-emitting element 300 to cover from the side surface of the first semiconductor layer 310 to the side surface of the electrode layer 370. However, the embodiments are not limited to this example. The insulating film 380 may also cover the active layer 330 and the outer surfaces of only some of the semiconductor layers, or may cover only a part of the outer surface of the electrode layer 370 to partially expose the outer surface of the electrode layer 370. In some embodiments, the upper surface of the insulating film 380 may be circular in cross-section in a region adjacent to at least one end of the light-emitting element 300.

[0218] The thickness of the insulating film 380 may be in the range of 10 nm to 1.0 μm, but is not limited thereto. The thickness of the insulating film 380 may be about 40 nm.

[0219] The insulating film 380 may include an insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN), or aluminum oxide (Al2O3). Thus, it can prevent (or reduce the chance of) an electrical short circuit that may occur when the active layer 330 directly contacts the electrode that transmits an electrical signal to the light-emitting element 300. In some embodiments, since the insulating film 380 protects the outer surface of the light-emitting element 300 including the active layer 330, a reduction in luminous efficiency can be prevented or substantially avoided.

[0220] In some embodiments, the outer surface of the insulating film 380 can be treated. When manufacturing the display device 10, the light-emitting elements 300 dispersed in ink (e.g., a predetermined or set ink) can be ejected onto the electrodes and then aligned. Here, the surface of the insulating film 380 can be hydrophobic or hydrophilic treated so that the light-emitting elements 300 remain separated in the ink and do not aggregate with other adjacent light-emitting elements 300.

[0221] The length h of the light-emitting element 300 may be in the range of 1 μm to 10 μm or 2 μm to 6 μm, and in some embodiments, may be in the range of 3 μm to 5 μm. In some embodiments, the diameter of the light-emitting element 300 may be in the range of 300 nm to 700 nm, and the aspect ratio of the light-emitting element 300 may be 1.2 to 100. However, the embodiments are not limited to this example, and the plurality of light-emitting elements 300 included in the display device 10 may also have different diameters according to differences in the composition of the active layer 330. The diameter of the light-emitting element 300 may be (or may preferably be) about 500 nm.

[0222] Now, a process of manufacturing the display device 10 will be described with reference to other drawings. The sequence of the manufacturing process of the display device 10 will be described in detail below, but the method of forming each component will not be described.

[0223] Figures 10 to 18 are cross-sectional views showing nine parts of a process of manufacturing a display device according to some embodiments of the present disclosure.

[0224] First, with reference to Figure 10 , a first substrate 101 is prepared, and a buffer layer 102, a semiconductor layer, a first gate insulating layer 103, a first gate conductive layer, a first protective layer 105, and a first interlayer insulating layer 107 are formed on the first substrate 101. The conductive layer and the insulating layer can be formed by a conventional process because those of ordinary skill in the art will be able to describe such elements from the details provided in other parts of the present disclosure, and thus their detailed descriptions will not be provided in detail.

[0225] Next, with reference to Figure 11 , a first base conductive layer SDL1 is formed on the first interlayer insulating layer 107. The first base conductive layer SDL1 can be placed on the entire surface of the first interlayer insulating layer 107 and patterned in a subsequent process to form a first data conductive layer. For example, portions of the first base conductive layer SDL1 disposed in the non-emission area NEA can form source / drain electrodes SDE1 and SDE2 of the driving transistor DT, portions of the first base conductive layer SDL1 disposed in the emission area EMA can form electrode base layers 230 and 240, and portions of the first base conductive layer SDL1 disposed in the pad area PDA can form a pad base layer 710.

[0226] As described above, in the display device 10 according to the exemplary embodiment, the first data conductive layer and the electrodes 210 and 220 can be patterned and formed in the same process. The first base conductive layer SDL1 can be patterned simultaneously with an electrode conductive layer RMTL (see Figure 16 ) disposed on the first base conductive layer SDL1 in a subsequent process to form the electrode base layers 230 and 240 and the pad base layer 710. However, the first base conductive layer SDL1 disposed in the non-emission area NEA can be patterned along the shape of the wiring and conductive patterns provided in each pixel PX or sub-pixel PXn.

[0227] With reference to Figure 12, the portion of the first substrate conductive layer SDL1 disposed in the non-emission area NEA is patterned to form a second substrate conductive layer SDL2 including a plurality of wirings and conductive patterns. The second substrate conductive layer SDL2 may be entirely disposed in the emission area EMA and the pad area PDA, but may be partially patterned in the non-emission area NEA. The portion of the second substrate conductive layer SDL2 disposed in the non-emission area NEA may form the wirings and conductive patterns of each pixel PX or sub-pixel PXn. In some embodiments, the portions of the second substrate conductive layer SDL2 disposed in the emission area EMA and the pad area PDA may be patterned simultaneously with the electrode conductive layer RMTL (e.g., see Figure 16 ).

[0228] Next, referring to Figures 13 to 15 , a via layer is formed on the second substrate conductive layer SDL2. A first planarization layer 480 is formed on the second substrate conductive layer SDL2 in the non-emission area NEA, and inner dams 410 and 420 and an outer dam 450 are formed on the second substrate conductive layer SDL2 in the emission area EMA. According to some embodiments, during the manufacturing process of the display device 10, the first planarization layer 480, the inner dams 410 and 420, and the outer dam 450 are formed in the same process but may be formed to have different heights. For example, the first planarization layer 480, the inner dams 410 and 420, and the outer dam 450 may be formed to have different heights by a patterning process using a half-tone mask.

[0229] First, referring to Figure 13 , an insulating material layer VIA is formed to cover the first interlayer insulating layer 107 and the second substrate conductive layer SDL2. The insulating material layer VIA may include the same material as the material of the via layer and may include, for example, an organic insulating material (such as polyimide (PI)).

[0230] Next, referring to Figure 14 and Figure 15 , the insulating material layer VIA is patterned using a half-tone mask HTM to form the first planarization layer 480, the inner dams 410 and 420, and the outer dam 450. Since slits are formed in some areas of the half-tone mask HTM, the amount of transmitted light may vary according to the area. As shown in the drawings, different slits may be formed in the portions of the half-tone mask HTM corresponding to the non-emission area NEA and the emission area EMA, and different amounts of light may be transmitted through the areas where the slits are located. Therefore, different amounts of light may irradiate different areas of the insulating material layer VIA, and the amount of the insulating material layer VIA removed by the exposure and development processes may vary according to the position. As a result, the first planarization layer 480, the inner dams 410 and 420, and the outer dam 450 may be formed to have different heights.

[0231] According to some embodiments, in the display device 10, the heights HA and HB of the inner dams 410 and 420 may be less than the heights HC and HD of the outer dam 450 and the first planarization layer 480. In some embodiments, the height HD of the first planarization layer 480 may be less than the height HC of the outer dam 450.

[0232] The inner dams 410 and 420 may be spaced apart from each other to provide an area in which the light-emitting elements 300 may be disposed, and may be light reflection blockers that reflect light emitted from the light-emitting elements 300. For example, the inner dams 410 and 420 may be high enough to provide an area in which the light-emitting elements 300 may be disposed and that reflects light emitted from the light-emitting elements 300. On the other hand, the outer dam 450 may separate each sub-pixel PXn while preventing or substantially preventing the ink in which the light-emitting elements 300 are dispersed from overflowing to other adjacent sub-pixels PXn during the manufacturing process of the display device 10. Accordingly, the outer dam 450 according to some embodiments may be formed to have a height greater than the heights HA and HB of the inner dams 410 and 420 in order to prevent or reduce the chance of overflow of the ink in which the light-emitting elements 300 are dispersed.

[0233] The first planarization layer 480 may be disposed in the non-emission area NEA to planarize the steps formed by circuit elements (e.g., transistors DT, SCT, and SST disposed under the first planarization layer 480) while protecting the circuit elements. Since the first planarization layer 480 (unlike the inner dams 410 and 420 and the outer dam 450) may be formed over the entire non-emission area NEA, the first planarization layer 480 may be formed to be relatively thick. In some embodiments, the height HD of the first planarization layer 480 may be greater than the heights of the inner dams 410 and 420 and the outer dam 450.

[0234] Next, referring to Figures 16 to 18 , an electrode conductive layer RMTL is formed to cover the via layer and is patterned simultaneously with the second substrate conductive layer SDL2 to form electrode substrate layers 230 and 240 and electrodes 210 and 220.

[0235] First, referring to Figure 16, an electrode conductive layer RMTL is formed on the entire surface of the first interlayer insulating layer 107. The electrode conductive layer RMTL can be formed of the same material as that of each of the electrodes 210 or 220. The electrode conductive layer RMTL can be directly disposed on the via layer and the second substrate conductive layer SDL2 on which no via layer is provided. For example, the electrode conductive layer RMTL can be placed on the first planarization layer 480 of the non-emission region NEA, and the inner dikes 410 and 420 and the outer dike 450 of the emission region EMA to cover them. Here, the electrode conductive layer RMTL can also be disposed on the inclined side surfaces of the inner dikes 410 and 420. In some embodiments, the electrode conductive layer RMTL can be placed on the second substrate conductive layer SDL2 provided in the pad region PDA.

[0236] Next, referring to Figure 17 and Figure 18 , the electrode conductive layer RMTL and the second substrate conductive layer SDL2 are concurrently (e.g., simultaneously) patterned to form electrode substrate layers 230 and 240 and electrodes 210 and 220. The electrode substrate layers 230 and 240 and the electrodes 210 and 220 can be formed by a conventional patterning process. For example, photoresists PR1 to PR3 can be formed on the electrode conductive layer RMTL, and the regions where no photoresists PR1 to PR3 are provided can be exposed and developed to form the electrode substrate layers 230 and 240 and the electrodes 210 and 220.

[0237] The photoresists PR1 and PR2 can be provided in the regions of the electrode conductive layer RMTL corresponding to the regions where the electrode substrate layers 230 and 240 and the electrodes 210 and 220 are provided. As shown in Figure 17 , the first photoresist PR1 can be provided in the region of the electrode conductive layer RMTL that overlaps with the first inner dike 410, and the second photoresist PR2 can be provided in the region of the electrode conductive layer RMTL that overlaps with the second inner dike 420. The electrode conductive layer RMTL and the second substrate conductive layer SDL2 on which the first photoresist PR1 and the second photoresist PR2 are provided can be patterned to form the first electrode 210, the first electrode substrate layer 230, the second electrode 220, and the second electrode substrate layer 240. In some embodiments, the third photoresist PR3 can be placed on the electrode conductive layer RMTL provided in the pad region PDA, and the pad substrate layer 710 and the pad electrode 720 can be formed in this region.

[0238] Referring to Figure 18, the electrode conductive layer RMTL and the second substrate conductive layer SDL2 are patterned using photoresists PR1 to PR3 to form electrode substrate layers 230 and 240, electrodes 210 and 220, pad substrate layers 710, and pad electrodes 720. The second substrate conductive layer SDL2 and the electrode conductive layer RMTL in the regions where the photoresists PR1 to PR3 are not provided can be removed by patterning, and the second substrate conductive layer SDL2 and the electrode conductive layer RMTL in the regions overlapping with the photoresists PR1 to PR3 can be left. In the display device 10 according to the exemplary embodiment, the electrode substrate layers 230 and 240 and the electrodes 210 and 220 can be patterned in the same process and can be provided in substantially the same shape. Specifically, the pad substrate layer 710 and the pad electrode 720 provided in the pad region PDA can have substantially the same width. This has been described in detail above.

[0239] In the region where the via layer is provided among the regions where the photoresists PR1 to PR3 are not provided, the second substrate conductive layer SDL2 located under the via layer may not be patterned. The second substrate conductive layer SDL2 provided under the first planarization layer 480 and the outer bank 450 may not be removed and may be formed to have the same width as the widths of the first planarization layer 480 and the outer bank 450. Specifically, the second substrate conductive layer SDL2 provided under the outer bank 450 may form the data line DTL provided in each pixel PX or sub-pixel PXn. The data line DTL may be the remaining part after the second substrate conductive layer SDL2 is patterned along the outer bank 450, and the side surface of the data line DTL may be exposed without contacting the outer bank 450. However, as described above, the side surface of the data line DTL may contact the first insulating layer 510.

[0240] Next, although not shown in the drawings, a first insulating layer 510 is formed on the first electrode 210 and the second electrode 220, and then the light-emitting element 300 is placed between the first electrode 210 and the second electrode 220 or between the first inner bank 410 and the second inner bank 420.

[0241] In some embodiments, the light-emitting elements 300 dispersed in the ink (e.g., a predetermined or set ink) may be ejected into the emission area EMA of each pixel PX or sub-pixel PXn by an inkjet process and may be aligned between the first electrode 210 and the second electrode 220 by a process of forming an electric field therebetween. When an alignment signal is transmitted to the first electrode 210 and the second electrode 220 after the light-emitting elements 300 dispersed in the ink are ejected into the emission area EMA, an electric field may be formed between the electrodes 210 and 220, and dielectrophoretic force may be applied to the light-emitting elements 300 through the electric field. The dielectrophoretic force applied to the light-emitting elements 300 may change the orientation direction and position of the light-emitting elements 300 in the ink, thereby aligning the light-emitting elements 300 between the first electrode 210 and the second electrode 220.

[0242] Here, any one of the first electrode 210 and the second electrode 220 may be grounded, and an alternating current (AC) power source may be applied to the other electrode. For example, when the first electrode 210 is grounded and the AC power source is applied to the second electrode 220, the AC power source may be directly applied to the second electrode 220 instead of the second voltage wiring VSL. The process of applying the AC power source to the second electrode 220 may be performed through the wiring connected to the second electrode 220 during the manufacturing process of the display device 10, and then the process of disconnecting the wiring may be performed.

[0243] Next, a second insulating layer 520, contact electrodes 262 and 261, a third insulating layer 530, and a fourth insulating layer 550 are formed on the light-emitting elements 300 to complete the display device 10.

[0244] Now, various embodiments of the display device 10 will be described.

[0245] The first electrode 210 and the second electrode 220 may be electrically connected to a first data conductive layer (e.g., the source / drain electrodes SDE1 and SDE2 of the driving transistor DT or the second voltage wiring VSL) provided in the non-emission area NEA. In Figure 5 and Figure 6 , the first electrode base layer 230 is directly connected to the second source / drain electrode SDE2 of the driving transistor DT, and the first electrode 210 is electrically connected to the driving transistor DT through the first electrode base layer 230. However, the embodiments are not limited to this example. In some embodiments, the first electrode base layer 230 may be electrically connected to the driving transistor DT through a bridge pattern provided on a different layer, or the first electrode 210 may be directly electrically connected to the driving transistor DT.

[0246] Figure 19 is a layout diagram of the sub-pixel PXn of the display device 10_1 according to some embodiments of the present disclosure. Figure 20A cross-sectional view taken along line II-II' and a part of the non-display area NDA according to some embodiments of the present disclosure. Figure 19 and a part of the non-display area NDA.

[0247] Referring to Figure 19 and Figure 20 , the display device 10_1 according to an exemplary embodiment may further include a first bridge pattern BP1_1 and a second bridge pattern BP2_1. The first bridge pattern BP1_1 is connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT and the first electrode base layer 230_1, and the second bridge pattern BP2_1 is connected to the second voltage wiring VSL and the second electrode base layer 240_1. The current embodiment is different from the embodiments of Figure 5 and Figure 6 in that the first electrode base layer 230_1 and the source / drain electrode SDE1 or SDE2 of the driving transistor DT are connected through the bridge patterns BP1_1 and BP2_1 respectively, and the second electrode base layer 240_1 and the second voltage wiring VSL are connected without being directly connected to each other. Since those skilled in the art will be able to describe such elements through the details provided in other parts of the present disclosure, any redundant description will be omitted, and the differences will be mainly described below.

[0248] In Figure 19 and Figure 20 of the display device 10_1, the first electrode base layer 230_1 may not be directly connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT, but may be electrically connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT through the first bridge pattern BP1_1 disposed under the first electrode base layer 230_1. The second electrode base layer 240_1 may also not be directly connected to the second voltage wiring VSL, but may be electrically connected to the second voltage wiring VSL through the second bridge pattern BP2_1 disposed under the second electrode base layer 240_1. In the current embodiment, the first interlayer insulating layer 107_1, the bridge pattern layer, and the second interlayer insulating layer 108_1 may be disposed between the first data conductive layer and the first protective layer 105.

[0249] The first interlayer insulating layer 107_1 is the same as that referred to above Figure 6The described first interlayer insulating layer 107 is substantially the same. The first interlayer insulating layer 107_1 may be disposed on the first protective layer 105 to serve as an insulating film between the first protective layer 105 and the conductive layer disposed on the first interlayer insulating layer 107_1. The second interlayer insulating layer 108_1 is disposed on the first interlayer insulating layer 107_1. The second interlayer insulating layer 108_1 may serve as an insulating film between the bridge pattern layer disposed between the first interlayer insulating layer 107_1 and the second interlayer insulating layer 108_1 and the first data conductive layer disposed on the second interlayer insulating layer 108_1. In the current embodiment, the bridge pattern layer may be further disposed between the first data conductive layer and the first gate conductive layer, and a plurality of interlayer insulating layers 107_1 and 108_1 may be disposed between the first data conductive layer, the bridge pattern layer, and the first gate conductive layer. Accordingly, the member of the first data conductive layer connected to the conductive layer disposed below the first data conductive layer may be connected through a contact hole penetrating the first interlayer insulating layer 107_1 and the second interlayer insulating layer 108_1. For example, the source / drain electrodes SDE1 and SDE2 of the driving transistor DT may respectively contact portions of the first active material layer ACT1 through the first contact hole CT1 and the second contact hole CT2 penetrating the first interlayer insulating layer 107_1, the second interlayer insulating layer 108_1, the first protective layer 105, and the first gate insulating layer 103. The first interlayer insulating layer 107_1 and the second interlayer insulating layer 108_1 are the same as the first interlayer insulating layer 107 and the second interlayer insulating layer 108 described above, because those of ordinary skill in the art will be able to describe such elements through the details provided in other parts of the present disclosure, and thus their detailed descriptions will not be provided in detail.

[0250] The bridge pattern layer may include a first bridge pattern BP1_1 and a second bridge pattern BP2_1 and may be disposed between the first interlayer insulating layer 107_1 and the second interlayer insulating layer 108_1.

[0251] The first bridge pattern BP1_1 may be disposed between the emission area EMA and the non-emission area NEA to be stacked with the first electrode base layer 230_1 and the source / drain electrode SDE1 or SDE2 of the driving transistor DT in the thickness direction. The first bridge pattern BP1_1 may be connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT and the first electrode base layer 230_1 through the contact holes CT5 and CT6 penetrating the second interlayer insulating layer 108_1. For example, the first bridge pattern BP1_1 may contact the second source / drain electrode SDE2 of the driving transistor DT through the fifth contact hole CT5 that penetrates the second interlayer insulating layer 108_1 to expose a part of the upper surface of the first bridge pattern BP1_1. In some embodiments, the first bridge pattern BP1_1 may contact the first electrode base layer 230_1 through the sixth contact hole CT6 that penetrates the second interlayer insulating layer 108_1 to expose a part of the upper surface of the first bridge pattern BP1_1.

[0252] Accordingly, the first electrode base layer 230_1 may be electrically connected to the driving transistor DT through the first bridge pattern BP1_1, and the first electrode 210_1 may be electrically connected to the driving transistor DT through the first electrode base layer 230_1 and the first bridge pattern BP1_1. In some embodiments, the first electrode base layer 230_1 and the first electrode 210_1 may be spaced apart from the boundary between the emission area EMA and the non-emission area NEA. For example, the first electrode base layer 230_1 and the first electrode 210_1 may be spaced apart from the first planarization layer 480.

[0253] In some embodiments, the second electrode base layer 240_1 may be electrically connected to the second voltage wiring VSL through a second bridge pattern BP2_1 (e.g., see Figure 19 ) disposed between the first interlayer insulating layer 107_1 and the second interlayer insulating layer 108_1.

[0254] The second bridge pattern BP2_1 may be disposed in the emission area EMA and under the outer embankment 450 that overlaps with the second voltage wiring VSL. For example, the second bridge pattern BP2_1 may be disposed between the outer embankment 450 and the second voltage wiring VSL to overlap them in the thickness direction and may also be disposed to overlap the second electrode base layer 240_1 in the thickness direction. The second bridge pattern BP2_1 may be connected to the second voltage wiring VSL and the second electrode base layer 240_1 through contact holes penetrating the first interlayer insulating layer 107_1 and the second interlayer insulating layer 108_1. For example, the second bridge pattern BP2_1 may contact the second voltage wiring VSL through a seventh contact hole CT7 that penetrates the first interlayer insulating layer 107_1 to expose a part of the upper surface of the second voltage wiring VSL. In some embodiments, the second bridge pattern BP2_1 may contact the second electrode base layer 240_1 through an eighth contact hole CT8 that penetrates the second interlayer insulating layer 108_1 to expose a part of the upper surface of the second bridge pattern BP2_1.

[0255] Accordingly, the second electrode base layer 240_1 may be electrically connected to the second voltage wiring VSL through the second bridge pattern BP2_1, and the second electrode 220_1 may be electrically connected to the second voltage wiring VSL through the second electrode base layer 240_1 and the second bridge pattern BP2_1. In some embodiments, the second electrode base layer 240_1 and the second electrode 220_1 may be spaced apart from the outer embankment 450 in the emission area EMA.

[0256] As described above, the first electrode 210_1 may also be directly connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT.

[0257] Figure 21 is a layout diagram of a sub-pixel PXn of the display device 10_2 according to some embodiments of the present disclosure. Figure 22 is along according to some embodiments of the present disclosure Figure 21 A cross-sectional view taken along line III-III' and a part of the non-display area NDA.

[0258] Referring to Figure 21 and Figure 22 , in the display device 10_2 according to the exemplary embodiment, at least a part of the first electrode 210_2 may be disposed on the first planarization layer 480 of the non-emission area NEA, and may be electrically connected to the driving transistor DT through a contact hole CT9 (see Figure 21 ) that penetrates the first planarization layer 480 to expose the source / drain electrode SDE1 or SDE2 of the driving transistor DT. The current embodiment is the same as Figure 5 and Figure 6The embodiment is different in that: the first electrode 210_2 is directly connected to the source / drain electrode SDE1 or SDE2 of the driving transistor DT, and the first electrode substrate layer 230_2 is not directly electrically connected to the driving transistor DT. Since those of ordinary skill in the art will be able to describe such elements through the details provided in other parts of the present disclosure, any redundant description will be omitted, and the differences will be mainly described below.

[0259] In Figure 21 and Figure 22 In the display device 10_2 of, the first electrode substrate layer 230_2 may be spaced apart from the source / drain electrodes SDE1 and SDE2 of the driving transistor DT, and may not be directly connected to the source / drain electrodes SDE1 or SDE2 of the driving transistor DT. When forming the second substrate conductive layer SDL2 during the manufacturing process of the display device 10_2, the source / drain electrodes SDE1 and SDE2 of the driving transistor DT may be spaced apart from other parts.

[0260] In some embodiments, before the process of forming the electrode conductive layer RMTL, the ninth contact hole CT9 is formed in the first planarization layer 480 to penetrate the first planarization layer 480 and expose a part of the upper surface of the source / drain electrode SDE1 or SDE2 of the driving transistor DT. Then, the electrode conductive layer RMTL and the via layer formed entirely on the second substrate conductive layer SDL2 can contact the source / drain electrode SDE1 or SDE2 of the driving transistor DT through the ninth contact hole CT9, and the electrode conductive layer RMTL and the second substrate conductive layer SDL2 are patterned together to form the first electrode 210_2. The first electrode 210_2 can be directly connected to the driving transistor DT through the ninth contact hole CT9 that penetrates the first planarization layer 480. Since those of ordinary skill in the art will be able to describe such elements through the details provided in other parts of the present disclosure, no redundant description will be provided.

[0261] Figure 23 is a cross-sectional view of a sub-pixel PXn of a display device 10_3 according to some embodiments of the present disclosure. Figure 24 is according to some embodiments of the present disclosure Figure 23 A schematic enlarged view of a partial QL2 of.

[0262] Referring to Figure 23 and Figure 24 , in the display device 10_3 according to the exemplary embodiment, the contact electrodes 261_3 and 262_3 contacting both ends of the light-emitting element 300 may include a material with a high reflectivity, and reflect the light emitted from the light-emitting element 300 toward the lower surface of the first substrate 101. The current embodiment and Figure 7The embodiments differ in that: Since the contact electrodes 261_3 and 262_3 include different materials, the display device 10_3 has a bottom emission structure. Since those skilled in the art will be able to describe such elements through the details provided in other parts of the present disclosure, no redundant description will be provided, and the differences will be mainly described below.

[0263] In Figure 23 and Figure 24 the display device 10_3, each of the first contact electrode 261_3 and the second contact electrode 262_3 may include a material having a high reflectivity to reflect the light emitted from the light-emitting element 300. The light-emitting element 300 may receive electrical signals from the electrodes 210 and 220 and the contact electrodes 261_3 and 262_3, and emit light in a specific wavelength band. The light may be generated by the active layer 330 of the light-emitting element 300 and emitted through both ends of the light-emitting element 300. Here, if the contact electrodes 261_3 and 262_3 contacting both ends of the light-emitting element 300 include a material having a high reflectivity, the light emitted from the light-emitting element 300 may travel toward the lower surface of the first substrate 101. In some exemplary embodiments, the contact electrodes 261_3 and 262_3 may include the same materials as the electrodes 210 and 220.

[0264] Since the contact electrodes 261_3 and 262_3 are also disposed on the second insulating layer 520 disposed on the light-emitting element 300, the light emitted from the light-emitting element 300 may be reflected toward the first insulating layer 510 and the first interlayer insulating layer 107 disposed below the light-emitting element 300. In the display device 10_3 according to the exemplary embodiment, the emission area EMA where the light-emitting element 300 is disposed may be separated from the non-emission area NEA where the circuit elements are disposed, and the light-emitting element 300 may not be stacked with the circuit elements in the thickness direction. Therefore, even if the light travels toward the first insulating layer 510 or the first interlayer insulating layer 107 on which the light-emitting element 300 is disposed, the light may not be reflected by the conductive layer constituting the circuit element. According to some embodiments, the contact electrodes 261_3 and 262_3 including a material having a high reflectivity may reflect the light emitted from the light-emitting element 300 downward (e.g., toward the lower surface of the first substrate 101). Therefore, the display device 10_3 may have a bottom emission structure.

[0265] A display device according to some embodiments includes an emission region in which light-emitting elements are provided and a non-emission region in which circuit elements are provided, and the light-emitting elements and the circuit elements may not overlap in the thickness direction. Electrodes electrically connected to the light-emitting elements and an electrode base layer electrically connected to the light-emitting elements may be patterned in the same process during a manufacturing process. An inner bank may be provided between the electrodes and the electrode base layer, and the light-emitting elements may be provided in a region formed by the inner bank.

[0266] In a display device according to some embodiments, wirings and electrodes provided in the emission region and the non-emission region may be formed in the same process. Accordingly, the number of manufacturing processes can be reduced.

[0267] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the exemplary embodiments without substantially departing from the principles of the present disclosure. Therefore, the disclosed exemplary embodiments of the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, the display device comprising: Substrate; A first electrode substrate layer and a second electrode substrate layer, spaced apart from each other on the substrate; A first electrode and a second electrode, the first electrode being on the first electrode substrate layer and the second electrode being on the second electrode substrate layer; A first inner bank and a second inner bank, the first inner bank being between the first electrode substrate layer and the first electrode, and the second inner bank being between the second electrode substrate layer and the second electrode; A light-emitting element, between the first electrode and the second electrode, at least one end of the light-emitting element being electrically connected to the first electrode or the second electrode; A first contact electrode, contacting the end of the light-emitting element and the first electrode; And A second contact electrode, contacting the other end of the light-emitting element and the second electrode, wherein, side surfaces of at least one end of each of the first electrode substrate layer and the second electrode substrate layer are in the same line as side surfaces of the corresponding one of the first electrode and the second electrode, and wherein, at least one end of the light-emitting element is on the first electrode or the second electrode.

2. The display device according to claim 1, wherein, The first electrode covers the outer surface of the first inner bank, and the second electrode covers the outer surface of the second inner bank.

3. The display device according to claim 1 or 2, wherein, At least a part of the lower surface of the first electrode directly contacts the upper surface of the first electrode substrate layer, and at least a part of the lower surface of the second electrode directly contacts the upper surface of the second electrode substrate layer.

4. The display device according to claim 3, wherein, At least one side surface of each of the first electrode substrate layer and the second electrode substrate layer does not contact the corresponding one of the first electrode and the second electrode.

5. The display device according to claim 3, wherein, The first electrode and the second electrode do not directly contact the substrate.

6. The display device according to claim 3, wherein, The first inner bank and the second inner bank are directly on the first electrode substrate layer and the second electrode substrate layer respectively.

7. The display device according to claim 2, wherein, The distance between the first electrode and the second electrode is less than the distance between the first inner bank and the second inner bank.

8. The display device according to claim 2, the display device further comprising a first insulating layer between the first electrode and the second electrode and covering at least a portion of each of the first electrode and the second electrode, wherein, The light-emitting element is on the first insulating layer.

9. The display device according to claim 8, wherein, The first electrode substrate layer and the second electrode substrate layer directly contact the first insulating layer.

10. The display device according to claim 1, wherein, The substrate includes an emission region and a non-emission region, and The first electrode, the second electrode and the light-emitting element are in the emission region, wherein, the display device further includes a first data conductive layer in the non-emission region.

11. The display device according to claim 10, the display device further comprising a first interlayer insulating layer on the substrate, wherein, The first data conductive layer and the first electrode substrate layer are directly on the first interlayer insulating layer.

12. The display device according to claim 10 or 11, wherein, The first electrode is electrically connected to the first data conductive layer.

13. The display device according to claim 10, wherein, The substrate further includes a non-display region, and wherein, the display device further includes a pad substrate layer in the non-display region and a pad electrode on the pad substrate layer.

14. The display device according to claim 13, wherein, The pad substrate layer is at the same layer as the first electrode substrate layer, and the pad electrode is at the same layer as the first electrode.

15. The display device according to claim 10, the display device further comprising: A first planarization layer, on the first data conductive layer in the non-emission region; And An outer bank, surrounding the first electrode and the second electrode in the emission region, wherein, the first planarization layer, the outer bank and the first inner bank are at the same layer.

16. The display device according to claim 15, wherein, The first planarization layer, the outer dam, and the first inner dam have different heights.

17. The display device according to claim 15, the display device further comprising a data line between the outer embankment and the substrate, wherein, At least one side surface of the data line does not contact the outer dam.

18. A display device, the display device comprising: A substrate having an emission region and a non-emission region; A first interlayer insulating layer on the substrate; A first data conductive layer on the first interlayer insulating layer and including source and drain electrodes of a driving transistor and a plurality of electrode base layers in the emission region; A via layer on the first data conductive layer and including a first planarization layer in the non-emission region and an inner dam on the plurality of electrode base layers; A plurality of electrodes respectively on the plurality of electrode base layers; And A plurality of light-emitting elements between the plurality of electrodes, wherein the plurality of electrode base layers include a first electrode base layer and a second electrode base layer spaced apart from the first electrode base layer, wherein the plurality of electrodes include a first electrode on the first electrode base layer and a second electrode on the second electrode base layer, wherein the display device further includes: a first contact electrode contacting an end of the plurality of light-emitting elements and the first electrode; and a second contact electrode contacting the other end of the plurality of light-emitting elements and the second electrode, wherein the plurality of light-emitting elements are between the first electrode and the second electrode, and wherein at least one end of the plurality of light-emitting elements is on the first electrode or the second electrode.

19. The display device according to claim 18, wherein, The inner dam includes a first inner dam between the first electrode base layer and the first electrode, a second inner dam between the second electrode base layer and the second electrode, and wherein the first electrode and the second electrode respectively cover outer surfaces of the first inner dam and the second inner dam.

20. The display device according to claim 19, wherein, A width of the first inner dam measured in one direction is less than a width of the first electrode base layer measured in the one direction.

21. The display device according to claim 18 or 20, wherein, At least a part of a lower surface of the first electrode directly contacts the first electrode base layer.

22. The display device according to claim 18, wherein, A height of the first planarization layer is greater than a height of the inner dam.

23. The display device according to claim 22, wherein, The via layer further includes an outer dam at a periphery of the emission region, wherein a height of the outer dam is greater than the height of the inner dam but less than the height of the first planarization layer.

24. The display device according to claim 18, wherein, The substrate further includes a non-display region, wherein the first data conductive layer further includes a pad base layer in the non-display region, and wherein a pad electrode is further provided on the pad base layer.

25. The display device according to claim 24, wherein, The pad electrode is at the same layer as the first electrode.

26. The display device according to claim 24, wherein, A width of the pad base layer measured in one direction is the same as a width of the pad electrode measured in the one direction.

27. The display device according to claim 18, the display device further comprising: A semiconductor layer in the non-emission region of the substrate and including a first active material layer of the driving transistor; A first gate insulating layer on the semiconductor layer; And A first gate electrode of the driving transistor on the first gate insulating layer, wherein the source and drain electrodes of the driving transistor contact the first active material layer through contact holes penetrating the first interlayer insulating layer and the first gate insulating layer.

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