Digital integration processing method based on CNN cellular neural network structure

Abstract

The present invention provides a digital integrated processing method based on the CNN cellular neural network structure, supports synchronous and efficient two-dimensional neighborhood matrix calculation, performs synchronous block calculation on all points on the image pixel matrix, realizes the design of a proprietary chip for efficient image processing, achieves high efficiency and low power consumption factors, has the advantages of low cost, supports multiple data structures and data accuracy, and perfectly supports various mainstream protocols and neural network models.

Description

Technical Field

[0001] The present invention relates to the technical field of digital integrated processing, and in particular to a digital integrated processing method based on a CNN cellular neural network structure. Background Art

[0002] At present, with the rise of artificial intelligence, the status of image recognition is becoming more and more important. As an important part of the field of image recognition, the computing unit of image processing has also been developing. From CPU general computing to GPU one-dimensional parallel computing, the development of proprietary computing integrated circuits is getting faster and faster. The computing units of existing processors have more or less their own disadvantages: CPU, the classic von Neumann system, is a general-purpose processor that accesses memory through the control module to call data for processing, and the control logic is complex. Its single computing unit is powerful, but the computing power cannot be shared between computing cores. It is good at processing a single complex computing task, but not good at parallelizing a large number of tasks. GPU, based on high throughput design, cache occupies less space and is only for supporting Thread. It has a large number of computing units and is good at large-scale repeated computing application scenarios, but can only perform one-dimensional operations, not good at two-dimensional operations on neighborhood regional data, and the computing speed is slow. Proprietary image acceleration processors are mostly based on traditional convolutional neural networks. They are restricted by the convolution layer structure and data structure, and the computing speed is not high, the accuracy is limited, and few have learning capabilities. Existing computing integrated circuit units either sacrifice high-speed parallel capabilities for the sake of single-unit computing power, or increase computing throughput at the expense of simplifying computing units, or are constrained by structural design. Therefore, it is particularly important to solve the problems of weak parallel processing capabilities of computing units in traditional architecture processors, weak independent computing capabilities of computing units with high throughput, lack of two-dimensional computing capabilities due to structural and data constraints, and high power consumption for large image computing when converting two-dimensional images into one-dimensional data multiplication. Summary of the invention

[0003] The purpose of the present invention is to provide a digital integrated processing method based on the CNN cellular neural network structure, which supports efficient two-dimensional neighborhood matrix calculation, performs synchronous block calculation on all points on the image pixel matrix, realizes the design of a proprietary chip for efficient image processing, achieves high efficiency and low power consumption factors, and has the advantages of low cost, supports multiple data structures, and perfectly supports various mainstream protocols and neural network models.

[0004] The present invention provides a digital integration processing method based on a CNN cellular neural network structure, the method comprising the following steps:

[0005] Step 1: The image is processed by a set of circuits composed of cell circuit units. The circuit is input in the form of a pixel matrix for collection. Each circuit unit participates in processing the image pixels at the same time.

[0006] Step 2: The cell circuit unit takes a certain pixel in the image as the processing object, and the circuit transmits the pixel information of the object image, the pixel information around the computing unit, and the computing parameters to the circuit module;

[0007] Step 3: Use a multiplier unit to multiply all pixel data with the operation parameter to obtain optimized pixel data;

[0008] Step 4: The processed pixel data is passed through a three-layer adder, and the adjacent data on the structure are first calculated, and then added two by two and summarized to finally obtain the processed pixel data;

[0009] Step 5: Calculate the relevant connection points in the neighborhood of the cell circuit unit respectively, and the calculation results are transmitted to the addition unit for calculation after the register beats a beat rhythm;

[0010] Step 6: The unit operation parts correspond to different data widths respectively; structurally, the neighborhood processing parameters are added in pairs, and finally summarized, using the idea of ​​exchanging space for time to accelerate the calculation process of multi-bit width and multi-data multiplication and addition.

[0011] A further improvement is that the number of multipliers in step three is 9, and they form a multiplication unit, and the relevant connection points in the cell neighborhood are calculated respectively.

[0012] A further improvement is that in step 4, there are 8 adders forming the adding unit part, and there are three adding units from the input, corresponding to different data widths and input preprocessing methods. A further improvement is that the calculation template in step 5 is a correlation connection matrix relationship.

[0013] A further improvement is that the data structure of the computing unit in step six contains multiple formats, supports fixed-point and high-precision floating-point, and has a self-learning and adjustment function.

[0014] The beneficial effects of the present invention are as follows: the target unit can be subjected to block calculation in the neighborhood range, the operation unit can perform direct convolution calculation on the matrix without splitting the matrix into one-dimensional operations, direct calculation, flexible control, multi-core concept, repeated use, and low power consumption after the operation unit is scaled up. The structural design of the adder is optimized, and the operation time can be effectively improved for multi-bit data input. Different large pixel blocks (14*14 / 20*20) can be effectively processed. The design structure can use a higher frequency clock, coupled with a special storage structure, effectively reducing the risk of timing errors, eliminating loads, and reducing the probability of glitches. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1This is the structural block diagram A of the CNN cellular neural network system of the present invention.

[0016] Figure 2 This is the structural block diagram B of the CNN cellular neural network system of the present invention.

[0017] Figure 3 This is the CNN cellular neural network circuit diagram A of the present invention.

[0018] Figure 4 The present invention Figure 3 Enlarged view of center frame 1.

[0019] Figure 5 The present invention Figure 3 Enlarged view of the middle frame 2.

[0020] Figure 6 The present invention Figure 3 Enlarged view of the 3rd position in the middle frame.

[0021] Figure 7 The present invention Figure 3 Enlarged view of 4 locations in the middle frame.

[0022] Figure 8 The present invention Figure 3 Enlarged view of position 5 in the middle frame.

[0023] Fig. 9 The present invention Figure 3 Enlarged view of position 6 in the middle frame.

[0024] Fig.10 The present invention Figure 3 Enlarged view of position 7 in the middle frame.

[0025] Fig.11 The present invention Figure 3 Enlarged view of position 8 in the middle frame.

[0026] Fig.12 The present invention Figure 3 Enlarged view of position 9 in the middle frame.

[0027] Fig.13 This is the CNN cellular neural network circuit diagram B of the present invention.

[0028] Fig.14 The present invention Fig.13 Enlarged view of center frame 1.

[0029] Fig.15 The present invention Fig.13 Enlarged view of the middle frame 2.

[0030] Fig.16 It is a circuit diagram of a multiplier of the present invention.

[0031] Fig.17 It is the circuit diagram of adder A of the present invention.

[0032] Fig.18 It is the circuit diagram of adder B of the present invention.

[0033] Fig.19 It is the circuit diagram of adder C of the present invention. DETAILED DESCRIPTION

[0034] In order to deepen the understanding of the present invention, the present invention will be further described in detail below in conjunction with examples. The examples are only used to explain the present invention and do not constitute a limitation on the protection scope of the present invention.

[0035] The system structure diagram of the CNN cellular neural network computing unit is as follows Figure 1 , Figure 2 As shown, taking image processing as an example, after the image passes through the cache unit, it is expanded on the cell circuit unit in units of pixels. All cell units in the cell unit circuit set simultaneously calculate all corresponding pixels of the image and the pixels in their surrounding neighborhood according to the connection relationship. Refine to each cell unit circuit, take a certain pixel in the image as the processing object, and the circuit passes the object image pixel information, the calculation surrounding pixel information and the calculation parameters to the circuit module. In the first stage, a multiplier unit is used to multiply all pixel data with the calculation weight parameter to obtain optimized pixel data. In the second stage, the processed pixel data is passed through three layers of adders, added two by two, and finally the processed pixel data is obtained.

[0036] Figure 3 and Fig.13 The circuit diagram of the cellular neural network circuit describes the architecture of different data structures and data precision respectively. The process is as follows: the target pixel information and the pixel information i1 to i9 in the surrounding neighborhood are transmitted to the circuit in parallel with the coefficient data p1 to p9 of the correlation matrix. After multiplication by the multiplier, the weight value of the correlation is obtained. The first type of adder performs a first-level accumulation, enters the register storage, and then enters the second-level adder for accumulation and summary. Finally, the third-level adder accumulates to obtain the final value cnn_out. The data format of the i series and the p series is determined by the input data and parameter settings. In the optional mode using the selector, cnn_out is allowed to feedback the aforementioned parameters, and dynamically compare and change the parameter settings to adapt to related applications. Figure 3 This is a diagram of the first type of data structure and data precision. Figure 4 and Figure 5 This is the multiplier operation part, in which the correlation coefficient weights are multiplied and all the related points in the matrix are associated and calculated. Figure 6 , Figure 7 , Figure 8 and Fig. 9 It is the adder operation, which performs the first half of the tree accumulation. Fig.10 and Fig.11 It is the second part of the adder operation, which performs the second half of the tree accumulation. Fig.12 The final accumulated value is combined with parameters and pixel data to shift, integrate and optimize to obtain the eigenvalue. Fig.13 This is a diagram of the second type of data structure and data precision. Fig.14 and Fig.15 They are multiplication and addition operations and integrated shift operations respectively.

[0037] Fig.16 It is a multiplier in the cellular neural network circuit, used to multiply the filter parameters and pixel data. The entire multiplication unit is composed of 9 multiplier structures, which respectively perform operations on the relevant connection points in the cell neighborhood. In the multiplication circuit structure, the pixel data i and the parameter data p are expanded, and the operation method is selected according to the information in the parameter data. After that, the two data are multiplied after the bit-filling operation according to the selected parameter structure to obtain the output value m. The operation result of the multiplication unit is transmitted to the addition unit for calculation after the register beats a beat rhythm.

[0038] Fig.17 , Fig.18 , Fig.19 It is the adder of the cellular neural network operation unit. There are 8 adders in total to form the adding unit part. There are two types of adding units in terms of input, corresponding to different data widths respectively. From the structure, it forms the addition of two neighborhood processing parameters, and finally summarizes them. The idea of ​​exchanging space for time accelerates the calculation process of multi-bit width and multi-data addition. The adding circuit takes two types of data with different structures m_1 and m_2 as input, and uses the selection signals of different structures as control inputs m_1_e, m_2_e, m_1_s, and m_2_s. According to the selection of the parameter model, the control signal is mixed and matched to synthesize, so as to control the input of the two types of data in time-sharing, forming shift addition. Finally, the target data is output in time-sharing through the shift register to obtain the superposition values ​​sum_m and sum_e.

[0039] The design principle of the entire process is to directly and synchronously perform matrix convolution operations on the entire image according to specific model parameters and the correlation connection matrix relationship of all pixel values ​​in the neighborhood of the target point, so as to achieve the goal of image (pixel point) processing according to the established parameter model.

Claims

1. A digital integration processing method based on CNN cellular neural network structure, characterized by: The method comprises the following steps: Step 1: The image is processed by a set of circuits composed of cell circuit units. The circuit is input in the form of a pixel matrix for collection. Each circuit unit participates in processing the image pixels at the same time. Step 2: The cell circuit unit takes a certain pixel in the image as the processing object, and the circuit transmits the pixel information of the object image, the pixel information around the computing unit, and the computing parameters to the circuit module; Step 3: Use a multiplier unit to multiply all pixel data with the operation parameter to obtain optimized pixel data; Step 4: The processed pixel data is passed through a three-layer adder, and the adjacent data on the structure are first calculated, and then added two by two and summarized to finally obtain the processed pixel data; Step 5: Calculate the relevant connection points in the neighborhood of the cell circuit unit respectively, and the calculation results are transmitted to the addition unit for calculation after the register beats a beat rhythm; Step 6: The calculation units correspond to different data widths and have different data structures and data precision types. The neighborhood processing parameters are structurally added in pairs and then summarized. The idea of ​​exchanging space for time is used to accelerate the calculation process of multi-bit width and multi-data multiplication and addition.

2. A digital integration processing method based on CNN cellular neural network structure as claimed in claim 1, characterized in that: The number of multipliers in step three is 9, and they form a multiplication unit, and perform operations on the relevant connection points in the cell neighborhood.

3. A digital integration processing method based on CNN cellular neural network structure as claimed in claim 1, characterized in that: In the step 4, there are 8 adders in total, forming the adding unit part. From the input point of view, there are three types of adding units in total, corresponding to different data widths and input preprocessing methods respectively.

4. A digital integration processing method based on CNN cellular neural network structure as claimed in claim 3, characterized in that: The adder connection method adopts the method of adding the local similarities first and summing them up at the end.

5. A digital integration processing method based on CNN cellular neural network structure as claimed in claim 1, characterized in that: The calculation template in step five is a correlation connection matrix relationship.

6. A digital basic processing method based on CNN cellular neural network structure as claimed in claim 1, characterized in that: The various data types in step six include fixed-point and floating-point. Fixed-point includes mainstream input image formats and models; floating-point has high precision and learning adjustment feedback functions.

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