Micro-electromechanical system device and method for forming the same

Abstract

A microelectromechanical system (MEMS) device includes: a MEMS substrate; at least one movable element, which is laterally defined in a matrix layer overlying the MEMS substrate; and a top cover substrate, which is partially bonded to the matrix layer by a bonding material. A first movable element selected from the at least one movable element is located inside a first chamber, which is laterally bounded by the matrix layer and vertically bounded by a first top cover surface overlying the first movable element. The first top cover surface includes an array of multiple downwardly protruding bumps, and the multiple downwardly protruding bumps include corresponding portions of a dielectric material layer. Each of the multiple downwardly protruding bumps has an inverted vertical cross-sectional profile. The MEMS device may include, for example, an accelerometer.

Description

Technical Field

[0001] The disclosed embodiments relate to a micro-electromechanical system device and a method for forming the same. Background Art

[0002] Micro-electromechanical system (MEMS) devices include devices fabricated using semiconductor technology to form mechanical and electrical features. MEMS devices may include moving parts with micron or submicron dimensions and mechanisms for electrically coupling the moving parts to electrical signals, which may be input signals that cause movement of the moving parts or output signals that result from movement of the moving parts. MEMS devices are useful devices that can be integrated with other devices, such as semiconductor devices, to act as sensors or actuators. Summary of the invention

[0003] According to an embodiment of the present disclosure, a micro-electromechanical system device includes a micro-electromechanical system substrate, at least one movable element and a top cover substrate. At least one movable element is laterally confined in a matrix layer, and the matrix layer is overlying the micro-electromechanical system substrate. The top cover substrate is bonded to the matrix layer, wherein a first movable element selected from the at least one movable element is located inside a first chamber, the first chamber is laterally bounded by the matrix layer and vertically bounded by a first top cover surface overlying the first movable element, and wherein the first top cover surface includes an array of multiple downwardly protruding bumps, and the multiple downwardly protruding bumps include corresponding portions of a bump-containing material layer.

[0004] According to an embodiment of the present disclosure, a method for forming a micro-electromechanical system device includes: forming at least one movable element, the at least one movable element being laterally confined in a matrix layer located above a micro-electromechanical system substrate; forming a recessed area on the front side of a top cover substrate; forming a top cover side bonding dielectric layer above the uppermost surface of the top cover substrate and in the recessed area of ​​the top cover substrate; forming a plurality of grooves extending through the top cover side bonding dielectric layer into the top cover substrate in the recessed area; forming a bump-containing material layer on the top cover side bonding dielectric layer, wherein a plurality of portions of the bump-containing material layer overlying the plurality of grooves form an array of a plurality of upwardly protruding bumps; and bonding the top cover substrate to the matrix layer so that the front side of the top cover substrate faces the matrix layer, and a first chamber is formed by the matrix layer and the top cover substrate, the first chamber including a first movable element selected from the at least one movable element, wherein a surface of the array of the plurality of upwardly protruding bumps provides a first top cover surface in the first chamber after being placed upside down on the first movable element during bonding.

[0005] According to an embodiment of the present disclosure, a method for forming a micro-electromechanical system device includes: forming at least one movable element, the at least one movable element being laterally confined in a matrix layer located above a micro-electromechanical system substrate; forming a plurality of first grooves on the front side of a top cover substrate; making a region of the top cover substrate including the plurality of first grooves concave in a vertical direction, wherein a concave horizontal surface is formed in the concave region of the top cover substrate, and a plurality of second grooves replicating the pattern of the plurality of first grooves extend downward from the concave horizontal surface in a vertical direction; forming a plurality of first grooves on the topmost surface of the top cover substrate and on the front side of a top cover substrate; forming a plurality of second grooves on the topmost surface of the top cover substrate and on the front side of a top cover substrate; forming a plurality of first grooves on the top cover substrate and on the front side of a top cover substrate; forming a plurality of second grooves on the top cover substrate and on the front side of a top cover substrate; forming a plurality of first ... A bump-containing material layer is formed in the recessed area, wherein a plurality of portions of the bump-containing material layer overlying the plurality of second grooves form an array of a plurality of upwardly protruding bumps; and the top cover substrate is bonded to the matrix layer so that the front side of the top cover substrate faces the matrix layer, and a first chamber is formed by the matrix layer and the top cover substrate, the first chamber comprising a first movable element selected from the at least one movable element, wherein a surface of the array of the plurality of upwardly protruding bumps provides a first top cover surface in the first chamber after being placed upside down on the first movable element during bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present invention will be better understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a vertical cross-sectional view of an exemplary structure for forming a MEMS structure after forming a first dielectric material layer over a matrix material layer according to an embodiment of the present invention.

[0008] Figure 1B is a vertical cross-sectional view of an exemplary structure after forming a first conductive material layer according to an embodiment of the present invention.

[0009] Figure 1C is a vertical cross-sectional view of an exemplary structure after forming a second dielectric material layer according to an embodiment of the present invention.

[0010] Figure 1D is a vertical cross-sectional view of an exemplary structure after forming a second conductive material layer according to an embodiment of the present invention.

[0011] Figure 1E is a vertical cross-sectional view of an exemplary structure after forming a third dielectric material layer and bonding a MEMS substrate according to an embodiment of the present invention.

[0012] Figure 1F is a vertical cross-sectional view of an exemplary structure after thinning the matrix material layer according to an embodiment of the present invention.

[0013] Figure 1G is a vertical cross-sectional view of an exemplary structure after forming a matrix-side bonding dielectric layer according to an embodiment of the present invention.

[0014] Figure 1H is a vertical cross-sectional view of an exemplary structure after patterning a matrix material layer into movable elements and a matrix layer according to an embodiment of the present invention.

[0015] Fig. 1I is a vertical cross-sectional view of an exemplary structure after detaching a movable element from a first dielectric material layer by removing portions of the first dielectric material layer, in accordance with an embodiment of the present invention.

[0016] Figure 2A is a vertical cross-sectional view of a first exemplary structure for forming a cap structure after forming a first recessed area according to an embodiment of the present invention.

[0017] Figure 2B is a vertical cross-sectional view of the first exemplary structure after forming a cap side bonding dielectric layer in accordance with an embodiment of the present invention.

[0018] Figure 2C is a vertical cross-sectional view of the first exemplary structure after forming an opening through the cap-side bonding dielectric layer in the first recessed region in accordance with an embodiment of the present invention.

[0019] Figure 2D is a vertical cross-sectional view of the first exemplary structure after forming a trench beneath an opening through a cap-side bonding dielectric layer in accordance with an embodiment of the present invention.

[0020] Figure 2E yes Figure 2D Magnified view of area E in FIG.

[0021] Figure 2F yes Figure 2D A top view of a first exemplary structure in a first configuration is shown.

[0022] Figure 2G yes Figure 2D A top view of a second configuration of the first exemplary structure is shown.

[0023] Figure 2H is a vertical cross-sectional view of the first exemplary structure after forming a bump-containing material layer according to an embodiment of the present invention.

[0024] Fig.2I yes Figure 2HMagnified view of region I in FIG.

[0025] Figure 2J yes Figure 2H A top view of a first exemplary structure in a first configuration is shown.

[0026] Figure 2K yes Figure 2H A top view of a second configuration of the first exemplary structure is shown.

[0027] Figure 2L is a vertical cross-sectional view of the first exemplary structure after removing a top horizontal portion of the bump-containing material layer in accordance with an embodiment of the present invention.

[0028] Figure 2M is a vertical cross-sectional view of a first exemplary structure after forming a first etch mask layer and an opening in a cap-side bonding dielectric layer in accordance with an embodiment of the present invention.

[0029] Figure 2N is a vertical cross-sectional view of the first exemplary structure after forming a second etch mask layer and recessing a portion of the cap substrate in a vertical direction according to an embodiment of the present invention.

[0030] Fig.2O is a vertical cross-sectional view of the first exemplary structure after forming a second recessed region according to an embodiment of the present invention.

[0031] Figure 3 is a first exemplary micro-electromechanical system (MEMS) device according to an embodiment of the present invention.

[0032] Figure 4A is a vertical cross-sectional view of a second exemplary structure for forming a cap structure after forming a patterned hard mask layer in accordance with an embodiment of the present invention.

[0033] Figure 4B is a vertical cross-sectional view of the second exemplary structure after forming a patterned etch mask layer according to an embodiment of the present invention.

[0034] Figure 4C is a vertical cross-sectional view of the second exemplary structure after forming a first trench and an in-process recess region in accordance with an embodiment of the present invention.

[0035] Figure 4D is a vertical cross-sectional view of a second exemplary structure after forming a first recessed region and a second trench extending in a vertical direction from the first recessed region and after forming a second recessed region according to an embodiment of the present invention.

[0036] Figure 4Eis a vertical cross-sectional view of the second exemplary structure after forming a bump-containing material layer according to an embodiment of the present invention.

[0037] Figure 4F yes Figure 4E Magnified view of area F in FIG.

[0038] Figure 4G yes Figure 4E A top view of a first configuration of a second exemplary structure is shown.

[0039] Figure 4H yes Figure 4E A top view of a second configuration of a second exemplary structure is shown.

[0040] Figure 5 is a second exemplary micro-electromechanical system (MEMS) device according to an embodiment of the present invention.

[0041] Figure 6 is a process flow diagram illustrating operations for forming a MEMS device assembly in accordance with an embodiment of the present invention.

[0042] Figure 7 is a process flow diagram illustrating operations for forming a MEMS device assembly according to another embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0044] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0045] The present invention relates to a micro-electromechanical system (MEMS) device including a bump stopper structure and a method for forming a MEMS device. Some MEMS devices may include a MEMS assembly layer and a top cover structure layer. The MEMS assembly may include a moving plate (i.e., a movable element) or a sensing element that records the acceleration of the device or the angular velocity of the device. Sometimes, because the moving plate in the MEMS assembly is micron-sized, the moving plate may adhere to a complementary top cover structure due to stiction, and the complementary top cover structure includes the moving plate together with the MEMS assembly. In the case where two surfaces with an area below the micron level are close together (as in an accelerometer), the two surfaces may adhere together. At this scale, electrostatic forces and / or Van der Waals forces and hydrogen bonding forces become important. The phenomenon of two such surfaces adhering together in this way is also called stiction. Stiction may be related to hydrogen bonding or residual contamination. Various embodiments described herein provide a bump structure in a top cover structure. The bump structure reduces the surface area of ​​the top cover structure that can contact the moving plate of the MEMS assembly. By reducing the surface area of ​​the contact surface, the possibility of stiction can also be reduced.

[0046] Reference Figure 1A, showing an exemplary structure for forming a MEMS assembly according to an embodiment of the present invention. The exemplary structure includes a matrix material layer 10L. The matrix material layer 10L may include a first semiconductor material, which may include silicon, germanium, silicon-germanium alloy or compound semiconductor material that may be doped to locally change conductivity or other suitable materials within the contemplated scope of the present invention. In one embodiment, the thickness of the matrix material layer 10L may be in the range of 30 microns to 1 millimeter (mm), although smaller thicknesses and larger thicknesses may also be used. In one embodiment, the upper portion of the matrix material layer 10L may include a hydrogen-implanted layer so that the lower portion of the matrix material layer 10L can be subsequently cleaved. In this case, the depth of the hydrogen-implanted layer from the top surface of the matrix material layer 10L may be in the range of 100 nanometers (nm) to 3 microns, such as 300nm to 1,000nm, although smaller depths and larger depths may also be used. The exemplary structure may include various regions for forming various devices including at least one microelectromechanical system (MEMS) device. For example, the exemplary structure may include a first device region 101 and a second device region 102. In a non-limiting exemplary example, components of an accelerometer for measuring linear acceleration may be formed in the first device region 101, and a gyroscope for measuring angular velocity may be formed in the second device region 102. In other non-limiting embodiments, a structure having repeated first device regions 101 or second device regions 102 may be formed to form multiple sensors of the same type.

[0047] A first dielectric material layer 20 may be formed over the top surface of the matrix material layer 10L. The first dielectric material layer 20 may include dielectric materials such as silicon oxide, silicon nitride, organosilicate glass, porous low-k dielectric materials, or spin-on glass (SOG) materials. Other suitable materials within the contemplated scope of the present invention may also be used. The first dielectric material layer 20 may be deposited by chemical vapor deposition, physical vapor deposition, or spin coating. The thickness of the first dielectric material layer 20 may be in the range of 100 nm to 600 nm, although smaller thicknesses and larger thicknesses may also be used. In one embodiment, the first dielectric material layer 20 may include a densified undoped silicate glass material formed by the decomposition of tetraethylorthosilicate (TEOS).

[0048] Reference Figure 1B, the first dielectric material layer 20 may be patterned by a combination of a photolithography process and at least one etching process to form various cavities that may include line cavities and through-hole cavities. For example, a first photoresist layer (not shown) may be applied on the first dielectric material layer 20, and the first photoresist layer may be patterned photolithographically to form a through-hole opening therethrough. A first anisotropic etching may be performed to transfer the pattern of the through-hole opening through the upper portion of the first dielectric material layer 20 to form a through-hole cavity. The first photoresist layer may be removed, and a second photoresist layer (not shown) may be applied on the first dielectric material layer 20. The second photoresist layer may be patterned photolithographically to form a linear opening therethrough. A second anisotropic etching process may be performed to transfer the pattern of the linear opening through the upper portion of the first dielectric material layer 20 to form a line cavity, and the through-hole cavity is extended to the top surface of the matrix material layer 10L. The second photoresist layer may be removed, for example, by an ashing process or other suitable process. At least one conductive material (first conductive structure 22) may be deposited in the via cavity and the line cavity. Excess portions of the at least one conductive material (first conductive structure 22) may be removed from above a level including the top surface of the first dielectric material layer 20. The remainder of the at least one conductive material in the first dielectric material layer 20 constitutes the first conductive structure 22. The first conductive structure 22 may include a doped semiconductor material (e.g., doped polysilicon) or a metallic material such as an elemental metal, an intermetallic alloy, a conductive metal nitride material, or a metal semiconductor compound (e.g., a metal silicide).

[0049] Reference Figure 1C, a second dielectric material layer 30 may be deposited over the first conductive structure 22 and the first dielectric material layer 20. The second dielectric material layer 30 may include a dielectric material such as silicon oxide, silicon nitride, organosilicate glass, porous low-k dielectric material, or spin-on glass (SOG) material. Other suitable materials within the contemplated scope of the present invention may also be used. The second dielectric material layer 30 may be deposited by chemical vapor deposition, physical vapor deposition, or spin coating. The thickness of the second dielectric material layer 30 may be in the range of 100 nm to 600 nm, although smaller thicknesses and larger thicknesses may also be used. In one embodiment, the second dielectric material layer 30 may include a layer stack, the layer stack including a plurality of dielectric material layers including an etch stop layer such as a silicon nitride layer or an aluminum oxide layer. In the case of using a layer stack for the second dielectric material layer 30, the upper layer within the layer stack may include a densified undoped silicate glass material formed by decomposition of tetraethyl orthosilicate (TEOS). The second dielectric material layer 30 may be patterned to form various via cavities. The top surface of the corresponding first conductive structure 22 may be physically exposed at the bottom of each via cavity passing through the second dielectric material layer 30 .

[0050] Reference Figure 1D , at least one conductive material may be deposited in the through hole cavity through the second dielectric material layer 30 and on the second dielectric material layer 30. The at least one conductive material may be patterned, for example, by applying a photoresist layer over the at least one conductive material and patterning the photoresist layer and transferring the pattern of the photoresist layer through the at least one conductive material. Subsequently, the photoresist layer may be removed, for example, by an ashing process or other suitable process. The remaining patterned portion of the at least one conductive material may constitute a second conductive structure 32. The second conductive structure 32 may include a doped semiconductor material (e.g., doped polysilicon) or a metallic material such as an elemental metal, an intermetallic alloy, a conductive metal nitride material, or a metal semiconductor compound (e.g., a metal silicide).

[0051] In general, at least one level of conductive structures (first conductive structures 22, second conductive structures 32) may be formed on or within the corresponding dielectric material layers (first dielectric material layers 20, second dielectric material layers 30) located above the matrix material layer 10L. Various patterning methods may be used to form a combination of the at least one level of conductive structures (first conductive structures 22, second conductive structures 32) and the at least one dielectric material layer (first dielectric material layers 20, second dielectric material layers 30). Such patterning methods include, but are not limited to, single damascene patterning methods, dual damascene patterning methods, layer deposition and patterning methods, and the like. In the case where a hydrogen planting layer (not shown) is present in the matrix material layer 10L, the processing temperature may be selected to be lower than a temperature that allows hydrogen atoms in the hydrogen planting layer to be decomposed (which may occur at a temperature ranging from 500 degrees Celsius to 600 degrees Celsius). Although only two levels of conductive structures (first conductive structure 22, second conductive structure 32) are described herein, it is understood that as many levels of conductive structures as possible can be formed in the embodiment structure as needed. The pattern of the conductive structure (first conductive structure 22, second conductive structure 32) can be optimized so as to realize the functions of various MEMS devices to be formed subsequently.

[0052] Reference Figure 1E , a dielectric material layer may be deposited on the uppermost conductive structure (e.g., the second conductive structure 32). The deposited dielectric material layer is referred to herein as a distal dielectric material layer or a third dielectric material layer 40 (in embodiments where the deposited dielectric material layer is formed on the second conductive structure 32). In one embodiment, the deposited dielectric material layer may be a silicon oxide layer having a thickness ranging from 100 nm to 1,000 nm.

[0053] A substrate may be formed on the top surface of the third dielectric material layer 40, or a substrate may be bonded to the top surface of the third dielectric material layer 40. The bonded substrate may be a handle substrate, which is subsequently used to provide mechanical support for the underlying material layers including the matrix material layer 10L, the first dielectric material layer 20, the first conductive structure 22, the second dielectric material layer 30, the second conductive structure 32, and the third dielectric material layer 40. Considering that the matrix material layer is subsequently patterned into a movable element of a MEMS device, the bonded substrate is referred to herein as a MEMS substrate 50. Although smaller thicknesses and larger thicknesses may also be used, the thickness of the MEMS substrate 50 may be in the range of 30 microns to 3 mm, for example, 100 microns to 1 mm. The MEMS substrate 50 may be a semiconductor substrate, a conductive substrate, an insulating substrate, or a composite substrate including a plurality of layers. In one embodiment, the MEMS substrate 50 may be a semiconductor substrate such as a commercially available silicon substrate. The MEMS substrate 50 may be formed over the third dielectric material layer 40 or attached to the third dielectric material layer 40 , for example, using oxide-to-semiconductor bonding.

[0054] Reference Figure 1F , the matrix material layer 10L may be thinned to provide a thinned matrix material layer 10T. Although smaller thicknesses and larger thicknesses may also be used, the thickness of the thinned matrix material layer 10T may be in the range of 100 nm to 10 microns, for example, 300 nm to 5 microns. In one embodiment, the thinning of the matrix material layer 10L may be performed by grinding, polishing, an isotropic etching process, an anisotropic etching process, or a combination thereof. In an embodiment in which a hydrogen planting layer may be provided within the matrix material layer 10L, a cleaving process may be used to remove a distal portion of the matrix material layer 10L that is further away from the MEMS substrate 50 than the hydrogen planting layer. For the cleaving process, annealing may be performed at a high temperature process in the range of 500 degrees Celsius to 600 degrees Celsius to induce bubbling of hydrogen atoms at the level of the hydrogen planting layer within the matrix material layer 10L. Subsequently, the exemplary structure may be flipped so that the thinned matrix material layer 10T faces upward and the MEMS substrate 50 faces downward.

[0055] Reference Figure 1G, a bonding material may be deposited on the top surface of the thinned matrix material layer 10T to form a bonding dielectric layer, which is referred to herein as a matrix-side bonding dielectric layer 62. The bonding material of the matrix-side bonding dielectric layer 62 may include silicon oxide, a polymer material, or a dielectric adhesive material. In one embodiment, the matrix-side bonding dielectric layer 62 includes silicon oxide and has a thickness ranging from 100 nm to 1,000 nm, although smaller thicknesses and larger thicknesses may also be used. The matrix-side bonding dielectric layer 62 may be patterned to form openings, which may be in areas (e.g., regions 101 and 102) where movable elements are subsequently patterned from the thinned matrix material layer 10T and in areas where etchant access holes are subsequently formed through the thinned matrix material layer 10T.

[0056] Reference Figure 1H , a photoresist layer (not shown) may be applied over the thinned matrix material layer 10T and the matrix-side bonding dielectric layer 52, and the photoresist layer may be patterned photolithographically to form openings in regions defining gaps 19 between the movable element to be subsequently patterned out of the thinned matrix material layer 10T and the matrix layer. In other words, the pattern of the openings in the photoresist layer may include a pattern of gaps 19 between the movable element to be subsequently patterned out of the thinned matrix material layer 10T and the matrix layer. Furthermore, the pattern of the openings in the photoresist layer may include a pattern of etchant-reached holes to be subsequently formed through the thinned matrix material layer 10T.

[0057] An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the thinned matrix material layer 10T. The thinned matrix material layer 10T may be divided into a plurality of portions, the plurality of portions including the movable elements (movable elements 10a, movable elements 10b) and the matrix layer 10 surrounding each of the movable elements (movable elements 10a, movable elements 10b) in the lateral direction. In general, the movable elements (movable elements 10a, movable elements 10b) may include any element capable of bending, vibrating, deforming, shifting, rotating, twisting and other types of changes in shape, position and / or orientation. In an illustrative example, the movable elements (movable elements 10a, movable elements 10b) may include a first movable element 10a used in an accelerometer and a second movable element 10b used in a gyroscope. Additional movable elements (not shown) may be patterned out of the thinned matrix material layer 10T. The remaining continuous portion of the thinned matrix material layer 10T that surrounds each of the movable elements (movable elements 10a, 10b) in the lateral direction constitutes a fixed portion of the MEMS device, and the relative movement of the movable elements (movable elements 10a, 10b) relative to the fixed portion can be measured. The remaining fixed portion of the MEMS device is referred to as the matrix layer 10 in this article. The movable elements (movable elements 10a, 10b) and the matrix layer 10 may include the same material. In one embodiment, the movable elements (movable elements 10a, 10b) and the matrix layer 10 may include the same semiconductor material, which is referred to as the first semiconductor material in this article. A subset and / or portion of the movable elements (movable elements 10a, 10b) may be doped with a p-type dopant and / or an n-type dopant as needed. A gap 19 extending downward to the first dielectric material layer 20 may be formed between the matrix layer 10 and the various movable elements (the movable element 10 a , the movable element 10 b ).

[0058] Reference Fig. 1I, the movable elements (movable elements 10a, 10b) can be detached from the first dielectric material layer 20 by removing portions of the first dielectric material layer 20, the portions of the first dielectric material layer 20 being connected to the surrounding environment via gaps 19 extending vertically between the matrix layer 10 and the various movable elements (movable elements 10a, 10b). An isotropic etchant can be applied into the gaps 19 to remove the portions of the first dielectric material layer 20 connected to the gaps 19, the isotropic etchant etching the material of the first dielectric material layer 20 selective to the materials of the matrix layer 10, the movable elements (movable elements 10a, 10b), the matrix-side bonding dielectric layer 62, the first conductive structure 22, and the uppermost sublayer (which may be an etch stop dielectric layer) within the second dielectric material layer 30. For example, the first dielectric material layer 20 may include borosilicate glass, organosilicate glass, porous low-k dielectric material, or a polymer material dissolved in an organic solvent, the matrix-side bonding dielectric layer 62 may include densified undoped silicate glass, and the uppermost sublayer of the second dielectric material layer 30 may include silicon nitride or aluminum oxide. A cavity 29 extending in the lateral direction may be formed under the movable element (movable element 10a, movable element 10b) to detach the movable element (movable element 10a, movable element 10b) from the underlying structure (e.g., the first conductive structure 22, the first dielectric material layer 20, etc.). A MEMS assembly is provided, which may include a MEMS substrate 50, a conductive structure (a first conductive structure 22, a second conductive structure 32) formed on a dielectric material layer (a first dielectric material layer 20, a second dielectric material layer 30, a third dielectric material layer 40) or in the dielectric material layer (a first dielectric material layer 20, a second dielectric material layer 30, a third dielectric material layer 40) and overlying the MEMS substrate 50, and a combination of a matrix layer 10 and movable elements (a movable element 10a, a movable element 10b) enclosed in the MEMS assembly and overlying the dielectric material layer (a first dielectric material layer 20, a second dielectric material layer 30, a third dielectric material layer 40). In general, at least one movable element (a movable element 10a, a movable element 10b) may be laterally defined in the matrix layer 10 located on the MEMS substrate 50, and a patterned matrix-side bonding dielectric layer 62 may be located on the top surface of the matrix layer 10.

[0059] Reference Figure 2A, a first exemplary structure for forming a top cover structure is shown. The first exemplary structure includes a substrate, which is referred to as a top cover substrate 70 in this article. The top cover substrate 70 may include a semiconductor material, an insulating material and / or a conductive material. In one embodiment, the top cover substrate 70 may include a semiconductor material, which is referred to as a second semiconductor material in this article. For example, the top cover substrate 70 may include a silicon substrate. Although smaller thicknesses and larger thicknesses may also be used, the thickness of the top cover substrate 70 may be in the range of 60 microns to 1 mm. In one embodiment, a complementary metal oxide semiconductor (CMOS) device such as a field effect transistor (not shown) may be provided on the back side of the top cover substrate 70.

[0060] The top cover substrate 70 may have Fig. 1I The top cover substrate 70 may include a first device region 201, a second device region 202, and an optional additional device region (not shown). The first device region 201 of the top cover substrate 70 may have a mirror image pattern of the patterns of the various device regions (first device region 101, second device region 102) of the MEMS assembly shown in FIG. Fig. 1I The first device region 101 of the MEMS assembly shown in FIG. 1 may have a mirror image shape, and the second device region 202 of the cap substrate 70 may have a Fig. 1I A mirror image shape of the second device region 102 of the MEMS assembly is shown.

[0061] A photoresist layer 77 may be applied over the top surface of the cap substrate 70. The photoresist layer 77 may then be patterned photolithographically to form openings therethrough. One of the openings in the photoresist layer 77 may be formed at Fig. 1I In the mirror image area of ​​the area of ​​the first movable element 10a in the MEMS assembly shown. An etching process may be performed to recess the portion of the top surface of the top cover substrate 70 that is not covered by the photoresist layer 77. For example, an anisotropic etching process may be performed to recess the portion of the top surface of the top cover substrate 70 that is located in the area not covered by the photoresist layer 77 in the vertical direction. A first recessed area 71a may be formed in the area of ​​the first device region 201 that is located on the front side of the top cover substrate 70. A horizontal recessed surface may be formed below the volume of the first recessed area 71a. Although smaller vertical offset distances and larger vertical offset distances may also be used, the vertical offset distance (which is the vertical recessed distance) between the horizontal recessed surface of the first recessed area 71a and the uppermost surface of the top cover substrate 70 may be in the range of 300nm to 6 microns, for example, 600nm to 3 microns. Subsequently, the photoresist layer 77 may be removed, for example, by ashing.

[0062] Reference Figure 2B, a bonding material may be deposited on the top side of the cap substrate 70 to form a bonding dielectric layer, which is referred to herein as a cap-side bonding dielectric layer 72. The bonding material of the cap-side bonding dielectric layer 72 may include silicon oxide, a polymer material, or a dielectric adhesive material. In one embodiment, the cap-side bonding dielectric layer 72 may include the same bonding material as the matrix-side bonding dielectric layer 62. In one embodiment, although a smaller thickness and a larger thickness may also be used, the cap-side bonding dielectric layer 72 may include silicon oxide and the thickness may be within the range of 100nm to 1,000nm. The cap-side bonding dielectric layer 72 may be deposited conformally or non-conformally. For example, the cap-side bonding dielectric layer 72 may include undoped silicate glass formed by the decomposition of tetraethyl orthosilicate. The cap-side bonding dielectric layer 72 may be formed on the uppermost (non-depressed) surface and the depressed surface of the cap substrate 70.

[0063] Reference Figure 2C , a photoresist layer 78 may be applied over the top cover side bonding dielectric layer 72, and the photoresist layer 78 may be patterned photolithographically to form an array of openings 73 passing therethrough. In different embodiments, the array of openings 73 in the photoresist layer 78 may have a periodic line and space pattern, two periodic line and space patterns that intersect each other to form intersections, or a two-dimensional periodic array with discrete openings. If the two periodic line and space patterns intersect each other, the line pattern in the length direction may be perpendicular to each other between the first periodic line and space pattern and the second periodic line and space pattern. Although smaller and larger sizes may also be used, the width of each opening may be in the range of 30nm to 600nm, and the width of each space may be in the range of 30nm to 1,200nm. An etching process such as a first anisotropic etching process may be implemented to transfer the pattern in the photoresist layer 78 via the top cover side bonding dielectric layer 72.

[0064] Reference Figure 2D , Figure 2E , Figure 2F and Figure 2G, the pattern of the opening 73 in the top cover side bonding dielectric layer can be transferred to the underlying portion of the top cover substrate 70 by a second anisotropic etching process. The second anisotropic etching process can use a photoresist layer 78 as an etching mask layer. In one embodiment, during the second anisotropic etching process, the photoresist layer 78 may be consumed, and the top cover side bonding dielectric layer 72 can be used as an etching mask layer. In another embodiment, the photoresist layer 78 can be removed, for example, by ashing, and the top cover side bonding dielectric layer 72 can be used as an etching mask layer. An array of grooves 75 can be formed under the array of openings via the top cover side bonding dielectric layer 72. The grooves 75 can be formed under the openings via the top cover side bonding dielectric layer 72, and the pattern of the openings in the top cover side bonding dielectric layer 72 is repeated. The depth of the groove 75 as measured between the top surface of the cap-side bonding dielectric layer 72 in the first recessed area 71a and the bottommost surface of the groove 75 may be in the range of 200nm to 4,000nm. The depth of the groove 75 may be optimized to balance the manufacturing cost and the degassing capability. For example, if the depth of the groove 75 exceeds 4,000nm, the duration of the anisotropic etching process may be significantly extended, and the processing cost of the anisotropic etching step may become uneconomically high. If the depth of the groove 75 is less than 200nm, the volume of the outgassing material that may be provided in the groove 75 may not be sufficient to provide sufficient outgassing, and the pressure inside the cavity may be unacceptably low even after outgassing.

[0065] The groove 75 may extend through the cap side bonding dielectric layer 72 into the cap substrate 70 within the first recessed region 71a. The groove 75 may be formed as Figure 2F or a one-dimensional array as shown in Figure 2G In a one-dimensional array, a unit pattern (e.g., a pattern of a single groove 75) is repeated in one direction, while in a two-dimensional array, a unit pattern (e.g., a pattern of intersections formed by two perpendicular grooves 75) is repeated in two directions.

[0066] Reference Figure 2H , Fig.2I , Figure 2J and Figure 2K, the bump-containing material layer 82 may be deposited by a non-conformal deposition process. The bump-containing material layer 82 includes an array of bumps as will be described below. The bump-containing material layer 82 may include a buffer material, the buffer material including at least one of a semiconductor material and an outgassing dielectric material. The buffer material may be composed of a semiconductor material, may be composed of an outgassing dielectric material, or may include a combination of a semiconductor material and an outgassing dielectric material. In one embodiment, the bump-containing material layer 82 may include and / or consist essentially of amorphous silicon, which may be undoped amorphous silicon or doped amorphous silicon. Alternatively, or additionally, the bump-containing material layer 82 may include and / or consist essentially of an outgassing dielectric material. The outgassing dielectric material may include undoped silicate glass, doped silicate glass, or a combination thereof. In the case where the bump-containing material layer 82 includes an outgassing dielectric material, the gas may be trapped in the bump-containing material layer 82 during the deposition of the bump-containing material layer 82 and may subsequently be released into a vacuum cavity (e.g., a first cavity to be subsequently formed to contain the bump-containing material layer 82). Fig. 1I In the first movable element 10a shown in . In an illustrative example, the bump-containing material layer 82 may include undoped silicate glass formed by plasma decomposition of tetraethyl orthosilicate. Alternatively, the bump-containing material layer 82 may include silicon oxynitride or other suitable dielectric outgassing materials. In one embodiment, the bump-containing material layer 82 may be deposited at a temperature not higher than about 500 degrees Celsius. For example, the bump-containing material layer 82 may be deposited in a plasma enhanced chemical vapor deposition (PECVD) process. The deposition temperature may be in the range of about 300 degrees Celsius to about 500 degrees Celsius, and silane, disilane, tetraethyl orthosilicate or other suitable precursor gases for buffer materials may be decomposed in a plasma environment. The thickness of the bump-containing material layer 82 on a flat horizontal surface may be in the range of 30nm to 600nm, for example 600nm to 300nm. Generally, the thickness of the bump-containing material layer 82 may be greater than half the width of the groove 75, and the thickness of the bump-containing material layer 82 is selected to maintain topographical changes (bumps) that are caused by forming a seal over the groove 75. In this case, the thickness of the bump-containing material layer 82 may be less than the width of the groove 75. In the case where the width of the groove 75 is in the range of 60 nm to 600 nm, the thickness of the bump-containing material layer 82 may be greater than half the width of the groove 75 (e.g., greater than 30 nm) and may be less than four times the width of the groove 75 (e.g., less than 600 nm).

[0067] A bump-containing material layer 82 may be formed over the cap-side bonding dielectric layer 72. The non-conformal nature of the deposition process for forming the bump-containing material layer 82 causes voids 79 to form within the trench 85. Specifically, the non-conformal deposition process may deposit a buffer material of the bump-containing material layer 82 on the sidewalls of the trench 75, thereby lining the sidewalls of the trench 75 with the buffer material. When the buffer material of the bump-containing material layer 82 accumulates at a higher deposition rate at the upper periphery of the trench 75 than at the bottom of the trench 75 during the non-conformal deposition process, pinch-off may occur at the top of each trench 75. Therefore, the non-conformal deposition process forms voids 79 in the volume of the trench 75 that is not filled with the buffer material.

[0068] In addition, the deposited buffer material is clamped at the top portion of the groove 75, which causes the top surface of the bump-containing material layer 82 to be locally convex, thereby forming a hillock or a bump. Therefore, the portion of the bump-containing material layer 82 overlying the groove 75 forms an array of multiple bumps 82B protruding upward. In general, the bump-containing material layer 82 can be formed by a non-conformal deposition process, which forms each of the multiple bumps 82B protruding upward to have a hillock-shaped vertical cross-sectional profile. Each of the multiple bumps 82B protruding upward overlies a corresponding gap 79 in the multiple gaps 79. The vertical distance between the uppermost surface of the multiple bumps 82B protruding upward and the horizontal plane can be in the range of 105% to 150% of the thickness of the horizontal extension portion of the bump-containing material layer 82, for example, 31.5nm to 900nm, and the horizontal plane includes the interface between the top cover side bonding dielectric layer 72 and the horizontal extension portion of the bump-containing material layer 82.

[0069] In one embodiment, the plurality of protruding bumps 82B may have a hill-shaped vertical cross-sectional profile. The first device region 201 of the cap substrate 70 may have a vertically recessed horizontal surface that is offset upward from the uppermost horizontal surface of the cap substrate 70 in the vertical direction. The groove 75 extends downward from the vertically recessed horizontal surface of the cap substrate 70 into the cap substrate 70 in the vertical direction, and is located under the corresponding protruding bump 82B in the plurality of protruding bumps 82B. The gap 79 in the groove 75 may not have any solid phase material or any liquid phase material. The gap 79 may be included in the sidewall of the groove 75, and may be located under the corresponding protruding bump 82B. The surface of the groove 75 may be lined with a buffer material containing a bump material layer 82. Each of the plurality of gaps 79 includes an encapsulated cavity, which is defined by a corresponding continuous surface of the buffer material containing a bump material layer 82 without any holes passing therethrough.

[0070] Reference Figure 2L, the top horizontal portion of the bump-containing material layer 82 may be removed from above the horizontal top surface of the cap-side bonding dielectric layer 72. For example, a chemical mechanical planarization process may be performed to remove the horizontal portion of the bump-containing material layer 82 overlying the cap-side bonding dielectric layer 72. The remaining portion of the bump-containing material layer 82 may be laterally confined within the perimeter of the first recessed region 71a.

[0071] Reference Figure 2M , a first etch mask layer 92 may be formed over the bump material layer 82 and the cap side bonding dielectric layer 72. The first etch mask layer 92 may include a hard mask material such as silicon nitride or a dielectric metal oxide. The first etch mask layer 92 may be patterned to form an opening in the second device region 202. An etching process such as an isotropic etching process or an anisotropic etching process may be performed to etch through the cap side bonding dielectric layer 72, the physically exposed portion located below the opening of the first etch mask layer 92. Thus, an opening 91 through the cap side bonding dielectric layer 72 may be formed in the second device region 202.

[0072] Reference Figure 2N , a second etch mask layer 93 may be formed to cover a small portion of the area of ​​the opening 91 through the top cover side bonding dielectric layer 72. The second etch mask layer 93 may be a patterned hard mask layer, or may be a patterned soft mask layer (e.g., a patterned photoresist layer). In one embodiment, the second etch mask layer 93 may cover the central area of ​​the opening in the top cover side bonding dielectric layer 72 in the second device region 202. A recessed area may be formed by recessing the unmasked portion of the top cover substrate 70 in the vertical direction by an anisotropic etching process, the unmasked portion not covered by the first etch mask layer 92 or not covered by the second etch mask layer 93, the recessed area being referred to herein as an in-process recessed area 81. An "in-process" element refers to an element that is subsequently modified. Subsequently, the second etch mask layer 93 may be selectively removed relative to the first etch mask layer 92.

[0073] Reference Fig.2O , an anisotropic etching process may be performed to vertically recess the portion of the cap substrate 70 that is not covered by the first etch mask layer 92. A second recessed region 71 b may be formed in the region of the opening 91 that passes through the cap-side bonding dielectric layer 72. Subsequently, the first etch mask layer 92 may be selectively removed relative to the cap-side bonding dielectric layer 72 and the bump-containing material layer 82.

[0074] The second recessed area 71b (if provided) is an additional recessed area that can be formed adjacent to the first recessed area 71a. The second recessed area 71b includes an additional upwardly protruding bump that protrudes upward from the recessed surface of the second recessed area 71b. The recessed surface of the second recessed area 71b may be located within the area of ​​the recessed area 81 being processed, and the additional upwardly protruding bump may be laterally surrounded by the area of ​​the recessed surface of the second recessed area 71b. In one embodiment, the top surface of the additional upwardly protruding bump includes a flat horizontal surface of the top cover substrate 70 that is recessed in the vertical direction relative to the uppermost surface of the top cover substrate 70. The recessed depth of the top surface of the additional upwardly protruding bump may be 1000 mm / s. Fig.2O The vertical etching distance of the anisotropic etching process at the processing step shown. Fig. 1I When the MEMS assembly shown is bonded to form a chamber, the top surface of the additional upwardly projecting bump can serve as a capping surface that terminates, for example, Fig. 1I The vertical movement of the movable element such as the second movable element 10 b shown in FIG.

[0075] Reference Figure 3 , you can Fig.2O The first exemplary structure shown is joined to Fig. 1I The MEMS assembly is shown to form a first exemplary micro-electromechanical system (MEMS) device 300. In this illustrated embodiment, the top cover substrate 70 can be bonded to the matrix layer 10 so that the front side of the top cover substrate 70 (i.e., the upper side as shown in FIG. 2O) faces the matrix layer 10 (effectively Fig.2O In one embodiment, the top cover substrate 70 may be bonded to the matrix layer 10 by bonding the matrix side bonding dielectric layer 62 to the top cover side bonding dielectric layer 72. The matrix side bonding dielectric layer 62 may be located on the top surface of the matrix layer 10. The top cover side bonding dielectric layer 72 extends below the bottom surface of the top cover substrate 70 and may be bonded to the matrix side bonding dielectric layer 62.

[0076] A first chamber 109 including a first movable element 10a may be formed by the matrix layer 10 and the top cover substrate 70. The first chamber 109 includes a first head volume 57a overlying the first movable element 10a. Figure 2H-2K The surface of the array of upwardly projecting bumps 192B formed at the process step shown provides a first top cover surface over the first movable element 10a in the first chamber 109. Figure 3 The processing steps are shown upside down, so Figure 2H-2K The array of upwardly projecting bumps 82B formed at the processing step shown becomes Figure 3An array of downwardly protruding bumps within the first exemplary MEMS device 300 shown. The first chamber 109 may be bounded in the lateral direction by the matrix layer 10 and may be bounded in the vertical direction by the first cap surface overlying the first movable element 10a. The first cap surface includes an array of upwardly protruding bumps 82B, which include corresponding portions of the bump-containing material layer 82. The vertically concave horizontal surface within the first device region 201 becomes a vertically convex horizontal surface 70S. The upwardly protruding bumps 82B become downwardly protruding bumps 82B. The grooves 75 become inverted grooves 75. The first MEMS device 100 includes the first movable element 10a, the first chamber 109, and the first cap surface. The first MEMS device 100 may form an accelerometer.

[0077] The second chamber 209 including the second movable element 10b can be formed by aligning the second recessed area 71b of the cap substrate 70 on the second movable element 10b during bonding the cap substrate 70 to the matrix layer 10. The second chamber 209 may include a second head volume 57b overlying the second movable element 10b. The second chamber 209 may be bounded in a vertical direction by a second cap surface overlying the second movable element 10b. The second cap surface may include a flat horizontal surface of the cap substrate 70 located within the second recessed area 71b. The second chamber 209 may be bounded in a vertical direction by a second cap surface overlying the second movable element 10b. The second MEMS device 200 includes the second movable element 10b, the second chamber 209, and the second cap surface. The MEMS device of the present invention may be a composite MEMS device including a first MEMS device 100 (which may include an accelerometer) and a second MEMS device 200 (which may include a gyroscope).

[0078] Reference Figure 4A A second exemplary structure for forming a top cover structure includes a top cover substrate 70, which can be connected to Figure 2A The top cover substrate 70 is the same as shown. A patterned hard mask layer 182 can be formed on the top surface of the top cover substrate 70. The patterned hard mask layer 182 can be formed by depositing a hard mask material such as silicon oxide, silicon nitride and / or a dielectric metal oxide and by patterning the deposited hard mask material. The deposited hard mask material can be patterned, for example, by applying a photoresist layer and patterning the photoresist layer and using an etching process to transfer the pattern in the photoresist layer (not shown) through the deposited hard mask material, and the etching process selectively etches the deposited hard mask material relative to the material of the top cover substrate 70. For example, an anisotropic etching process can be implemented to transfer the pattern in the photoresist layer through the deposited hard mask material. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0079] The plurality of openings in the patterned hard mask layer 182 may include a first opening formed in the first device region 201 and a second opening formed in the second device region 202. The first device region 201 of the cap substrate 70 may have Fig. 1I The first device region 101 of the MEMS assembly shown in FIG. 1 may have a mirror image shape, and the second device region 202 of the cap substrate 70 may have a Fig. 1I A mirror image shape of the second device region 102 of the MEMS assembly is shown.

[0080] Reference Figure 4B , a patterned etch mask layer 95 may be formed on the patterned hard mask layer 182 and on the front side of the cap substrate 70. The patterned etch mask layer 95 may be a patterned soft mask layer (e.g., a patterned photoresist layer). In one embodiment, the patterned etch mask layer 95 may include an array of openings 73 located in the first device region 201 and openings within the region of the openings in the patterned hard mask layer 182 located in the second device region 202. In various embodiments, the array of openings 73 in the patterned etch mask layer 95 located in the first device region 201 may have a periodic line and space pattern, two periodic line and space patterns that intersect each other to form intersections, or a two-dimensional periodic array with discrete openings. If the two periodic line and space patterns intersect each other, the linear patterns in the length direction may be perpendicular to each other between the first periodic line and space pattern and the second periodic line and space pattern. Each opening 73 may have a width ranging from 30 nm to 600 nm, and each space may have a width ranging from 30 nm to 1,200 nm, although smaller and larger sizes may also be used. The patterned etch mask layer 95 may cover the center area of ​​the opening in the patterned hard mask layer 182 in the second device region 202 .

[0081] Reference Figure 4CIn an embodiment, a first anisotropic etching process may be performed to etch portions of the cap substrate 70 that are not masked by the combination of the patterned etch mask layer 95 and the patterned hard mask layer 182. An array of first trenches 75a may be formed below the array of openings in the patterned etch mask layer 95. The depth of the first trench 75a as measured between the top surface of the cap substrate 70 and the lowermost surface of the first trench 75a may range from 200 nm to 4,000 nm, although smaller depths and greater depths may also be used. The depth of the first trench 75a may be optimized to balance manufacturing cost and degassing capability. For example, if the depth of the first trench 75a exceeds 4,000 nm, the duration of the anisotropic etching process may be significantly extended, and the processing cost of the anisotropic etching step may become uneconomically high. If the depth of the first groove 75a is less than 200nm, the volume of outgassing material that may be provided in the first groove 75a may not be sufficient to provide sufficient outgassing, and the pressure inside the cavity may be unacceptably low even after outgassing. The first grooves 75a may be formed in a one-dimensional array or a two-dimensional array. In an embodiment implementing a one-dimensional array, a unit pattern (e.g., a pattern of a single first groove) may be repeated in one direction, while in an embodiment implementing a two-dimensional array, a unit pattern (e.g., a pattern of intersections where two perpendicular first grooves intersect) is repeated in two directions.

[0082] The unmasked portion of the cap substrate 70 may be recessed in the vertical direction by the first anisotropic etching process to form a recessed region, which is not covered by the combination of the patterned etch mask layer 95 and the patterned hard mask layer 182 in the second device region 202, and is referred to herein as an in-process recessed region 81. Subsequently, the patterned etch mask layer 95 may be selectively removed relative to the patterned hard mask layer 182.

[0083] Reference Figure 4D , a second anisotropic etching process may be performed using the patterned hard mask layer 182 as an etching mask. The region of the cap substrate 70 including the first trench 75a may be anisotropically etched by the second anisotropic etching process and the region may be recessed in a vertical direction to form a first recessed region 71a. During the second anisotropic etching process, the first trench 75a may be further etched to form a second trench 75b extending downward from the recessed horizontal surface of the first recessed region 71a. The second trench 75b repeats the pattern of the first trench 75a and extends downward from the recessed horizontal surface of the first device region 201 in a vertical direction. The depth of the second trench 75b may be in the range of 200nm to 4,000nm, although smaller depths and larger depths may also be used.

[0084] The second anisotropic etching process causes the portion of the top cover substrate 70 in the second device region 202 that is not covered by the patterned hard mask layer 182 to be recessed in the vertical direction. A second recessed region 71b may be formed in the region of the opening of the patterned hard mask layer 182 overlying the recessed region 81 being processed. The second recessed region 71b (if provided) is an additional recessed region formed adjacent to the first recessed region 71a. The second recessed region 71b includes an upwardly protruding bump that protrudes upward from the recessed surface of the second recessed region 71b. The upwardly protruding bump may be surrounded in the lateral direction by the area of ​​the recessed surface of the second recessed region 71b. The recessed depth of the top surface of the upwardly protruding bump may be the vertical etching distance of the second anisotropic etching process. Subsequently, the patterned hard mask layer 182 may be selectively removed relative to the top cover substrate 70, for example, by a wet etching process.

[0085] Reference Figure 4E , Figure 4F , Figure 4G and Figure 4H , the bump-containing material layer 192 can be deposited by a non-conformal deposition process. The bump-containing material layer 192 includes a bonding material, which may include silicon oxide, a polymer material, or a dielectric adhesion material. In one embodiment, the bump-containing material layer 192 may include the same bonding material as the matrix-side bonding dielectric layer 62. In one embodiment, although smaller thicknesses and larger thicknesses may also be used, the bump-containing material layer 192 may include silicon oxide, and the vertical thickness is in the range of 30nm to 300nm, such as 60nm to 150nm. For example, the bump-containing material layer 192 may include undoped silicate glass formed by the decomposition of tetraethyl orthosilicate in a plasma enhanced chemical vapor deposition (PECVD) process as a non-conformal deposition process. The bump-containing material layer 192 may be formed on all physically exposed surfaces of the top cover substrate 70 located on the front side of the top cover substrate 70.

[0086] The non-conformal nature of the deposition process to form the bump-containing material layer 192 may cause voids 79 to form within the second trenches 75b. Specifically, the non-conformal deposition process may deposit the dielectric material of the bump-containing material layer 192 on the sidewalls of the second trenches 75b, such that the sidewalls of the second trenches 75b are lined with dielectric material. When the dielectric material of the bump-containing material layer 192 accumulates at a higher deposition rate at the upper periphery of the second trenches 75b than at the bottom of the second trenches 75b during the non-conformal deposition process, pinching may occur at the top of each second trench 75b. Thus, the non-conformal deposition process forms voids 79 in the volume of the second trenches 75b that is not filled with dielectric material.

[0087] In addition, the deposited dielectric material is clamped at the top portion of the second groove 75b, which causes the top surface of the bump-containing material layer 192 to be locally raised, thereby forming a hillock or bump. Therefore, the portion of the bump-containing material layer 192 that overlies the second groove 75b forms an array of a plurality of bumps 192B that protrude upward. Generally speaking, the bump-containing material layer 192 can be formed by a non-conformal deposition process that forms each of the plurality of bumps 192B that protrude upward to have a hillock-shaped vertical cross-sectional profile. Each of the plurality of bumps 192B that protrude upward overlies a corresponding void 79 in the void 79.

[0088] In one embodiment, the plurality of protruding bumps 192B may have a hill-shaped vertical cross-sectional profile. The first device region 201 of the cap substrate 70 may have a vertically recessed horizontal surface that is offset upward from the uppermost horizontal surface of the cap substrate 70 in the vertical direction. The second groove 75b extends downward from the vertically recessed horizontal surface of the cap substrate 70 into the cap substrate 70 in the vertical direction, and is located under the corresponding protruding bumps 192B in the plurality of protruding bumps 192B. The void 79 in the second groove 75b may not have any solid phase material or any liquid phase material. The void 79 may be included in the sidewall of the second groove 75b, and may be located under the corresponding protruding bumps 192B. The surface of the second groove 75b may be lined with a dielectric material containing a bump material layer 192. Each of the plurality of voids 79 includes an encapsulated cavity, which is defined by a corresponding continuous surface of the dielectric material containing the bump material layer 192 without any holes passing therethrough.

[0089] Reference Figure 5 , you can Figure 4E-4H The second exemplary structure shown is joined to Fig. 1I 4E ) to form a second exemplary microelectromechanical system (MEMS) device 400. In this case, the top cover substrate 70 can be bonded to the matrix layer 10 so that the front side (i.e., the upper side as shown in FIG. 4E ) of the top cover substrate 70 faces the matrix layer 10. In one embodiment, the top cover substrate 70 can be bonded to the matrix layer 10 by bonding the matrix side bonding dielectric layer 62 to the bump-containing material layer 192. The matrix side bonding dielectric layer 62 can be located on the top surface of the matrix layer 10. The bump-containing material layer 192 extends below the bottom surface of the top cover substrate 70 and can be bonded to the matrix side bonding dielectric layer 62.

[0090] A first chamber 109 including a first movable element 10a may be formed by the matrix layer 10 and the top cover substrate 70. The first chamber 109 includes a first head volume 57a overlying the first movable element 10a. Figure 4E-4HThe surface of the array of upwardly projecting bumps 192B formed at the process step shown provides a first top cover surface over the first movable element 10a in the first chamber 109. Figure 5 The processing steps are shown upside down, so Figure 4E-4H The array of upwardly projecting bumps 192B formed at the processing step shown becomes Figure 5 Array of downwardly protruding bumps in the second exemplary MEMS device 400 shown. The first chamber 109 may be bounded in the lateral direction by the matrix layer 10 and may be bounded in the vertical direction by the first cap surface overlying the first movable element 10a. The first cap surface includes an array of upwardly protruding bumps 192B, which include corresponding portions of the dielectric material layer (which may be the bump-containing material layer 192). The vertically concave horizontal surface in the first device region 201 becomes a vertically convex horizontal surface 70S. The upwardly protruding bumps 192B become downwardly protruding bumps 192B. The second groove 75b becomes an inverted groove 75. The first MEMS device 100 includes the first movable element 10a, the first chamber 109, and the first cap surface.

[0091] The second chamber 209 including the second movable element 10b can be formed by aligning the second recessed area 71b of the top cover substrate 70 on the second movable element 10b during bonding the top cover substrate 70 to the matrix layer 10. The second chamber 209 includes a second head volume 57b overlying the second movable element 10b. The second chamber 209 can be bounded in the vertical direction by a second top cover surface overlying the second movable element 10b. The second top cover surface may include a flat (horizontal) bottom surface of the bump material layer 192 located in the second recessed area 71b and offset upward from the lowermost surface of the top cover substrate 70 in the vertical direction. The second chamber 209 can be bounded in the vertical direction by a second top cover surface overlying the second movable element 10b. The second MEMS device 200 includes a second movable element 10b, a second chamber 209, and a second top cover surface. The MEMS device of the present invention may be a composite MEMS device 400 including a first MEMS device 100 (which may include an accelerometer) and a second MEMS device 200 (which may include a gyroscope).

[0092] Figure 6 6 is a process flow diagram illustrating the operations of a method 600 for forming a MEMS device 300. The MEMS device 300 may include a first MEMS device 100 and / or a second MEMS device 200, and may optionally include additional MEMS devices disposed on the same MEMS substrate 50. In step 610, the MEMS device 300 may be formed according to the reference Figure 1A-1IThe process steps shown and described in more detail above form at least one movable element (movable element 10a, movable element 10b) in the matrix layer 10 overlying the MEMS substrate 50. The at least one movable element (movable element 10a, movable element 10b) can be formed first and arranged aside, or with Figure 2A-Figure 2O The top cover structure shown in FIG. is formed simultaneously or Figure 2A-Figure 2O The top cover structure shown in is then formed. Figure 6 The top cover structure is shown to be formed in steps 620-660, however, a person of ordinary skill in the art will recognize that various embodiments may implement the disclosed steps in various orders. In step 620, a first recessed area 71a may be formed on the front side of the top cover substrate 70. In step 630, a top cover side bonding dielectric layer 72 may be formed on the uppermost surface of the top cover substrate 70 and in the first recessed area 71a of the top cover substrate 70. In step 640, a groove 75 extending through the top cover side bonding dielectric layer 72 into the top cover substrate 70 may be formed in the area of ​​the first recessed area. In step 650, a bump material layer 82 may be formed on the top cover side bonding dielectric layer 72. As described above with reference to Figure 2A-Figure 2O As discussed, the portion of the bump-containing material layer 82 overlying the groove 75 may form an array of a plurality of bumps 82B protruding upward. In addition, the bump-containing material layer 82 may be formed by a non-conformal deposition process that forms each of the plurality of bumps 82B protruding upward to have a mound-shaped vertical cross-sectional profile. In some embodiments, the non-conformal deposition process may deposit the buffer material of the bump-containing material layer 82 on the sidewalls of the groove 75, so that the sidewalls of the groove are lined with the buffer material, and voids 79 are formed in the volume of the groove 75 that is not filled with the buffer material. Each of the plurality of bumps 82B protruding upward overlies a corresponding void in the plurality of voids.

[0093] In step 670, the top cover substrate 70 can be bonded to the matrix layer 10 so that the front side of the top cover substrate 70 faces the matrix layer 10, and a first chamber 109 including a first movable element 10a (which is one of the at least one movable element (movable element 10a, movable element 10b)) is formed by the matrix layer 10 and the top cover substrate 70, wherein after being placed upside down on the first movable element 10a during bonding, the surface of the array of upward protruding bumps 82B provides a first top cover surface within the first chamber 109.

[0094] Figure 7is a process flow diagram illustrating the operations of another embodiment method 700 of forming a MEMS device 400. The MEMS device 400 may include a first MEMS device 100 and / or a second MEMS device 200, and may optionally include additional MEMS devices disposed on the same MEMS substrate 50. In step 610, the MEMS device 400 may be formed according to the reference Figure 1A-1I The process steps shown and described in more detail above form at least one movable element (eg, movable element 10a) within the matrix layer 10 overlying the MEMS substrate 50. Figure 1A-1I The process steps shown and described in more detail above form at least a second movable element (e.g., movable element 10b) within the matrix layer 10 overlying the MEMS substrate 50. A matrix-side bonding dielectric layer 62 located at the top surface of the matrix layer may be formed. The at least first and second movable elements (e.g., movable elements 10a, 10b) may be formed first and positioned alongside, simultaneously with, or after the cap structure.

[0095] although Figure 7The top cover structure is shown to be formed in steps 720-750, however, a person skilled in the art will recognize that various embodiments can implement the disclosed steps in various orders. In step 720, a first groove 75a can be formed on the front side of the top cover substrate 70. Optionally, in step 720, a processing recessed area 81 can be optionally formed. In step 730, a first recessed area 71a can be formed by recessing the area of ​​the top cover substrate 70 including the first groove 75a in the vertical direction, and the first recessed area 71a has a second groove 75b extending downward therefrom. A recessed horizontal surface can be formed in the first recessed area 71a of the top cover substrate 70. The second groove 75B repeating the pattern of the first groove 75a extends downward from the recessed horizontal surface in the vertical direction. A second recessed area 71b can be optionally formed. In step 740, a bump-containing material layer 192 is formed on the uppermost surface of the top cover substrate 70 and in the first recessed area 71a of the top cover substrate 70. If the second recessed area 71b is provided, a bump-containing material layer 192 is formed on all surfaces of the second recessed area 71b. The portion of the bump-containing material layer 192 overlying the second groove 75b has an array of a plurality of bumps 192B protruding upward. In step 750, the top cover substrate 70 is bonded to the matrix layer 10 so that the front side of the top cover substrate 70 faces the matrix layer 10, and a first chamber 109 including a first movable element 10a selected from the at least one movable element (movable element 10a, movable element 10b) is formed by the matrix layer 10 and the top cover substrate 70, wherein the surface of the array of bumps 192B protruding upward provides a first top cover surface in the first chamber 109 after being placed upside down on the first movable element 10a during bonding.

[0096] Referring to all the drawings and according to various embodiments of the present invention, there is provided a micro-electromechanical system (MEMS) device, the MEMS device comprising: a MEMS substrate 50; at least one movable element (a movable element 10a, a movable element 10b) defined laterally on a MEMS substrate 50; within the matrix layer 10 above the substrate 50; and a top cover substrate 70, bonded to the matrix layer 10, wherein a first movable element 10a selected from the at least one movable element (movable element 10a, movable element 10b) may be located inside the first chamber 109, the first chamber 109 may be bounded laterally by the matrix layer 10 and vertically by a first top cover surface overlying the first movable element 10a, and wherein the first top cover surface includes an array of multiple downwardly protruding bumps (bumps 82B or bumps 192B), the multiple downwardly protruding bumps (bumps 82B or bumps 192B) include corresponding portions of a bump-containing material layer (bump material layer 82 or bump material layer 192), and the bump-containing material layer (bump material layer 82 or bump material layer 192) may be a bump-containing material layer 82 or a bump-containing material layer 192.

[0097] In one embodiment, each of a plurality of downwardly protruding bumps (bumps 82B or bumps 192B) may have an inverted vertical cross-sectional profile. In one embodiment, the top cover substrate 70 may include a vertically protruding horizontal surface 70S, which is overlaid on the first chamber 109 and is offset upward from the proximal horizontal surface of the top cover substrate 70 in the vertical direction. The proximal horizontal surface of the top cover substrate 70 is overlaid on the matrix layer 10, and is the surface closest to the matrix layer 10 selected from all surfaces of the top cover substrate 70. The proximal surface of the element used herein refers to the surface of the element closest to the interface between the matrix side bonding dielectric layer 62 and the bump-containing material layer (bump-containing material layer 82 or bump-containing material layer 192). The distal surface of the element used herein refers to the surface of the element farthest from the interface between the matrix side bonding dielectric layer 62 and the bump-containing material layer (82 or 192).

[0098] In one embodiment, the MEMS device includes a plurality of inverted trenches (trench 75 or trench 75b), which extend upward from the vertically raised horizontal surface 70S of the top cover substrate 70 into the top cover substrate 70 in the vertical direction, and overlie a corresponding one of the plurality of downwardly protruding bumps (bump 82B or bump 192B). In one embodiment, the MEMS device includes a plurality of voids 79, which do not have any solid phase material or any liquid phase material, and are contained within a plurality of sidewalls of the inverted trenches (trench 75 or trench 75b) and overlie the corresponding downwardly protruding bumps (bump 82B or bump 192B). In one embodiment, the surface of the inverted groove (75 or 75b) is lined with material of a bump material layer (bump material layer 82 or bump material layer 192), and each of the plurality of voids 79 includes an enclosed cavity defined by a corresponding continuous surface of the material of the bump material layer (bump material layer 82 or bump material layer 192) without a hole passing therethrough.

[0099] In one embodiment, the MEMS device includes a matrix-side bonding dielectric layer 62 located on the top surface of the matrix layer 10. The bump-containing material layer (e.g., bump-containing material layer 192) extends below the bottom surface of the top cover substrate 70 and is bonded to the matrix-side bonding dielectric layer 62. In one embodiment, the at least one movable element (movable element 10a, movable element 10b) includes a second movable element 10b located inside a second chamber 209, and the second chamber 209 is bounded in a vertical direction by a second top cover surface overlying the second movable element 10b. The second top cover surface includes a portion of the bump-containing material layer (e.g., bump-containing material layer 192) and has a flat bottom surface.

[0100] In one embodiment, the matrix-side bonding dielectric layer 62 is located on the top surface of the matrix layer 10. The top cover side bonding dielectric layer 72 may be located between the bump-containing material layer (e.g., the bump-containing material layer 82) and the vertically raised horizontal surface 70S of the top cover substrate 70, may extend below the bottom surface of the top cover substrate 70, and may be bonded to the matrix-side bonding dielectric layer 62.

[0101] In one embodiment, the array of the plurality of downwardly protruding bumps (bumps 82B or bumps 192B) comprises a one-dimensional array or a two-dimensional array. The at least one movable element (movable element 10a, movable element 10b) and the matrix layer 10 comprise a first semiconductor material, and the cap substrate 70 comprises a second semiconductor material.

[0102] In one embodiment, the device including the first movable element 10a, the first cavity 109 and the array of multiple downwardly protruding bumps (bumps 82B, bumps 192B) comprises an accelerometer. The device including the second movable element 10b, the second cavity 209 and the second top cover surface comprises a gyroscope.

[0103] The array of downwardly protruding bumps (bumps 82B or bumps 192B) serves as a first top cover surface of the first movable element, and the first top cover surface serves as a termination surface of the first movable element 10a. For example, during over-acceleration, the array of downwardly protruding bumps (bumps 82B or bumps 192B) can be advantageously used to reduce the contact area when the first movable element 10a hits the first top cover surface. In other words, if the first movable element 10a hits the first top cover surface of the top cover substrate, the downwardly protruding bumps (bumps 82B or bumps 192B) provide a reduced contact area of ​​the first movable element 10a. The reduction in the contact area between the first movable element 10a and the top cover surface reduces the probability that the first movable element 10a sticks to the top cover substrate when it hits. By suppressing the first movable element 10a from sticking when in contact with the top cover substrate, the reliability and accuracy of a MEMS device (e.g., an accelerometer) including the first movable element 10a can be enhanced. Furthermore, if the bump-containing material layer 192 is used, the second top cover surface of the second MEMS device (eg, gyroscope) can provide a smaller contact surface with the second movable element 10 b to improve the reliability and accuracy of the second MEMS device.

[0104] In one embodiment, an environment at atmospheric pressure or at a pressure higher than atmospheric pressure may be employed during bonding of the MEMS substrate 50 to the cap substrate 70 via the bonding dielectric layer (bonding dielectric layer 62, bonding dielectric layer 72, or bump-containing material layer 192). A nitrogen environment or another inert environment may be employed during bonding of the MEMS substrate 50 to the cap substrate 70. If the bump-containing material layer 82 includes an outgassing material, the gas released from the bump-containing material layer 82 during or after bonding of the MEMS substrate 50 to the cap substrate 70 may increase the pressure in the first chamber 109. Such increased pressure may be advantageous in improving the mechanical damping of the first movable element 10a during movement of the first movable element 10a.

[0105] According to an embodiment of the present invention, a micro-electromechanical system (MEMS) device is provided. The MEMS device may include a MEMS substrate 50 and one or more movable elements (movable elements 10a, movable elements 10b). Each movable element (movable element 10a, movable element 10b) is laterally limited in a matrix layer 10 overlying the MEMS substrate 50. The top cover substrate 70 is bonded to the matrix layer 10, for example, by a bonding dielectric layer (bonding dielectric layer 62, bonding dielectric layer 72 or bump-containing material layer 192). The first movable element 10a may be located inside a first chamber 109, which is bounded by the matrix layer 10 in the lateral direction and by a first top cover surface overlying the first movable element 10a in the vertical direction. The first top cover surface may include an array of multiple downwardly protruding bumps (bumps 82B, bumps 192B), and the multiple downwardly protruding bumps (bumps 82B, bumps 192B) include corresponding portions of the bump-containing material layer, and the corresponding portions of the bump-containing material layer may be portions of the bump-containing material layer (bump-containing material layer 82, bump-containing material layer 192).

[0106] In an embodiment, each of the plurality of downwardly protruding bumps has an inverted hill-shaped vertical cross-sectional profile. In an embodiment, the top cover substrate includes a vertically protruding horizontal surface, the vertically protruding horizontal surface overlying the first chamber and offset upward from the proximal horizontal surface of the top cover substrate in the vertical direction, the proximal horizontal surface overlying the matrix layer and being the surface closest to the matrix layer selected from all surfaces of the top cover substrate. In an embodiment, the micro-electromechanical system device also includes a plurality of inverted grooves, the plurality of inverted grooves extending upward from the vertically protruding horizontal surface of the top cover substrate into the top cover substrate in the vertical direction, and overlying a corresponding one of the plurality of downwardly protruding bumps. In an embodiment, the micro-electromechanical system device also includes a plurality of voids, the plurality of voids do not have any solid phase material or any liquid phase material, and are contained in a plurality of sidewalls of the plurality of inverted grooves and overlying the corresponding downwardly protruding bumps. In an embodiment, multiple surfaces of the multiple inverted grooves are lined with the material of the bump-containing material layer, and each of the multiple voids includes an enclosed cavity defined by the corresponding surface of the material of the bump-containing material layer without a hole passing therethrough. In an embodiment, the micro-electromechanical system device also includes a matrix-side bonding dielectric layer located on the top surface of the matrix layer, wherein the bump-containing material layer extends below the bottom surface of the top cover substrate and is bonded to the matrix-side bonding dielectric layer. In an embodiment, the at least one movable element includes a second movable element located inside a second chamber, the second chamber being bounded in a vertical direction by a second top cover surface overlying the second movable element, and wherein the second top cover surface includes a portion of the bump-containing material layer and has a flat bottom surface. In an embodiment, the micro-electromechanical system device also includes a matrix-side bonding dielectric layer and a top cover side bonding dielectric layer. The matrix-side bonding dielectric layer is located on the top surface of the matrix layer. A cap side bonding dielectric layer is located between the bump-containing material layer and the vertically raised horizontal surface of the cap substrate, extends below the bottom surface of the cap substrate, and is bonded to the matrix side bonding dielectric layer. In an embodiment, the array of the plurality of downwardly protruding bumps comprises a one-dimensional array or a two-dimensional array. The at least one movable element and the matrix layer comprise a first semiconductor material. The cap substrate comprises a second semiconductor material. In an embodiment, a device comprising the first movable element, the first chamber, and the array of the plurality of downwardly protruding bumps comprises an accelerometer.

[0107] According to an embodiment of the present invention, a method for forming a micro-electromechanical system (MEMS) device is provided. At least one movable element (movable element 10a, movable element 10b) may be formed on a MEMS substrate 50, and the at least one movable element (movable element 10a, movable element 10b) may be laterally limited in a matrix layer 10. A recessed area 71a may be formed on the front side of a top cover substrate 70. A top cover side bonding dielectric layer 72 may be formed on the uppermost surface of the top cover substrate 70 and in the recessed area 71a of the top cover substrate 70. A plurality of grooves 75 extending through the top cover side bonding dielectric layer 72 to the top cover substrate may be formed in the recessed area 71a. A bump-containing material layer 82 may be formed on the top cover side bonding dielectric layer 72. A plurality of portions of the bump-containing material layer 82 overlying the plurality of grooves 75 form an array of a plurality of upwardly protruding bumps 82B. The top cover substrate 70 may be bonded to the matrix layer 10 such that the front side of the top cover substrate 70 faces the matrix layer 10. A first chamber 109 including the first movable element 10a may be formed by the matrix layer 10 and the top cover substrate 70. The surface of the array of the plurality of upwardly protruding bumps 82B provides a first top cover surface within the first chamber 109 after being placed upside down on the first movable element 10a during bonding.

[0108] In an embodiment, the bump-containing material layer is formed by a non-conformal deposition process, and the non-conformal deposition process forms each of the plurality of upwardly protruding bumps to have a hill-shaped vertical cross-sectional profile. In an embodiment, the bump-containing material layer includes a buffer material, and the buffer material includes at least one of a semiconductor material or a dielectric material. The non-conformal deposition process deposits the buffer material on the plurality of sidewalls of the plurality of grooves, so that the plurality of sidewalls of the plurality of grooves are lined with the buffer material, and a plurality of voids are formed in the volume of the plurality of grooves not filled by the buffer material, wherein each of the plurality of upwardly protruding bumps overlies a corresponding one of the plurality of voids. In an embodiment, the method further includes: forming a matrix-side bonding dielectric layer on the top surface of the matrix layer; and bonding the matrix-side bonding dielectric layer to the cap-side bonding dielectric layer. In an embodiment, the method also includes: forming an additional recessed area adjacent to the recessed area, so that the additional recessed area includes an additional upwardly protruding bump protruding upward from the recessed surface of the additional recessed area, wherein the top surface of the additional upwardly protruding bump includes a flat horizontal surface of the top cover substrate, and the flat horizontal surface is recessed from the uppermost surface of the top cover substrate in a vertical direction; forming a second chamber, the second chamber includes a second movable element selected from the at least one movable element, the second chamber is formed by aligning the additional recessed area above the second movable element during bonding the top cover substrate to the matrix layer, wherein the second chamber is bounded in the vertical direction by a second top cover surface overlying the second movable element and includes the flat horizontal surface of the top cover substrate.

[0109] According to an embodiment of the present invention, a method for forming a micro-electromechanical system (MEMS) device is provided. At least one movable element (movable element 10a, movable element 10b) is provided, and the at least one movable element (movable element 10a, movable element 10b) is laterally limited in a matrix layer 10 located on a MEMS substrate 50. A plurality of first grooves 75a can be formed on the front side of a top cover substrate 70. The region of the top cover substrate 70 including the plurality of first grooves 75a can be recessed in a vertical direction. A recessed horizontal surface can be formed in a recessed area 71a of the top cover substrate 70, and a second groove 75b replicating the pattern of the plurality of first grooves 75a extends downward from the recessed horizontal surface in a vertical direction. A bump-containing material layer 192 is formed on the uppermost surface of the top cover substrate 70 and in the recessed area 71a of the top cover substrate 70. In addition, a plurality of portions of the bump-containing material layer 192 overlying the plurality of second grooves 75b have an array of a plurality of upwardly protruding bumps 192B. The top cover substrate 70 may be bonded to the matrix layer 10 such that the front side of the top cover substrate 70 faces the matrix layer 10. A first chamber 109 including the first movable element 10a may be formed by the matrix layer 10 and the top cover substrate 70. After being placed upside down on the first movable element 10a during bonding, the surface of the array of the plurality of upwardly protruding bumps 192B provides a first top cover surface within the first chamber 109.

[0110] In an embodiment, the bump-containing material layer is formed by a non-conformal deposition process, the non-conformal deposition process forming each of the plurality of upwardly protruding bumps to have a mound-shaped vertical cross-sectional profile. In an embodiment, the non-conformal deposition process deposits a dielectric material of the bump-containing material layer on a plurality of sidewalls of the plurality of trenches, such that the plurality of sidewalls of the plurality of trenches are lined with the dielectric material, and a plurality of voids are formed in the volumes of the plurality of trenches not filled with the dielectric material, wherein each of the plurality of upwardly protruding bumps overlies a corresponding one of the plurality of voids. In an embodiment, the method also includes: forming a patterned etch mask layer on the front side of the top cover substrate, the patterned etch mask layer including a plurality of openings passing therethrough; anisotropically etching the material of the top cover substrate through the plurality of openings in the patterned etch mask layer by performing a first anisotropic etching process, thereby forming the plurality of first grooves; anisotropically etching the region of the top cover substrate including the plurality of first grooves using a patterned hard mask layer as an etching mask by performing a second anisotropic etching process; and removing the patterned hard mask layer before forming the bump material layer.

[0111] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present invention.

Claims

1. A micro-electromechanical system device, characterized in that include: MEMS substrates; at least one movable element laterally defined within a matrix layer overlying the MEMS substrate; as well as a capping substrate bonded to the matrix layer, wherein a first movable element selected from the at least one movable element is located within a first chamber, the first chamber being bounded laterally by the matrix layer and vertically by a first capping surface overlying the first movable element, and wherein the first capping surface comprises an array of a plurality of downwardly projecting bumps, the plurality of downwardly projecting bumps comprising corresponding portions of a bump-containing material layer, The top cover substrate comprises: a vertically raised horizontal surface, the vertically raised horizontal surface overlying the first cavity and offset upward from the proximal horizontal surface of the top cover substrate in a vertical direction, the proximal horizontal surface overlying the matrix layer and being a surface selected from all surfaces of the top cover substrate that is closest to the matrix layer; as well as A plurality of inverted grooves extend upwardly from the vertically raised horizontal surface of the cap substrate into the cap substrate in a vertical direction and overlie a respective one of the plurality of downwardly protruding bumps. 2 . The MEMS device according to claim 1 , wherein each of the plurality of downwardly protruding bumps has an inverted hill-shaped vertical cross-sectional profile. 3 . The MEMS device according to claim 1 , further comprising a plurality of voids, wherein the plurality of voids do not have any solid phase material or any liquid phase material and are contained within the plurality of sidewalls of the plurality of inverted grooves and overlie the corresponding downwardly protruding bumps.

4. The MEMS device according to claim 3, wherein: a plurality of surfaces of the plurality of reverse grooves are lined with a material of the bump-containing material layer; and Each of the plurality of voids comprises an enclosed cavity defined by a respective surface of the material of the bump-containing material layer without a hole therethrough. 5 . The MEMS device of claim 1 , further comprising a matrix-side bonding dielectric layer on a top surface of the matrix layer, wherein the bump-containing material layer extends below a bottom surface of the cap substrate and is bonded to the matrix-side bonding dielectric layer.

6. A micro-electromechanical system device according to claim 1, wherein the at least one movable element includes a second movable element located inside a second chamber, the second chamber is bounded by a second top cover surface overlying the second movable element in a vertical direction, and wherein the second top cover surface includes a portion of the bump-containing material layer and has a flat bottom surface.

7. The MEMS device according to claim 1, further comprising: a matrix-side bonding dielectric layer disposed on a top surface of the matrix layer; as well as A cap-side bonding dielectric layer is located between the bump-containing material layer and the vertically protruding horizontal surface of the cap substrate, extends below the bottom surface of the cap substrate, and is bonded to the matrix-side bonding dielectric layer.

8. The MEMS device according to claim 1, wherein: The array of the plurality of downwardly projecting bumps comprises a one-dimensional array or a two-dimensional array; The at least one movable element and the matrix layer comprise a first semiconductor material; and The cap substrate includes a second semiconductor material.

9. The MEMS device of claim 1, wherein the device including the first movable element, the first chamber, and the array of the plurality of downwardly projecting bumps comprises an accelerometer.

10. A method for forming a micro-electromechanical system device, characterized in that include: forming at least one movable element laterally defined within a matrix layer overlying a micro-electromechanical system substrate; forming a recessed area on the front side of the top cover substrate; forming a cap side bonding dielectric layer over the uppermost surface of the cap substrate and in the recessed region of the cap substrate; forming a plurality of trenches in the recessed region extending through the cap side bonding dielectric layer into the cap substrate; forming a bump-containing material layer on the cap-side bonding dielectric layer, wherein portions of the bump-containing material layer overlying the plurality of grooves form an array of a plurality of upwardly protruding bumps; as well as The top cover substrate is bonded to the matrix layer so that the front side of the top cover substrate faces the matrix layer, and a first chamber is formed by the matrix layer and the top cover substrate, the first chamber comprising a first movable element selected from the at least one movable element, wherein a surface of the array of the plurality of upwardly protruding bumps provides a first top cover surface in the first chamber after being placed upside down on the first movable element during bonding. 11 . The method of forming a MEMS device according to claim 10 , wherein the bump-containing material layer is formed by a non-conformal deposition process, wherein each of the plurality of upwardly protruding bumps is formed to have a hill-shaped vertical cross-sectional profile.

12. The method for forming a MEMS device according to claim 11, wherein: The bump-containing material layer includes a buffer material, wherein the buffer material includes at least one of a semiconductor material or a dielectric material; as well as The non-conformal deposition process deposits the buffer material on the multiple sidewalls of the multiple grooves, so that the multiple sidewalls of the multiple grooves are lined with the buffer material and a plurality of voids are formed in the volumes of the multiple grooves that are not filled with the buffer material, wherein each of the multiple upwardly protruding bumps overlies a corresponding one of the multiple voids.

13. The method for forming a MEMS device according to claim 10, further comprising: forming a matrix-side bonding dielectric layer on a top surface of the matrix layer; as well as The matrix-side bonding dielectric layer is bonded to the cap-side bonding dielectric layer.

14. The method for forming a MEMS device according to claim 10, further comprising: forming an additional recessed region adjacent to the recessed region such that the additional recessed region includes an additional upwardly protruding bump protruding upwardly from a recessed surface of the additional recessed region, wherein a top surface of the additional upwardly protruding bump includes a flat horizontal surface of the top cover substrate, the flat horizontal surface being recessed in a vertical direction from an uppermost surface of the top cover substrate; as well as A second chamber is formed, the second chamber including a second movable element selected from the at least one movable element, the second chamber being formed by aligning the additional recessed area over the second movable element during bonding the top cover substrate to the matrix layer, wherein the second chamber is vertically bounded by a second top cover surface overlying the second movable element and includes the flat horizontal surface of the top cover substrate.

15. A method for forming a micro-electromechanical system device, characterized in that include: forming at least one movable element laterally defined within a matrix layer overlying a micro-electromechanical system substrate; forming a plurality of first trenches on the front side of the cap substrate; Recessing a region of the cap substrate including the plurality of first grooves in a vertical direction, wherein a recessed horizontal surface is formed in the recessed region of the cap substrate, and a plurality of second grooves replicating a pattern of the plurality of first grooves extend downwardly from the recessed horizontal surface in the vertical direction; forming a bump-containing material layer on the uppermost surface of the top cover substrate and in the recessed area of ​​the top cover substrate, wherein a plurality of portions of the bump-containing material layer overlying the plurality of second grooves form an array of a plurality of upwardly protruding bumps; as well as The top cover substrate is bonded to the matrix layer so that the front side of the top cover substrate faces the matrix layer and a first chamber is formed by the matrix layer and the top cover substrate, the first chamber comprising a first movable element selected from the at least one movable element, wherein a surface of the array of the plurality of upwardly protruding bumps provides a first top cover surface in the first chamber after being placed upside down on the first movable element during bonding. 16 . The method of forming a MEMS device according to claim 15 , wherein the bump-containing material layer is formed by a non-conformal deposition process, wherein each of the plurality of upwardly protruding bumps is formed to have a hill-shaped vertical cross-sectional profile.

17. The method for forming a micro-electromechanical system device according to claim 16, wherein the non-conformal deposition process deposits the dielectric material of the bump material layer on the multiple sidewalls of the multiple grooves, so that the multiple sidewalls of the multiple grooves are lined with the dielectric material, and a plurality of voids are formed in the volumes of the multiple grooves not filled with the dielectric material, wherein each of the multiple upwardly protruding bumps overlies a corresponding one of the multiple voids.

18. The method for forming a MEMS device according to claim 15, further comprising: forming a patterned etch mask layer over the front side of the cap substrate, the patterned etch mask layer including a plurality of openings therethrough; anisotropically etching the material of the cap substrate through the plurality of openings in the patterned etch mask layer by performing a first anisotropic etching process, thereby forming the plurality of first trenches; anisotropically etching the region of the cap substrate including the plurality of first trenches using the patterned hard mask layer as an etch mask by performing a second anisotropic etching process; as well as The patterned hard mask layer is removed before forming the bump-containing material layer.

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