Display device

Abstract

Embodiments of the present application relate to a display device including a display panel including scan lines, emission control lines, and pixels connected to the scan lines and the emission control lines, a first emission driver that sequentially provides first emission control signals to odd-numbered ones of the emission control lines in a first frame section, a second emission driver that sequentially provides second emission control signals to even-numbered ones of the emission control lines in a second frame section consecutive to the first frame section, and a scan driver that sequentially provides scan signals to the scan lines in each of the first frame section and the second frame section.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0168209, filed on December 16, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention relate to a display device and a method of driving the display device. Background Art

[0004] A display device includes a display panel and a drive unit. The display panel includes scan lines, data lines, and pixels. The drive unit includes a scan driver that sequentially supplies scan signals to the scan lines, and a data driver that supplies data signals to the data lines. Each pixel emits light at a brightness level corresponding to the data signal supplied via the corresponding data line in response to the scan signal supplied via the corresponding scan line.

[0005] The display panel may further include an emission control line, and the driving unit may further include an emission driver that sequentially supplies an emission control signal to the emission control line. The emission period of the pixel may be controlled in response to the emission control signal.

[0006] High-speed frame driving may be required to drive a display device including a large-sized display panel. However, according to this high-speed frame driving method, the image quality of the display device may be deteriorated because the length of the segment to which the scan signal is supplied (or scan on time: SOT) is not sufficiently ensured.

[0007] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0008] Exemplary embodiments of the present invention provide a display device in which the length of a segment in which a scan signal is supplied and / or the length of a segment in which a data signal is written can be sufficiently ensured even when the display device is driven according to a high-speed frame driving method.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0010] A display device according to an exemplary embodiment of the present invention includes: a display panel including scan lines, emission control lines, and pixels connected to the scan lines and the emission control lines; a first emission driver that sequentially supplies a first emission control signal to odd-numbered emission control lines among the emission control lines in a first frame segment; a second emission driver that sequentially supplies a second emission control signal to even-numbered emission control lines among the emission control lines in a second frame segment continuous with the first frame segment; and a scan driver that sequentially supplies a scan signal to the scan lines in each of the first frame segment and the second frame segment.

[0011] The display device may further include a timing controller configured to generate a first start signal in the first frame segment, a second start signal in the second frame segment, and a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in the first and second frame segments. The first start signal may include an off-level pulse in the first frame segment, and the second start signal may include an off-level pulse in the second frame segment. The first, second, third, and fourth clock signals may have the same period, the second clock signal may be shifted from the first clock signal by a quarter period, the third clock signal may be shifted from the second clock signal by a quarter period, and the fourth clock signal may be shifted from the third clock signal by a quarter period. The first emission driver may generate the first emission control signal based on the first start signal and the first and third clock signals, and the second emission driver may generate the second emission control signal based on the second start signal and the second and fourth clock signals.

[0012] The first emission driver may provide a third emission control signal to the odd-numbered emission control lines in the second frame section, and the second emission driver may provide a fourth emission control signal to the even-numbered emission control lines in the first frame section.

[0013] The timing controller can further generate a third start signal in the second frame section, and further generate a fourth start signal in the first frame section. The third start signal can be maintained at an off level during the second frame section, and the fourth start signal can be maintained at an off level during the first frame section. The first emission driver can generate the third emission control signal based on the third start signal and the first clock signal and the third clock signal, and the second emission driver can generate the fourth emission control signal based on the fourth start signal and the second clock signal and the fourth clock signal.

[0014] The pixels can include a first pixel connected to a 2n-1th emission control line among the emission control lines and a 2n-3th scan line and a 2n-1th scan line among the scan lines, where n is a natural number, and a second pixel connected to a 2nth emission control line among the emission control lines and a 2n-2th scan line and a 2nth scan line among the scan lines.

[0015] A scan signal supplied to the 2n-1th scan line and a scan signal supplied to the 2nth scan line can overlap in some sections.

[0016] In a section in the first frame section in which a first emission control signal is supplied to the 2n-1th emission control line, the scan signal can be supplied to the 2n-3th scan line and the 2n-1th scan line, and in a section in the second frame section in which a second emission control signal is supplied to the 2nth emission control line, the scan signal can be supplied to the 2n-2th scan line and the 2nth scan line.

[0017] The display apparatus can further include a data driver that supplies a data signal to a data line in each of the first frame section and the second frame section, and the first pixel and the second pixel can be connected to an mth data line among the data lines, where m is a natural number.

[0018] The data driver can supply a first data signal to the mth data line in a section in the first frame section in which the scan signal is supplied to the 2n-1th scan line, and supply a second data signal to the mth data line in a section in the second frame section in which the scan signal is supplied to the 2nth scan line.

[0019] The first pixel may emit light at a grayscale corresponding to the first data signal in the first frame segment based on the first emission control signal supplied to the 2n-1th emission control line and the scan signal supplied to the 2n-1th scan line, and not emit light in the second frame segment based on the third emission control signal supplied to the 2n-1th emission control line.

[0020] The second pixel does not emit light in the first frame segment based on the fourth emission control signal provided to the 2nth emission control line, and can emit light at a grayscale corresponding to the second data signal in the second frame segment based on the second emission control signal provided to the 2nth emission control line and the second scanning signal provided to the 2nth scanning line.

[0021] Another exemplary embodiment of the present invention provides a method for driving a display device, the display device including: a first emission driver; a second emission driver; a scan driver; and a display panel including scan lines, emission control lines, and pixels connected to the scan lines and the emission control lines. The method includes: sequentially providing a first emission control signal to the odd-numbered emission control lines via the first emission driver in a first frame segment; and sequentially providing a second emission control signal to the even-numbered emission control lines via the second emission driver in a second frame segment continuous with the first frame segment. The scan driver may sequentially provide the scan signal to the scan lines in each of the first and second frame segments.

[0022] The display device may further include a timing controller, and the method may further include: generating, by the timing controller, a first start signal and a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in the first frame segment; and generating, by the timing controller, a second start signal and the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal in the second frame segment. The first start signal may have an off-level pulse in the first frame segment, and the second start signal may have an off-level pulse in the second frame segment. The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal may have the same period, the second clock signal may be shifted from the first clock signal by a quarter period, the third clock signal may be shifted from the second clock signal by a quarter period, and the fourth clock signal may be shifted from the third clock signal by a quarter period. The first emission driver may generate the first emission control signal based on the first start signal, the first clock signal, and the third clock signal, and the second emission driver may generate the second emission control signal based on the second start signal, the second clock signal, and the fourth clock signal.

[0023] The timing controller may further generate a fourth start signal in the first frame segment and a third start signal in the second frame segment, and the method may further include: in the first frame segment, providing a fourth emission control signal to the even-numbered emission control lines via the second emission driver based on the fourth start signal, the second clock signal, and the fourth clock signal; and in the second frame segment, providing a third emission control signal to the odd-numbered emission control lines via the first emission driver based on the third start signal, the first clock signal, and the third clock signal. The third start signal may be maintained at an off level during the second frame segment, and the fourth start signal may be maintained at an off level during the first frame segment.

[0024] The pixel may include: a first pixel, connected to the 2n-1th emission control line among the emission control lines and the 2n-3th scan line and the 2n-1th scan line among the scan lines, where n is a natural number; and a second pixel, connected to the 2nth emission control line among the emission control lines and the 2n-2th scan line and the 2nth scan line among the scan lines.

[0025] In the section of the first frame section in which the first emission control signal is provided to the 2n-1th emission control line, the scan signal may be provided to the 2n-3th scan line and the 2n-1th scan line, and in the section of the second frame section in which the second emission control signal is provided to the 2nth emission control line, the scan signal may be provided to the 2n-2th scan line and the 2nth scan line.

[0026] The display device may further include: a data driver providing a data signal to a data line, the first pixel and the second pixel may be connected to the mth data line among the data lines, where m is a natural number, and the data driver may provide a first data signal to the mth data line in the first frame segment and provide a second data signal to the mth data line in the second frame segment.

[0027] The first data signal may be provided to overlap with a section in which a scan signal is provided to the 2n-1th scan line, and the second data signal may be provided to overlap with a section in which a scan signal is provided to the 2nth scan line.

[0028] The method may further include: in the first frame segment, emitting light of the first pixel at a grayscale corresponding to the first data signal based on the first emission control signal provided to the 2n-1th emission control line and the scan signal provided to the 2n-1th scan line; and in the first frame segment, not emitting light based on the fourth emission control signal provided to the 2nth emission control line.

[0029] The method may further include: in the second frame segment, not emitting light of the first pixel based on the third emission control signal provided to the 2n-1th emission control line; and in the second frame segment, emitting light of the second pixel at a grayscale level corresponding to the second data signal based on the second emission control signal provided to the 2n emission control line and the scan signal provided to the 2n scan line.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0032] Figure 1 is a block diagram for explaining a display device according to an exemplary embodiment of the present application.

[0033] Figure 2 is a circuit diagram showing an example of a first pixel and a second pixel included in the display device of Figure 1 .

[0034] Figure 3 is a graph showing an example of signals measured in the first emission driver and the second emission driver of Figure 1 in a first frame section.

[0035] Figure 4A is a graph showing an example of signals measured in the first emission driver and the second emission driver of Figure 3 in a second frame section.

[0036] Figure 4B is a graph showing an example of signals measured in the first emission driver and the second emission driver of Figure 3 in a second frame section.

[0037] Figure 5A is a graph showing an example of signals measured in the scan driver and the data driver included in the display device of Figure 1 in a first frame section.

[0038] Figure 5B is a graph showing an example of signals measured in the scan driver and the data driver included in the display device of Figure 1 in a second frame section.

[0039] Figure 6 is a graph showing a comparative example of signals measured in the scan driver and the data driver included in the display device of Figure 1 in a first frame section and in a second frame section.

[0040] Figure 7A and Figure 7B is a waveform graph for explaining a driving method of the first pixel and the second pixel of Figure 2 .

[0041] Figure 8 is a flowchart showing a method of driving a display device according to an exemplary embodiment of the present application.

[0042] Figure 9A is a flowchart showing a method of driving a display device according to an exemplary embodiment of the present application in a first frame section.

[0043] Figure 9B is a flowchart showing a method of driving a display device according to an exemplary embodiment of the present application in a second frame section. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments of the present invention. As used herein, "embodiment" is a non-limiting example of a device or method using one or more of the present inventions disclosed herein. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or implemented using one or more equivalent arrangements. In other cases, known structures and devices are shown in block diagram form to avoid unnecessary ambiguity of the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration and characteristics of an exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the present invention.

[0045] Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter, individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0046] In the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in a reverse order to the described sequence. In addition, the same reference numerals represent the same elements.

[0047] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to another element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or intermediate layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element or intermediate layer. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system, such as the x-axis, the y-axis and the z-axis, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below could be named the second element without departing from the teachings of the present disclosure.

[0049] Spatially relative terms such as "below," "beneath," "beneath," "lower," "above," "upper," "above," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and thereby describe one element's relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and, as such, the spatially relative descriptors used herein interpreted accordingly.

[0050] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises, comprising" and / or "includes, including" illustrate the presence of stated features, wholes, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or increase of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as terms of degree, and are used as such to explain the inherent deviations in measurements, calculations and / or provided values ​​that one of ordinary skill in the art will recognize.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0052] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a block diagram for explaining a display device according to an exemplary embodiment of the present invention.

[0054] Reference Figure 1 , the display device 100 may include a display panel 110 , a timing controller 120 , a scan driver 130 , emission drivers 140 and 150 , and a data driver 160 .

[0055] The display panel 110 may include scan lines S, emission control lines E, data lines D, and pixels PX1 and PX2 .

[0056] The pixels PX1 and PX2 may be connected to at least one of the scan lines S, at least one of the emission control lines E, and one of the data lines D. For example, the first pixel PX1 may be connected to the 2n-1th scan line S2n-1 and the 2n-3th scan line S2n-3 among the scan lines S, the 2n-1th emission control line E2n-1 among the emission control lines E, and the mth data line Dm among the data lines D, where n and m are natural numbers. As another example, the second pixel PX2 may be connected to the 2nth scan line S2n and the 2n-2th scan line S2n-2 among the scan lines S, the 2nth emission control line E2n among the emission control lines E, and the mth data line Dm among the data lines D.

[0057] In an exemplary embodiment, a pixel located on an odd-numbered horizontal line (e.g., a first pixel PX1) emits light in a first frame segment (e.g., an odd-numbered frame segment or an even-numbered frame segment), and does not emit light in a second frame segment (e.g., an even-numbered frame segment or an odd-numbered frame segment) that is continuous with the first frame segment. Additionally, a pixel located on an even-numbered horizontal line (e.g., a second pixel PX2) does not emit light in the first frame segment, and emits light in the second frame segment. This will be referred to Figure 2 、 Figure 7A and Figure 7B This will be described later.

[0058] Pixels PX1 and PX2 may receive a voltage of a first power supply VDD, a voltage of a second power supply VSS, and a voltage of an initialization power supply Vint from the outside. The voltage of the first power supply VDD and the voltage of the second power supply VSS may be voltages required for the operation of pixels PX1 and PX2, and the first power supply VDD may have a voltage level higher than the voltage level of the second power supply VSS. In addition, the initialization power supply Vint may have a voltage level for initializing the driving transistor and / or light-emitting element included in pixels PX1 and PX2.

[0059] The timing controller 120 may receive a control signal CS and input image data DATA1 from an external device (e.g., a graphics processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and convert the input image data DATA1 to generate image data DATA2. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like.

[0060] In exemplary embodiments, the timing controller 120 may generate the first emission driving control signal ECS1 and the second emission driving control signal ECS2 based on the control signal CS.

[0061] The scan driver 130 may generate a scan signal based on a scan control signal SCS provided from the timing controller 120 and may sequentially provide the scan signal to the scan lines S. Here, the scan control signal SCS may include a scan start signal, and first, second, third, and fourth scan clock signals.

[0062] In an exemplary embodiment, the scan driver 130 may sequentially supply a scan signal having a pulse of an on-level (or an on-voltage level) to the scan lines S in each of the first frame segment and the second frame segment (e.g., in each of the odd-numbered frame segment and the even-numbered frame segment). For example, the scan driver 130 may be configured in the form of a shift register. Figure 5A 、 Figure 5B and Figure 6 The configuration of the scan driver 130 that generates the scan signal is described.

[0063] The emission drivers 140 and 150 can be divided into the configuration and operation of the first emission driver 140 and the second emission driver 150. However, the division of the emission drivers 140 and 150 is for the convenience of description. According to another design method, the first emission driver 140 and the second emission driver 150 can be integrated into a configuration (for example, a driving circuit and a module, etc.).

[0064] The first emission driver 140 may generate an emission control signal based on the first emission drive control signal ECS1 provided from the timing controller 120, and sequentially provide the emission control signal to at least some of the emission control lines E. For example, the first emission driver 140 may generate an emission control signal provided to odd-numbered emission control lines E, and sequentially provide the emission control signal to the odd-numbered emission control lines E. However, the present inventive concept is not limited thereto, and the first emission driver 140 may generate an emission control signal provided to even-numbered emission control lines E, and sequentially provide the emission control signal to the even-numbered emission control lines E. Here, the first emission drive control signal ECS1 may include a first emission start signal, a first emission clock signal, a third emission clock signal, and the like.

[0065] In an exemplary embodiment, the first emission driver 140 can sequentially provide the first emission control signal having a pulse of a cutoff level (or a cutoff voltage level) to the odd-numbered emission control line E (or the even-numbered emission control line E) in the first frame section (e.g., the odd-numbered frame section or the even-numbered frame section). In the first frame section, when the first emission control signal having the pulse of the cutoff level is sequentially provided to the odd-numbered emission control line E, the pixel (e.g., the first pixel PX1) connected to the odd-numbered emission control line E does not emit light in units of horizontal lines.

[0066] In addition, the first emission driver 140 can provide a third emission control signal maintained at a cutoff level during a second frame section to the odd-numbered emission control line E (or the even-numbered emission control line E) in the second frame section (e.g., the even-numbered frame section or the odd-numbered frame section). In the second frame section, when the third emission control signal maintained at the cutoff level during the second frame section is provided to the odd-numbered emission control line E, the pixel (e.g., the first pixel PX1) connected to the odd-numbered emission control line E does not emit light during the second frame section.

[0067] The second emission driver 150 can generate emission control signals based on the second emission driving control signal ECS2 provided from the timing controller 120 and sequentially provide the emission control signals to at least some of the emission control lines E. For example, the second emission driver 150 can generate emission control signals provided to the even-numbered emission control line E and sequentially provide the emission control signals to the even-numbered emission control line E. However, the inventive concept is not limited thereto, and the second emission driver 150 can generate emission control signals provided to the odd-numbered emission control line E and sequentially provide the emission control signals to the odd-numbered emission control line E. Here, the second emission driving control signal ECS2 can include a second emission start signal, and a second emission clock signal and a fourth emission clock signal, etc.

[0068] In an exemplary embodiment, the second emission driver 150 can sequentially provide the second emission control signal having a pulse of a cutoff level (or a cutoff voltage level) to the even-numbered emission control line E (or the odd-numbered emission control line E) in the second frame section (e.g., the even-numbered frame section or the odd-numbered frame section). In the second frame section, when the second emission control signal having the pulse of the cutoff level is sequentially provided to the even-numbered emission control line E, the pixel (e.g., the second pixel PX2) connected to the even-numbered emission control line E does not emit light in units of horizontal lines.

[0069] In addition, the second emission driver 150 may provide the fourth emission control signal maintained at the off level during the first frame segment to the even-numbered emission control line E (or the odd-numbered emission control line E) in the first frame segment (e.g., the odd-numbered frame segment or the even-numbered frame segment). In the first frame segment, when the fourth emission control signal maintained at the off level during the first frame segment is provided to the even-numbered emission control line E, the pixel connected to the even-numbered emission control line E (e.g., the second pixel PX2) does not emit light during the first frame segment.

[0070] In an exemplary embodiment, the first emission driver 140 and the second emission driver 150 may be configured in the form of a shift register.

[0071] Will refer to it later Figure 3 、 Figure 4A and Figure 4B Configurations of the first emission driver 140 for generating the first emission control signal and the second emission driver 150 for generating the second emission control signal are described.

[0072] The data driver 160 may generate a data signal based on the image data DATA2 and the data control signal DCS provided from the timing controller 120, and provide the data signal to the display panel 110 (or pixels PX1 and PX2) in each of the first frame segment and the second frame segment (e.g., in each of the odd-numbered frame segment and the even-numbered frame segment). The data control signal DCS may be a signal for controlling the operation of the data driver 160 and may include a load signal (or a data enable signal) indicating the output of a valid data signal.

[0073] At least one of the timing controller 120, the scan driver 130, the emission drivers 140 and 150, and the data driver 160 may be formed on the display panel 110 or implemented as an IC and connected to the display panel 110 in the form of a tape carrier package. In addition, at least two of the timing controller 120, the scan driver 130, the emission drivers 140 and 150, and the data driver 160 may be implemented as one IC.

[0074] Figure 2 It is shown that the Figure 1 1 is a circuit diagram of an example of a first pixel and a second pixel in a display device.

[0075] Reference Figure 2, each of the first pixel PX1 and the second pixel PX2 may include first, second, third, fourth, fifth, sixth, and seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor Cst, and a light emitting element LD.

[0076] Each of the first transistor TR1, the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 may be implemented as a P-type transistor, but the present invention is not limited thereto. For example, at least some of the first transistor TR1, the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 may be implemented as an N-type transistor.

[0077] Since the first pixel PX1 and the second pixel PX2 are substantially identical to each other, the first pixel PX1 of the first pixel PX1 and the second pixel PX2 will be described.

[0078] A first electrode of the first transistor TR1 (driving transistor) may be connected to the second node N2, or may be connected to the first power line (i.e., the power line to which the first power supply VDD is applied) via the fifth transistor TR5. A second electrode of the first transistor TR1 may be connected to the first node N1, or may be connected to the anode of the light-emitting element LD via the sixth transistor TR6. A gate electrode of the first transistor TR1 may be connected to the third node N3. The first transistor TR1 may control the amount of current flowing from the first power line to the second power line (i.e., the power line for delivering the second power supply VSS) via the light-emitting element LD in response to the voltage of the third node N3.

[0079] The second transistor T2 (switching transistor) may be connected between the mth data line Dm and the second node N2. A gate electrode of the second transistor TR2 may be connected to the 2n-1th scan line S2n-1. The second transistor TR2 may be turned on when a scan signal is supplied to the 2n-1th scan line S2n-1, and may electrically connect the mth data line Dm and the first electrode of the first transistor TR1.

[0080] The third transistor TR3 may be connected between the first node N1 and the third node N3. A gate electrode of the third transistor TR3 may be connected to the 2n-1th scan line S2n-1. The third transistor TR3 may be turned on when a scan signal is supplied to the 2n-1th scan line S2n-1, and may electrically connect the first node N1 and the third node N3. Therefore, when the third transistor TR3 is turned on, the first transistor TR1 may be connected in the form of a diode.

[0081] The storage capacitor Cst may be connected between the first power line and the third node N3. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor TR1.

[0082] The fourth transistor TR4 may be connected between the third node N3 and an initialization power line (i.e., a power line for delivering the initialization power Vint). The gate electrode of the fourth transistor TR4 may be connected to the 2n-3 scan line S2n-3. The fourth transistor TR4 may be turned on when a scan signal is supplied to the 2n-3 scan line S2n-3, and may supply the initialization power Vint to the first node N1. Here, the initialization power Vint may be set to a voltage level lower than the voltage level of the data signal.

[0083] The fifth transistor TR5 may be connected between the first power line and the second node N2. A gate electrode of the fifth transistor TR5 may be connected to the 2n-1th emission control line E2n-1. The fifth transistor TR5 may be turned off when the emission control signal is supplied to the 2n-1th emission control line E2n-1, and may be turned on in other cases.

[0084] The sixth transistor TR6 may be connected between the first node N1 and the light emitting element LD. A gate electrode of the sixth transistor TR6 may be connected to the 2n-1th emission control line E2n-1. The sixth transistor TR6 may be turned off when the emission control signal is supplied to the 2n-1th emission control line E2n-1, and may be turned on in other cases.

[0085] The seventh transistor TR7 may be connected between the initialization power supply line and the anode of the light-emitting element LD. The gate electrode of the seventh transistor TR7 may be connected to the 2n-1th scan line S2n-1. The seventh transistor TR7 may be turned on when a scan signal is supplied to the 2n-1th scan line S2n-1, and may supply the initialization power supply Vint to the anode of the light-emitting element LD.

[0086] The anode of the light-emitting element LD can be connected to the first transistor TR1 via the sixth transistor TR6, and the cathode of the light-emitting element LD can be connected to the second power supply line. The light-emitting element LD can emit light having a predetermined brightness level in response to the current supplied from the first transistor TR1. The first power supply VDD can be set to have a voltage level higher than the voltage level of the second power supply VSS so that current flows to the light-emitting element LD.

[0087] In the second pixel PX2, the gate electrodes of the second transistor TR2, the third transistor TR3 and the seventh transistor TR7 can be connected to the 2n-th scan line S2n, the gate electrode of the fourth transistor TR4 can be connected to the 2n-2-th scan line S2n-2, and the gate electrode of the fifth transistor TR5 and the gate electrode of the sixth transistor TR6 can be connected to the 2n-th emission control line E2n.

[0088] The connection relationship between the first pixel PX1 and the second pixel PX2 is not limited thereto. For example, the gate electrode of the fourth transistor TR4 of the first pixel PX1 may be connected to the 2n-4th scan line (not shown), and the gate electrode of the fourth transistor TR4 of the second pixel PX2 may be connected to the 2n-3th scan line S2n-3.

[0089] Figure 3 It is shown that the Figure 1 FIG. 1 is a diagram illustrating an example of a first emission driver and a second emission driver in a display device.

[0090] Reference Figure 3 , the first emission driver 140 may include a plurality of stages ST11, ST12, ..., ST1n, ..., and ST1p, where p is a natural number and n is a natural number greater than 1 and less than p. The plurality of stages ST11, ST12, ..., ST1n, ..., and ST1p may be connected to at least some of the emission control lines E (see Figure 1 ) and can be driven in response to a clock signal. For example, a plurality of stages ST11, ST12, ..., ST1n, ..., and ST1p can be connected to odd-numbered emission control lines E1, E3, ..., E2n-1, ..., and E2p-1, respectively, and use the first emission start signal FLM1 (or the output signal of the previous stage, that is, the emission control signal of the previous stage) and the first emission clock signal ECLK1 and the third emission clock signal ECLK3 to generate an emission control signal. In this way, the plurality of stages ST11, ST12, ..., ST1n, ..., and ST1p can sequentially provide the first emission control signal to the odd-numbered emission control lines E1, E3, ..., E2n-1, ..., and E2p-1.

[0091] The second emission driver 150 may include a plurality of stages ST21, ST22, ..., ST2n, ..., and ST2p. The plurality of stages ST21, ST22, ..., ST2n, ..., and ST2p may be connected to at least some of the emission control lines E (see FIG. Figure 1) and can be driven in response to the clock signal. For example, the plurality of stages ST21, ST22, ..., ST2n, ..., and ST2p can be connected to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p, respectively, and use the second emission start signal FLM2 (or the output signal of the previous stage, that is, the emission control signal of the previous stage) and the second emission clock signal ECLK2 and the fourth emission clock signal ECLK4 to generate the emission control signal. In this way, the plurality of stages ST21, ST22, ..., ST2n, ..., and ST2p can sequentially provide the second emission control signal to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p.

[0092] In an exemplary embodiment, the plurality of stages ST11, ST12, . . . , ST1n, . . . , and ST1p of the first emission driver 140 and the plurality of stages ST21, ST22, . . . , ST2n, . . . , and ST2p of the second emission driver 150 may have substantially the same circuit structure.

[0093] Reference Figure 4A and Figure 4B 1 and 150, and the first emission start signals FLM1 and FLM2, and the emission control signals generated by the first emission driver 140 and the second emission driver 150.

[0094] Figure 4A It is shown that in the first frame segment, Figure 3 FIG. 1 is a diagram of examples of signals measured in a first transmit driver and a second transmit driver. Figure 4B It is shown that in the second frame segment, Figure 3 FIG. 1 is a diagram of examples of signals measured in a first transmit driver and a second transmit driver.

[0095] Reference Figure 1 、 Figure 3 and Figure 4A , the first frame segment Frame1 may correspond to an odd-numbered frame segment. However, the inventive concept is not limited thereto, and the first frame segment Frame1 may correspond to an even-numbered frame segment.

[0096] In the first frame section Frame1, the timing controller 120 can generate a first emission start signal FLM1 and a second emission start signal FLM2 as well as a first emission clock signal ECLK1, a second emission clock signal ECLK2, a third emission clock signal ECLK3, and a fourth emission clock signal ECLK4.

[0097] In the first frame section Frame1, the first emission start signal FLM1 can have an off-level pulse (e.g., a logic high level pulse). A pulse width of the off-level pulse included in the first emission start signal FLM1 can be set based on a scan signal provided to the pixels PX1 and PX2 (see FIG. 1). Here, a length of the pulse width of the off-level pulse included in the first emission start signal FLM1 can be defined as a second section 8H. The length of the second section 8H can be eight times the length of the first section 1H. However, the length of the pulse width of the off-level pulse included in the first emission start signal FLM1 is not limited thereto. For example, the first emission start signal FLM1 can include an off-level pulse having a pulse width corresponding to twelve times the length of the first section 1H. Figure 2

[0098] In the first frame section Frame1, the second emission start signal FLM2 can be a signal maintained at an off level (or a fourth emission start signal). In an embodiment, the second emission start signal FLM2 can be shifted to an off level before the first frame section Frame1 starts and maintained at the off level during the first frame section Frame1. For example, in a blank section of a previous frame section of the first frame section Frame1, the second emission start signal FLM2 can be shifted to an off level and maintained at the off level during the first frame section Frame1.

[0099] ​The first emission clock signal ECLK1, the second emission clock signal ECLK2, the third emission clock signal ECLK3 and the fourth emission clock signal ECLK4 may have the same period and may be shifted by a quarter period and generated sequentially. Here, the shifted segment may be defined as the first segment 1H, and the period may be defined as the third segment 4H. In an embodiment, the first emission clock signal ECLK1, the second emission clock signal ECLK2, the third emission clock signal ECLK3 and the fourth emission clock signal ECLK4 may have a period corresponding to four times the time of the first segment 1H (i.e., the length of the third segment 4H). The second emission clock signal ECLK2 may be generated by shifting the first segment 1H from the first emission clock signal ECLK1, the third emission clock signal ECLK3 may be generated by shifting the first segment 1H from the second emission clock signal ECLK2, and the fourth emission clock signal ECLK4 may be generated by shifting the first segment 1H from the third emission clock signal ECLK3. However, the number and period of the emission clock signals generated by the timing controller 120 are not limited thereto. For example, the timing controller 120 may generate six transmit clock signals, and the transmit clock signals may have a period corresponding to six times the time of the first section 1H. As another example, the timing controller 120 may generate four transmit clock signals, and the transmit clock signals may have a period corresponding to twice the time of the first section 1H.

[0100] The first emission driver 140 may generate first emission control signals to be provided to odd-numbered emission control lines E1, E3, . . . , E2n-1, . . . , and E2p-1 based on the first emission start signal FLM1 and the first and third emission clock signals ECLK1 and ECLK3.

[0101] In an exemplary embodiment, when the first emission start signal (or the first emission control signal of the previous stage) is at the off level and the first emission clock signal ECLK1 or the third emission clock signal ECLK3 shifts to the on level (or a logic low level), the first emission control signal may be changed from the on level to the off level. In addition, when the first emission start signal (or the first emission control signal of the previous stage) shifts to the on level and the first emission clock signal ECLK1 or the third emission clock signal ECLK3 shifts to the on level (or a logic low level), the first emission control signal may be changed from the off level to the on level.

[0102] For example, when the first emission start signal FLM1 is at an off-level and the third emission clock signal ECLK3 shifts to an on-level (i.e., at a first time point t1), the first emission control signal provided to the first emission control line E1 may change from an on-level to an off-level. Additionally, when the first emission start signal FLM1 shifts to an on-level and the first emission clock signal ECLK1 shifts to an on-level (i.e., at a second time point t2), the first emission control signal provided to the first emission control line E1 may change from an off-level to an on-level. Therefore, the first emission control signal provided to the first emission control line E1 may include an off-level pulse having a pulse width corresponding to the length of the fourth segment 6H. Here, the length of the fourth segment 6H may be six times the length of the first segment 1H.

[0103] In an exemplary embodiment, the emission control signals supplied to the odd-numbered emission control lines E1, E3, ..., E2n-1, ..., and E2p-1 may be shifted by a fifth segment 2H and sequentially generated. For example, the first emission control signal supplied to the third emission control line E3 may be shifted by a fifth segment 2H from the first emission control signal supplied to the first emission control line E1.

[0104] The second emission driver 150 may generate a second emission control signal to be provided to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p based on the second emission start signal FLM2 (or the fourth emission start signal) maintained at the off level in the first frame segment Frame1 and the second emission clock signal ECLK2 and the fourth emission clock signal ECLK4.

[0105] In an exemplary embodiment, since the second emission start signal FLM2 is maintained at the cut-off level in the first frame segment Frame1, the second emission control signal provided to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p may be a signal (or a fourth emission control signal) maintained at the cut-off level in the first frame segment Frame1.

[0106] Reference Figure 1 、 Figure 3 and Figure 4B , the second frame segment Frame2 may correspond to an even-numbered frame segment. However, the inventive concept is not limited thereto, and the second frame segment Frame2 may correspond to an odd-numbered frame segment.

[0107] In the second frame segment Frame2 , the timing controller 120 may generate first and second emission start signals FLM1 and FLM2 and first, second, third, and fourth emission clock signals ECLK1 , ECLK2 , ECLK3 , and ECLK4 .

[0108] In the second frame segment Frame2, the second emission start signal FLM2 may have an off-level pulse (e.g., a logic high level pulse). The pulse width of the off-level pulse included in the second emission start signal FLM2 may be set equal to the pulse width of the off-level pulse included in the first emission start signal FLM1 in the first frame segment Frame1.

[0109] In the second frame segment Frame2, the first transmission start signal FLM1 may be a signal (or a third transmission start signal) maintained at the cutoff level. In an exemplary embodiment, the first transmission start signal FLM1 may be shifted to the cutoff level before the start of the second frame segment Frame2 and maintained at the cutoff level during the second frame segment Frame2. For example, in a blank segment of the frame segment preceding the second frame segment Frame2, the first transmission start signal FLM1 may be shifted to the cutoff level and maintained at the cutoff level during the second frame segment Frame2.

[0110] The first emission clock signal ECLK1, the second emission clock signal ECLK2, the third emission clock signal ECLK3 and the fourth emission clock signal ECLK4 are respectively Figure 4A The first emission clock signal ECLK1, the second emission clock signal ECLK2, the third emission clock signal ECLK3, and the fourth emission clock signal ECLK4 described above are substantially the same or similar, and therefore, overlapping descriptions will not be repeated.

[0111] The second emission driver 150 may generate second emission control signals to be provided to even-numbered emission control lines E2 , E4 , . . . , E2 n , . . . , and E2 p based on the second emission start signal FLM2 and the second and fourth emission clock signals ECLK2 and ECLK4 .

[0112] In an exemplary embodiment, when the second emission start signal FLM2 (or the second emission control signal of the previous stage) is at the off level and the second emission clock signal ECLK2 or the fourth emission clock signal ECLK4 shifts to the on level (or a logic low level), the second emission control signal may be changed from the on level to the off level. In addition, when the second emission start signal FLM2 (or the second emission control signal of the previous stage) shifts to the on level and the second emission clock signal ECLK2 or the fourth emission clock signal ECLK4 shifts to the on level (or a logic low level), the second emission control signal may be changed from the off level to the on level.

[0113] For example, when the second emission start signal FLM2 is at the off-level and the fourth emission clock signal ECLK4 shifts to the on-level (i.e., at the third time point t3), the second emission control signal provided to the second emission control line E2 can be changed from the on-level to the off-level. In addition, when the second emission start signal FLM2 shifts to the on-level and the second emission clock signal ECLK2 shifts to the on-level (i.e., at the fourth time point t4), the second emission control signal provided to the second emission control line E2 can be changed from the off-level to the on-level. Therefore, the second emission control signal provided to the second emission control line E2 can include an on-level pulse having a pulse width corresponding to the length of the fourth segment 6H. Here, the length of the fourth segment 6H can be six times the length of the first segment 1H.

[0114] In an exemplary embodiment, the second emission control signals supplied to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p may be shifted by a fifth segment 2H and sequentially generated. For example, the second emission control signal supplied to the fourth emission control line E4 may be shifted by a fifth segment 2H from the second emission control signal supplied to the second emission control line E2.

[0115] The first emission driver 140 may generate a first emission control signal to be provided to the odd-numbered emission control lines E1, E3, ..., E2n-1, ..., and E2p-1 based on the first emission start signal FLM1 (or the third emission start signal) maintained at the cut-off level in the second frame segment Frame2 and the first emission clock signal ECLK1 and the third emission clock signal ECLK3.

[0116] In an exemplary embodiment, since the first emission start signal FLM1 is maintained at the cut-off level in the second frame segment Frame2, the first emission control signal provided to the odd-numbered emission control lines E1, E3, ..., E2n-1, ..., and E2p-1 may be a signal (or a third emission control signal) maintained at the cut-off level in the second frame segment Frame2.

[0117] As reference Figure 3 、 Figure 4A and Figure 4B As described above, the first emission driver 140 may provide the first emission control signal (or third emission control signal) maintained at the cut-off level in the second frame segment Frame2 (e.g., the even-numbered frame segment) to the odd-numbered emission control lines E1, E3, ..., E2n-1, ..., and E2p-1. In addition, the second emission driver 150 may provide the second emission control signal (or fourth emission control signal) maintained at the cut-off level in the first frame segment Frame1 (e.g., the odd-numbered frame segment) to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p. Therefore, the pixels connected to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p (e.g., Figure 2 The second pixel PX2 of the second pixel PX2) can be maintained in the non-light emitting state in the first frame segment Frame1, and the pixels connected to the odd-numbered emission control lines E1, E3, . . . , E2n-1, . . . , and E2p-1 (for example, Figure 2 The first pixel PX1) may be maintained in a non-light emitting state in the second frame segment Frame2.

[0118] Figure 5A is shown in the first frame segment, including Figure 1 FIG. 1 is a diagram showing an example of signals measured in a scan driver and a data driver in a display device. Figure 5B is shown in the second frame segment, including Figure 1 FIG. 1 is a diagram showing an example of signals measured in a scan driver and a data driver in a display device. Figure 6 It is shown that in the first frame segment and the second frame segment, Figure 1 FIG. 1 is a diagram showing a comparative example of signals measured in a scan driver and a data driver in a display device.

[0119] Reference Figure 1 and Figure 5A In the first frame segment Frame1, the timing controller 120 may generate a first scanning clock signal SCLK1, a second scanning clock signal SCLK2, a third scanning clock signal SCLK3, and a fourth scanning clock signal SCLK4.

[0120] The first scan clock signal SCLK1, the second scan clock signal SCLK2, the third scan clock signal SCLK3 and the fourth scan clock signal SCLK4 may have the same period P and may be shifted by a first section 1H and sequentially generated. Here, the length of the shifted first section 1H may be the same as the reference period P. Figure 4A and Figure 4BThe lengths of the described first sections 1H are substantially the same.

[0121] The second scan clock signal SCLK2 can be generated by shifting the first segment 1H from the first scan clock signal SCLK1, the third scan clock signal SCLK3 can be generated by shifting the first segment 1H from the second scan clock signal SCLK2, and the fourth scan clock signal SCLK4 can be generated by shifting the first segment 1H from the third scan clock signal SCLK3.

[0122] The scan driver 130 can generate scan signals to be provided to the scan lines S1, S2, S3, S4,..., S2n-3, S2n-2, S2n-1, S2n,..., S2p-1 and S2p based on the scan start signal and the first scan clock signal SCLK1, the second scan clock signal SCLK2, the third scan clock signal SCLK3 and the fourth scan clock signal SCLK4.

[0123] In an exemplary embodiment, the scan signals may be generated in synchronization with the first, second, third, and fourth scan clock signals SCLK1, SCLK2, SCLK3, and SCLK4, and may be shifted by a first section 1H and sequentially generated.

[0124] In an exemplary embodiment, the scan signals may overlap in some sections. For example, the scan signal supplied to the second scan line S2 may be generated by shifting the scan signal supplied to the first scan line S1 by a first section 1H and may overlap each other in some sections.

[0125] In the first frame section Frame1, the data driver 160 may supply only data signals corresponding to grayscale values ​​of pixels located on odd-numbered horizontal lines to the data lines D. In addition, in the first frame section Frame1, the data driver 160 may supply data signals to the data lines D in response to a section in which scan signals are supplied to the odd-numbered scan lines S1, S3, . . . , S2n-3, and S2n-1.

[0126] For example, in the first frame segment Frame1, the data driver 160 can continuously provide data signals DS[1], DS[3], DS[5], ..., DS[2n-3], DS[2n-1], DS[2n+1], ..., and DS[2p-1] corresponding to the grayscale values ​​of pixels located on odd-numbered horizontal lines (e.g., the first pixel PX1) to the mth data line Dm, thereby corresponding to a segment in which scan signals are provided to odd-numbered scan lines S1, S3, ..., S2n-3, S2n-1, ..., and S2p-1.

[0127] Referring to Figure 5A and Figure 5B The first scan clock signal SCLK1, the second scan clock signal SCLK2, the third scan clock signal SCLK3, and the fourth scan clock signal SCLK4 generated in the second frame section Frame2 and the scan signal are substantially the same as described with reference to Figure 5A The first scan clock signal SCLK1, the second scan clock signal SCLK2, the third scan clock signal SCLK3, and the fourth scan clock signal SCLK4 generated in the first frame section Frame1 and the scan signal are substantially the same as described with reference to

[0128] Referring to Figure 1 and Figure 5B In the second frame section Frame2, the data driver 160 can provide the data signal corresponding to the gray scale value of the pixel located on the even-numbered horizontal line to the data line D. Also, in the second frame section Frame2, the data driver 160 can provide the data signal to the data line D in response to the section in which the scan signal is provided to the even-numbered scan lines S2, S4, …, S2n-2, S2n, …, and S2p.

[0129] For example, in the second frame section Frame2, the data driver 160 can continuously provide the data signals DS[2], DS[4], …, DS[2n-4], DS[2n-2], DS[2n], …, and DS[2p] corresponding to the gray scale values of the pixels (e.g., the second pixel PX2) located on the even-numbered horizontal lines to the m-th data line Dm, thereby corresponding to the section in which the scan signal is provided to the even-numbered scan lines S2, S4, …, S2n-2, S2n, …, and S2p.

[0130] Referring to Figure 6 In the first frame section Frame1 and the second frame section Frame2, the timing controller 120 can generate a first scan clock signal SCLK1' and a second scan clock signal SCLK2'. The first scan clock signal SCLK1' and the second scan clock signal SCLK2' can have the same period P' and can be sequentially generated with a sixth section 1H' shifted. Here, the length of the sixth section 1H' can be the same as or different from the length of the first section 1H described with reference to Figure 5A and Figure 5B The first scan clock signal SCLK1', the second scan clock signal SCLK2', the third scan clock signal SCLK3', and the fourth scan clock signal SCLK4' generated in the first frame section Frame1 and the scan signal are substantially the same as described with reference to

[0131] For example, when the display device 100 is driven at a driving frequency of 120 Hz according to the first mode (refer to Figure 1 )hour, Figure 5A The first segment 1H and Figure 6 The sixth segment 1H' may have a length corresponding to 2.8 μs. In addition, when the display device 100 is driven at a driving frequency of 60 Hz according to the second mode (refer to Figure 1 )hour, Figure 5A The first segment 1H and Figure 6 The sixth segment 1H′ may have a length corresponding to 5.5 μs.

[0132] In this case, according to Figure 6 Comparative example, when the display device 100 is driven at 120 Hz according to the first mode (refer to Figure 1 ) can be used according to the high resolution large size display panel 110 (refer to Figure 1 ) high-speed driving method to drive the display device 100 (refer to Figure 1 However, since the length of the sixth segment 1H' cannot be sufficiently ensured (for example, 2.8 μs), the length of the segment to which the scan signal is supplied and / or the length of the segment to which the data signal is written (for example, 1.69 μs) cannot be sufficiently ensured. Therefore, degradation of image quality may occur.

[0133] In addition, when the display device 100 is driven at 60 Hz according to the second mode (refer to Figure 1 ), the length of the sixth segment 1H' is sufficiently ensured (e.g., 5.5 μs), so that the length of the segment to which the scan signal is supplied and / or the length of the segment to which the data signal is written (e.g., 4.18 μs) can be sufficiently ensured. However, according to the driving method of the second mode, since the display device 100 (see Figure 1 ) is driven at a low driving frequency, so the driving method of the second mode may not be suitable for a high-resolution large-size display panel 110 (refer to Figure 1 ).

[0134] In this case, as referenced Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B As described above, in the driving method in which the pixels connected to the even-numbered emission control lines E2, E4, ..., E2n, ..., and E2p are maintained in the non-light-emitting state in the first frame segment Frame1 and the pixels connected to the odd-numbered emission control lines E1, E3, ..., E2n-1, ..., and E2p-1 are maintained in the non-light-emitting state in the second frame segment Frame2, although the display device 100 is driven at 120 Hz according to the first mode (see FIG. Figure 1), but the data driver 160 (see Figure 1 ) can supply only data signals corresponding to pixels located on odd-numbered horizontal lines in the first frame segment Frame1, and only data signals corresponding to pixels located on even-numbered horizontal lines in the second frame segment Frame2. Therefore, the length of the segment in which the data signal is written can be sufficiently ensured. Therefore, it is possible to realize the display of a large-size display panel 110 (refer to FIG. 1 ) suitable for high-resolution display. Figure 1 ) high-speed driving method to drive the display device 100 (refer to Figure 1 ), and it is also possible to sufficiently ensure the length of the segment in which the scan signal is supplied and / or the length of the segment in which the data signal is written.

[0135] Figure 7A and Figure 7B Is used to explain Figure 2 1 and 2 are waveform diagrams of a driving method for a first pixel and a second pixel.

[0136] Reference Figure 4A 、 Figure 5A and Figure 7A , Figure 7A Shown is a reference Figure 4A and Figure 5A The first emission control signal of the first emission control line E2n-1 and the second emission control signal of the second emission control line E2n in the first frame segment Frame1 described, the scanning signals of the scan lines S2n-3, S2n-2, S2n-1 and S2n, and the data signals DS[2n-5], DS[2n-3], DS[2n-1] and DS[2n+1] of the data line Dm.

[0137] Similarly, refer to Figure 4B 、 Figure 5B and Figure 7B , Figure 7B Shown is a reference Figure 4B and Figure 5B The first emission control signal of the first emission control line E2n-1 and the second emission control signal of the second emission control line E2n in the second frame segment Frame2 are described, the scanning signals of the scan lines S2n-3, S2n-2, S2n-1 and S2n, and the data signals DS[2n-4], DS[2n-2] and DS[2n] of the data line Dm.

[0138] First, refer to Figure 2 and Figure 7AAt the fifth time point t5, the first emission control signal supplied to the 2n-1th emission control line E2n-1 may be changed from an on-level to an off-level. Thus, the fifth transistor TR5 and the sixth transistor TR6 of the first pixel PX1 may be turned off. In this case, the current flowing from the first power supply VDD to the second power supply VSS may be controlled to prevent light emission from the light-emitting element LD.

[0139] At the sixth time point t6, the scan signal supplied to the 2n-3 th scan line S2n-3 may be changed from the off level to the on level. Thus, the fourth transistor TR4 of the first pixel PX1 may be turned on. In this case, the initialization power supply Vint may be applied to the gate electrode (i.e., the third node N3) of the first transistor TR1 of the first pixel PX1 to initialize the gate electrode of the first transistor TR1.

[0140] At the seventh time point t7, the scan signal supplied to the 2n-3 th scan line S2n-3 may be changed from the on level to the off level, and thus the fourth transistor TR4 of the first pixel PX1 may be turned off.

[0141] At the eighth time point t8, the scan signal supplied to the 2n-1th scan line S2n-1 may be changed from the off level to the on level. Therefore, the second transistor TR2 of the first pixel PX1 may be turned on to transmit the data signal DS[2n-1] supplied through the mth data line Dm to the second node N2.

[0142] The third transistor TR3 of the first pixel PX1 may be turned on according to the scan signal of the on level supplied to the 2n-1th scan line S2n-1. The turned-on third transistor TR3 may connect the first transistor TR1 in the form of a diode.

[0143] In addition, the seventh transistor TR7 of the first pixel PX1 can be turned on according to the scan signal of the on level supplied to the 2n-1th scan line S2n-1. The turned-on seventh transistor TR7 can transmit the initialization power Vint to the anode of the light emitting element LD to initialize the light emitting element LD.

[0144] At the ninth time point t9, the scan signal supplied to the 2n-1th scan line S2n-1 may be changed from the on level to the off level, thereby turning off the second transistor TR2, the third transistor TR3, and the seventh transistor TR7 of the first pixel PX1.

[0145] At the tenth time point t10, the first emission control signal supplied to the 2n-1th emission control line E2n-1 may be changed from an off level to an on level. Thus, the fifth transistor TR5 and the sixth transistor TR6 of the first pixel PX1 may be turned on. A driving current may be formed between the first power supply VDD and the second power supply VSS, so that the light emitting element LD of the first pixel PX1 may emit light at a grayscale corresponding to the data signal DS[2n-1].

[0146] In the first frame segment Frame1, the second emission control signal provided to the 2nth emission control line E2n may be a signal (or a fourth emission control signal) maintained at the cut-off level. Therefore, the fifth transistor TR5 and the sixth transistor TR6 of the second pixel PX2 may be maintained in the cut-off state. Therefore, the second pixel PX2 may maintain a non-luminous state in the first frame segment Frame1.

[0147] Next, refer to Figure 2 and Figure 7B In the second frame segment Frame2, the first emission control signal provided to the 2n-1th emission control line E2n-1 may be a signal (or a third emission control signal) maintained at the cut-off level. Therefore, the fifth transistor TR5 and the sixth transistor TR6 of the first pixel PX1 may remain in the cut-off state. Therefore, the first pixel PX1 may remain in the non-luminous state in the second frame segment Frame2.

[0148] In the second frame segment Frame2, the second pixel PX2 may receive the second emission control signal through the 2n-th emission control line E2n, the 2n-2-th scan line S2n-2, and the 2n-th scan line S2n. Since the remaining operations except for the above operations are substantially the same as those of the first pixel PX1 in the first frame segment Frame1, the repeated description will not be repeated.

[0149] Therefore, the first pixel PX1 can emit light at a grayscale corresponding to the data signal DS[2n-1] provided by the m-th data line Dm based on the first emission control signal supplied to the 2n-1th emission control line E2n-1 and the scan signals supplied to the 2n-3th scan line S2n-3 and the 2n-1th scan line S2n-1 in the first frame segment Frame1. In addition, the first pixel PX1 does not emit light based on the first emission control signal (or the third emission control signal) supplied to the 2n-1th emission control line E2n-1 and maintained at the cut-off level in the second frame segment Frame2. Similarly, the second pixel PX2 does not emit light based on the second emission control signal (or the fourth emission control signal) supplied to the 2nth emission control line E2n and maintained at the cut-off level in the first frame segment Frame1. In addition, the second pixel PX2 can emit light at a grayscale corresponding to the data signal DS[2n] provided through the mth data line Dm based on the second emission control signal provided to the 2nth emission control line E2n and the scan signal provided to the 2n-2th scan line S2n-2 and the 2nth scan line S2n in the second frame segment Frame2.

[0150] As reference Figure 2 、 Figure 7A and Figure 7B The display device 100 including the first emission driver 140 and the second emission driver 150 (see Figure 1 ) can independently drive pixels located on odd-numbered horizontal lines (e.g., first pixels PX1) and pixels located on even-numbered horizontal lines (e.g., second pixels PX2) in the first frame segment Frame1 or the second frame segment Frame2. Therefore, even when the display device 100 is driven according to the high-speed driving method (refer to Figure 1 ), the length of the segment in which the scan signal is supplied and / or the length of the segment in which the data signal is written can also be sufficiently ensured.

[0151] Figure 8 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention.

[0152] Reference Figure 1 and Figure 8 , Figure 8 The driving method of the display device can be Figure 1 The display device 100 performs

[0153] Figure 8The driving method can drive the display device 100 including the display panel 110, the emission drivers 140 and 150, and the scan driver 130. The display panel 110 includes a scan line S, an emission control line E, and pixels PX1 and PX2 connected to the scan line S and the emission control line E. Here, the display device 100 can be connected to Figure 1 The display devices 100 are substantially the same.

[0154] according to Figure 8 For the driving method, refer to Figure 8 , in a first frame segment (eg, an odd-numbered frame segment or an even-numbered frame segment), the first transmit driver (eg, Figure 1 The first emission driver 140 of the embodiment sequentially supplies a first emission control signal to odd-numbered emission control lines (S810).

[0155] Afterwards, according to Figure 8 In the driving method, in a second frame segment (eg, an even-numbered frame segment or an odd-numbered frame segment) continuous with the first frame segment, the second emission driver (eg, Figure 1 The second emission driver 150) sequentially supplies the second emission control signal to the even-numbered emission control lines (S820).

[0156] Here, the scan driver (e.g. Figure 1 The scan driver 130 may sequentially provide a scan signal to the scan lines in each of the first frame section and the second frame section.

[0157] Figure 9A is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention in a first frame section. Figure 9B is a flowchart illustrating a method of driving a display device according to an exemplary embodiment of the present invention in a second frame section.

[0158] Reference Figure 1 、 Figure 9A and Figure 9B , Figure 9A and Figure 9B The driving method of the display device can be Figure 1 The display device 100 performs

[0159] First, according to Figure 9AIn the driving method, in the first frame segment, the first emission start signal and the fourth emission start signal and the first emission clock signal, the second emission clock signal, the third emission clock signal and the fourth emission clock signal can be generated by the timing controller (S910). Here, the configuration of the timing controller for generating the first emission start signal and the fourth emission start signal and the first emission clock signal, the second emission clock signal, the third emission clock signal and the fourth emission clock signal can be the same as that of the reference Figure 1 、 Figure 3 、 Figure 4A and Figure 4B The configuration of the timing controller 120 described for generating the first emission start signal FLM1 having a cut-off level pulse, the second emission start signal FLM2 (or the fourth emission start signal) maintained at the cut-off level during the first frame segment Frame1, and the first emission clock signal ECLK1, the second emission clock signal ECLK2, the third emission clock signal ECLK3 and the fourth emission clock signal ECLK4 is the same.

[0160] Afterwards, according to Figure 9A In the driving method, in the first frame segment, the first emission control signal can be sequentially provided to the first emission control line through the first emission driver based on the first emission start signal and the first emission clock signal and the third emission clock signal, and the fourth emission control signal can be provided to the second emission control line through the second emission driver based on the fourth emission start signal and the second emission clock signal and the fourth emission clock signal (S920). Here, the operations of the first emission driver and the second emission driver in the first frame segment can be the same as those in the reference Figure 1 、 Figure 3 、 Figure 4A and Figure 4B The operations of the first emission driver 140 and the second emission driver 150 are described to be substantially the same.

[0161] Afterwards, according to Figure 9A In a driving method, in a first frame segment, the first pixel may be controlled to emit light at a grayscale corresponding to the first data signal, and the second pixel may be controlled not to emit light based on a fourth emission control signal (S930). Here, the configuration in which the first pixel emits light and the second pixel does not emit light in the first frame segment may be the same as that in the reference Figure 2 and Figure 7A The described configuration in which the first pixel PX1 emits light and the second pixel PX2 does not emit light in the first frame section Frame1 is substantially the same.

[0162] Next, according to Figure 9BIn the driving method, in the second frame segment, the second emission start signal and the third emission start signal and the first emission clock signal, the second emission clock signal, the third emission clock signal and the fourth emission clock signal can be generated by the timing controller (S940). Here, the configuration in which the second emission start signal and the third emission start signal and the first emission clock signal, the second emission clock signal, the third emission clock signal and the fourth emission clock signal are generated by the timing controller can be the same as that in the reference Figure 1 、 Figure 3 、 Figure 4A and Figure 4B The configuration described in which, during the second frame segment Frame2, the first emission start signal FLM1 (or the third emission start signal) maintained at the cut-off level, the second emission start signal FLM2 having a cut-off level pulse, and the first emission clock signal ECLK1, the second emission clock signal ECLK2, the third emission clock signal ECLK3 and the fourth emission clock signal ECLK4 are generated by the timing controller 120 is basically the same.

[0163] Afterwards, according to Figure 9B In the driving method, in the second frame segment, the third emission control signal may be provided to the first emission control line through the first emission driver based on the third emission start signal and the first emission clock signal and the third emission clock signal, and the second emission control signal may be provided to the second emission control line through the second emission driver based on the second emission start signal and the second emission clock signal and the fourth emission clock signal (S950). Here, the operations of the first emission driver and the second emission driver in the second frame segment may be the same as those in the reference Figure 1 、 Figure 3 、 Figure 4A and Figure 4B The operations of the first emission driver 140 and the second emission driver 150 are described to be substantially the same.

[0164] Afterwards, according to Figure 9B In the driving method, in the second frame segment, the first pixel may be controlled not to emit light based on the third emission control signal, and the second pixel may be controlled to emit light at a grayscale corresponding to the second data signal (S960). Here, the configuration in which the first pixel does not emit light and the second pixel emits light in the second frame segment may be the same as that in the reference Figure 2 and Figure 7B The described configuration in which the first pixel PX1 does not emit light and the second pixel PX2 emits light in the second frame section Frame2 is substantially the same.

[0165] The display device according to the present invention can independently drive pixels located on odd-numbered horizontal lines and pixels located on even-numbered horizontal lines in the first frame segment or the second frame segment. Therefore, even when the display device is driven according to a high-speed driving method, the length of the segment to which the scan signal is supplied and / or the length of the segment to which the data signal is written can be sufficiently ensured.

[0166] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, wherein: The display device includes: A display panel comprising scan lines, emission control lines, and pixels connected to the scan lines and the emission control lines; a first emission driver configured to sequentially provide a first emission control signal to odd-numbered emission control lines among the emission control lines in a first frame section; a second emission driver configured to sequentially provide a second emission control signal to even-numbered emission control lines among the emission control lines in a second frame section continuous with the first frame section; and a scan driver configured to sequentially supply a scan signal to the scan lines in each of the first frame section and the second frame section, The display device further includes a timing controller configured to generate a first start signal in the first frame segment, generate a second start signal in the second frame segment, and generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in the first frame segment and the second frame segment. The first start signal has a cutoff level pulse in the first frame section, and the second start signal has a cutoff level pulse in the second frame section; The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same period, the second clock signal is shifted from the first clock signal by a quarter period, the third clock signal is shifted from the second clock signal by a quarter period, and the fourth clock signal is shifted from the third clock signal by a quarter period; The first emission driver generates the first emission control signal based on the first start signal and the first clock signal and the third clock signal; The second emission driver generates the second emission control signal based on the second start signal and the second clock signal and the fourth clock signal; A pulse width of the off-level pulse of the first start signal in the first frame section and a pulse width of the off-level pulse of the second start signal in the second frame section are each q times the period, where q is an integer of 2 or greater.

2. The display device according to claim 1, wherein the first emission driver providing a third emission control signal to the odd-numbered emission control lines in the second frame section; and The second emission driver provides a fourth emission control signal to the even-numbered emission control lines in the first frame section.

3. The display device according to claim 2, wherein: The timing controller further generates a third start signal in the second frame segment, and further generates a fourth start signal in the first frame segment; The third start signal is maintained at the cutoff level during the second frame section, and the fourth start signal is maintained at the cutoff level during the first frame section; The first emission driver generates the third emission control signal based on the third start signal and the first and third clock signals; and The second emission driver generates the fourth emission control signal based on the fourth start signal and the second and fourth clock signals.

4. The display device according to claim 3, wherein The pixels include: a first pixel connected to the 2n-1th emission control line among the emission control lines and the 2n-3th scan line and the 2n-1th scan line among the scan lines, where n is a natural number; and The second pixel is connected to the 2nth emission control line among the emission control lines and the 2n-2nd scan line and the 2nth scan line among the scan lines.

5. The display device according to claim 4, wherein The scan signal supplied to the 2n-1th scan line and the scan signal supplied to the 2nth scan line overlap in some sections. The display device according to claim 5 , wherein: supplying the scan signal to the 2n-3 scan line and the 2n-1 scan line within a section of the first frame section in which the first emission control signal is supplied to the 2n-1th emission control line; and In a section of the second frame section in which a second emission control signal is supplied to the 2n-th emission control line, the scan signal is supplied to the 2n-2-th scan line and the 2n-th scan line.

7. The display device according to claim 6, wherein: The display device further includes a data driver configured to provide a data signal to a data line in each of the first frame section and the second frame section. The first pixel and the second pixel are connected to the mth data line among the data lines, where m is a natural number.

8. The display device according to claim 7, wherein: The data driver provides a first data signal to the mth data line in a section of the first frame section in which the scan signal is provided to the 2n-1th scan line, and provides a second data signal to the mth data line in a section of the second frame section in which the scan signal is provided to the 2nth scan line.

9. The display device according to claim 8, wherein The first pixel emits light at a grayscale corresponding to the first data signal in the first frame segment based on the first emission control signal supplied to the 2n-1th emission control line and the scanning signal supplied to the 2n-1th scanning line, and does not emit light in the second frame segment based on the third emission control signal supplied to the 2n-1th emission control line.

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