Data driving device and gamma voltage circuit for driving pixels arranged in display

Abstract

The present invention provides a data driving device and a gamma voltage circuit for driving pixels arranged in a display. The embodiment can reduce the area of ​​a digital-to-analog converter circuit by inserting one reference voltage and generating a plurality of gamma voltages.

Description

Technical Field

[0001] The present embodiment relates to a technology for generating a gamma voltage for outputting image data in a data driving device of a display device. Background Art

[0002] The display device may include a panel, a gate driving device, a data driving device, and a timing controller. The data driving device may receive image data from a data processing device, may convert the image data into an analog signal (eg, a data voltage), and may send the analog signal to the panel.

[0003] The data driving device may include a digital-to-analog converter (DAC) that converts the image data into an analog signal. The digital-to-analog converter may output one of the gamma voltages as the analog signal according to the image data.

[0004] The digital-to-analog converter can select and output one of a plurality of gamma voltages in response to image data having a specific number of bits. Therefore, as the number of bits of the image data increases, the number of gamma voltages increases, and a plurality of elements for selecting the gamma voltages may be required. As the number of elements increases, the area occupied by the digital-to-analog converter in the data driving device may also increase.

[0005] For example, to process n-bit image data (n is a natural number of 1 or greater), 2 (n+1) - 2 selection elements. In the case of 10-bit image data, each DAC may require 2046 elements.

[0006] In this regard, the present embodiment provides a gamma voltage generation technology that can reduce the area of ​​a digital-to-analog converter while maintaining the existing image data processing capability. Summary of the invention

[0007] In this context, an object of the present embodiment is to provide a technique for generating a plurality of gamma voltages by inserting one reference voltage.

[0008] Another object of the present embodiment is to provide a technology for providing a bias current through a current mirror and generating a plurality of gamma voltages using the mirror current.

[0009] In order to achieve the above-mentioned purpose, an embodiment provides a data driving device for driving pixels arranged in a display panel, the data driving device comprising: a first selection circuit configured to receive a portion of bits of image data for driving the pixels, and select one of a plurality of voltages included in a first gamma reference voltage as a second gamma reference voltage according to the portion of bits; a second voltage generating unit configured to generate a plurality of gamma voltages by increasing or decreasing the second gamma reference voltage; and a second selection circuit configured to receive remaining bits of the image data, and select a gamma voltage from the plurality of gamma voltages as a data voltage for driving the pixels according to the remaining bits.

[0010] The data driving device may include a buffer configured to receive the one gamma voltage from the second selection circuit, amplify the one gamma voltage, and output the amplified voltage as the data voltage.

[0011] In the data driving device, the second voltage generating unit is configured to increase or decrease the second gamma reference voltage using a mirror current.

[0012] The data driving device may include a bias unit configured to provide a bias current to the second voltage generating unit by generating a reference current and mirroring the reference current to the second voltage generating unit.

[0013] In the data driving device, the bias unit may receive a portion of the voltages included in the first gamma reference voltage, and may generate the reference current through the received voltages.

[0014] In the data driving device, the second voltage generating unit may include a plurality of resistor arrays, and the second gamma reference voltage may be increased through one resistor array and may be decreased through another resistor array.

[0015] In the data driving device, the second gamma reference voltage may be applied to a node where the one resistor array and the other resistor array meet.

[0016] Another embodiment provides a gamma voltage circuit for generating a gamma voltage for image data including k upper bits and m lower bits, k being a natural number and m being a natural number, the gamma voltage circuit comprising: a resistor array including a plurality of resistors and a node formed by the plurality of resistors connected between a high power supply voltage and a low power supply voltage, and configured to form a node voltage at the node by distributing the high power supply voltage and the low power supply voltage to the plurality of resistors; a switch circuit configured to receive the node voltage and output a voltage selected from the node voltage according to the k upper bits; and a voltage generating circuit configured to receive the selected one voltage, and generating a plurality of gamma voltages from a selected voltage; and a bias unit comprising a bias resistor array, the bias resistor array being configured to receive a first node voltage and a second node voltage from the resistor array and to generate a current through a difference between the first node voltage and the second node voltage, and the bias unit being configured to mirror the current to the voltage generating circuit, wherein the voltage generating circuit may include a voltage generating resistor array for generating the plurality of gamma voltages, and is configured to increase or decrease a selected voltage through the current mirrored by the voltage generating resistor array and the bias unit, thereby generating the plurality of gamma voltages.

[0017] In the gamma voltage circuit, the bias resistor array and the voltage generating resistor array may have the same characteristics.

[0018] In the gamma voltage circuit, the bias resistor array may have characteristics different from characteristics of a portion of the resistor array.

[0019] In the gamma voltage circuit, the bias resistor array may have characteristics different from characteristics of a resistor connected between a first node forming the first node voltage and a second node forming the second node voltage.

[0020] In the gamma voltage circuit, wherein the bias unit may include a buffer configured to receive the first node voltage and the second node voltage and apply the first node voltage and the second node voltage to the bias resistor array.

[0021] In the gamma voltage circuit, the buffer may apply the first node voltage and the second node voltage to both ends of the bias resistor array.

[0022] In the gamma voltage circuit, the voltage generating resistor array may include an upper resistor array configured to increase the selected one voltage and a lower resistor array configured to decrease the selected one voltage.

[0023] In the gamma voltage circuit, a selected one of the voltages may be applied to a node where the upper resistor array and the lower resistor array meet.

[0024] As described above, according to this embodiment, the number of selection elements of the digital-to-analog converter can be reduced, thereby reducing the area occupied by the digital-to-analog converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a block diagram of a display device according to an embodiment;

[0027] Figure 2 is a block diagram of a data driven device;

[0028] Figure 3 is a block diagram of a data driving apparatus according to an embodiment;

[0029] Figure 4 is a circuit diagram of a data driving device according to an embodiment;

[0030] Figure 5 is a diagram showing an operation example of a data driving device for 4-bit image data according to an embodiment; and

[0031] Figure 6 It shows that according to Figure 5 A table of the second gamma reference voltage, the gamma voltage and the data voltage is shown. DETAILED DESCRIPTION

[0032] Figure 1 is a block diagram of a display device according to an embodiment.

[0033] Reference Figure 1 The display device 100 may include a panel 110, a data driving device 120, a gate driving device 130, a data processing device 140, and the like.

[0034] The panel 110 may have a plurality of data lines DL and a plurality of gate lines GL arranged therein, and may have a plurality of pixels arranged therein. A pixel may include a plurality of sub-pixels SP. Here, the sub-pixels may be R (red), G (green), B (blue), W (white), etc. One pixel may include sub-pixels SP of RGB, sub-pixels SP of RGBG, sub-pixels SP of RGBW, etc. Hereinafter, for ease of description, description will be made under the assumption that one pixel includes sub-pixels of RGB.

[0035] The data driving device 120 , the gate driving device 130 , and the data processing device 140 generate signals for displaying an image on the panel 110 .

[0036] The gate driving device 130 may provide a gate driving signal of an on voltage or an off voltage to the gate line GL. If the gate driving signal of the on voltage is provided to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. In addition, if the gate driving signal of the off voltage is provided to the sub-pixel SP, the connection between the sub-pixel SP and the data line DL is released. The gate driving device 130 may be referred to as a "gate driver".

[0037] The data driving device 120 may provide a data voltage Vdata to the sub-pixel SP through the data line DL. The data voltage Vdata provided to the data line DL may be provided to the sub-pixel SP according to a gate driving signal. The data driving device 120 may be referred to as a "source driver".

[0038] The data driving device 120 may generate a plurality of gamma voltages and may output a data voltage Vdata corresponding to the image data RGB among the plurality of gamma voltages. The data driving device 120 may include a digital-to-analog converter and a buffer. The digital-to-analog converter may select one of the plurality of gamma voltages in response to the image data RGB and may output the selected one voltage to the buffer. The buffer may amplify the selected one voltage and may provide it to the data line DL.

[0039] The data driving device 120 may include at least one integrated circuit, and the at least one integrated circuit may be connected to a bonding pad of the panel 110 by a tape automated bonding (TAB) type or a chip on glass (COG) type, or may be directly formed on the panel 110, or may be formed to be integrated on the panel 110 in some embodiments. In addition, the data driving device 120 may be implemented by a chip on film (COF) type.

[0040] The data processing device 140 may provide control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 may send a gate control signal GCS for starting scanning to the gate driving device 130. In addition, the data processing device 140 may output image data RGB to the data driving device 120. In addition, the data processing device 140 may send a data control signal DCS to each sub-pixel SP for controlling the data driving device 120 to provide a data voltage Vdata. The data processing device 140 may be referred to as a "timing controller", and the data driving device 120 may be referred to as a "source driver".

[0041] Figure 2 It is a block diagram of a general data driving device.

[0042] Reference Figure 2 The data driving device 20 may include a gamma voltage circuit 21 and a channel CH. In addition, a digital-to-analog converter DAC and a buffer BF may be included in the channel CH.

[0043] The data driving device 20 may select one of the gamma voltages Vg and amplify the selected voltage, thereby outputting a data voltage Vdata.

[0044] The gamma voltage circuit 21 can generate a gamma voltage Vg. The gamma voltage circuit 21 can receive two or more power supply voltages, can divide the two or more power supply voltages using a resistor array (also referred to as a "resistor string"), and can generate a gamma voltage Vg. A series of resistor arrays can be referred to as a "voltage divider". Multiple resistors constituting a series of resistor arrays form nodes at various connection points, and gamma voltages Vg can be formed at these nodes. Since these nodes are formed at various connection points of multiple resistors, the gamma voltage Vg can include multiple voltages.

[0045] The digital-to-analog converter DAC of the channel CH may generate a data voltage Vdata from the gamma voltage Vg. The digital-to-analog converter DAC may select one of a plurality of voltages included in the gamma voltage (Vg) in response to the image data RGB. The digital-to-analog converter DAC may output the selected voltage as the data voltage Vdata. The digital-to-analog converter DAC may include a plurality of switching elements for selecting one of the plurality of voltages.

[0046] The gamma voltage Vg may include a plurality of voltages equal to the number of binary signals generated by the number of bits of the image data RGB. For example, if the data driving device 20 processes 8-bit (n=8) image data RGB, the gamma voltage circuit 21 may generate a plurality of voltages including 256 (2 8 ) voltages of the gamma voltage Vg. In addition, the digital-to-analog converter DAC may need 510 (=256×2-2) switching elements capable of selecting 256 voltages. If the number of bits of the image data RGB increases, the number of resistor arrays for generating the gamma voltage Vg and the number of switching elements for selecting the gamma voltage Vg may increase, thereby increasing the area occupied by the data driving device 20.

[0047] The buffer BF of the channel CH may receive and amplify the data voltage Vdata, and may apply the amplified data voltage Vdata to the data line.

[0048] Figure 3 is a block diagram of a data driving device according to an embodiment.

[0049] Reference Figure 3The data driving device 120 according to the embodiment may include a first voltage generating unit 310-V, a first selection circuit 310-S, a second voltage generating unit 320-V, a second selection circuit 320-S, an output circuit 330, and a bias unit 340. Here, the first selection circuit 310-S and the second selection circuit 320-S may correspond to a digital-to-analog converter DAC.

[0050] The data driving device 120 may perform the voltage generation process several times to generate the data voltage Vdata. For example, the data driving device 120 may perform a first voltage distribution of a high power supply voltage and a low power supply voltage during a first voltage generation process, thereby generating a first voltage. Subsequently, the data driving device 120 may perform a voltage change (increase or decrease the voltage) on the first voltage during a second voltage generation process, thereby generating a second voltage. The data driving device 120 may generate and output the data voltage Vdata from the second voltage.

[0051] The first voltage generating unit 310-V may receive a high power voltage and a low power voltage and may distribute the high power voltage and the low power voltage to generate and output a first gamma reference voltage Vg_ref1. The first voltage generating unit 310-V may include a resistor array including a series of resistors for voltage distribution.

[0052] The number of voltages generated by the first voltage generating unit 310-V through voltage distribution may be determined according to the bits of the image data RGB. For example, if n-bit image data RGB (n is a natural number of 1 or greater) is processed, the total number of voltages generated by the first voltage generating unit 310-V may be 2. n The first voltage generating unit 310-V can output 2 n Multiple voltages among the voltages are used as the first gamma reference voltage Vg_ref1.

[0053] The number of voltages included in the first gamma reference voltage Vg_ref1 may be determined according to the number of bits in the image data RGB received by the first selection circuit 310-S. Since the first selection circuit 310-S receives only a portion of the bits of the image data RGB, the number of voltages included in the first gamma reference voltage Vg_ref1 may also be determined according to the portion of the bits.

[0054] For example, the n-bit image data RGB may include k-bit image data RGB_k and m-bit image data RGB_m. n=k+m, where "n", "k", and "m" may be natural numbers of 1 or greater. If the first selection circuit 310-S receives only the k-bit image data RGB_k, the first gamma reference voltage Vg_ref1 may include 2 k A voltage.

[0055] The first selection circuit 310-S may select and output the second gamma reference voltage Vg_ref2 from the first gamma reference voltage Vg_ref1. For example, the first selection circuit 310-S may include a switch array including a plurality of switches (e.g., transistors). Each switch may select one of a plurality of voltages included in the first gamma reference voltage Vg_ref1, and may output the selected one voltage as the second gamma reference voltage Vg_ref2.

[0056] The first selection circuit 310-S may receive a portion of the bits of the image data RGB, and may select and output the second gamma reference voltage Vg_ref2 from the first gamma reference voltage Vg_ref1 in response to the portion of the bits. For example, if the first selection circuit 310-S receives the k-bit image data RGB_k among the k+m-bit image data RGB, the first selection circuit 310-S may include 2 (k+1) -2 switches. The first selection circuit 310-S can select 2 of the first gamma reference voltage Vg_ref1. k one of the voltages.

[0057] The second voltage generating unit 320-V may receive the second gamma reference voltage Vg_ref2, and may generate and output a gamma voltage Vg including a plurality of voltages from the second gamma reference voltage Vg_ref2. The second voltage generating unit 320-V may receive one voltage selected from the first gamma reference voltage Vg_ref1 as the second gamma reference voltage Vg_ref2, and may increase or decrease the second gamma reference voltage Vg_ref2, thereby generating and outputting a gamma voltage Vg including a plurality of voltages.

[0058] The second voltage generating unit 320-V may increase or decrease the second gamma reference voltage Vg_ref2 using the mirror current to generate the gamma voltage Vg. The second voltage generating unit 320-V may output the increased voltage or the decreased voltage as the gamma voltage Vg to the second selecting circuit 320-S.

[0059] The second voltage generating unit 320 -V may include a plurality of resistor arrays. The second voltage generating unit 320 -V may increase the second gamma reference voltage Vg_ref2 through one resistor array, and may decrease the second gamma reference voltage Vg_ref2 through another resistor array.

[0060] Here, the second gamma reference voltage Vg_ref2 may be applied to a node where one resistor array and another resistor array meet. The one resistor array may generate an increased voltage of the second gamma reference voltage Vg_ref2 according to the mirror current. The other resistor array may generate a decreased voltage of the second gamma reference voltage Vg_ref2 according to the mirror current.

[0061] The bias unit 340 may generate a reference current and may mirror the reference current to the second voltage generating unit 320-V, thereby providing a bias current to the second voltage generating unit 320-V. The bias current may be provided in the form of a mirror current of the second voltage generating unit 320-V.

[0062] The bias unit 340 may receive a portion of a voltage obtained by dividing the high power voltage and the low power voltage from the first voltage generating unit 310 -V, and may generate a reference current through the received voltage.

[0063] The second voltage generating unit 320-V may generate the gamma voltage Vg to include a plurality of voltages, and may determine the number of voltages included in the gamma voltage Vg according to the number of bits in the image data RGB received by the second selection circuit 320-S. Since the second selection circuit 320-S receives only a portion of the bits of the image data RGB, the number of voltages included in the gamma voltage Vg may also be determined according to the portion of the bits.

[0064] For example, the n-bit image data RGB may include k-bit image data RGB_k and m-bit image data RGB_m. n=k+m, where "n", "k" and "m" may be natural numbers of 1 or more. If the second selection circuit 320-S receives only the m-bit image data RGB_m, the gamma voltage Vg may include 2 m A voltage.

[0065] The second selection circuit 320-S may receive remaining bits of the image data that are not received by the first selection circuit 310-S, and may select and output one of a plurality of voltages included in the gamma voltage Vg in response to the remaining bits, thereby generating a data voltage for the image data.

[0066] The second selection circuit 320-S may select and output the data voltage Vdata from the gamma voltage Vg. For example, the second selection circuit 320-S may include a switch array including a plurality of switches (e.g., transistors). Each switch may select one of a plurality of voltages included in the gamma voltage Vg, and may output the selected one voltage as the data voltage Vdata.

[0067] For example, if the second selection circuit 320-S receives the m-bit image data RGB_m among the k+m-bit image data RGB, the second selection circuit 320-S may include 2 (m+1) -2 switches. The second selection circuit 320-S can select 2 switches included in the gamma voltage Vg. m One of the voltages.

[0068] The output circuit 330 may amplify the data voltage Vdata and may apply it to the data line. The output circuit 330 may include a buffer for amplifying the data voltage Vdata.

[0069] Figure 4 is a circuit diagram of a data driving device according to an embodiment.

[0070] Reference Figure 4 , a circuit of a first voltage generating unit 310 -V, a second voltage generating unit 320 -V and a bias unit 340 of the data driving device 120 is shown.

[0071] Although the gamma voltages Vg may include voltages of different polarities, the following description will be made assuming that the gamma voltages Vg include only positive voltages.

[0072] The first voltage generating unit 310-V may include a resistor array 410. The resistor array 410 may include a plurality of resistors connected in series with each other. In addition, the resistor array 410 may include a node formed by a plurality of resistors connected between a high power supply voltage VH and a low power supply voltage VL. The node may include a point where one resistor meets another resistor, an end of the resistor to which the high power supply voltage VH is applied, or an end of the resistor to which the low power supply voltage VL is applied. Figure 4 , the value of the resistor included in the first voltage generating unit 310 -V may be represented as “R”.

[0073] The resistor array 410 may distribute the high power supply voltage VH and the low power supply voltage VL to a plurality of resistors connected in series, thereby forming a node voltage at each node. The number of node voltages may vary according to the number of bits of the image data RGB.

[0074] For example, if the image data RGB has 4 bits, the resistor array 410 can generate 16 node voltages V1 to V16 and can include 15 resistors connected in series with each other. Since the high power supply voltage VH and the low power supply voltage VL must be divided by resistors, the resistors can have the same resistance value R.

[0075] The first voltage generating unit 310-V may output a portion of the 16 node voltages V1 to V16 as the first gamma reference voltage Vg_ref1. The voltage output from the first voltage generating unit 310-V may be different according to the number of bits received by the first selection circuit 310-S in the image data RGB. The number of node voltages output to the first gamma reference voltage Vg_ref1 may be changed according to the number of bits of the image data RGB received by the first selection circuit 310-S.

[0076] For example, if the k-bit image data RGB_k received by the first selection circuit 310-S has 1 bit, the first voltage generation unit 310-V may output two node voltages as the first gamma reference voltage Vg_ref1. If the k-bit image data RGB_k received by the first selection circuit 310-S has 2 bits, the first voltage generation unit 310-V may output four node voltages as the first gamma reference voltage Vg_ref1.

[0077] The first selection circuit 310-S may receive a first gamma reference voltage Vg_ref1 and may output a second gamma reference voltage Vg_ref2. Among the node voltages received as the first gamma reference voltage Vg_ref1 from the first voltage generating unit 310-V, the first selection circuit 310-S may select only one node voltage. The first selection circuit 310-S may include a switch circuit to select only one node voltage. The first selection circuit 310-S may include a plurality of switches corresponding to the k-bit image data RGB_k to be received. Among the node voltages received as the first gamma reference voltage Vg_ref1 through the switches, the first selection circuit 310-S may select only one node voltage as the second gamma reference voltage Vg_ref2.

[0078] The second voltage generating unit 320-V may include a voltage generating circuit 420. The voltage generating circuit 420 may receive the second gamma reference voltage Vg_ref2 and may generate a gamma voltage Vg from the second gamma reference voltage Vg_ref2. The gamma voltage Vg may include a plurality of voltages.

[0079] The voltage generating circuit 420 may include a resistor array 421. The resistor array 421 may receive the second gamma reference voltage Vg_ref2, and may generate a gamma voltage Vg using the second gamma reference voltage Vg_ref2 and a current Imir flowing through the resistor array 421. The resistor array 421 may increase or decrease the second gamma reference voltage Vg_ref2, thereby generating a plurality of voltages, and the gamma voltage Vg may include a plurality of generated voltages.

[0080] The current Imir may be provided from the bias unit 340. The bias unit 340 may mirror the reference current Iref to the voltage generating circuit 420 of the second voltage generating unit 320-V, thereby providing the current Imir.

[0081] The second selection circuit 320-S may receive the gamma voltage Vg from the second voltage generating unit 320-V. The second selection circuit 320-S may select one of a plurality of voltages included in the gamma voltage Vg in response to the m-bit image data RGB_m. Similar to the first selection circuit 310-S, the second selection circuit 320-S may further include switches corresponding to the m-bit image data RGB_m, and each switch may select one of a plurality of voltages included in the gamma voltage Vg.

[0082] The bias unit 340 may include a bias circuit 430. The bias circuit 430 may receive a plurality of node voltages from the resistor array 410. For example, in the case of 4-bit image data RGB, the bias circuit 430 may receive two node voltages among 16 node voltages V1 to V16. The received node voltages may be input to the buffer and then may be applied to both ends of the resistor array 411.

[0083] The bias circuit 430 may include a resistor array 411 for generating a current according to a voltage difference between a plurality of received node voltages. The current generated by the resistor array 411 may be referred to as a "reference current Iref". The bias circuit 430 may mirror the reference current Iref to the resistor array 421 of the voltage generating circuit 420. The mirrored reference current Iref may be used in the voltage generating circuit 420 to increase or decrease the second gamma reference voltage Vg_ref2.

[0084] Here, the resistor array 411 of the bias circuit 430 may have the same characteristics as the characteristics of the resistor array 421 of the second voltage generating unit 320-V. Both the resistor arrays 411 and 421 may include the same number of resistors. In addition, the resistors constituting both the resistor arrays 411 and 421 may have the same resistance value. For example, the resistor array 411 of the bias circuit 430 and the resistor array 421 of the second voltage generating unit 320-V may include three resistors, respectively, and each resistor may have a value R′.

[0085] In addition, in terms of characteristics, the resistor array 411 of the bias circuit 430 may be different from a portion of the resistor array 410. In terms of the number of resistors therein, the resistor array 411 of the bias circuit 430 may be different from a portion of the resistor array 410. In addition, in terms of resistance values ​​between resistors constituting the resistor array, the resistor array 411 of the bias circuit 430 may be different from a portion of the resistor array 410. For example, the resistance value of the resistor constituting a portion of the resistor array 410 may be R, and the resistance value of the resistor constituting the resistor array 411 of the bias circuit 430 may be R', which are different from each other.

[0086] Here, the resistor array 411 of the bias circuit 430 may have characteristics different from those of resistors between nodes at which voltages input from the resistor array 410 to the bias circuit 430 are formed. For example, if the 7th node voltage V7 and the 10th node voltage V10 are input to the bias circuit 430, the resistor array 411 may have characteristics different from those of resistors between the 7th node and the 10th node of the resistor array 410. The three resistors between the 7th node and the 10th node of the resistor array 410 may have a resistance value of R, and the three resistors of the resistor array 411 may have a resistance value of R'.

[0087] Figure 5 is a diagram showing an operation example of a data driving device for 4-bit image data according to an embodiment, and Figure 6 It shows that according to Figure 5 A table of the second gamma reference voltage, the gamma voltage and the data voltage is shown.

[0088] Reference Figure 5 , shows a configuration of a circuit for processing 4-bit image data RGB by the data driving device 120. The first selection circuit 310-S may perform selection in response to 2-bit image data RGB_2 of the 4-bit image data RGB, and the second selection circuit 320-S may perform selection in response to the remaining 2-bit image data RGB_2.

[0089] The first voltage generating unit 310-V may output a node voltage corresponding to 2 bits among 16 node voltages V1 to V16 as a first gamma reference voltage Vg_ref1. The first gamma reference voltage Vg_ref1 may include a node voltage (V2.5) of 2.5V, a node voltage (V6.5) of 6.5V, a node voltage (V10.5) of 10.5V, and a node voltage (V14.5) of 14.5V.

[0090] In addition, the bias circuit 430 of the bias unit 340 may receive a plurality of node voltages from the resistor array 410 of the first voltage generating unit 310-V. For example, the input voltage may include a node voltage (V7) of 7V and a node voltage (V10) of 10V. Here, the resistor array 411 of the bias circuit 430 may have characteristics different from those of the resistor between the 7th node N7 and the 10th node N10. Since the resistor array 411 of the bias circuit 430 may have the same resistor characteristics as those of the resistor array 421 of the voltage generating circuit 420, the resistor array 421 of the voltage generating circuit 420 may also have characteristics different from those of the resistor between the 7th node N7 and the 10th node N10.

[0091] For example, the resistor structure between the 7th node N7 and the 10th node N10 has a series connection of three resistors with a resistance value of R, while the resistor array 411 of the bias circuit 430 and the resistor array 421 of the voltage generating circuit 420 may have a series connection of four resistors with a resistance value of R' or R' / 2.

[0092] The first selection circuit 310-S may select only one voltage from the first gamma reference voltage Vg_ref1. For example, the first selection circuit 310-S may select V2.5 as the second gamma reference voltage Vg_ref2. The first selection circuit 310-S may send V2.5 to the voltage generation circuit 420 of the second voltage generation unit 320-V.

[0093] If V2.5 is input to the second voltage generating unit 320-V, V2.5 may be applied to the resistor array 421 on the opposite side. Here, the resistor array 421 generating the gamma voltage Vg may include an upper resistor array 421-1 for increasing a specific voltage and a lower resistor array 421-2 for decreasing a specific voltage. The second gamma reference voltage Vg_ref2 may be applied to a node where the upper resistor array 421-1 and the lower resistor array 421-2 of the resistor array 421 meet.

[0094] The upper resistor array 421-1 may increase V2.5 applied as the second gamma reference voltage Vg_ref2, and may generate a third gamma voltage Vg3 of 3 V and a fourth gamma voltage Vg4 of 4 V. On the other hand, the lower resistor array 421-2 may reduce V2.5 applied as the second gamma reference voltage Vg_ref2, and may generate a second gamma voltage Vg2 of 2 V and a first gamma voltage Vg1 of 1 V. The upper resistor array 421-1 and the lower resistor array 421-2 may generate the first gamma voltage Vg1 to the fourth gamma voltage Vg4 using the current Imir mirrored by the bias unit 340.

[0095] The second selection circuit 320-S may select one of the first to fourth gamma voltages Vg1 to Vg4 as the data voltage Vdata in response to the 2-bit image data RGB_2. The second selection circuit 320-S may transmit the selected voltage to the buffer.

[0096] Reference Figure 6 , the table shown shows the second gamma reference voltage Vg_ref2, the gamma voltage Vg, and the data voltage Vdata, which are generated when the first selection circuit 310-S and the second selection circuit 320-S process the 4-bit image data RGB by 2 bits respectively. The k-bit image data RGB_k processed by the first selection circuit 310-S can be defined as the most significant bit (MSB), and can be 2 bits in this example. The m-bit image data RGB_m processed by the second selection circuit 320-S can be defined as the least significant bit (LSB), and can be 2 bits in this example.

[0097] Therefore, if the image data RGB is 0000, 0001, 0010, and 0011, the second gamma reference voltage Vg_ref2 may be V2.5, and V1, V2, V3, and V4 may be generated as the gamma voltages Vg. The second selection circuit 320-S may output V1, V2, V3, and V4 according to the bit signals of the image data RGB of 0000, 0001, 0010, and 0011, respectively.

[0098] Likewise, if the image data RGB is 0100, 0101, 0110, and 0111, the second gamma reference voltage Vg_ref2 may be V6.5, and V5, V6, V7, and V8 may be generated as the gamma voltages Vg. The second selection circuit 320-S may output V5, V6, V7, and V8 according to the bit signals of the image data RGB of 0100, 0101, 0110, and 0111, respectively.

[0099] If the image data RGB is 1000, 1001, 1010, and 1011, the second gamma reference voltage Vg_ref2 may be V10.5, and V9, V10, V11, and V12 may be generated as the gamma voltages Vg. The second selection circuit 320-S may output V9, V10, V11, and V12 according to the bit signals of the image data RGB of 1000, 1001, 1010, and 1011, respectively.

[0100] If the image data RGB is 1100, 1101, 1110, and 1111, the second gamma reference voltage Vg_ref2 may be V14.5, and V13, V14, V15, and V16 may be generated as the gamma voltages Vg. The second selection circuit 320-S may output V13, V14, V15, and V16 according to the bit signals of the image data RGB of 1100, 1101, 1110, and 1111, respectively.

[0101] CROSS-REFERENCE TO RELATED APPLICATIONS

[0102] This application claims priority to Korean Patent Application No. 10-2019-0167533, filed on December 16, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A data driving device for driving pixels arranged in a display panel, the data driving device comprising: a first voltage generating unit configured to distribute a high power supply voltage and a low power supply voltage and generate a plurality of node voltages; a first selection circuit configured to receive a portion of bits of image data for driving the pixel and select one of a plurality of voltages included in the plurality of node voltages as a second gamma reference voltage according to the portion of bits; a second voltage generating circuit configured to generate a plurality of gamma voltages by increasing and decreasing the second gamma reference voltage; a bias circuit configured to receive a portion of the plurality of node voltages, generate a reference current using the portion of the plurality of node voltages, and provide a bias current to the second voltage generating circuit by mirroring the reference current to the second voltage generating circuit; as well as a second selection circuit configured to receive remaining bits of the image data and select a gamma voltage from the plurality of gamma voltages as a data voltage for driving the pixel according to the remaining bits, The second voltage generating circuit is configured to increase and decrease the second gamma reference voltage using the bias current. 2 . The data driving device of claim 1 , further comprising a buffer configured to receive the one gamma voltage from the second selection circuit, amplify the one gamma voltage, and output the amplified voltage as the data voltage.

3. The data driving device according to claim 1, wherein: The second voltage generating circuit includes a plurality of resistor arrays, and is configured to increase the second gamma reference voltage using one resistor array and to decrease the second gamma reference voltage using another resistor array.

4. The data driving device according to claim 3, wherein: The second gamma reference voltage is applied to a node where the one resistor array and the other resistor array meet.

5. A gamma voltage circuit for generating a gamma voltage for image data including k upper bits and m lower bits, where k is a natural number and m is a natural number, the gamma voltage circuit comprising: a resistor array including a plurality of resistors and a node formed by the plurality of resistors connected between a high power supply voltage and a low power supply voltage, and configured to form a node voltage between the high power supply voltage and the low power supply voltage at the node; a switch circuit configured to receive a portion of the node voltages and output a voltage selected from the portion of the node voltages according to the k upper bits; a voltage generating circuit configured to receive the selected one voltage and generate a plurality of gamma voltages according to the selected one voltage; as well as a bias circuit comprising a bias resistor array configured to receive a first node voltage and a second node voltage from the resistor array and generate a current for a difference between the first node voltage and the second node voltage, and the bias circuit is configured to mirror the current to the voltage generating circuit, The voltage generating circuit includes a voltage generating resistor array configured to generate the plurality of gamma voltages, and is configured to increase and decrease a selected voltage through the voltage generating resistor array and the current mirrored by the bias circuit, thereby generating the plurality of gamma voltages.

6. The gamma voltage circuit according to claim 5, wherein: The biasing resistor array and the voltage generating resistor array have the same characteristics.

7. The gamma voltage circuit according to claim 6, wherein: The bias resistor array has characteristics that are different from characteristics of a portion of the resistor array.

8. The gamma voltage circuit according to claim 7, wherein: The bias resistor array has characteristics different from characteristics of resistors connected between a first node forming the first node voltage and a second node forming the second node voltage.

9. The gamma voltage circuit according to claim 5, wherein: The bias circuit includes a buffer configured to receive the first node voltage and the second node voltage and apply the first node voltage and the second node voltage to the bias resistor array.

10. The gamma voltage circuit according to claim 9, wherein: The buffer is configured to apply the first node voltage and the second node voltage across the bias resistor array.

11. The gamma voltage circuit according to claim 5, wherein: The voltage generating resistor array includes an upper resistor array configured to increase a selected one of the voltages and a lower resistor array configured to decrease the selected one of the voltages.

12. The gamma voltage circuit according to claim 11, wherein: A selected one of the voltages is applied to the node where the upper resistor array and the lower resistor array meet.

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