Managing pre-programming of memory devices for reflow processes

Abstract

The present application relates to managing pre-programming of a memory device for a reflow process. A logic state to be stored at a memory cell of a memory device is determined, wherein the logic state is to be represented by a threshold voltage stored at the memory cell. A verification reference voltage associated with the logic state is determined. The verification reference voltage defines a target voltage level for the threshold voltage associated with the logic state. After heat is applied to the memory device, the verification reference voltage is updated using a compensation amount for an expected shift in the threshold voltage of the memory cell. Prior to applying the heat to the memory device, multiple sets of multiple programming pulses are applied to the memory cell until a threshold condition is met. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell relative to an updated verification reference voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory devices, and more particularly, to managing pre-programming of memory devices for a reflow process. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] One aspect of the present application relates to a method comprising: determining a logic state to be stored at a memory cell of a memory device, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verification reference voltage associated with the logic state, the verification reference voltage defining a target voltage level of the threshold voltage associated with the logic state; updating the verification reference voltage after applying heat to the memory device using an amount of compensation for an expected shift in the threshold voltage of the memory cell; and before applying the heat to the memory device, applying multiple groups of multiple programming pulses to the memory cell until a threshold condition is met, wherein the threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell relative to the updated verification reference voltage.

[0004] Another aspect of the present application relates to a system comprising: a memory device; and a processing device operatively coupled to the memory device, the processing device being configured to perform operations comprising: determining a logic state to be stored at a memory cell of the memory device, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verification reference voltage associated with the logic state, the verification reference voltage defining a target voltage level for the threshold voltage associated with the logic state; updating the verification reference voltage after applying heat to the memory device using an amount of compensation for an expected shift in the threshold voltage of the memory cell; and applying multiple sets of multiple programming pulses to the memory cell until a threshold condition is met before applying the heat to the memory device, wherein the threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell relative to the updated verification reference voltage.

[0005] Another aspect of the present application relates to a method, comprising: determining a logic state to be stored at a memory cell of a memory device, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verification reference voltage associated with the logic state, the verification reference voltage defining a target voltage level of the threshold voltage associated with the logic state; after applying heat to the memory device, determining an amount of compensation for an expected shift in the threshold voltage of the memory cell based at least on a thermal distribution used in association with the heat; updating the verification reference voltage using the compensation amount; and determining whether to continue applying programming pulses to the memory cell based on the updated verification reference voltage, wherein the programming pulses were applied to the memory cell before the heat was applied to the memory device.

[0006] Another aspect of the present application relates to an apparatus comprising: a plurality of memory cells; and a processing device configured to perform operations comprising: determining a logic state to be stored at a memory cell of the plurality of memory cells, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verification reference voltage associated with the logic state, the verification reference voltage defining a target voltage level of the threshold voltage associated with the logic state; updating the verification reference voltage after applying heat to the apparatus using an amount of compensation for an expected shift in the threshold voltage of the memory cell; and applying multiple sets of multiple programming pulses to the memory cell until a threshold condition is met before applying the heat to the apparatus, wherein the threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell relative to the updated verification reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be construed as limiting the present disclosure to specific embodiments, but are only for explanation and understanding.

[0008] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0009] Figure 2 is a block diagram of an example method of reading pre-programmed data after a reflow process according to some embodiments of the present disclosure.

[0010] Figure 3 is a flow chart of an example method of applying a programming pulse to a memory cell according to some embodiments of the present disclosure.

[0011] Figure 4is a block diagram of an example method of reading pre-programmed data after a reflow process according to some other embodiments of the present disclosure.

[0012] Figure 5 Flowchart of an example method of determining whether to continue applying programming pulses to memory cells according to some embodiments of the present disclosure.

[0013] Figure 6 is a block diagram of an example computer system upon which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure relate to managing pre-programming of memory devices for a reflow process. The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components, such as a memory device, that stores data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0015] The memory component may include a nonvolatile memory device that stores data from a host system. A nonvolatile memory device is a package of one or more dies. The dies in the package may be assigned to one or more channels for communicating with a memory subsystem controller. A nonvolatile memory device includes cells (i.e., electronic circuits that store information) that are grouped into pages to store data bits. The nonvolatile memory device may include a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of nonvolatile memory that can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. Another example of a nonvolatile memory device is a NAND memory device. hereinafter combined with Figure 1 Other examples of non-volatile memory devices are described.

[0016] Each of the memory devices may include one or more memory cell arrays. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and have various logical states related to the number of bits being stored. The logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of such values. For example, a single-level cell (SLC) may store one bit of information and have two logical states. As another example, a triple-level cell (TLC) may store 3 bits of information and have eight logical states (e.g., 000, 001, 010, 011, 100, 101, 110, and 111).

[0017] Memory devices may be pre-programmed in the factory (e.g., via a tester) before the memory devices are soldered onto a printed circuit board and dispatched to a customer. Conventional pre-programming operations involve applying a series of incremental programming pulses (i.e., a single pulse at a time) to the memory cell until the desired voltage level (i.e., threshold voltage) for indicating the corresponding logic state is stored in the memory cell.

[0018] After the pre-programming stage, the memory device undergoes a reflow process. The reflow process involves soldering the memory device to the printed circuit board by applying solder paste (e.g., lead-free solder paste) to both the memory device and the printed circuit board to permanently connect them together and baking the memory device and the printed circuit board at a high temperature. Subsequently, the data stored in the memory cells of the memory device is read to check the data integrity. Because the memory device is heated at a high temperature, the threshold voltage programmed to the memory cell by a conventional pre-programming operation may shift, causing data retention issues. Therefore, a memory cell that was pre-programmed to store a certain logic state (e.g., 010) may instead be read as storing a different logic state (e.g., 011) after the reflow process. This threshold voltage shift may be attributed to the rapid loss of charge stored in the memory cell during the conventional pre-programming operation or to the heat applied during the reflow process causing a redistribution of such charge.

[0019] Aspects of the present disclosure address the above and other deficiencies by providing a memory subsystem that estimates the amount of shift in the threshold voltage of a memory cell that may be caused by heat applied during a reflow process, and pre-compensates the threshold voltage of a logic state of the memory cell by this amount during a pre-programming operation. The memory subsystem may determine the amount of threshold voltage shift based at least on the heat profile used in the reflow process. Thus, after the reflow process, the threshold voltage of the memory cell will shift to a given voltage level, thereby reducing data retention loss issues.

[0020] Other aspects of the present disclosure further provide memory subsystems that, in addition to the pre-compensation techniques described above, apply multiple groups of multiple programming pulses to memory cells during a pre-programming operation. In these embodiments, the same group of multiple programming pulses may be applied continuously at the same voltage level. As a result, rapid charge loss that causes a shift in the threshold voltage may be suppressed. In addition, in these embodiments, the next group of multiple programming pulses may also be applied continuously at the same voltage level, but at a higher level than the previous group of multiple programming pulses.

[0021] Advantages of the present disclosure include, but are not limited to, ensuring data integrity after the reflow process by reducing read error rates. As a result, the reliability of the memory subsystem can be improved. Data retention issues caused by subjecting the memory to high temperatures during the reflow process can also be minimized.

[0022] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0024] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., included in a vehicle, industrial equipment, or one of a networked business device), or such a computing device that includes a memory and a processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, such as writing data to the memory subsystem 110 and reading data from the memory subsystem 110.

[0027] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting a Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access memory components, such as the memory device 130, when the memory subsystem 110 is coupled to the host system 120 through a PCIe interface. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0028] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices 130 may be grouped into pages that may refer to logical units of a memory device used to store data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although non-volatile memory components such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), or non-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells.

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0035] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, the memory device 130 includes a local media controller 135 that operates with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] In some embodiments, a memory device (e.g., memory device 130) includes a preprogramming management component 113 that manages preprogramming operations performed before a reflow process. In some embodiments, the preprogramming management component 113 is part of a local media controller (e.g., local media controller 135) of the memory device. In some embodiments, the memory subsystem 110 includes a preprogramming management component 113 that manages preprogramming operations performed before a reflow process. In some embodiments, the memory subsystem controller 115 includes at least a portion of the preprogramming management component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some other embodiments, the preprogramming management component 113 may be part of a host system 110, an application, or an operating system.

[0039] The preprogramming management component 113 may determine a logic state to be stored at a memory cell of the memory device 130, 140. In addition, the preprogramming management component 113 may determine a verification reference voltage associated with the logic state. After applying heat (e.g., during a reflow process) to the memory device 130, 140, the preprogramming management component 113 may further determine an amount of compensation for a shift in the threshold voltage of the memory cell based on at least a thermal profile associated with the heat (e.g., a thermal profile used in the reflow process). The preprogramming management component 113 may further update the verification reference voltage using the compensation amount. The preprogramming management component 113 may determine whether to continue applying programming pulses to the memory cell based on the updated verification reference voltage. Before applying heat to the memory device 130, 140, a programming pulse is applied to the memory cell.

[0040] In some other implementations, the preprogramming management component 113 may determine a logic state to be stored at a memory cell of the memory device 130, 140. The logic state may be represented by a threshold voltage stored at the memory cell. The preprogramming management component 113 may also determine a verification reference voltage associated with the logic state. The verification reference voltage may define a target voltage level for the threshold voltage associated with the logic state. After determining the verification reference voltage, the preprogramming management component 113 may update the verification reference voltage using an amount of compensation for a shift in the threshold voltage of the memory cell that is expected to occur after applying heat to the memory device 130, 140. Before applying the heat to the memory device 130, 140, the preprogramming management component 113 may apply multiple sets of multiple programming pulses to the memory cell until a threshold condition is met. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell relative to the updated verification reference voltage. More details about the operation of the preprogramming management component 113 are described below.

[0041] Figure 2 2 is a block diagram of an example method 200 for reading pre-programmed data after a reflow process according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, portions of the method 200 are performed by Figure 1 The method is performed by the pre-programmed management component 113 of the embodiment. Although the method is described in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the embodiments should be understood as examples only, and the processes described can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0042] At operation 210, the processing device pre-programs the memory cells to store logic states. The pre-programming operation corresponds to a programming operation performed at a factory, plant, or other facility before the memory devices are soldered onto a printed circuit board and dispatched to a customer. The pre-programming operation may be performed in parallel on thousands of memory devices. However, the processing device may program the memory cells of the memory devices in a manner similar to other programming operations, where programming pulses are applied to the memory cells until a desired voltage is stored at the memory cells.

[0043] Diagram 220 illustrates an example of threshold voltage distribution during pre-programming of logic states to memory cells according to some embodiments of the present disclosure. As illustrated, vertical axis 221 represents the number of memory cells and horizontal axis 222 represents the threshold voltage.

[0044] On the threshold voltage axis 222, a verification reference voltage (VR) and an updated verification reference voltage (VR*) are marked. The verification reference voltage (sometimes also referred to as a program verification voltage) may define a target voltage level for a threshold voltage associated with a logic state. The processing device may instead use the updated verification reference voltage (VR*) in order to compensate for an expected shift in the threshold voltage after the memory device is exposed to heat during the reflow operation 240. In one embodiment, the processing device may determine the updated verification reference voltage (VR*) based on a thermal profile associated with the heat (e.g., a thermal profile used in the reflow process). The processing device may calculate the expected shift amount of the threshold voltage (as indicated by arrow 223) after the reflow operation 240 using an activation energy prediction model (e.g., an Arrhenius model). Then, the processing device may add the expected threshold voltage shift amount (arrow 223) to the verification reference voltage (VR) to update the verification reference voltage (VR*). Therefore, the processing device may ensure that the threshold voltage of the memory cell remains within the target voltage level defined by the original verification reference voltage (VR) after the shift caused by the reflow process.

[0045] In another embodiment, the processing device may determine the expected amount of shift 223 further based on the logic state being programmed. For example, the processing device may determine a smaller expected amount of shift for logic state 010 when compared to higher logic state 111. However, in another embodiment, the processing device may determine a larger expected amount of shift for a memory device that is to undergo multiple reflow operations 240 than for a memory device that is to undergo a single reflow operation 240.

[0046] As illustrated, after an initial programming pulse has been applied to the memory cells to store a logic state, a threshold voltage distribution 225A may be formed by the memory cells. Threshold voltage distribution 225A represents an initial distribution of memory cells having a range of threshold voltages. As indicated by distributions 225B to 225D, programming pulses may be successively applied to the memory cells to push the distribution in a direction toward an updated verification reference voltage (VR*), as indicated by arrow 228. Once the processing device determines that the lower end of the distribution (e.g., distribution 225D) is equal to and / or greater than the updated verification reference voltage (VR*), the processing device may determine to stop applying programming pulses to the memory cells. In other words, if all memory cells for storing a logic state have a threshold voltage equal to or greater than the updated verification reference voltage (VR*), then the pre-programming operation 210 ends.

[0047] Diagram 230 illustrates an example of pre-program pulses and verify pulses for pre-programming logic states to memory cells according to some embodiments of the present disclosure. As illustrated, vertical axis 231 represents voltage level and horizontal axis 232 represents time.

[0048] As mentioned above, the pre-programming operation involves two phases, a first phase of applying programming pulses to applicable memory cells, and a second phase of verifying whether the threshold voltage has reached a target voltage level, i.e., an updated verification reference voltage (VR*). For example, the processing device may apply a programming pulse (PGM 235A) at 15V to the memory cell. Subsequently, the processing device may apply an updated verification reference voltage (VR* 237A) to the memory cell and confirm whether the threshold voltage of the memory cell is below or above the verification reference voltage 237A. In the event that it is determined that not all threshold voltages of the memory cells are equal to or greater than the verification reference voltage (VR* 237A), then the processing device may determine the voltage level of the next programming pulse. In one embodiment, the processing device may determine to increase the voltage level by an increment 239 (e.g., 0.4V). Sometimes, the incremental voltage 239 is referred to as a voltage step (V STEP ).

[0049] Therefore, the processing device may apply a programming pulse 235B at a voltage level of 17V. Subsequently, the processing device may apply an updated verification reference voltage (VR*237B) at the same voltage level as before to check whether the threshold distribution of the memory cells has reached the updated verification reference voltage (VR*437B). The processing device may perform programming and verification operations until all threshold voltages of the memory cells are equal to or greater than the updated verification reference voltage. In this way, the processing device may overcompensate the memory cells during the pre-programming operation 210 so that after the reflow process 240, the threshold distribution of the memory cells will shift to the original verification reference voltage as if the shift had not occurred.

[0050] At operation 240, the memory device undergoes a reflow process. The reflow process involves soldering the memory device to the printed circuit board by applying solder paste (e.g., lead-free solder paste) to both the memory device and the printed circuit board to permanently connect them together and baking the memory device and the printed circuit board at a high temperature (e.g., 230° C. to 255° C.). During the baking process, heat may be gradually applied to the memory device as the temperature increases, and after reaching a peak temperature, the heat may be reduced so that the memory device may cool. The memory device may undergo multiple (e.g., three or more) reflow processes.

[0051] At operation 250, the processing device may read the data stored at the memory cell. As depicted, diagram 260 illustrates an example of a threshold voltage distribution of memory cells after a reflow process according to some embodiments of the present disclosure. Vertical axis 261 represents the number of memory cells, and horizontal axis 262 represents the threshold voltage.

[0052] Distribution 265 represents the threshold voltage distribution of the memory cells after the reflow process. As the memory devices (and therefore, the memory cells) heat at this high temperature, the threshold voltages stored at the memory cells by the pre-programming operation 210 begin to shift. In other words, the charge stored at the memory cells is lost or redistributed, thereby changing the threshold voltages. Thus, as illustrated, after the memory cells have been exposed to heat, the original distribution 225D has shifted by a shift amount 263. Because the processing device can estimate the shift amount during the pre-programming operation 210 (by updating the verify reference voltage (VR*)) and pre-compensate for the amount, the resulting threshold distribution 265 has shifted to the voltage level of the original verify reference voltage (VR). As a result, when the read voltage (RV) is applied, the processing device can eliminate or reduce read errors because no memory cells have a threshold voltage shifted below the read voltage (RV).

[0053] Threshold distribution 267 represents what the distribution would be if the original verify reference voltage (VR) were to be used in pre-programming operation 210. As illustrated, distribution 267 would be shifted by the same or similar amount 263 as distribution 265. However, there may be read errors because some memory cells have threshold voltages below the read voltage (RV). It should also be noted that not all threshold voltages are shifted by the same amount, therefore, distribution 265 is skewed to the right.

[0054] Figure 3 Flowchart of an example method 300 of applying a programming pulse to a memory cell according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The pre-programmed management component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0055] At operation 310, a processing device determines a logic state to be stored at a memory cell of a memory device. The processing device may receive a logic state from a host system (e.g., Figure 1 The host system 120 of the memory cell receives data for storage. Therefore, the processing device can determine the logic state from the data. The logic state (ie, the bit information) can be determined by the threshold voltage (V TH) is represented. For example, a triple-level cell (TLC) can store three bits of information and therefore has eight logic states (e.g., 000, 001, 010, 011, 100, 101, 110, and 111). For simplicity, in this description, the higher the number of bits, the higher the logic state. For each logic state, the memory cell should have a different threshold voltage (V TH ). Therefore, the higher the logic state, the higher the threshold voltage (V TH ) the higher.

[0056] At operation 320, the processing device determines a verification reference voltage (VR) associated with the logic state. In some embodiments, the verification reference voltage (VR) (sometimes also referred to as a program verification voltage) may define a threshold voltage (V TH ) target voltage level. For each logic state, the processing device may assign a corresponding verification reference voltage (VR). In one embodiment, the verification reference voltage (VR) of the logic state may correspond to a threshold voltage (V TH ) should be at a minimum voltage level in order for the corresponding memory cell to be determined to store a logic state. The processing device may select a verification reference voltage (VR) corresponding to the logic state determined at operation 510 from a lookup table that lists verification reference voltages for each logic state.

[0057] At operation 330, after applying heat to the memory device, the processing device determines a threshold voltage (V TH In some implementations, the compensation amount corresponds to the threshold voltage (V TH ) is an approximation of the amount of shift that occurs in ). The compensation amount may correspond to a positive value (to compensate for the threshold voltage (V TH ) or a negative value (to compensate for the threshold voltage (V TH )'s upward shift).

[0058] Heat will be applied to the memory device after the memory cell has been programmed (e.g., after operation 540). The heat will be applied as part of a reflow process. The reflow process involves soldering the memory device to the printed circuit board by applying solder paste (e.g., lead-free solder paste) to both the memory device and the printed circuit board to permanently connect them together and baking the memory device and the printed circuit board at a high temperature (e.g., 230° C. to 255° C.). Heat may be applied to the memory device gradually as the temperature increases, and after reaching a peak temperature, the memory device will cool. Because the memory device, and therefore the memory cell, is heated at this high temperature, the threshold voltage stored at the memory cell begins to shift. In other words, the charge stored at the memory cell is lost or redistributed, thereby changing the threshold voltage.

[0059] A thermal profile associated with the heat (e.g., a thermal profile used in a reflow process) may include a temperature associated with the heat and a time period for which the heat is applied to the memory device. In one embodiment, the temperature associated with the heat corresponds to a peak temperature (e.g., 255° C.), and the time period corresponds to a duration for which the heat reaches the peak temperature when applied to the memory device (e.g., 60 seconds). The processing device may determine the compensation amount based on the thermal profile using an activation energy prediction model (e.g., an Arrhenius model).

[0060] In other embodiments, the processing device may additionally determine the compensation amount based on the logic state. Thus, the processing device may determine different compensation amounts for different logic states. In one embodiment, the processing device may determine a default compensation amount calculated using a model based on a thermal profile associated with heat (e.g., a thermal profile used in a reflow process). The processing device may then adjust the compensation amount based on the logic state. For example, the processing device may adjust the default compensation amount associated with a higher logic state (e.g., 111) to be at a higher voltage level than the compensation amount associated with a lower logic state (e.g., 010). The processing device may adjust the default compensation amount based on a linear or nonlinear relationship.

[0061] In other additional embodiments, the processing device may also determine the compensation amount based on the number of times heat is applied to the memory device. The processing device may determine the number of times heat is to be applied from a preconfigured table. In the event that the processing device determines that heat will be applied once, the processing device may not adjust the default compensation amount calculated from the model. However, in the event that the processing device determines that heat will be applied multiple times, the processing device may adjust the default compensation amount to a higher voltage level. The processing device may adjust the default compensation amount based on a linear or nonlinear relationship. When determining the compensation amount based on different factors, the processing device may refer to a lookup table that lists compensation amounts for various situations to determine the appropriate compensation amount.

[0062] At operation 340, the processing device updates the verification reference voltage (VR) using the compensation amount. The processing device may combine the verification reference voltage (VR) with the compensation amount. For example, the processing device may increase the verification reference voltage (VR) (e.g., 4V) by 2V because the threshold voltage (V TH ) will shift downward or become smaller by approximately 2V.

[0063] At operation 350, the processing device may determine whether to continue applying programming pulses (PGM) to the memory cells based on the updated verification reference voltage (VR*). The programming pulses (PGM) are applied to the memory cells to change the logic state or threshold voltage (V TH ) is stored to the memory cell. For example, a programming pulse is applied to the memory cell before heat is applied to the memory device.

[0064] To determine whether to continue applying the programming pulse (PGM), the processing device may determine the current threshold voltage (V TH ) is compared with the updated verification reference voltage (VR*). In one embodiment, when the current threshold voltage (V TH ) is less than the updated verification reference voltage (VR*), the processing device may determine the current threshold voltage (V TH ) has not reached the updated verification reference voltage (VR*). In this case, the processing device may determine to continue applying the programming pulse (PGM) to the memory cell. Therefore, the processing device may apply the programming pulse (PGM) (at a higher voltage level) to the memory cell.

[0065] On the other hand, when the current threshold voltage (V TH ) is equal to or greater than the updated verification reference voltage (VR*), the processing device may determine the threshold voltage (V TH ) has been reached. In response to this determination, the processing device may determine not to continue applying the programming pulse (PGM) to the memory cell. Therefore, the processing device may pre-compensate the threshold voltage (V TH ) in the expected shift. In this way, even at the threshold voltage (V TH ) shifts due to the reflow process, the threshold voltage (V TH ) will also be within the target voltage level set by the original verification reference voltage (VR). Therefore, by adjusting the target voltage by the estimated shift amount, the threshold voltage (V TH ) will remain within the target range defined by the original verification reference voltage (VR), even after the shift. Therefore, the error rate of reading the logic state can be reduced.

[0066] Figure 44 is a block diagram of an example method 400 for reading pre-programmed data after a reflow process according to some other embodiments of the present disclosure. The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, portions of the method are performed by Figure 1 The method is performed by the pre-programmed management component 113 of the embodiment. Although the method is described in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the embodiments should be understood as examples only, and the processes described can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0067] At operation 410, the processing device preprograms the memory cells to store logic states, similar to operation 210. Graph 420 illustrates an example of a threshold voltage distribution during preprogramming of logic states to memory cells according to some embodiments of the present disclosure. As illustrated, the vertical axis 421 represents the number of memory cells, and the horizontal axis 422 represents the threshold voltage.

[0068] As marked on threshold voltage axis 422, the processing device may determine a corresponding verify reference voltage (VR) for the logic state to be stored at the memory cell. The processing device may then update the verify reference voltage (VR*) by adding amount 423 to compensate for the shift in threshold voltage expected to occur after the memory device was exposed to heat during reflow operation 440. As described above with respect to amount 223, the processing device may similarly calculate amount 423 by using an activation energy prediction model and taking into account the thermal profile associated with the heat to be used in operation 440 and any other factors (e.g., the thermal profile used in the reflow process).

[0069] The processing device may apply a set of multiple programming pulses at the same voltage level to the memory cells specifying the storage logic state. Threshold voltage distribution 425A represents the distribution of the threshold voltages of the memory cells after the initial application of multiple programming pulses. As illustrated, when distribution 425A is Figure 2 When comparing distribution 425A (the threshold voltage distribution when only one programming pulse has been applied to the memory cell) with distribution 425A, it can be observed that distribution 425A is tighter than distribution 225A. That is, distribution 425A has a threshold voltage range 426 that is narrower than range 427 of distribution 225A. By applying multiple programming pulses one after another, charge loss at the memory cell is better maintained or suppressed.

[0070] The remainder of the pre-programming operation 410 is similar to the above described operation 210. For example, multiple programming pulses are applied to the memory cells to push threshold voltage distributions 425B-425C toward direction 428 until the lower end of distribution 425D reaches the updated verify reference voltage (VR*).

[0071] Diagram 430 illustrates an example of pre-programming pulses and verification pulses to pre-program logic states to memory cells according to some embodiments of the present disclosure. As illustrated, vertical axis 431 represents voltage levels and horizontal axis 432 represents time. Similar to diagram 230, a series of programming pulses and verification pulses are applied to the memory cells over time until the threshold distribution of the memory cells meets the minimum voltage requirement set by the updated verification reference voltage (VR*).

[0072] For example, the processing device may initially apply two programming pulses at 15V (435A). When applying two programming pulses, the processing device may apply the programming pulses continuously. In one embodiment, once the electric field used to apply the first programming pulse is removed, the processing device may apply a second programming pulse. Although diagram 430 illustrates applying two programming pulses, the processing device may apply a different number of programming pulses throughout pre-programming operation 410.

[0073] In one embodiment, the processing device may set the number of programming pulses to a fixed number (e.g., two). However, in another embodiment, the processing device may determine the number of programming pulses based on the number of times the reflow operation 440 is performed on the memory device. If the memory device will undergo multiple reflow operations 440, the processing device may determine to use a higher number (e.g., three) of programming pulses. However, in another embodiment, the processing device may determine the number of programming pulses based on the logic state being programmed into the memory cell. For a higher logic state (e.g., logic state 111), the processing device may use a higher number (e.g., three) of programming pulses as opposed to using a smaller number (e.g., two) of programming pulses for a lower logic state (e.g., logic state 010).

[0074] Subsequently, the processing device may apply the updated verification reference voltage (VR* 437A) to the memory cell and confirm whether the threshold voltage of the memory cell is lower than or higher than the verification reference voltage 437A. For example, in response to determining that the threshold voltage is lower than the verification reference voltage 437A, the processing device may apply the next set of multiple programming pulses 435B. The processing device may apply an incremental voltage (or voltage step (V STEP)) 439 (e.g., 0.4V) is added to the voltage level of the previous set of programming pulses 435A to determine the voltage level of programming pulse 435B. In one embodiment, the processing device may apply the same incremental voltage (V STEP ) 439. In another embodiment, the processing device may change the incremental voltage (V STEP ) 439. For example, the processing device may reduce the incremental voltage (V STEP ) 439. However, in another embodiment, the processing device may use a smaller incremental voltage (V STEP )439.

[0075] Subsequently, the processing device may apply an updated verification reference voltage (VR* 437B) at the same voltage level as before to check whether the threshold distribution of the memory cells has reached the updated verification reference voltage. The processing device may perform programming and verification operations until all threshold voltages of the memory cells are equal to or greater than the updated verification reference voltage.

[0076] At operation 440, the memory device undergoes a reflow process similar to the reflow process of operation 240. Thus, the memory device may be subjected to high temperature (eg, 255° C.) heating for a period of time (eg, 60 seconds).

[0077] At operation 450, the processing device may read the data stored at the memory cell. As depicted, diagram 460 illustrates an example of a threshold voltage distribution of memory cells after a reflow process according to some embodiments of the present disclosure. Vertical axis 461 represents the number of memory cells, and horizontal axis 462 represents the threshold voltage.

[0078] Distribution 465 represents the threshold voltage distribution of the memory cells after the reflow process. Due to the heat applied during the reflow operation 440, the charge stored at the memory cells is lost or redistributed when compared to the threshold voltage distribution 425D of the memory cells before the reflow operation 440, thereby causing the threshold voltage to shift, as illustrated by threshold voltage distribution 465. However, because the processing device can estimate the amount of shift and pre-compensate for the amount during the pre-programming operation 410 (by updating the verify reference voltage (VR*)), the resulting threshold distribution 465 has shifted to the voltage level of the original verify reference voltage (VR). As a result, when the read voltage (RV) is applied, the processing device can eliminate or reduce read errors because no memory cells have a threshold voltage shifted below the read voltage (RV).

[0079] Threshold distribution 265 represents the post-reflow threshold voltage distribution of memory cells pre-programmed using a single programming pulse but having the same voltage level range. As illustrated, distribution 465 has a tighter threshold voltage distribution than distribution 265. In addition, distribution 465 is less skewed to the right than distribution 265. Thus, applying multiple programming pulses can suppress charge loss even after reflow operation 440.

[0080] Figure 5 Flowchart of an example method 500 for determining whether to continue applying a programming pulse (PGM) to a memory cell according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The pre-programmed management component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0081] At operation 510, the processing device determines a logic state to be stored at a memory cell of the memory device, similar to operation 310. The logic state (ie, bit information) may be determined by a threshold voltage (V TH For example, a triple-level cell (TLC) can store three bits of information and therefore has eight logical states (e.g., 000, 001, 010, 011, 100, 101, 110, and 111, in ascending order).

[0082] At operation 520, the processing device determines a verification reference voltage (VR) associated with the logic state in a similar manner as described with respect to operation 320. The verification reference voltage (VR) (sometimes also referred to as a program verification voltage) may define a threshold voltage (V TH ) target voltage level. In one embodiment, the verification reference voltage (VR) may correspond to the threshold voltage (V TH In another embodiment, the verification reference voltage (VR) can set the threshold voltage (V TH The processing device may determine different verification reference voltages (VR) for different logic states.

[0083] At operation 530, after applying heat to the memory device, the processing device uses a threshold voltage (VTH ) to update the verification reference voltage (VR) by a compensation amount corresponding to the threshold voltage (V TH ) is an approximation of the amount of shift that occurs in ). The compensation amount may correspond to a positive value (to compensate for the threshold voltage (V TH ) or a negative value (to compensate for the threshold voltage (V TH )'s upward shift).

[0084] In one embodiment, the processing device may determine the compensation amount based on the logic state and the thermal distribution associated with the heat (e.g., the thermal distribution used in the reflow process). Heat will be applied to the memory device as part of the reflow process to solder the memory device to the printed circuit board, as described above with respect to operation 330. For example, the thermal distribution may include a temperature associated with the heat and a time period for applying the heat to the memory device. For example, as described above with respect to operation 330, the processing device may calculate the compensation amount based on an activation energy prediction model (e.g., an Arrhenius model) by considering the logic state and the thermal distribution associated with the heat (e.g., the thermal distribution used in the reflow process). Therefore, the processing device may estimate the threshold voltage (V TH ) will shift by how much after the reflow process.

[0085] In one embodiment, the processing device may determine different compensation amounts for different logic states. For example, the processing device may determine that the compensation amount associated with a lower logic state (e.g., 010) is less than the compensation amount associated with a higher logic state (e.g., 111). In addition, the higher the temperature of the heat or the longer the heat is applied to the memory device, the greater the compensation amount. Figure 3 In another embodiment, the processing device may incorporate other factors, such as the number of times heat is applied to the memory device when determining the compensation amount, such as the above relative to Figure 3 Once the compensation amount is determined, the processing device may update the verification reference voltage (VR) by combining the verification reference voltage (VR) with the compensation amount.

[0086] At operation 540, before applying heat to the memory device, the processing device applies multiple sets of multiple programming pulses (PGM) to the memory cell until the threshold condition is met. For example, the processing device may apply or send instructions to apply a set of multiple programming pulses (PGM) to the memory cell to determine (or store) the threshold voltage (V TH) to the memory cell. In some embodiments, the processing device may apply programming pulses (PGM) in multiple cycles or in steps. For each step, the processing device may apply a set of multiple programming pulses (PGM). In one embodiment, the processing device may apply multiple programming pulses (PGM) at the same voltage level. In another embodiment, the processing device may apply each programming pulse (PGM) to the memory cell continuously. In other words, when the electric field used to apply the previous same set of programming pulses is removed, the processing device may apply the next same set of programming pulses. Then, for the next set of multiple programming pulses (PGM), the processing device may apply programming pulses (PGM) at an incrementally increasing voltage level.

[0087] In another embodiment, the processing device may determine the number of programming pulses (PGM) comprising a group based on the logic state. Instead of applying the same number (e.g., two) of programming pulses (PGM), the processing device may change the number of programming pulses (PGM) depending on the logic state stored at the memory cell. For example, for a higher logic state (e.g., a logic state greater than 010), the processing device may determine to apply three programming pulses (PGM). As another example, the processing device may determine to gradually increase the number of programming pulses (PGM) for higher logic states, such as applying three programming pulses (PGM) for logic states 010 to 100 and applying four programming pulses (PGM) for logic states 101 to 111.

[0088] The processing device can compare the updated verification reference voltage (VR*) with the current threshold voltage (V TH ) to determine whether a threshold condition is met; in some embodiments, the threshold condition may be related to the threshold voltage (V TH ) with respect to the updated verification reference voltage (VR*). In one embodiment, when the threshold voltage (V TH ) is equal to or greater than the updated verification reference voltage (VR*), the processing device may determine that the threshold condition is met. In another embodiment, when the threshold voltage (V TH ) is equal to or less than the updated verification reference voltage (VR*), the processing device may determine that the threshold condition is met. The processing device may use different threshold conditions for different logic states. For example, the processing device may determine that the updated verification reference voltage (VR*) is the threshold voltage (V TH As another example, the processing device may determine the updated verification reference voltage (VR*) to be the threshold voltage (V THIn response to determining that the threshold condition is met, the processing device may stop or send an instruction to stop applying the programming pulse (PGM) to the memory cell.

[0089] On the other hand, in response to determining that the threshold condition is not met, the processing device may apply the next set of multiple programming pulses (PGM) to the memory cell. The processing device may use a higher voltage level for this set of programming pulses (PGM) than the previous set. The difference between two voltage levels is sometimes referred to as a voltage step. In one embodiment, the processing device may determine the difference in voltage levels for two consecutive sets of multiple programming pulses (PGM) based on the number of times a set of multiple programming pulses (PGM) has been applied to the memory cell and / or the number of times heat is to be applied to the memory device. For example, as the number of groups of applied programming pulses (PGM) increases, the processing device may reduce the voltage step of subsequent groups. As another example, when the number of times heat is applied to the memory device is three (relative to one), the processing device may reduce the voltage step for all or part of the multiple programming pulse (PGM) groups.

[0090] Figure 6 An example machine illustrating a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0091] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0092] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0093] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate via a network 620.

[0094] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution of the instructions thereof by the computer system 600, with the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0095] In one embodiment, instructions 626 include instructions for implementing instructions corresponding to read and write voltage management components (e.g., Figure 1 The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0096] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent series of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0097] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0098] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0099] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. Structures for a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0100] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0101] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: determining a logic state to be stored at a memory cell of a memory device, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verify reference voltage associated with the logic state, the verify reference voltage defining a target voltage level for the threshold voltage associated with the logic state; determining an amount of voltage compensation based at least on the logic state and a thermal profile associated with heat applied to the memory device during a reflow operation, the thermal profile including a temperature associated with the heat and a time period for which the heat is applied to the memory device; updating the verify reference voltage using the voltage compensation amount for an expected shift in the threshold voltage of the memory cell after applying the heat to the memory device; as well as Prior to applying the heat to the memory device, multiple sets of multiple programming pulses are applied to the memory cells until a threshold condition is met, wherein the threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell with respect to an updated verify reference voltage. 2 . The method of claim 1 , wherein updating the verification reference voltage further comprises combining the verification reference voltage with the voltage compensation amount. 3 . The method of claim 2 , wherein the voltage compensation amount associated with a lower logic state is less than the voltage compensation amount associated with a higher logic state.

4. The method of claim 1 , wherein applying the plurality of sets of programming pulses comprises: applying a first plurality of programming pulses to the memory cell to determine the threshold voltage to the memory cell; determining whether the threshold condition is met by comparing the updated verify reference voltage to a current threshold voltage of the memory cell; as well as In response to determining that the threshold condition is not met, a second plurality of programming pulses are applied to the memory cells, the second plurality of programming pulses being applied at a higher voltage level than the first plurality of programming pulses.

5. The method of claim 1 , wherein applying the plurality of sets of programming pulses comprises: A set of multiple programming pulses is applied at the same voltage level, each of the multiple programming pulses being applied successively to the memory cell.

6. The method of claim 1 , wherein applying the plurality of sets of programming pulses comprises: A number of a set of programming pulses is determined based on the logic state.

7. The method of claim 1 , wherein applying the plurality of sets of programming pulses comprises: A difference in voltage levels for two consecutive sets of pluralities of programming pulses is determined based on at least one of a number of times a set of pluralities of programming pulses have been applied to the memory cell or a number of times the heat is to be applied to the memory device.

8. A system comprising: Memory device; as well as a processing device operatively coupled to the memory device, the processing device being configured to perform operations comprising: determining a logic state to be stored at a memory cell of the memory device, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verify reference voltage associated with the logic state, the verify reference voltage defining a target voltage level for the threshold voltage associated with the logic state; determining an amount of voltage compensation based at least on the logic state and a thermal profile associated with heat applied to the memory device during a reflow operation, the thermal profile including a temperature associated with the heat and a time period for which the heat is applied to the memory device; updating the verify reference voltage using the voltage compensation amount for an expected shift in the threshold voltage of the memory cell after applying the heat to the memory device; as well as Prior to applying the heat to the memory device, multiple sets of multiple programming pulses are applied to the memory cells until a threshold condition is met, wherein the threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell with respect to an updated verify reference voltage. 9 . The system of claim 8 , wherein updating the verify reference voltage comprises combining the verify reference voltage with the voltage compensation amount.

10. The system of claim 9, wherein the voltage compensation amount associated with a lower logic state is less than the voltage compensation amount associated with a higher logic state.

11. The system of claim 8, wherein applying the plurality of sets of programming pulses comprises: applying a first plurality of programming pulses to the memory cell to determine the threshold voltage to the memory cell; determining whether the threshold condition is met by comparing the updated verify reference voltage to a current threshold voltage of the memory cell; responsive to determining that the threshold condition is not met, applying a second plurality of programming pulses to the memory cell, the second plurality of programming pulses being applied at a higher voltage level than the first plurality of programming pulses; as well as Responsive to determining that the threshold condition is met, applying the sets of multiple programming pulses to the memory cells is stopped.

12. The system of claim 8, wherein applying the plurality of sets of programming pulses comprises: A set of multiple programming pulses is applied at the same voltage level, each of the multiple programming pulses being applied successively to the memory cell.

13. The system of claim 8, wherein applying the plurality of sets of programming pulses comprises: The number of programming pulses comprising a group is determined based on the logic state.

14. The system of claim 8, wherein applying the plurality of sets of programming pulses comprises: A difference in voltage levels for two consecutive sets of pluralities of programming pulses is determined based on at least one of a number of times a set of pluralities of programming pulses have been applied to the memory cell or a number of times the heat is to be applied to the memory device.

15. A method comprising: determining a logic state to be stored at a memory cell of a memory device, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verify reference voltage associated with the logic state, the verify reference voltage defining a target voltage level for the threshold voltage associated with the logic state; determining, after applying heat to the memory device, an amount of voltage compensation for an expected shift in the threshold voltage of the memory cell based at least on a thermal profile used in association with the heat, wherein the thermal profile includes a temperature associated with the heat and a time period for which the heat is applied to the memory device; Using the voltage compensation amount to update the verification reference voltage; as well as Whether to continue applying programming pulses to the memory cell is determined based on an updated verify reference voltage, wherein the programming pulses are applied to the memory cell before the heat is applied to the memory device.

16. The method of claim 15, wherein the temperature associated with the heat corresponds to a peak temperature, and the time period corresponds to a duration for the heat to reach the peak temperature when applied to the memory device.

17. The method of claim 15, wherein determining whether to continue applying the programming pulse to the memory cell comprises: comparing a current threshold voltage of the memory cell to the updated verify reference voltage; in response to determining that the threshold voltage of the memory cell has not reached the updated verification reference voltage, determining to continue applying the programming pulse to the memory cell; as well as In response to determining that the threshold voltage of the memory cell has reached the updated verification reference voltage, it is determined not to continue applying the programming pulse to the memory cell.

18. The method of claim 15, wherein determining the voltage compensation amount is further based on at least one of the logic state or a number of times the heat is applied to the memory device.

19. An apparatus comprising: a plurality of memory cells; as well as A processing device configured to perform operations including: determining a logic state to be stored at a memory cell of the plurality of memory cells, the logic state to be represented by a threshold voltage stored at the memory cell; determining a verify reference voltage associated with the logic state, the verify reference voltage defining a target voltage level for the threshold voltage associated with the logic state; determining an amount of voltage compensation based at least on the logic state and a thermal profile associated with heat applied to the plurality of memory cells during a reflow operation, the thermal profile including a temperature associated with the heat and a time period for which the heat is applied to the plurality of memory cells; updating the verify reference voltage using the voltage compensation amount for an expected shift in the threshold voltage of the memory cell after applying the heat to the device; as well as Prior to applying the heat to the apparatus, multiple sets of multiple programming pulses are applied to the memory cells until a threshold condition is met, wherein the threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell with respect to an updated verify reference voltage.

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