Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, conductive patterns on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, edges of the conductive patterns including stepped portions such that an end portion of one conductive pattern does not overlap with a conductive pattern positioned above the one conductive pattern in the vertical direction, insulating patterns between the conductive patterns, sidewall insulating patterns on sidewalls of the conductive patterns to cover the sidewalls of the conductive patterns, upper pad patterns on upper surfaces of the stepped portions of the conductive patterns, an insulating interlayer covering the conductive patterns, the insulating patterns, the sidewall insulating patterns, and the upper pad patterns, and contact plugs through the insulating interlayer, the contact plugs respectively contacting the upper pad patterns.

Description

[0001] Korean Patent Application No. 10-2019-0168614, entitled "Semiconductor Device", filed on December 17, 2019 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to semiconductor devices. Background Technology

[0003] Recently, vertical memory devices in which memory cells are vertically stacked from the surface of a substrate have been considered. The edge portions of the stacked conductive patterns included in the memory cells may have a stepped shape, and the upper surfaces of the edge portions may each serve as pad patterns. Contact plugs may be formed on each of the pad patterns. Summary of the Invention

[0004] An embodiment can be implemented by providing a semiconductor device comprising: a substrate; conductive patterns located on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to the surface of the substrate, the edges of the conductive patterns including stepped portions such that the end of one conductive pattern does not overlap with a conductive pattern positioned above said conductive pattern in the vertical direction; insulating patterns located between the conductive patterns; sidewall insulating patterns located on the sidewalls of the conductive patterns to cover the sidewalls of the conductive patterns; an upper pad pattern located on the upper surface of the stepped portions of the conductive patterns; an insulating interlayer covering the conductive patterns, insulating patterns, sidewall insulating patterns and upper pad patterns; and contact plugs passing through the insulating interlayer, the contact plugs respectively contacting the upper pad patterns.

[0005] The embodiment can be implemented by providing a semiconductor device comprising: a substrate; conductive patterns located on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to the surface of the substrate, the conductive patterns comprising polysilicon, the edges of the conductive patterns including stepped portions such that the end of one conductive pattern does not overlap with a conductive pattern positioned above said conductive pattern in the vertical direction; insulating patterns located between the conductive patterns; sidewall insulating patterns located on the sidewalls of the conductive patterns to cover the sidewalls of the conductive patterns, the sidewall insulating patterns being respectively located on the insulating patterns; and an upper pad pattern located on the steps of the conductive patterns. On the upper surface of a portion, the upper pad pattern includes polysilicon; an insulating interlayer covering the conductive pattern, the insulating pattern, the sidewall insulating pattern, and the upper pad pattern; a channel structure passing through the conductive pattern and the insulating pattern, the channel structure being connected to the substrate, and the channel structure including a dielectric layer structure, a channel, a buried insulating pattern, and an upper conductive pattern; and contact plugs passing through the insulating interlayer, the contact plugs contacting the upper pad patterns respectively, wherein the upper surface of one upper pad pattern is closer to the substrate in the vertical direction than the upper surface of the adjacent sidewall insulating pattern in the vertical direction, the adjacent sidewall insulating pattern being one level higher than the one upper pad pattern.

[0006] The embodiment can be implemented by providing a semiconductor device comprising: a substrate; conductive patterns located on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to the surface of the substrate, the conductive patterns comprising polysilicon, the edges of the conductive patterns including stepped portions such that the end of one conductive pattern does not overlap with a conductive pattern positioned above said conductive pattern in the vertical direction; insulating patterns located between the conductive patterns; sidewall insulating patterns located on the sidewalls of the conductive patterns respectively to cover the sidewalls of the conductive patterns; upper pad patterns located on the upper surface of the stepped portions of the conductive patterns, the upper pad patterns comprising polysilicon; an insulating interlayer covering the conductive patterns, insulating patterns, sidewall insulating patterns and upper pad patterns; and contact plugs passing through the insulating interlayer, the contact plugs respectively contacting the upper pad patterns, wherein the bottom of each contact plug is located at the upper surface or inner portion of a stacked structure including an upper pad pattern and a lower conductive pattern contacting said upper pad pattern, and the thickness of each upper pad pattern in the vertical direction is less than the thickness of the stacked structure of a conductive pattern and an insulating pattern in the vertical direction. Attached Figure Description

[0007] Features will become apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 and Figure 2 These are cross-sectional views and plan views of a semiconductor device according to an example embodiment;

[0009] Figure 3This is a cross-sectional view of a portion of the pad structure in a semiconductor device;

[0010] Figures 4 to 15 These are cross-sectional and plan views of stages in a method of manufacturing a semiconductor device according to an exemplary embodiment;

[0011] Figure 16 and Figure 17 These are cross-sectional views and plan views of a semiconductor device according to an example embodiment;

[0012] Figures 18 to 23 These are cross-sectional and plan views of stages in a method of manufacturing a semiconductor device according to an exemplary embodiment;

[0013] Figure 24 and Figure 25 These are cross-sectional views and plan views of a semiconductor device according to an example embodiment; and

[0014] Figures 26 to 31 These are cross-sectional and plan views of stages in a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0015] In the following text, the direction substantially perpendicular to the upper surface of the substrate is defined as the vertical direction. Two directions substantially parallel to the upper surface of the substrate and intersecting each other are defined as the first direction and the second direction, respectively. In the example embodiment, the first direction and the second direction may be substantially perpendicular to each other.

[0016] Figure 1 and Figure 2 These are cross-sectional and plan views of a semiconductor device according to an example embodiment. Figure 3 This is a cross-sectional view of a portion of the pad structure in a semiconductor device.

[0017] Reference Figures 1 to 3 The substrate 100 may include a first region and a second region. The first region may be a cell region where memory cells are disposed, and the second region may be a wiring region where wiring is formed. In an embodiment, the second region may be located on the side of the edge of the first region (e.g., in a first direction). In an embodiment, as... Figure 1 and Figure 2 As shown, the second region may be located on one side of an edge of the first region. Alternatively, only a portion of the first region may be shown in the figures. In an embodiment, the width of the first region in the first direction may be greater than the width of the second region in the first direction.

[0018] The substrate 100 may include semiconductor materials such as silicon or germanium.

[0019] The lower insulating layer 101 may be located on the substrate 100. The conductive pattern structure 106c may be located on the lower insulating layer 101.

[0020] The conductive pattern structure 106c can extend from the first region to the second region. The conductive pattern structure 106c can extend in a first direction parallel to the surface of the substrate 100.

[0021] Multiple conductive pattern structures 106c may be spaced apart from each other in a second direction. An opening 134 may be located between the conductive pattern structures 106c. In one embodiment, a unit block may be divided by the opening 134. In this case, the opening 134 may be located between the unit blocks.

[0022] First, the conductive pattern structure 106c on the first region can be described.

[0023] The conductive pattern structure 106c on the first region may include alternately stacked conductive patterns 104b and insulating patterns 102b. In one embodiment, the conductive patterns 104b may be spaced apart from each other in a vertical direction from the upper surface of the substrate 100. In another embodiment, each of the conductive patterns 104b may have a line shape or a strip shape extending in a first direction.

[0024] The upper and lower surfaces (e.g., the surface facing away from the substrate 100 and the surface facing the substrate 100) of the conductive pattern 104b and the insulating pattern 102b can be substantially flat.

[0025] In one embodiment, the conductive pattern 104b may have a first thickness t1 in the vertical direction. The insulating pattern 102b may have a second thickness t2 in the vertical direction that is less than the first thickness t1.

[0026] The conductive pattern 104b may include a ground select line (GSL), a serial select line (SSL), and a word line located between the ground select line and the serial select line.

[0027] The conductive pattern 104b may include polysilicon.

[0028] The conductive pattern structure 106c on the second region can be described below.

[0029] The edge or side of the conductive pattern structure 106c in the second region may have a stepped shape. The conductive pattern structure 106c in the second region may include an insulating pattern 102b, a conductive pattern 104b, an upper pad pattern 114, and a sidewall insulating pattern 110.

[0030] The insulating pattern 102b and conductive pattern 104b of the conductive pattern structure 106c in the second region can extend from the insulating pattern 102b and conductive pattern 104b of the conductive pattern structure 106c in the first region (e.g., they can be continuous with the insulating pattern 102b and conductive pattern 104b of the conductive pattern structure 106c in the first region). In an embodiment, the insulating pattern 102b and conductive pattern 104b in the second region can have the same stacked structure as the stacked structure of the insulating pattern 102b and conductive pattern 104b in the first region. In an embodiment, each of the insulating patterns 102b can be located between the conductive patterns 104b in the vertical direction, such that the conductive patterns 104b can be spaced apart from each other in the vertical direction by means of the insulating patterns 102b. The conductive patterns 104b can extend in a first direction (e.g., longitudinally).

[0031] Additionally, the edges of the insulating pattern 102b and the conductive pattern 104b in the second region may have a stepped shape. The insulating pattern 102b that contacts the bottom (e.g., the side facing the substrate 100) of one of the conductive patterns 104b may have a length in the first direction greater than the length of the conductive pattern 104b located on that insulating pattern 102b. In an embodiment, the insulating pattern 102b that contacts the bottom of one of the conductive patterns 104b may protrude from or beyond the conductive pattern 104b located on that insulating pattern 102b along the first direction.

[0032] In each conductive pattern 104b in the second region, the portion that does not overlap with the conductive pattern 104b positioned above it (e.g., an adjacent conductive pattern 104b that is further away from the substrate 100 in the vertical direction) may be referred to as a stepped portion. At least a portion of the stepped portion of each conductive pattern 104b may serve as a pad pattern 112. In an embodiment, in each conductive pattern 104b, the portion that overlaps with the conductive pattern 104b positioned above it and the sidewall insulating pattern 110 may be a pad pattern 112.

[0033] Sidewall insulating patterns 110 may be located on the sidewalls of conductive patterns 104b respectively. Sidewall insulating patterns 110 may cover the sidewalls of conductive patterns 104b (e.g., each of conductive patterns 104b). Sidewall insulating patterns 110 may be located on insulating patterns 102b respectively.

[0034] The sidewall insulating pattern 110 may include an insulating material having (e.g., high) etch selectivity relative to the conductive pattern 104b and the insulating pattern 102b (e.g., it may be etched at different rates relative to the conductive pattern 104b and the insulating pattern 102b under the same etch conditions). In embodiments, the sidewall insulating pattern 110 may include, for example, a nitride such as silicon nitride.

[0035] In one embodiment, the upper surface of the sidewall insulating pattern 110 (e.g., the surface facing away from the substrate 100 in the vertical direction) and the upper surface of the lower pad pattern 112 may be substantially coplanar with each other. In another embodiment, the lower surface of the sidewall insulating pattern 110 (e.g., the surface facing the substrate 100) may be substantially coplanar with the lower surface of the lower pad pattern 112, or the lower surface of the sidewall insulating pattern 110 may be lower than the lower surface of the lower pad pattern 112 (e.g., closer to the substrate 100 in the vertical direction than the lower surface of the lower pad pattern 112).

[0036] The upper pad pattern 114 may at least cover the entire upper surface of the lower pad pattern 112. In one embodiment, the upper pad pattern 114 may be located on the upper surface of the lower pad pattern 112 and a portion of the upper surface of the sidewall insulating pattern 110. In one embodiment, the end of the upper pad pattern 114 may protrude from or beyond the end of the lower pad pattern 112 below it in a first direction. In another embodiment, the end of the upper pad pattern 114 may not protrude from or beyond the end of the sidewall insulating pattern 110 below it in the first direction.

[0037] The upper pad pattern 114 may include silicon. In one embodiment, the upper pad pattern 114 may include polycrystalline silicon. The upper pad pattern 114 may include silicon formed from the lower pad pattern 112 by epitaxial growth.

[0038] In an embodiment, the upper surface of the upper pad pattern 114 may be lower than the upper surface of the sidewall insulating pattern 110 positioned at a level above the upper pad pattern 114 (e.g., closer to the substrate 100 in the vertical direction). In other words, the upper surface of the upper pad pattern 114 may be closer to the substrate 100 in the vertical direction than the upper surface of an adjacent sidewall insulating pattern 110 that is a level higher than the upper pad pattern. In an embodiment, the thickness of the upper pad pattern 114 (in the vertical direction) may be less than the thickness of the stacked structure of one of the conductive patterns 104b and one of the insulating patterns 102b. If the thickness of the upper pad pattern is greater than the thickness of the stacked structure of one of the conductive patterns and one of the insulating patterns, bridging failures between adjacent upper pad patterns may occur.

[0039] A structure formed by stacking one of the lower pad patterns 112 and one of the upper pad patterns 114 can be used as a pad structure 116. A contact plug 142 can be located on the pad structure 116. The vertical thickness of the pad structure 116 can be greater than the first thickness t1 of one of the conductive patterns 104b.

[0040] In one embodiment, the upper pad pattern 114 may be formed on the uppermost conductive pattern 104b in the conductive pattern structure 106c. In another embodiment, the upper pad pattern 114 located on or at the top of the conductive pattern structure 106c (e.g., furthest from the substrate 100 in the vertical direction) may be formed on the first region and the second region.

[0041] The first insulating interlayer 118 may cover the conductive pattern structure 106c. The upper surface of the first insulating interlayer 118 may be substantially flat. The first insulating interlayer 118 may include silicon oxide.

[0042] The channel structure 130 can pass through the conductive pattern structure 106c and the first insulating interlayer 118 on the first region, and the channel structure 130 can be electrically connected to the substrate 100.

[0043] In one embodiment, a semiconductor pattern 120 may also be formed between the substrate 100 and the channel structure 130. The semiconductor pattern 120 may include, for example, monocrystalline silicon or polycrystalline silicon.

[0044] The channel structure 130 may include a dielectric layer structure 122, a channel 124, a buried insulating pattern 126, and an upper conductive pattern 128. The channel 124 may have a hollow cylindrical shape or a cup shape. The channel 124 may include polycrystalline silicon or monocrystalline silicon. The buried insulating pattern 126 may fill the internal space of the channel 124. The dielectric layer structure 122 may surround the outer wall of the channel 124. The dielectric layer structure 122 may include a tunnel insulating layer, a charge storage layer, and a barrier layer sequentially stacked on the outer wall of the channel 124. The upper conductive pattern 128 may be formed on the buried insulating pattern 126, and the upper conductive pattern 128 may be electrically connected to the channel 124.

[0045] The second insulating layer 132 may be formed on the first insulating layer 118. The first insulating layer 118 and the second insulating layer 132 may comprise the same material, such that the first insulating layer 118 and the second insulating layer 132 may be combined into a single insulating layer.

[0046] In one embodiment, the second insulating pattern 136 may fill the opening 134 between the conductive pattern structures 106c. In another embodiment, a common source electrode may be formed by passing through the second insulating pattern 136 in the opening 134, and the common source electrode may be connected to the substrate 100. The common source electrode may be spaced apart from the conductive pattern 104b by the second insulating pattern 136.

[0047] The contact plug 142 can pass through the first insulating layer 118 and the second insulating layer 132, such that the contact plug 142 can contact the pad structure 116 respectively. In an embodiment, the contact plug 142 can be electrically connected to the conductive pattern 104b respectively. In an embodiment, the contact plug 142 may include a blocking metal pattern and a metal pattern.

[0048] Contact plugs 142 can contact the upper pad pattern 114. The bottom of contact plug 142 can be located on the upper surface or inner portion of the stacked structure including the stacked upper pad pattern 114 and lower pad pattern 112. In an embodiment, the bottom of contact plug 142 can be located on the upper surface or inner portion of the pad structure 116. In an embodiment, the bottom of contact plug 142 that contacts the pad structure 116 located relative to the upper step (e.g., a step vertically away from the base 100) can be located in the lower inner portion of the pad structure 116 (e.g., it can penetrate deeply into the pad structure 116). The bottom of contact plug 142 that contacts the pad structure 116 located relative to the lower step (e.g., a step vertically close to the base 100) can be located in the upper inner portion or upper surface of the pad structure 116 (e.g., it can penetrate shallowly into the pad structure 116).

[0049] In one embodiment, the thickness of the portion where the bottom of the contact plug 142 is located (e.g., a pad or connecting structure) can be increased, thereby increasing the process margin for forming the contact plug 142. In another embodiment, defects in the contact plug 142 can be reduced. In yet another embodiment, non-contact (e.g., disconnection) or punching defects (where the contact plug 142 extends into the conductive pattern beneath the target pad structure) between the contact plug 142 and the pad structure 116 can be reduced.

[0050] Wiring that is electrically connected to the upper surface of the contact plug 142 can also be formed on the second insulating interlayer 132. In an embodiment, the wiring may have a line shape extending in a second direction. Wiring that is electrically connected to the channel structure 130 can also be formed on the second insulating interlayer 132.

[0051] Figures 4 to 15 These are cross-sectional and plan views of stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0052] Figures 4 to 6 , Figure 8 , Figure 9 , Figure 11 , Figure 13 and Figure 15 It is a sectional view. Figure 7 , Figure 10 , Figure 12and Figure 14 It's a floor plan.

[0053] Reference Figure 4 A lower insulating layer 101 can be formed on a substrate 100 including a first region and a second region. A first conductive layer 104 and an insulating layer 102 can be alternately and repeatedly formed on the lower insulating layer 101 to form a stacked structure. In an embodiment, the lower insulating layer 101 and the insulating layer 102 can be formed of an oxide such as silicon oxide, silicon carbonate, or silicon oxyfluoride. In an embodiment, the first conductive layer 104 can be formed of polycrystalline silicon.

[0054] In one embodiment, the lower insulating layer 101 that directly contacts the substrate 100 may have a greater vertical thickness than each of the insulating layers 102 above it. In another embodiment, each insulating layer 102 may have a smaller thickness than each of the first conductive layers 104. By reducing the thickness of each insulating layer 102, the height of the stacked structure can be reduced.

[0055] Reference Figure 5 A portion of the insulating layer 102 and the first conductive layer 104 can be etched to form a first initial conductive pattern structure 106a with a stepped shape at the edge portions. The first initial conductive pattern structure 106a may include alternately stacked initial conductive patterns 104a and initial insulating patterns 102a. The lower insulating layer 101 may be retained on the surface of the substrate 100 with a predetermined thickness, such that the surface of the substrate 100 can be covered by the lower insulating layer 101. In an embodiment, the surface of the substrate 100 adjacent to the first initial conductive pattern structure 106a may not be exposed.

[0056] In one embodiment, the edge portion of the first initial conductive pattern structure 106a may have a stepped shape (e.g., a downward step in the first direction). In another embodiment, the edge portion of the first initial conductive pattern structure 106a may have a stepped shape (e.g., a downward step) in each of the first and second directions.

[0057] The upper surface of the initial insulating pattern 102a may be exposed at the stepped portion of the first initial conductive pattern structure 106a. In one embodiment, the initial insulating pattern 102a at the stepped portion may have a thickness smaller than the thickness of the insulating layer 102 during deposition. In another embodiment, the initial insulating pattern 102a positioned at the stepped portion may have a thickness substantially the same as the thickness of the insulating layer 102 during deposition.

[0058] Reference Figure 6 and Figure 7The initial conductive pattern 104a exposed by the sidewalls of the first initial conductive pattern structure 106a can be partially etched to form a conductive pattern 104b. In an embodiment, an undercut portion 108 defined by the conductive pattern 104b and the initial insulating pattern 102a positioned on and below the conductive pattern 104b can be formed by an etching process.

[0059] The etching process may include an isotropic etching process. In an embodiment, the isotropic etching process may include a wet etching process or an isotropic dry etching process.

[0060] In this embodiment, the width of the undercut portion 108 (in the first direction) can be approximately to approximately To increase the width of the undercut portion in the first direction, the length of the initial conductive pattern 104a (in the first direction) can be increased. Therefore, the width of the first initial conductive pattern structure 106a in the first direction will increase. The width of the undercut portion 108 in the first direction is maintained at approximately... A larger size can help prevent bridging failures between pad patterns in subsequent processes. In an embodiment, the width of the undercut portion 108 in the first direction can be approximately... to approximately

[0061] Reference Figure 8 This can form a sidewall insulating pattern 110 to fill the undercut portion 108.

[0062] In one embodiment, an insulating layer can be conformally formed on the surface of the first initial conductive pattern structure 106a to fill the undercut portion 108. Subsequently, the insulating layer can be anisotropically etched to form a sidewall insulating pattern 110.

[0063] The sidewall insulating pattern 110 may include an insulating material having a high etch selectivity relative to the conductive pattern 104b and the initial insulating pattern 102a. In an embodiment, the sidewall insulating pattern 110 may be formed of a nitride such as silicon nitride.

[0064] Reference Figure 9 and Figure 10 An initial insulating pattern 102a located on the stepped portion of the first initial conductive pattern structure 106a can be etched to form an insulating pattern 102b. The etching process exposes the upper surface of the stepped portion of the conductive pattern 104b and the upper surface of the sidewall insulating pattern 110. The etching process may include anisotropic etching. The sidewall insulating pattern 110 can be formed on the sidewall of the conductive pattern 104b.

[0065] In one embodiment, the sidewalls of the sidewall insulating pattern 110 and the sidewalls of the insulating pattern 102b may correspond to the sidewalls of the stepped portion of the first initial conductive pattern structure 106a. In another embodiment, the upper surface of the conductive pattern 104b and the upper surface of the sidewall insulating pattern 110 may be exposed at the stepped portion of the first initial conductive pattern structure 106a.

[0066] After the etching process, the lower insulating layer 101 in contact with the surface of the substrate 100 can maintain a predetermined thickness. In an embodiment, this surface of the substrate 100 can be covered by the lower insulating layer 101.

[0067] In the first initial conductive pattern structure 106a, the conductive pattern 104b on the first region can be used as a gate pattern, and the conductive pattern 104b on the second region can be connected to the gate pattern. In an embodiment, the exposed step portion of the conductive pattern 104b on the second region can be used as a pad pattern 112.

[0068] Reference Figure 11 and Figure 12 The upper pad pattern 114 can be formed on the lower pad pattern 112 using a selective epitaxial growth process. The upper pad pattern 114 can be formed by using the lower pad pattern 112 (including polysilicon) as seed silicon for growth. In one embodiment, the upper pad pattern 114 may include polysilicon. In another embodiment, a second initial conductive pattern structure 106b can be formed.

[0069] When performing a selective epitaxial growth process, the upper pad pattern 114 can be grown in both the vertical and horizontal directions. In an embodiment, the upper pad pattern 114 can be formed on a portion of the upper surface of the sidewall insulating pattern 110 and the upper surface of the lower pad pattern 112.

[0070] The upper surface of the upper pad pattern 114 may be lower than the upper surface of the sidewall insulating pattern 110 positioned above the upper pad pattern 114 at a certain level (e.g., it may be lower than the upper surface of the sidewall insulating pattern 110 that is laterally adjacent to the upper pad pattern 114 in a first direction). When the upper surface of the upper pad pattern 114 is higher than the upper surface of the sidewall insulating pattern 110 positioned at a certain level, the upper pad pattern 114 and the lower pad pattern 112 positioned at a certain level may be in contact with each other.

[0071] The structure of one of the lower pad patterns 112 and one of the upper pad patterns 114 stacked together can be used as pad structure 116.

[0072] In one embodiment, an upper pad pattern 114 may be formed on the uppermost conductive pattern 104b (e.g., the conductive pattern 104b furthest from the substrate 100 in the vertical direction) in the second initial conductive pattern structure 106b. In another embodiment, the conductive pattern 104b and the upper pad pattern 114 may be stacked on top of the second initial conductive pattern structure 106b in the first region and the second region.

[0073] Reference Figure 13 and Figure 14 A first insulating interlayer 118 can be formed to cover the second initial conductive pattern structure 106b.

[0074] In one embodiment, an oxide layer, such as silicon oxide, silicon carbonate, or silicon oxyfluoride, may be formed on the second initial conductive pattern structure 106b, and the upper surface of the oxide layer may be planarized to form the first insulating interlayer 118. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0075] Subsequently, channel holes exposing the surface of the substrate 100 can be formed through the second initial conductive pattern structure 106b and the first insulating interlayer 118 in the first region. Channel structures 130 can be formed in the channel holes respectively. In an embodiment, a semiconductor pattern 120 contacting the substrate 100 can also be formed under each channel structure 130.

[0076] In one embodiment, a selective epitaxial growth process can be performed on the substrate 100 exposed by the channel via to form a semiconductor pattern 120. A channel structure 130 including a dielectric layer structure 122, a channel 124, a buried insulating pattern 126, and an upper conductive pattern 128 can be formed on the semiconductor pattern 120.

[0077] A second insulating layer 132 can be formed on the first insulating layer 118 to cover the trench structure 130.

[0078] The second initial conductive pattern structure 106b and the first insulating interlayer 118 and the second insulating interlayer 132 can be anisotropically etched to form an opening 134 extending longitudinally in the first direction. In an embodiment, the opening 134 can be used to separate the unit blocks of the semiconductor device.

[0079] In one embodiment, a second insulating pattern 136 may be formed to fill the opening 134. In another embodiment, a common-source electrode connected to the substrate may be formed through the second insulating pattern 136 in the opening 134. The common-source electrode may be spaced apart from the conductive pattern 104b by the second insulating pattern 136.

[0080] In one embodiment, the second initial conductive pattern structure 106b can be separated from each other, thereby forming a conductive pattern structure 106c on the side of the opening 134. The conductive pattern structure 106c can extend in a first direction. The surface of the substrate 100 can be exposed by the bottom of the opening 134.

[0081] The conductive pattern structure 106c on the first region may include an insulating pattern 102b and a conductive pattern 104b. The conductive pattern structure 106c on the second region may include an insulating pattern 102b, a conductive pattern 104b, an upper pad pattern 114, and a sidewall insulating pattern 110.

[0082] Reference Figure 15 The first insulating interlayer 118 and the second insulating interlayer 132 can be etched to form contact holes 140 of the exposed pad structure 116, respectively. In an embodiment, the bottom of each of the contact holes 140 may expose a lower pad pattern 112 or an upper pad pattern 114.

[0083] In one embodiment, the pad structure 116 has a stepped shape, and the vertical heights of the upper surfaces of the pad structure 116 (e.g., relative to the substrate 100) may differ from each other. In another embodiment, during the etching process, the contact hole 140 may be formed on the pad structure 116 positioned at the upper level before forming the contact hole 140 on the pad structure 116 positioned at the lower level. During the etching process, the pad structure 116 positioned at the upper level may be over-etched. In another embodiment, the pad structure 116 may include a stacked lower pad pattern 112 and an upper pad pattern 114, and the pad structure 116 may have sufficient thickness. In another embodiment, punching defects caused by over-etching, such as the bottom of the contact hole 140 extending below or through the lower surface of the lower pad pattern, can be reduced.

[0084] Refer again Figure 1 and Figure 2 Conductive material can be formed in the contact hole 140 to form the contact plug 142.

[0085] In one embodiment, a barrier metal layer may be conformally formed on the surfaces of the contact hole 140 and the second insulating interlayer 132, and a metal layer may be formed on the barrier metal layer. The metal layer and the barrier metal layer may be planarized until the upper surface of the second insulating interlayer 132 can be exposed to form the contact plug 142.

[0086] Wiring that electrically connects to the upper surface of the contact plug 142 can also be formed on the second insulating interlayer 132. Additionally, wiring that electrically connects to the channel structure 130 can also be formed on the second insulating interlayer 132.

[0087] Figure 16 and Figure 17These are cross-sectional and plan views of a semiconductor device according to an example embodiment.

[0088] Apart from the shape of the conductive pattern structure on the second region, the semiconductor device is similar to the reference Figures 1 to 3 The semiconductor devices described are essentially the same. Therefore, repeated descriptions can be omitted or only briefly described.

[0089] Reference Figure 16 and Figure 17 The edge portion of the conductive pattern structure 107b in the second region may have a stepped shape. The conductive pattern structure 107b in the second region may include an insulating pattern 102b, a conductive pattern 105a, an upper pad pattern 114a, and a sidewall insulating pattern 150a. The insulating pattern 102b and the conductive pattern 105a in the conductive pattern structure 107b in the second region may extend from the insulating pattern 102b and the conductive pattern 105a in the conductive pattern structure 107b in the first region.

[0090] The edge portions of the insulating pattern 102b and conductive pattern 105a in the second region may have a stepped shape. A portion of the stepped portion of each conductive pattern 105a may serve as a pad pattern 112a. In an embodiment, the portion of each conductive pattern 105a that does not overlap with the conductive pattern 105a and the sidewall insulating pattern 150a positioned thereon may be a pad pattern 112a.

[0091] Sidewall insulating pattern 150a may be formed on the sidewall of the underlying pad pattern 112a. Sidewall insulating pattern 150a may include an insulating material having a high etch selectivity relative to the conductive pattern 105a. In one embodiment, sidewall insulating pattern 150a may be formed of a nitride such as silicon nitride. In another embodiment, sidewall insulating pattern 150a may include silicon oxide. In yet another embodiment, sidewall insulating pattern 150a may have a structure with a stack of silicon oxide and silicon nitride layers.

[0092] The upper surface of the sidewall insulating pattern 150a on the sidewall of one of the conductive patterns 105a may be higher than the upper surface of the conductive pattern 105a. In an embodiment, the upper surface of the sidewall insulating pattern 150a on the sidewall of an adjacent conductive pattern 105a may protrude from the upper surface of the conductive pattern 105a (e.g., it may protrude further from the substrate 100 in the vertical direction).

[0093] In one embodiment, the width of the sidewall insulating pattern 150a in the first direction may be less than about half the width of the stepped portion of the conductive pattern 105a in the first direction. In another embodiment, the width of the sidewall insulating pattern 150a in the first direction may be greater than the thickness of the insulating pattern 102b in the first region.

[0094] The upper pad pattern 114a may at least cover the upper surface of the lower pad pattern 112a. The upper pad pattern 114a may include silicon. In one embodiment, the upper pad pattern 114a may include polycrystalline silicon. The upper pad pattern 114a may include silicon formed by epitaxial growth from the lower pad pattern 112a.

[0095] In one embodiment, the upper surface of the upper pad pattern 114a may be coplanar with the upper surface of the sidewall insulating pattern 150a, or the upper surface of the upper pad pattern 114a may be lower than the upper surface of the sidewall insulating pattern 150a. In another embodiment, the thickness of the upper pad pattern 114a (e.g., in the vertical direction) may be less than the thickness of the stacked structure including one of the conductive patterns 105a and one of the insulating patterns 102b.

[0096] In one embodiment, conductive pattern 105a and upper pad pattern 114a may be stacked on top of conductive pattern structure 107b. In another embodiment, the uppermost upper pad pattern 114a in conductive pattern structure 107b may be located on both the first region and the second region.

[0097] A first insulating interlayer 118 may cover the conductive pattern structure 107b. A channel structure 130 electrically connected to the substrate 100 may pass through the conductive pattern structure 107b on the first region and the first insulating interlayer 118. A second insulating interlayer 132 may be formed on the first insulating interlayer 118.

[0098] The contact plug 142, passing through the first insulating interlayer 118 and the second insulating interlayer 132, can respectively contact the pad structure 116a. The pad structure 116a may include a stacked lower pad pattern 112a and an upper pad pattern 114a.

[0099] Figures 18 to 23 These are cross-sectional and plan views of stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0100] Figure 18 , Figure 19 , Figure 21 and Figure 23 It is a sectional view. Figure 20 and Figure 22 It's a floor plan.

[0101] Reference Figure 18 First, you can execute the following as referenced. Figures 4 to 5 The process shown is used to form a first initial conductive pattern structure 106a on a lower insulating layer. The first initial conductive pattern structure 106a may include alternately stacked conductive patterns 105a and initial insulating patterns 102a.

[0102] A spacer insulating layer 150 may be conformally formed on the first initial conductive pattern structure 106a and the lower insulating layer 101. The upper surface of the spacer insulating layer 150 formed on at least a portion of the stepped portion of the first initial conductive pattern structure 106a may be flat.

[0103] When the spacer insulating layer 150 is thick, the horizontal portion of the subsequently formed upper pad pattern will be reduced. In an embodiment, the thickness of the spacer insulating layer 150 may be less than about half the width of the stepped portion in the first direction in the first initial conductive pattern structure 106a. If the thickness of the spacer insulating layer 150 is too thin, the height of the subsequently formed upper pad pattern will be reduced. In an embodiment, the thickness of the spacer insulating layer 150 may be greater than the vertical thickness of each initial insulating pattern 102a in the first region.

[0104] The spacer insulating layer 150 may include an insulating material having a high etch selectivity relative to the conductive pattern 105a. In one embodiment, the spacer insulating layer 150 may be formed of a nitride such as silicon nitride. In another embodiment, the spacer insulating layer 150 may be formed of silicon oxide. In yet another embodiment, the spacer insulating layer 150 may have a structure of stacked silicon oxide and silicon nitride layers.

[0105] Reference Figure 19 and Figure 20 The spacer insulating layer 150 can be etched anisotropically to form a sidewall insulating pattern 150a on the sidewall of the first initial conductive pattern structure 106a.

[0106] The sidewall insulating pattern 150a can help protect the conductive pattern 105a and the initial insulating pattern 102a at the stepped portion of the first initial conductive pattern structure 106a.

[0107] Subsequently, the initial insulating pattern 102a on the step portion adjacent to the sidewall insulating pattern 150a in the first initial conductive pattern structure 106a can be etched anisotropically to form the insulating pattern 102b.

[0108] In one embodiment, the conductive pattern 105a may be exposed at a stepped portion adjacent to the sidewall insulating pattern 150a. The stepped portion in each conductive pattern 105a may serve as a pad pattern 112a.

[0109] The upper surface of the sidewall insulating pattern 150a on the sidewall of the conductive pattern 105a may be higher than the upper surface of the stepped portion of the conductive pattern (e.g., farther from the substrate 100 in the vertical direction). In an embodiment, the upper surface of the sidewall insulating pattern 150a on the sidewall of the conductive pattern 105a may protrude from or beyond the upper surface of the stepped portion of the conductive pattern 105. In an embodiment, a recess defined by the sidewall insulating pattern 150a may be formed on the stepped portion of the conductive pattern 105.

[0110] Reference Figure 21 and Figure 22 A selective epitaxial growth process can be performed on the lower pad pattern 112a to form the upper pad pattern 114a. The upper pad pattern 114a can be formed by using the lower pad pattern 112a, which includes polysilicon, as seed silicon. In an embodiment, the upper pad pattern 114a may include polysilicon. By performing the process, a second initial conductive pattern structure 107a can be formed.

[0111] In one embodiment, an upper pad pattern 114a may be formed in a recess formed by the sidewall insulating pattern 150a. In another embodiment, the upper surface of the upper pad pattern 114a may be coplanar with the upper surface of the sidewall insulating pattern 150a, or the upper surface of the upper pad pattern 114a may be lower than the upper surface of the sidewall insulating pattern 150a. If the upper surface of the upper pad pattern 114a is higher than the upper surface of the sidewall insulating pattern 150a, upper pad patterns at multiple levels may come into contact with each other through or due to overgrowth of the upper pad pattern 114a.

[0112] In one embodiment, an upper pad pattern 114a may be formed on the uppermost conductive pattern 105a in the first initial conductive pattern structure 106a. In another embodiment, the conductive pattern 105a and the upper pad pattern 114a may be stacked on top of the second initial conductive pattern structure 107a.

[0113] Reference Figure 23 , can execute reference Figure 13 and Figure 14 The same process is used to form the conductive pattern structure 107b, the channel structure 130, the first insulating interlayer 118, and the second insulating interlayer 132. Furthermore, openings can be formed, and insulating patterns can be formed within these openings.

[0114] Refer again Figure 16 and Figure 17 The first insulating interlayer 118 and the second insulating interlayer 132 can be etched to form contact holes for exposing the pad structure 116a, respectively. In an embodiment, the bottom of each contact hole may expose either the lower pad pattern 112a or the upper pad pattern 114a.

[0115] A conductive layer can be formed in the contact hole, so contact plugs can be formed separately in the contact hole.

[0116] Figure 24 and Figure 25 These are cross-sectional and plan views of a semiconductor device according to an example embodiment.

[0117] In addition to the shape of the conductive pattern structure on the second region, the semiconductor device can be compared with a reference. Figures 1 to 3 The semiconductor devices shown in the description are essentially the same. Therefore, repeated descriptions may be omitted or only briefly described.

[0118] Reference Figure 24 and Figure 25 The edge portion of the conductive pattern structure 107d in the second region can have a stepped shape.

[0119] The conductive pattern structure 107d on the second region may include an insulating pattern 103a, a conductive pattern 105a, an upper pad pattern 114b, and a spacer insulating layer 160. The insulating pattern 103a and conductive pattern 105a in the conductive pattern structure 107d on the second region may extend from the insulating pattern 103a and conductive pattern 105a in the conductive pattern structure 107d on the first region. The edge of the conductive pattern 105a on the second region may have a stepped shape. A portion of the stepped portion of each conductive pattern 105a may serve as the lower pad pattern 112b.

[0120] The spacer insulating layer 160 can cover the surface of the stacked structure of insulating pattern 103a and conductive pattern 105a. The spacer insulating layer 160 can conformally cover the surface of the stepped portion of conductive pattern 105a.

[0121] The spacer insulating layer 160 may include an insulating material having a high etch selectivity relative to the conductive pattern 105a. In one embodiment, the spacer insulating layer 160 may include a nitride such as silicon nitride. In another embodiment, the spacer insulating layer 160 may include silicon oxide.

[0122] In one embodiment, the spacer insulating layer 160 may have a thickness less than about half the width of the stepped portion of the conductive pattern structure 107d in the first direction. In another embodiment, the thickness of the spacer insulating layer 160 may be greater than the vertical thickness of each of the insulating patterns 103a in the first region.

[0123] The spacer insulating layer 160 may include a hole 162 that exposes the stepped portion of the conductive pattern 105a (see reference). Figure 27In one embodiment, the hole 162 may pass through the spacer insulating layer 160 and the insulating pattern 103a on the stepped portion. The conductive pattern 105a exposed at the bottom of the hole 162 may serve as a pad pattern 112b.

[0124] An upper pad pattern 114b may be formed in each hole 162. The upper pad pattern 114b may contact the upper surface of the conductive pattern 105a. In an embodiment, the upper pad pattern 114b may be formed on the lower pad pattern 112b.

[0125] The upper pad pattern 114b may include silicon. In one embodiment, the upper pad pattern 114b may include polycrystalline silicon. The upper pad pattern 114b may include silicon formed by epitaxial growth from the lower pad pattern 112b.

[0126] In one embodiment, the upper pad pattern 114b may fully or partially fill the hole 162. In another embodiment, the upper surface of the upper pad pattern 114b may be coplanar with the upper inlet of the hole 162. In yet another embodiment, the upper surface of the upper pad pattern 114b may be lower than the upper inlet of the hole 162.

[0127] In an embodiment, the thickness of the upper pad pattern 114b can be less than the thickness of the stacked structure of a conductive pattern 105a and an insulating pattern 103a.

[0128] The upper pad pattern 114b may cover a portion of the upper surface of the stepped portion of the conductive pattern 105a. The upper pad pattern 114b located on the upper surface of the stepped portion of the conductive pattern 105a may have an isolated (e.g., discontinuous) shape. In an embodiment, the upper pad pattern 114b with an isolated shape may be stacked on the uppermost conductive pattern 105a in the conductive pattern structure 107d.

[0129] The first insulating interlayer 118 may cover the conductive pattern structure 107d. The channel structure 130 may pass through the conductive pattern structure 107d and the first insulating interlayer 118 in the first region, and the channel structure 130 may be electrically connected to the substrate 100. The second insulating interlayer 132 may be formed on the first insulating interlayer 118.

[0130] The contact plug 142 can pass through the first insulating layer 118 and the second insulating layer 132, and the contact plug 142 can contact the pad structure 116b stacked by the lower pad pattern 112b and the upper pad pattern 114b, respectively.

[0131] Figures 26 to 31 These are cross-sectional and plan views of stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0132] Figure 26 , Figure 27 and Figure 29 It is a sectional view. Figure 28 , Figure 30 and Figure 31 It's a floor plan.

[0133] Reference Figure 26 First, it can be executed and referenced. Figures 4 to 5 The same process is used to form a first initial conductive pattern structure 106a on the lower insulating layer. The first initial conductive pattern structure 106a may include alternately stacked conductive patterns 105a and initial insulating patterns 102a.

[0134] A spacer insulating layer 160 may be conformally formed on the first initial conductive pattern structure 106a and the lower insulating layer 101. The upper surface of the spacer insulating layer 160 formed on at least a portion of the stepped portion in the first initial conductive pattern structure 106a may be flat.

[0135] If the spacer insulating layer 160 is too thick, the horizontal portion of the subsequently formed upper pad pattern will be reduced. In an embodiment, the spacer insulating layer 160 may have a thickness smaller than approximately half the width of the stepped portion in the first direction in the first conductive pattern structure 106a. If the spacer insulating layer 160 is too thin, the height of the subsequently formed upper pad pattern will be reduced. In an embodiment, the thickness of the spacer insulating layer 160 may be greater than the vertical thickness of each initial insulating pattern 102a in the first region.

[0136] The spacer insulating layer 160 may include an insulating material having a high etch selectivity relative to the conductive pattern 105a. In one embodiment, the spacer insulating layer 160 may be formed of a nitride such as silicon nitride. In another embodiment, the spacer insulating layer 160 may be formed of silicon oxide.

[0137] Reference Figure 27 and Figure 28 The spacer insulating layer 160 on the stepped portion of the first initial conductive pattern structure 106a and the initial insulating pattern 102a below the spacer insulating layer 160 can be etched to form holes 162. The initial insulating pattern 102a can be etched into an insulating pattern 103a. The upper surface of the conductive pattern 105a can be exposed by the bottom of each hole 162. The conductive pattern 105a exposed by the holes 162 can be used as a pad pattern 112b.

[0138] Reference Figure 29 and Figure 30A selective epitaxial growth process can be performed on the lower pad pattern 112b of the stepped portion to form the upper pad pattern 114b. The upper pad pattern 114b can be formed by using the lower pad pattern 112b, which includes polysilicon, as seed silicon. In an embodiment, the upper pad pattern 114b may include polysilicon. By performing the process, a second initial conductive pattern structure 107c can be formed.

[0139] In one embodiment, an upper pad pattern 114b may be formed in each hole 162. In another embodiment, the upper pad pattern 114b may fully fill the hole 162 or may partially fill the hole 162.

[0140] The upper pad pattern 114b on the upper surface of the stepped portion of the conductive pattern 105a can have an isolated shape.

[0141] An upper pad pattern 114b with an isolated shape can be formed on the uppermost conductive pattern 105a in the first initial conductive pattern structure 106a.

[0142] Reference Figure 31 It can be executed and referenced. Figure 13 and Figure 14 The same process shown is used to form the conductive pattern structure 107d, the channel structure 130, the first insulating interlayer 118, and the second insulating interlayer 132. In an embodiment, an opening 134 may be formed, and a second insulating pattern 136 may be formed in the opening 134.

[0143] Refer again Figure 24 and Figure 25 The first insulating interlayer 118 and the second insulating interlayer 132 can be etched to form contact holes that expose a pad structure 116b of a stacked lower pad pattern 112b and an upper pad pattern 114b. In an embodiment, the bottom of each contact hole may expose either the lower pad pattern 112b or the upper pad pattern 114b.

[0144] A conductive layer can be formed in the contact hole, so contact plugs 142 can be formed in the contact hole respectively.

[0145] In the semiconductor device according to the example embodiment, defects in contact plugs connected to conductive patterns can be reduced. The semiconductor device can be used in a variety of electronic products.

[0146] One or more embodiments may provide a vertical memory device.

[0147] One or more embodiments may provide a semiconductor device with reduced process defects.

[0148] In an example embodiment, the semiconductor device may include an upper pad pattern formed on a stepped portion of a conductive pattern. Therefore, punching defects in contact plugs, whether non-contact or contact plugs, can be reduced.

[0149] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art that, as of the time of filing this application, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Base; Conductive patterns are located on a substrate and are spaced apart from each other in a vertical direction perpendicular to the surface of the substrate. The edges of the conductive patterns include stepped portions such that the end of one conductive pattern does not overlap with a conductive pattern positioned above it in the vertical direction. An insulating pattern is positioned between conductive patterns; A sidewall insulating pattern is located on the sidewall of the conductive pattern to cover the sidewall of the conductive pattern; The upper pad pattern is located on the upper surface of the stepped portion of the conductive pattern; An insulating interlayer covering conductive patterns, insulating patterns, sidewall insulating patterns, and an upper pad pattern; as well as The contact plugs pass through the insulating layer and then contact the patterns on the pads. In a first direction parallel to the surface of the substrate, one of the insulating patterns has a length greater than that of a conductive pattern directly located on the insulating pattern and protrudes from the sidewall of the conductive pattern.

2. The semiconductor device according to claim 1, wherein, Both the conductive pattern and the pad pattern include polycrystalline silicon.

3. The semiconductor device according to claim 2, wherein, The pad pattern comprises polycrystalline silicon formed by epitaxial growth from the upper surface of the conductive pattern.

4. The semiconductor device according to claim 1, wherein, The sidewall insulating pattern comprises an insulating material with a high etch selectivity relative to the conductive pattern and the insulating pattern.

5. The semiconductor device according to claim 1, wherein, The upper surface of the sidewall insulating pattern and the upper surface of the stepped portion of the conductive pattern are coplanar.

6. The semiconductor device according to claim 1, wherein, One end of one of the upper pad patterns protrudes laterally beyond the end of one of the conductive patterns that contacts the substrate side of the upper pad pattern.

7. The semiconductor device according to claim 1, wherein, At least a portion of the upper surface of the pad pattern that contacts the sidewall insulation pattern on the substrate side.

8. The semiconductor device according to claim 1, wherein, The upper surface of an upper pad pattern is closer to the substrate in the vertical direction than the upper surface of an adjacent sidewall insulating pattern, which is one level higher than the upper pad pattern.

9. The semiconductor device according to claim 1, wherein, The upper surface of a sidewall insulating pattern is farther from the substrate in the vertical direction than the upper surface of a conductive pattern in contact with the sidewall insulating pattern on the stepped portion is farther from the substrate in the vertical direction.

10. The semiconductor device according to claim 1, wherein, The upper pad pattern covers the entire upper surface of the conductive pattern's stepped portion that is not covered by the insulating pattern.

11. The semiconductor device according to claim 1, wherein, The bottom of each contact plug is located on the upper surface or inner portion of a stacked structure comprising an upper pad pattern and a lower conductive pattern in contact with the upper pad pattern.

12. The semiconductor device according to claim 1, wherein, The bottom surface of the sidewall insulation pattern contacts the insulation pattern.

13. A semiconductor device, the semiconductor device comprising: Base; Conductive patterns are located on a substrate and are spaced apart from each other in a vertical direction perpendicular to the surface of the substrate. The conductive patterns include polysilicon and the edges of the conductive patterns include stepped portions such that the end of one conductive pattern does not overlap with a conductive pattern positioned above it in the vertical direction. An insulating pattern is positioned between conductive patterns; Sidewall insulating patterns are located on the sidewalls of the conductive pattern to cover the sidewalls of the conductive pattern, and the sidewall insulating patterns are respectively located on the insulating pattern; The upper pad pattern is located on the upper surface of the stepped portion of the conductive pattern, and the upper pad pattern comprises polycrystalline silicon. An insulating interlayer covering conductive patterns, insulating patterns, sidewall insulating patterns, and an upper pad pattern; The channel structure passes through conductive and insulating patterns and is connected to the substrate. The channel structure includes a dielectric layer structure, a channel, a buried insulating pattern, and an upper conductive pattern. as well as The contact plugs pass through the insulating layer and then contact the patterns on the pads. In this configuration, the upper surface of one upper pad pattern is closer to the base in the vertical direction than the upper surface of the adjacent sidewall insulating pattern in the vertical direction. The adjacent sidewall insulating pattern is one level higher than the upper pad pattern. In a first direction parallel to the surface of the substrate, one of the insulating patterns has a length greater than that of a conductive pattern directly located on the insulating pattern and protrudes from the sidewall of the conductive pattern.

14. The semiconductor device according to claim 13, wherein, The upper surface of the sidewall insulating pattern and the upper surface of the stepped portion of the conductive pattern are coplanar.

15. The semiconductor device according to claim 13, wherein, The bottom surface of the sidewall insulation pattern contacts the insulation pattern.

16. A semiconductor device, the semiconductor device comprising: Base; Conductive patterns are located on a substrate and are spaced apart from each other in a vertical direction perpendicular to the surface of the substrate. The conductive patterns include polysilicon and the edges of the conductive patterns include stepped portions such that the end of one conductive pattern does not overlap with a conductive pattern positioned above it in the vertical direction. An insulating pattern is positioned between conductive patterns; Sidewall insulating patterns are located on the sidewalls of the conductive pattern to cover the sidewalls of the conductive pattern; The upper pad pattern is located on the upper surface of the stepped portion of the conductive pattern, and the upper pad pattern comprises polycrystalline silicon. An insulating interlayer covering conductive patterns, insulating patterns, sidewall insulating patterns, and an upper pad pattern; as well as The contact plugs pass through the insulating layer and then contact the patterns on the pads. in: The bottom of each contact plug is located on the upper surface or inner portion of a stacked structure comprising an upper pad pattern and a lower conductive pattern in contact with the upper pad pattern. The thickness of each pad pattern in the vertical direction is less than the thickness of a structure consisting of a conductive pattern and an insulating pattern stacked together in the vertical direction. In a first direction parallel to the surface of the substrate, one of the insulating patterns has a length greater than that of a conductive pattern directly located on the insulating pattern and protrudes from the sidewall of the conductive pattern.

17. The semiconductor device according to claim 16, wherein, The upper surface of the sidewall insulating pattern and the upper surface of the stepped portion of the conductive pattern are coplanar.

18. The semiconductor device according to claim 16, wherein, The end of the upper pad pattern protrudes laterally beyond the end of the lower conductive pattern that contacts the substrate side of the upper pad pattern.

19. The semiconductor device according to claim 16, wherein, The upper surface of the sidewall insulating pattern is farther from the substrate in the vertical direction than the upper surface of the conductive pattern in contact with the sidewall insulating pattern on the stepped portion is farther from the substrate in the vertical direction.

20. The semiconductor device of claim 16, wherein, The upper pad pattern covers the entire upper surface of the conductive pattern's stepped portion that is not covered by the insulating pattern.

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