Display device including thin film transistor and method for manufacturing the same

Abstract

A display device and a method for manufacturing the display device are disclosed. The display device includes: a substrate; a light shielding layer and a signal line on the substrate; a buffer layer on the light shielding layer and the signal line; an active layer on the buffer layer; a gate insulating film on the active layer; a gate electrode on the gate insulating film; a protective layer on the gate electrode; a first electrode of a display device on the protective layer; and a connecting electrode configured to connect the signal line and the active layer to each other, wherein the light shielding layer and the signal line are arranged on the same layer, and the connecting electrode and the first electrode are formed of the same material. Therefore, for the manufacturing process of the display device, it is not necessary to provide an additional mask process for forming the light shielding layer. In addition, in the manufacturing process of the display device, it is not necessary to perform an additional mask process for forming the source electrode and the drain electrode of the thin film transistor. Therefore, a display device with a simplified structure and a method for manufacturing the display device using a simplified process can be provided.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0165361, filed on Dec. 12, 2019, which is hereby incorporated by reference in its entirety as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. In more detail, the present disclosure relates to a display device capable of simplifying a structure and a manufacturing process and a method for manufacturing the display device. Background Art

[0004] Display devices that display various information on a screen are technology-intensive devices that incorporate core technologies in the field of information communication. Recently, display devices have been developed to achieve thin profile, light weight, portability, and high performance. Typical examples of display devices may be liquid crystal display (LCD) devices and organic light emitting diode display (OLED) devices.

[0005] Generally, a display device is manufactured by performing a mask process using an optical mask several times. Each mask process requires cleaning, exposure, development, and etching steps, etc. Therefore, each additional mask process results in an increase in manufacturing time and cost, and an increase in the possibility of defects and defect rate. As a result, the yield rate is reduced. Summary of the invention

[0006] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a display device capable of simplifying a structure and a manufacturing process, and a method of manufacturing the display device.

[0007] Another object of the present disclosure is to provide a method for manufacturing a display device and a display device manufactured by the method, which method is conducive to simplifying the structure and manufacturing process by omitting the process of forming a source electrode and a drain electrode of a thin film transistor.

[0008] According to one aspect of the present disclosure, the above-mentioned purpose and other purposes can be achieved by providing a display device, which includes: a substrate; a light-shielding layer and a signal line on the substrate; a buffer layer on the light-shielding layer and the signal line; an active layer on the buffer layer; a gate insulating film on the active layer; a gate electrode on the gate insulating film; a protective layer on the gate electrode; a first electrode of a display device on the protective layer; and a connecting electrode configured to connect the signal line and the active layer to each other, wherein the light-shielding layer and the signal line may be arranged on the same layer, and the connecting electrode and the first electrode may be formed of the same material.

[0009] The connecting electrode may be arranged on the same layer as the first electrode.

[0010] The light shielding layer may be formed of the same material as the signal line.

[0011] The signal line may include at least one of a data line and a driving power line.

[0012] The light shielding layer may be connected to the signal line.

[0013] The light shielding layer and the signal line may be formed as one body.

[0014] The gate insulating film may be provided on the entire upper surface of the substrate including an upper surface of the active layer.

[0015] The active layer may be disposed between the gate electrode and the substrate.

[0016] The active layer may include an oxide semiconductor material.

[0017] The active layer may include: a first oxide semiconductor layer on the buffer layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0018] The display device may further include a light emitting layer disposed on the first electrode.

[0019] The display device may further include a capacitor connected to the first electrode, wherein any one electrode of the capacitor is formed integrally with the light shielding layer.

[0020] The first electrode may be directly connected to the light shielding layer and the active layer.

[0021] The display device may further include a liquid crystal layer disposed on the first electrode.

[0022] According to another aspect of the present disclosure, a method for manufacturing a display device is provided, comprising: forming a light-shielding layer and a signal line on a substrate; forming a buffer layer on the light-shielding layer and the signal line; forming an active layer on the buffer layer; forming a gate insulating film on the active layer; forming a gate electrode on the gate insulating film; selectively providing conductivity to the active layer by using the gate electrode as a mask to selectively realize a conductive area in the active layer; forming a protective layer on the gate electrode; forming a first electrode of a display device on the protective layer; and forming a connecting electrode, the connecting electrode being configured to connect the signal line and the active layer to each other, wherein the light-shielding layer and the signal line are manufactured using the same material through the same process, and the connecting electrode and the first electrode are manufactured using the same material through the same process.

[0023] The step of selectively realizing a conductive region in the active layer may be performed by a doping process.

[0024] The connection electrode may be formed in at least some portions of a contact hole penetrating some portions of each of the protection layer, the gate insulating film, and the buffer layer.

[0025] The first electrode may extend to at least some portions of a contact hole penetrating some portions of each of the protection layer, the gate insulating film, and the buffer layer, and the first electrode may be directly connected to the light shielding layer and the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings:

[0027] Figure 1 is a schematic diagram illustrating a display device according to one embodiment of the present disclosure;

[0028] Figure 2 yes Figure 1 The circuit diagram of any pixel;

[0029] Figure 3 It is a graphic Figure 2 A plan view of pixels;

[0030] Figure 4 is along Figure 3 A cross-sectional view taken along line II';

[0031] Figure 5 is along Figure 3 A cross-sectional view taken along line II-II';

[0032] Figure 6 is a cross-sectional view illustrating a pixel of a display device according to another embodiment of the present disclosure;

[0033] Figure 7 is a cross-sectional view illustrating a pixel of a display device according to another embodiment of the present disclosure;

[0034] Figure 8 is a plan view illustrating a pixel of a display device according to another embodiment of the present disclosure;

[0035] Fig. 9 is along Figure 8 A cross-sectional view taken along line III-III';

[0036] Fig.10 is a circuit diagram of any one pixel of a display device according to another embodiment of the present disclosure;

[0037] Fig.11 is a circuit diagram of any one pixel of a display device according to another embodiment of the present disclosure;

[0038] Fig.12 is a circuit diagram of any one pixel of a display device according to another embodiment of the present disclosure;

[0039] Fig.13 It is a graphic Fig.12 A plan view of pixels;

[0040] Fig.14 is along Fig.13 A cross-sectional view taken along line IV-IV';

[0041] Fig.15 is along Fig.13 A cross-sectional view taken along the line V-V';

[0042] Fig.16 is a plan view illustrating a pixel of a display device according to another embodiment of the present disclosure;

[0043] Fig.17 is along Fig.16 A cross-sectional view taken along line VI-VI';

[0044] FIG. 18A to FIG. 18G is a cross-sectional view illustrating a method of manufacturing a display device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments listed here. Rather, these embodiments are provided to make the disclosure comprehensive and complete and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0046] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited to the details shown. Similar reference numerals represent similar elements throughout. In the following description, when it is determined that a detailed description of a related known function or configuration would unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted.

[0047] Where “including,” “having,” and “comprising” are used in the description of the present application, additional parts may be added unless “only” is used. Terms in the singular form may include plural forms unless otherwise indicated.

[0048] When interpreting an element, even if it is not explicitly stated, the element should be interpreted as including a range of error.

[0049] When describing a positional relationship, for example, when the positional relationship is described as "on", "above", "below", "under", and "after", the situation where there is no contact between them may be included unless "just" or "directly" is used.

[0050] If it is mentioned that a first element is located "on" a second element, it does not mean that the first element is necessarily located on the second element in the figure. The upper and lower parts of the objects involved may vary depending on the positioning of the objects. Therefore, the case where the first element is located "on" the second element includes the case where the first element is located "below" the second element in the figure or in the actual construction, as well as the case where the first element is located "above" the second element.

[0051] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "directly" or "directly" is used.

[0052] It will be understood that, although the terms "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish elements from each other. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. The terms "first horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be interpreted based only on the geometric relationship in which each direction is perpendicular to each other, and may refer to a direction with a wider pointing range within the scope of the components of the present disclosure that can be functionally operated.

[0053] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0054] As can be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure can be combined or combined with each other in part or in whole, and can be technically interoperable and driven with each other in various ways. The embodiments of the present disclosure can be implemented independently of each other, or implemented together in a mutually dependent relationship.

[0055] In the drawings, the same or similar parts are denoted by the same reference numerals although they are depicted in different drawings.

[0056] In the embodiments of the present disclosure, for ease of description, source electrodes and drain electrodes are distinguished from each other. However, source electrodes and drain electrodes may be used interchangeably. Thus, a source electrode may be a drain electrode, and a drain electrode may be a source electrode. In addition, a source electrode in any one embodiment of the present disclosure may be a drain electrode in other embodiments of the present disclosure, and a drain electrode in any one embodiment of the present disclosure may be a source electrode in other embodiments of the present disclosure.

[0057] In one or more embodiments of the present disclosure, for ease of description, the source region is separated from the source electrode region, and the drain region is separated from the drain electrode region. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region may be a source electrode, and the drain region may be a drain electrode. In addition, the source region may be a drain electrode, and the drain region may be a source electrode.

[0058] Figure 1 is a schematic diagram illustrating a display device 100 according to one embodiment of the present disclosure.

[0059] like Figure 1 As shown in , a display device 100 according to one embodiment of the present disclosure includes a display panel 110 , a gate driver 120 , a data driver 130 , and a controller 140 .

[0060] The display panel 110 includes gate lines GL and data lines DL, and pixels P arranged at intersections of the gate lines GL and data lines DL. The pixels P include a display device 710 and a pixel driver PDC configured to drive the display device 710. An image is displayed on the display panel 110 by driving the pixels P.

[0061] The controller 140 controls the gate driver 120 and the data driver 130 .

[0062] The controller 140 outputs a gate control signal GCS for controlling the gate driver 120 and a data control signal DCS for controlling the data driver 130 by using a vertical / horizontal synchronization signal and a clock signal provided from an external system (not shown). In addition, the controller 140 samples input video data provided from the external system, then rearranges the sampled video data, and provides the rearranged digital video data RGB to the data driver 130.

[0063] The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst) and a gate clock (GCLK). In addition, the gate control signal GCS may include a control signal for controlling a shift register.

[0064] The data control signal DCS includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), and a polarity control signal (POL).

[0065] The data driver 130 supplies data voltages to the data lines DL of the display panel 110. In detail, the data driver 130 converts the video data RGB supplied from the controller 140 into data voltages and supplies the data voltages to the data lines DL.

[0066] The gate driver 120 sequentially provides gate pulses (GP) to the gate lines GL in a 1-frame period. Here, "1 frame" means a period of time during which an image is output by using the display panel 110. In addition, the gate driver 120 provides a gate-off signal for turning off the switching device to the gate lines GL in the remaining period of 1 frame in which the gate pulse (GP) is not provided. Hereinafter, the gate pulse (GP) and the gate-off signal (Goff) are collectively referred to as a scan signal SS.

[0067] According to one embodiment of the present disclosure, the gate driver 120 may be disposed on the display panel 110. A structure in which the gate driver 120 is directly disposed on the display panel 110 may be referred to as a gate-in-panel (GIP) structure.

[0068] Figure 2 yes Figure 1 The circuit diagram of any pixel P, Figure 3 It is a graphic Figure 2 The plane diagram of pixel P, Figure 4 is along Figure 3 A cross-sectional view taken along line II'.

[0069] Reference Figure 2 , Figure 3 and Figure 4 The display device 100 according to one embodiment of the present disclosure may include a substrate 210, a pixel driver PDC on the substrate 210, and a display device 710 (or a light emitting device) connected to the pixel driver PDC. The pixel driver PDC includes thin film transistors TR1 and TR2.

[0070] Figure 2 The circuit diagram of corresponds to an equivalent circuit diagram of one pixel P in the display device 100, which includes an organic light emitting diode (OLED) used as the light emitting device 710. Therefore, the display device 100 according to one embodiment of the present disclosure is an organic light emitting diode (OLED) display device.

[0071] Figure 2The pixel driver PDC includes a first thin film transistor TR1 corresponding to a switching transistor and a second thin film transistor TR2 corresponding to a driving transistor.

[0072] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and the first thin film transistor TR1 is turned on or off by a scan signal SS supplied through the gate line GL.

[0073] The data line DL provides a data voltage Vdata to the pixel driver PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0074] The driving power line PL provides a driving voltage Vdd to the display device 710 , and the second thin film transistor TR2 controls the driving voltage Vdd. Here, the driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) corresponding to the display device 710 .

[0075] The data line DL and the driving power line PL are lines for transmitting signals. Therefore, according to one embodiment of the present disclosure, the data line DL and the driving power line PL may be referred to as a signal line. In addition, the gate line GL transmits a signal, so the gate line GL may also be referred to as a signal line.

[0076] When the first thin film transistor TR1 is turned on, the data voltage Vdata provided through the data line DL is provided to the gate electrode G2 of the second thin film transistor TR2 connected to the display device 710. The data voltage Vdata is charged in the first capacitor C1 provided between the source electrode S2 and the gate electrode G2 of the second thin film transistor TR2. The first capacitor C1 corresponds to a storage capacitor (Cst).

[0077] The amount of current supplied to the organic light emitting diode (OLED) corresponding to the display device 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray level of light emitted from the display device 710 may be controlled.

[0078] Reference Figure 4 The display device 100 includes a substrate 210; light shielding layers LS1, LS2 and signal lines DL, PL on the substrate 210; a buffer layer 220 on the light shielding layers LS1, LS2 and the signal lines DL, PL; an active layer A1, A2 on the buffer layer 220; a gate insulating film 230 on the active layer A1, A2; gate electrodes G1, G2 on the gate insulating film 230; a protective layer 250 on the gate electrodes G1, G2; and a first electrode 711 of the display device 710 disposed on the protective layer 250. Figure 4 In the illustrated display device 100 , the first electrode 711 of the display device 710 corresponds to a pixel electrode.

[0079] The substrate 210 may be formed of glass or plastic. The substrate 210 may be formed of plastic having flexibility, such as polyimide (PI).

[0080] The light shielding layers LS1 and LS2 and the signal lines DL and PL are disposed on the substrate 210 .

[0081] The light shielding layers LS1 and LS2 have light shielding properties. The light shielding layers LS1 and LS2 are formed of a material capable of blocking light, such as a metal material. The light shielding layers LS1 and LS2 prevent incident light provided from the outside and protect the active layers A1 and A2.

[0082] According to one embodiment of the present disclosure, the signal line may include at least one of a data line DL and a driving power line PL. Figure 4 The data lines DL and the driving power lines PL corresponding to the signal lines may be provided on the same layer as the light shielding layers LS1 and LS2.

[0083] The light shielding layers LS1 and LS2 can be formed of the same material as the signal lines DL and PL. The light shielding layers LS1 and LS2 and the signal lines DL and PL can be manufactured in the same process.

[0084] Reference Figure 4 , the first capacitor electrode C11 of the first capacitor C1 is disposed on the substrate 210. The first capacitor electrode C11 of the first capacitor C1 may be disposed on the same layer as the light shielding layers LS1 and LS2, and may be formed of the same material as the light shielding layers LS1 and LS2.

[0085] In addition, the first capacitor electrode C11 of the first capacitor C1 may be formed integrally with the light shielding layer. For example, the first capacitor electrode C11 of the first capacitor C1 may be formed integrally with the second light shielding layer LS2.

[0086] exist Figure 4 In the embodiment, the light shielding layers LS1 and LS2 are separated from the signal lines DL and PL, however, the present invention is not limited to this structure. For example, the light shielding layers LS1 and LS2 may be connected to the signal lines DL and PL.

[0087] The buffer layer 220 is disposed on the light shielding layers LS1, LS2 and the signal lines DL, PL. The buffer layer 220 is formed of an insulating material and protects the active layers A1, A2 from moisture or oxygen provided from the outside. The buffer layer 220 may be formed of an insulating material, such as silicon oxide or silicon nitride.

[0088] The active layers A1 and A2 of the first and second thin film transistors TR1 and TR2 are disposed on the buffer layer 220. At least some portions of the active layer A1 of the first thin film transistor TR1 may overlap the first light shielding layer LS1. In addition, at least some portions of the active layer A2 of the second thin film transistor TR2 may overlap the second light shielding layer LS2.

[0089] According to one embodiment of the present disclosure, the active layers A1 and A2 may include oxide semiconductor materials. For example, the active layers A1 and A2 may include at least one of IZO (InZnO)-based oxide semiconductors, IGO (InGaO)-based oxide semiconductors, GO (GaO)-based oxide semiconductors, ITO (InSnO)-based oxide semiconductors, IGZO (InGaZnO)-based oxide semiconductors, IGTO (InGaSnO)-based oxide semiconductors, IGZTO (InGaZnSnO)-based oxide semiconductors, GZTO (GaZnSnO)-based oxide semiconductors, GZO (GaZnO)-based oxide semiconductors, and ITZO (InSnZnO)-based oxide semiconductors. However, one embodiment of the present disclosure is not limited to the above materials. The active layers A1 and A2 may be formed of other oxide semiconductor materials generally known to those skilled in the art.

[0090] According to one embodiment of the present disclosure, the active layers A1, A2 may include a first active layer A1 and a second active layer A2 disposed at the same layer and spaced apart from each other.

[0091] The first active layer A1 serves as an active layer of the first thin film transistor TR1 , and the second active layer A2 serves as an active layer of the second thin film transistor TR2 .

[0092] Reference Figure 4 The gate insulating film 230 is disposed on the active layers A1 and A2. The gate insulating film 230 has insulating properties. The gate insulating film 230 may be patterned together with the gate electrodes G1 and G2, or may not be patterned.

[0093] According to one embodiment of the present disclosure, Figure 4 As shown in , the gate insulating film 230 may be provided on the entire upper surface of the substrate 210 including the upper surfaces of the active layers A1, A2. In this case, the gate insulating film 230 is not patterned.

[0094] The gate electrodes G1 and G2 are disposed on the gate insulating film 230. The gate electrodes G1 and G2 may be portions extending from the gate line GL, or may be portions of the gate line GL. The gate electrodes G1 and G2 may include at least one of aluminum-based metals such as aluminum or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrodes G1 and G2 may have a multilayer structure including at least two layers having different physical properties.

[0095] Through the selective conduction process using the gate electrodes G1 and G2 as masks, some regions of the active layers A1 and A2 are made conductive, thus becoming conductive regions. In the embodiments of the present disclosure, "conducting" means "providing conductivity".

[0096] The regions of the active layers A1 and A2 that overlap with the gate electrodes G1 and G2 are not provided with conductivity, and thus do not become conductive regions, but become channel regions 31. The regions of the active layers A1 and A2 that do not overlap with the gate electrodes G1 and G2 are provided with conductivity, and thus become conductive regions 32 and 33. Generally, the conductive regions 32 and 33 are formed on both sides of the channel region 31.

[0097] According to one embodiment of the present disclosure, some regions of the active layers A1 and A2 may be provided with conductivity by a doping process using a dopant, thereby becoming conductive regions. In this case, the doped regions become conductive regions, and some regions of the active layers A1 and A2 may be doped with dopants via the gate insulating film 230. Thus, although the active layers A1 and A2 are not exposed to the outside from the gate insulating film 230, selective doping of the active layers A1 and A2 is possible. According to one embodiment of the present disclosure, the gate insulating film 230 may not be patterned.

[0098] Either one of the conductive regions 32 and 33 becomes the source region 32, and the other becomes the drain region 33. The source region 32 is used as a source connection region connected to the source electrodes S1 and S2, or the source region 32 itself is used as the source electrodes S1 and S2. The drain region 33 is used as a drain connection region connected to the drain electrodes D1 and D2, or the drain region 33 itself is used as the drain electrodes D1 and D2.

[0099] According to one embodiment of the present disclosure, for ease of explanation, the source region 32 and the drain region 33 are distinguished from each other. However, the source region 32 and the drain region 33 may be used interchangeably. Depending on the voltage, the source region 32 becomes the drain region 33, and the drain region 33 becomes the source region 32. In addition, the source region 32 becomes the source electrode S1, S2 or the drain electrode D1, D2, and the drain region 33 becomes the drain electrode D1, D2 or the source electrode S1, S2.

[0100] For ease of explanation, according to one embodiment of the present disclosure, the source region 32 is referred to as source electrodes S1 , S2 , and the drain region 33 is referred to as drain electrodes D1 , D2 .

[0101] According to one embodiment of the present disclosure, some portions of the conductive regions 32 and 33 are used as capacitor electrodes. Figure 4 Some portions of the drain connection region 33 in the conductive regions 32 and 33 of the first active layer A1 may serve as the second capacitor electrode C12 of the first capacitor C1. The second capacitor electrode C12 of the first capacitor C1 overlaps the first capacitor electrode C11, thereby forming the first capacitor C1.

[0102] Reference Figure 4 Any one electrode C11 of the first capacitor C1 may be integrally formed with the second light shielding layer LS2 , and the other electrode C12 of the first capacitor C1 may be integrally formed with the first active layer A1 .

[0103] Reference Figure 4 The passivation layer 240 is disposed on the gate electrodes G1 and G2. The passivation layer 240 protects the active layers A1 and A2 and the gate electrodes G1 and G2.

[0104] Typically, a source electrode and a drain electrode are disposed on the passivation layer 240. However, according to one embodiment of the present disclosure, no additional source electrode and drain electrode are disposed on the passivation layer 240. Thus, according to one embodiment of the present disclosure, a patterning process for forming the source electrode and the drain electrode may be omitted. As a result, the manufacturing process of the display device 100 may be simplified.

[0105] The protective layer 250 is disposed on the passivation layer 240. The protective layer 250 is provided to planarize the upper surfaces of the gate electrodes G1, G2 and protect the pixel driver PDC, and thus the protective layer 250 may be referred to as a planarization layer.

[0106] Reference Figure 4 , the display device 710 is disposed on the protective layer 250. In detail, the first electrode 711 of the display device 710 is disposed on the passivation layer 240, and the light emitting layer 712 and the second electrode 713 are sequentially disposed on the first electrode 711, thereby forming the display device 710. Figure 4 In the embodiment, the first electrode 711 is a pixel electrode, and the second electrode 713 is a common electrode.

[0107] The first electrode 711 of the display device 710 is electrically connected to the second active layer A2 and any one of the light shielding layers through the contact hole CH2. In detail, the first electrode 711 contacts the second light shielding layer LS2 through the second contact hole CH2 formed in the protective layer 250, the passivation layer 240, the gate insulating film 230 and the buffer layer 220, and also contacts the source region 32 of the second active layer A2. According to one embodiment of the present disclosure, the source region 32 of the second active layer A2 is used as the second source electrode S2. Thus, the first electrode 711 may be in direct contact with the source electrode S2 of the second thin film transistor TR2. In addition, some parts of the second light shielding layer LS2 may be used as the first capacitor electrode C11. Thus, the second source electrode S2 and the first capacitor electrode C11 are connected to each other through the first electrode 711 located in the second contact hole CH2.

[0108] In addition, the connection electrodes BR1 , BR2 , and BR3 are provided on the protective layer 250 .

[0109] The connection electrodes BR1, BR2, BR3 are formed of the same material as the first electrode 711. In addition, the connection electrodes BR1, BR2, BR3 and the first electrode 711 are provided in the same layer. The connection electrodes BR1, BR2, BR3 and the first electrode 711 can be manufactured by the same process.

[0110] The connection electrodes BR1 and BR3 are provided to connect the signal lines DL and PL with the active layers A1 and A2. In detail, the first connection electrode BR1 connects the driving power line PL with the second active layer A2. The first contact hole CH1 is provided to connect the driving power line PL and the second active layer A2 to each other, and the first connection electrode BR1 is formed in the first contact hole CH1. Figure 4 , the first connection electrode BR1 contacts the driving power line PL and also contacts the drain region 33 of the second active layer A2 at the same time. According to one embodiment of the present disclosure, the drain region 33 of the second active layer A2 is used as the second drain electrode D2. Thus, the first connection electrode BR1 is configured to connect the driving power line PL to the drain electrode D2 of the second thin film transistor TR2.

[0111] The third connection electrode BR3 is provided to connect the data line DL to the first active layer A1. For the connection between the data line DL and the first active layer A1, a fourth contact hole CH4 is provided. Figure 4, the third connection electrode BR3 contacts the data line DL and also contacts the source region 32 of the first active layer A1 at the same time. According to one embodiment of the present disclosure, the source region 32 of the first active layer A1 is used as the first source electrode S1. Thus, the third connection electrode BR3 is configured to connect the data line DL to the source electrode S1 of the first thin film transistor TR1.

[0112] In addition, the second connection electrode BR2 connects the second gate electrode G2 with the first active layer A1. A third contact hole CH3 is provided to connect the second gate electrode G2 with the first active layer A1. Figure 4 , the second connection electrode BR2 is in contact with the second gate electrode G2, and at the same time is also in contact with the drain region 33 of the first active layer A1. According to one embodiment of the present disclosure, the drain region 33 of the first active layer A1 is used as the first drain electrode D1, and some portions overlapping with the first capacitor electrode C11 are used as the second capacitor electrode C12. Thus, the second connection electrode BR2 is configured to connect the drain electrode D1 of the first thin film transistor TR1 with the second gate electrode G2 and at the same time connect the second capacitor electrode C12 with the second gate electrode G2.

[0113] The bank layer 750 is disposed on an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the light emitting device 710.

[0114] The light emitting layer 712 is disposed on the first electrode 711. Here, the light emitting layer 712 is an organic light emitting layer including an organic material. The second electrode 713 is disposed on the light emitting layer 712. Thus, the display device 710 can be completed.

[0115] Figure 4 The display device 710 shown in FIG. 7 corresponds to an organic light emitting diode (OLED). Thus, the display apparatus 100 according to one embodiment of the present disclosure corresponds to an organic light emitting diode (OLED) display apparatus.

[0116] According to one embodiment of the present disclosure, the thin film transistors TR1 and TR2 are formed of active layers A1 and A2 and gate electrodes G1 and G2. The thin film transistors TR1 and TR2 are connected to the signal lines PL and DL by using connection electrodes BR1 and BR3.

[0117] In the first thin film transistor TR1, the source region 32 of the first active layer A1 becomes the source electrode S1, and the drain region 33 becomes the drain electrode D1. In the second thin film transistor TR2, the source region 32 of the second active layer A2 becomes the source electrode S2, and the drain region 33 becomes the drain electrode D2.

[0118] like Figure 2 and Figure 4As shown in FIG. 7 , the first thin film transistor TR1 is used as a switching transistor configured to control a data voltage Vdata applied to the pixel driver PDC. The second thin film transistor TR2 is used as a driving transistor configured to control a driving voltage Vdd applied to the display device 710 .

[0119] According to one embodiment of the present disclosure, Figure 4 As shown in , the active layers A1 and A2 are disposed between the gate electrodes G1 and G2 and the substrate 210. Figure 4 As shown in , when the substrate 210 is the bottom, the structure of the thin film transistor in which the gate electrodes G1 and G2 are disposed above the active layers A1 and A2 is referred to as a top gate structure.

[0120] In addition, in contrast to the top gate structure, the structure of the thin film transistor in which the gate electrodes G1 and G2 are provided below the active layers A1 and A2 is referred to as a bottom gate structure.

[0121] In the case of a bottom-gate thin film transistor, capacitance is generated between the gate electrode and the source electrode or between the gate electrode and the drain electrode. Therefore, in order to turn on the thin film transistor, a relatively high voltage must be applied to the bottom gate structure compared to the top gate structure, which has the disadvantage of high power consumption.

[0122] In addition, compared with the bottom gate structure, the top gate structure thin film transistor has the advantage of relatively low power consumption. However, in the case of the top gate structure, there are disadvantages of a multi-layer structure of the manufacturing process and a large size of the thin film transistor.

[0123] However, according to one embodiment of the present disclosure, the active layers A1 and A2 can be in contact with the signal lines PL and DL by using the connection electrodes BR1 and BR3 without forming additional source electrodes and drain electrodes. Therefore, according to one embodiment of the present disclosure, the number of steps for forming a thin film transistor can be reduced, and the number of deposited layers can be reduced, thereby reducing the number of contact holes, thereby reducing manufacturing costs and reducing the occupied size of the thin film transistor.

[0124] According to one embodiment of the present disclosure, the aperture ratio of the display device 100 may be improved.

[0125] Figure 5 is along Figure 3 A cross-sectional view taken along line II-II'.

[0126] Reference Figure 5 , the first light shielding layer (LS1) is connected to the first gate electrode G1 by using the fourth connection electrode BR4. A fourth contact hole CH4 is provided to connect the first light shielding layer LS1 to the first gate electrode G1.

[0127] Since the first light shielding layer LS1 is connected to the first gate electrode G1, the first light shielding layer LS1 can be prevented from being in an unstable floating state. In addition, since the first light shielding layer LS1 is connected to the first gate electrode G1, it can produce the effect that occurs when gate electrodes are provided on both sides of the first active layer A1, thereby increasing the on-current of the first thin film transistor.

[0128] Figure 6 is a cross-sectional view illustrating a pixel of a display device 200 according to another embodiment of the present disclosure.

[0129] exist Figure 6 In the display device 200 shown in FIG. 1 , the active layers A1 and A2 have a multi-layer structure. Figure 6 , the active layers A1 and A2 include first oxide semiconductor layers A11 and A21 on the buffer layer 220; and second oxide semiconductor layers A12 and A22 on the first oxide semiconductor layers A11 and A21. In more detail, the first active layer A1 includes the first oxide semiconductor layer A11 on the buffer layer 220, and the second oxide semiconductor layer A12 on the first oxide semiconductor layer A11. The second active layer A2 includes the first oxide semiconductor layer A21 on the buffer layer 220, and the second oxide semiconductor layer A22 on the first oxide semiconductor layer A21.

[0130] According to one embodiment of the present disclosure, the first oxide semiconductor layer A11, A21 is used as a supporting layer configured to support the second oxide semiconductor layer A12, A22, and the second oxide semiconductor layer A12, A22 is used as a channel layer. Typically, the channel of the active layer A1, A2 is provided in the second oxide semiconductor layer A12, A22.

[0131] In order to improve the film stability, the first oxide semiconductor layers A11 and A21 used as the supporting layer may include gallium (Ga), wherein gallium (Ga) forms a stable bond with oxygen, so that the first oxide semiconductor layers A11 and A21 have excellent film stability. According to one embodiment of the present disclosure, the first oxide semiconductor layers A11 and A21 may include at least one of IGZO (InGaZnO)-based oxide semiconductor materials, IGO (InGaO)-based oxide semiconductor materials, IGTO (InGaSnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, GZO (GaZnO)-based oxide semiconductor materials, and GO (GaO)-based oxide semiconductor materials. However, one embodiment of the present disclosure is not limited to the above materials. The first oxide semiconductor layers A11 and A21 may be formed of other oxide semiconductor materials generally known to those skilled in the art.

[0132] The second oxide semiconductor layers A12 and A22 may include at least one of an IZO (InZnO)-based oxide semiconductor, an IGO (InGaO)-based oxide semiconductor, an ITO (InSnO)-based oxide semiconductor, an IGZO (InGaZnO)-based oxide semiconductor, an IGZTO (InGaZnSnO)-based oxide semiconductor, a GZTO (GaZnSnO)-based oxide semiconductor, a GZO (GaZnO)-based oxide semiconductor, and an ITZO (InSnZnO)-based oxide semiconductor. However, one embodiment of the present disclosure is not limited to the above materials. The second oxide semiconductor layers A12 and A22 may be formed of other oxide semiconductor materials generally known to those skilled in the art.

[0133] The second oxide semiconductor layers A12 and A22 have greater electrical characteristics than the first oxide semiconductor layers A11 and A21, and the first oxide semiconductor layers A11 and A21 may have greater film stability and greater resistance to etching than the second oxide semiconductor layers A12 and A22.

[0134] Figure 7 is a cross-sectional view illustrating a pixel of a display device 300 according to another embodiment of the present disclosure.

[0135] and Figure 4 compared to, Figure 7 The connection electrodes BR1, BR2, and BR3 do not extend to the upper surface of the protective layer 250. In detail, the first connection electrode BR1 connects the driving power line PL to the second active layer A2, however, the first connection electrode BR1 does not extend to the upper surface of the protective layer 250. The third connection electrode BR3 connects the data line DL to the first active layer A1, however, the third connection electrode BR3 does not extend to the upper surface of the protective layer 250. The second connection electrode BR2 connects the second gate electrode G2 to the first active layer A1, however, the second connection electrode BR2 does not extend to the upper surface of the protective layer 250.

[0136] like Figure 7 As shown in , the connection electrodes BR1, BR2, BR3 can be formed to a minimum size that allows electrical connection function. In this case, the occupied area of ​​the connection electrodes BR1, BR2, BR3 is reduced, so that the occupied area of ​​the first electrode 711 used as the pixel electrode is increased, thereby improving the aperture ratio of the display device 300.

[0137] Figure 8 is a plan view illustrating a pixel of a display device 400 according to another embodiment of the present disclosure. Fig. 9 is along Figure 8 A cross-sectional view taken along line III-III'.

[0138] Reference Figure 8 and Fig. 9 , the data line DL and the first light shielding layer LS1 are formed as one body. According to one embodiment of the present disclosure, the signal line DL and the light shielding layer LS may be formed as one body.

[0139] Reference Figure 8 and Fig. 9 When the signal line and the light shielding layer are formed as one body, the connection electrode for connecting the signal line and the light shielding layer to each other can be omitted (see Figure 3 and Figure 5 "BR4") and contact holes (see Figure 3 and Figure 5 of “CH5”).

[0140] In detail, Figure 3 and Figure 5 In comparison, Figure 8 and Fig. 9 In the case of the display device 400 shown, the fourth connection electrode BR4 and the fifth contact hole CH5 provided to connect the first gate electrode G1 and the first light shielding layer LS1 to each other may be omitted. Since the first light shielding layer LS1 is formed integrally with the data line DL, the first light shielding layer LS1 may be prevented from being in an unstable floating state.

[0141] Fig.10 is a circuit diagram of any one pixel of a display device 500 according to another embodiment of the present disclosure. Fig.10 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

[0142] Fig.10 The pixel P of the display device 500 shown in FIG. 5 includes an organic light emitting diode (OLED) as a display device 710, and a pixel driver PDC configured to drive the display device 710. The display device 710 is connected to the pixel driver PDC.

[0143] In the pixel (P), there are signal lines DL, GL, PL, RL, and SCL configured to provide signals to the pixel driver PDC.

[0144] The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the driving voltage Vdd for driving pixels is supplied to the driving power line PL, the reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

[0145] Reference Fig.10When the gate line of the (n)th pixel P is referred to as “GLn”, the gate line of the adjacent (n-1)th pixel P is “GLn-1”, and the “GLn-1” corresponding to the gate line of the (n-1)th pixel P is used as the sensing control line SCL of the (n)th pixel P.

[0146] For example, Fig.10 As shown in , the pixel driver PDC includes: a first thin film transistor TR1 (switching transistor), which is connected to the gate line GL and the data line DL; a second thin film transistor TR2 (driving transistor), which is configured to control the level of current provided to the display device 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1; and a third thin film transistor TR3 (reference transistor), which is configured to sense the characteristics of the second thin film transistor TR2.

[0147] The first capacitor C1 is located between the display device 710 and the gate electrode G2 of the second thin film transistor TR2. The first capacitor C1 is referred to as a storage capacitor (Cst).

[0148] As the first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, the first thin film transistor TR1 transmits the data voltage Vdata supplied to the data line DL to the gate electrode G2 of the second thin film transistor TR2.

[0149] The third thin film transistor TR3 is connected to the reference line RL and the first node n1 between the display device 710 and the second thin film transistor TR2. The third thin film transistor TR3 is turned on or off by the sensing control signal SCS and senses the characteristics of the second thin film transistor TR2 corresponding to the driving transistor in the sensing period.

[0150] The second node n2 connected to the gate electrode G2 of the second thin film transistor TR2 is connected to the first thin film transistor TR1. The first capacitor C1 is formed between the second node n2 and the first node n1.

[0151] When the first thin film transistor TR1 is turned on, the data voltage Vdata provided through the data line DL is provided to the gate electrode G2 of the second thin film transistor TR2. The first capacitor C1 formed between the source electrode S2 and the gate electrode G2 of the second thin film transistor TR2 is charged with the data voltage Vdata.

[0152] When the second thin film transistor TR2 is turned on, current is supplied to the display device 710 through the second thin film transistor TR2 using the driving voltage Vdd for driving the pixel, thereby emitting light from the display device 710 .

[0153] Fig.11 is a circuit diagram illustrating a pixel P applied to a display device 600 according to another embodiment of the present disclosure.

[0154] Fig.11 The pixel P of the display device 600 shown in FIG. 7 includes an organic light emitting diode (OLED) corresponding to a display device 710, and a pixel driver PDC configured to drive the display device 710. The display device 710 is connected to the pixel driver PDC.

[0155] The pixel driver PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0156] In the pixel P, there are signal lines DL, EL, GL, PL, SCL, and RL configured to provide driving signals to the pixel driver PDC.

[0157] and Fig.10 Compared with the pixel P, Fig.11 The pixel P further includes a light emitting control line EL. A light emitting control signal EM is provided to the light emitting control line EL.

[0158] In addition, Fig.10 Compared with the pixel driver PDC, Fig.11 The pixel driver PDC further includes a fourth thin film transistor TR4 corresponding to a light emission control transistor, and the fourth thin film transistor TR4 controls a light emission time point of the second thin film transistor TR2.

[0159] Reference Fig.11 When the gate line of the (n)th pixel P is referred to as “GLn”, the gate line of the adjacent (n-1)th pixel P is “GLn-1”, and the “GLn-1” corresponding to the gate line of the (n-1)th pixel P is used as the sensing control line SCL of the (n)th pixel P.

[0160] The first capacitor C1 is located between the display device 710 and the gate electrode G2 of the second thin film transistor TR2. In addition, the second capacitor C2 is located between one electrode of the display device 710 and a terminal to which the driving voltage Vdd is supplied among terminals of the fourth thin film transistor TR4.

[0161] As the first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, the first thin film transistor TR1 transmits the data voltage Vdata supplied to the data line DL to the gate electrode G2 of the second thin film transistor TR2.

[0162] The third thin film transistor TR3 is connected to the reference line RL and the first node n1 between the display device 710 and the second thin film transistor TR2. The third thin film transistor TR3 is turned on or off by the sensing control signal SCS and senses the characteristics of the second thin film transistor TR2 corresponding to the driving transistor in the sensing period.

[0163] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 according to the light emission control signal EM, or blocks the driving voltage Vdd. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2, thereby emitting light from the display device 710.

[0164] In addition to the above structure, the pixel driver PDC according to another embodiment of the present disclosure may be formed in various structures. For example, the pixel driver PDC may include five or more thin film transistors.

[0165] Fig.12 is a circuit diagram of any one pixel of the display device 700 according to another embodiment of the present disclosure. Fig.13 It is a graphic Fig.12 A floor plan of pixels. Fig.14 is along Fig.13 A cross-sectional view taken along line IV-IV'.

[0166] Fig.12 is an equivalent circuit diagram of a pixel P of a liquid crystal display device including liquid crystal (LC) used as a display device. Fig.12 The display device 700 corresponds to a liquid crystal display device.

[0167] Reference Fig.12 , Fig.13 and Fig.14 According to another embodiment of the present disclosure, a display device 700 includes a substrate 310, a pixel driver PDC on the substrate 310, and a liquid crystal capacitor Clc connected to the pixel driver PDC. Here, the liquid crystal capacitor Clc corresponds to a display device. Fig.12 As shown in , a pixel P of a liquid crystal display device may include a pixel driver PDC and a liquid crystal capacitor Clc corresponding to a display device.

[0168] The pixel driver PDC includes a thin film transistor TR1c connected to the gate line GL and the data line DL, and a storage capacitor Cst connected between the thin film transistor TR1c and the second electrode 372 of the display device. A liquid crystal capacitor Clc is connected between the thin film transistor TR1c and the second electrode 372 in parallel with the storage capacitor Cst.

[0169] The liquid crystal capacitor Clc corresponding to the display device is charged with a differential voltage between a data signal and a common voltage Vcom, and the amount of light transmission is controlled by driving the liquid crystal according to the charged voltage, the data signal is supplied to the first electrode 371 corresponding to the pixel electrode through the thin film transistor TR1c, and the common voltage Vcom is supplied to the second electrode 372 corresponding to the common electrode. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

[0170] Reference Fig.14 According to another embodiment of the present disclosure, a display device 700 includes a substrate 310, a light-shielding layer LS and a signal line DL on the substrate 310, a buffer layer 320 on the light-shielding layer LS and the signal line DL, an active layer A on the buffer layer 320, a gate insulating film 330 on the active layer A, a gate electrode G on the gate insulating film 330, and a pixel electrode (first electrode) 371 on the gate electrode G.

[0171] The substrate 310 may be formed of glass or plastic. The substrate 310 may be formed of plastic having flexibility, such as polyimide (PI).

[0172] A light shielding layer LS and data lines DL corresponding to signal lines are disposed on the substrate 310 .

[0173] The light shielding layer LS prevents incident light provided from the outside and protects the active layer A.

[0174] according to Fig.14 In the embodiment shown in , the signal line may include a data line DL. Fig.14 , the data line DL and the light shielding layer LS are arranged on the same layer.

[0175] The light shielding layer LS is formed of the same material as that of the data line DL corresponding to the signal line, and the light shielding layer LS and the data line DL can be manufactured through the same process.

[0176] exist Fig.14 In the embodiment, the light shielding layer LS is separated from the data line DL corresponding to the signal line, however, the structure is not limited to this structure. For example, the light shielding layer LS may be connected to the data line DL.

[0177] The buffer layer 320 is disposed on the light shielding layer LS and the data line DL corresponding to the signal line. The buffer layer 320 is formed of an insulating material, and the buffer layer 320 protects the active layer A from moisture or oxygen provided from the outside. The buffer layer 320 may be formed of an insulating material, such as silicon oxide or silicon nitride.

[0178] The active layer A of the thin film transistor TR1c is disposed on the buffer layer 320. At least some portions of the active layer A of the thin film transistor TR1c may overlap the light shielding layer LS.

[0179] According to one embodiment of the present disclosure, the active layer A may include an oxide semiconductor material. For example, the active layer A may include at least one of an IZO (InZnO)-based oxide semiconductor, an IGO (InGaO)-based oxide semiconductor, a GO (GaO)-based oxide semiconductor, an ITO (InSnO)-based oxide semiconductor, an IGZO (InGaZnO)-based oxide semiconductor, an IGTO (InGaSnO)-based oxide semiconductor, an IGZTO (InGaZnSnO)-based oxide semiconductor, a GZTO (GaZnSnO)-based oxide semiconductor, a GZO (GaZnO)-based oxide semiconductor, and an ITZO (InSnZnO)-based oxide semiconductor. However, one embodiment of the present disclosure is not limited to the above materials. The active layer A may be formed of other oxide semiconductor materials generally known to those skilled in the art.

[0180] However, one embodiment of the present disclosure is not limited to the above. The active layer A may have a multi-layer structure. Figure 6 In the same manner, the active layer A may include a first oxide semiconductor layer on the buffer layer 320 and a second oxide semiconductor layer on the first oxide semiconductor layer. The first oxide semiconductor layer serves as a supporting layer configured to support the second oxide semiconductor layer, and the second oxide semiconductor layer serves as a channel layer. In this case, generally, the channel of the active layer A is provided in the second oxide semiconductor layer.

[0181] The first oxide semiconductor layer used as the supporting layer may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an IGTO (InGaSnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, and a GO (GaO)-based oxide semiconductor material. The second oxide semiconductor layer may include at least one of an IZO (InZnO)-based oxide semiconductor, an IGO (InGaO)-based oxide semiconductor, an ITO (InSnO)-based oxide semiconductor, an IGZO (InGaZnO)-based oxide semiconductor, an IGZTO (InGaZnSnO)-based oxide semiconductor, a GZTO (GaZnSnO)-based oxide semiconductor, a GZO (GaZnO)-based oxide semiconductor, and an ITZO (InSnZnO)-based oxide semiconductor.

[0182] Reference Fig.14 , a gate insulating film 330 is disposed on the active layer A. The gate insulating film 330 has insulating properties. The gate insulating film 330 may be patterned together with the gate electrode G, or may not be patterned.

[0183] According to one embodiment of the present disclosure, Fig.14 As shown in , the gate insulating film 330 may be provided on the entire upper surface of the substrate 310 including the upper surface of the active layer A. In this case, the gate insulating film 330 is not patterned.

[0184] The gate electrode G is disposed on the gate insulating film 330. The gate electrode G may be a portion extending from the gate line GL, or may be some portion of the gate line GL. The gate electrode G may include at least one of an aluminum-based metal such as aluminum or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode G may have a multilayer structure including at least two layers having different physical properties.

[0185] Through the selective conduction process using the gate electrode G as a mask, a partial region of the active layer A is provided with conductivity, thereby becoming a conductive region.

[0186] The region of the active layer A overlapping with the gate electrode G is not provided with conductivity, and thus does not become a conductive region, but becomes the channel region 31. Some regions of the active layer A not overlapping with the gate electrode G are provided with conductivity, and thus become conductive regions 32 and 33. Generally, the conductive regions 32 and 33 are formed on both sides relative to the channel region 31.

[0187] According to one embodiment of the present disclosure, some regions of the active layer A may be provided with conductivity by a doping process using a dopant, thereby becoming a conductive region. In this case, the doped region becomes a conductive region. The dopant may pass through the gate insulating film 330 and be doped into some regions of the active layer A. Thus, although the active layer A is not exposed to the outside from the gate insulating film 330, selective doping of the active layer A is possible. According to one embodiment of the present disclosure, the gate insulating film 330 may not be patterned.

[0188] Either one of the conductive regions 32 and 33 becomes the source region 32, and the other becomes the drain region 33. The source region 32 functions as a source connection region connected to the source electrode S, or the source region 32 itself functions as the source electrode S. The drain region 33 functions as a drain connection region connected to the drain electrode D, or the drain region 33 itself functions as the drain electrode D.

[0189] For ease of explanation, Fig.14The source region 32 and the drain region 33 shown in FIG are distinguished from each other. However, the source region 32 and the drain region 33 may be used interchangeably. Depending on the voltage, the source region 32 may become the drain region 33, and the drain region 33 may become the source region 32. In addition, the source region 32 may become the source electrode S or the drain electrode D, and the drain region 33 may become the drain electrode D or the source electrode S.

[0190] For ease of explanation, Fig.14 In FIG. 1 , the source region 32 is referred to as a source electrode S, and the drain region 33 is referred to as a drain electrode D.

[0191] Reference Fig.14 , the passivation layer 340 is disposed on the gate electrode G. The passivation layer 340 protects the active layer A and the gate electrode G.

[0192] According to another embodiment of the present disclosure, no additional source electrode and drain electrode are provided on the passivation layer 340. Thus, according to another embodiment of the present disclosure, a patterning process for forming the source electrode and the drain electrode may be omitted. As a result, the manufacturing process of the display device 700 may be simplified.

[0193] The protective layer 350 is disposed on the passivation layer 340. The protective layer 350 is provided to planarize the upper surface of the gate electrode G and protect the pixel driver PDC, and thus the protective layer 350 may be referred to as a planarization layer.

[0194] Reference Fig.14 , the second electrode 372 of the display device is disposed on the protective layer 350. A common voltage is applied to the second electrode 372. Thus, the second electrode 372 may be referred to as a common electrode.

[0195] The interlayer insulating layer 360 is disposed on the second electrode 372 , and the first electrode 371 of the display device Clc is disposed on the interlayer insulating layer 360 .

[0196] The first electrode 371 and the second electrode 372 are interchangeable in position. Figure 12 to Figure 14 In another embodiment of the present disclosure shown, a liquid crystal capacitor Clc is used as a display device of a display apparatus 700, and the display device includes a first electrode 371 corresponding to a pixel electrode, a second electrode 372 corresponding to a common electrode, and a liquid crystal layer (LC).

[0197] In addition, refer to Fig.13 and Fig.14, the first electrode 371 has a linear electrode type, and the second electrode 372 has a planar electrode type, but is not limited to these types. For example, the first electrode 371 may have a planar electrode type, and the second electrode 372 may have a linear electrode type. In other ways, both the first electrode 371 and the second electrode 372 may have a linear electrode type, or both the first electrode 371 and the second electrode 372 may have a planar electrode type.

[0198] Reference Fig.14 The first electrode 371 is connected to the active layer A via the contact hole CH2. In detail, the first electrode 371 is directly connected to the active layer A via the contact hole CH2 formed in the interlayer insulating layer 360, the protective layer 350, the passivation layer 340 and the gate insulating film 330.

[0199] The connection electrode BRL1 is disposed on the interlayer insulating layer 360 .

[0200] The connection electrode BRL1 is formed of the same material as the first electrode 371 corresponding to the pixel electrode, and may be disposed at the same layer as the first electrode 371. The connection electrode BRL1 and the first electrode 371 may be manufactured together using the same material through the same process.

[0201] The connection electrode BRL1 connects the active layer A to the data line DL corresponding to the signal line. Fig.14 , a contact hole CHL1 is provided to connect the data line DL and the active layer A to each other.

[0202] A liquid crystal layer (LC) is disposed on the first electrode 371. In detail, the liquid crystal layer (LC) is disposed between the substrate 310 and the opposite substrate 410 thereof.

[0203] Reference Fig.14 , the color filter 421 is disposed on the opposite substrate 410, and the black matrix 430 is disposed between each color filter 421. The black matrix 430 is disposed to separate each pixel region.

[0204] exist Fig.14 In the embodiment, the color filter 421 is disposed on the counter substrate 410, but the structure is not limited to this. For example, the color filter 421 may be disposed on the substrate 310.

[0205] According to one embodiment of the present disclosure, the thin film transistor TR1c is formed of an active layer A and a gate electrode G. In the thin film transistor TR1c, the source region 32 of the active layer A becomes a source electrode S, and the drain region 33 becomes a drain electrode D.

[0206] exist Fig.14 In the thin film transistor TR1c shown in FIG. 1 , the active layer A is disposed between the gate electrode G and the substrate 310. Fig.14As shown in , when the substrate 310 is the bottom, the structure of the thin film transistor in which the gate electrode G is disposed above the active layer A is referred to as a top gate structure.

[0207] Compared with the bottom gate structure, the thin film transistor of the top gate structure has the advantage of relatively low power consumption. In addition, in the case of the thin film transistor according to another embodiment of the present disclosure, no additional process for forming the source electrode and the drain electrode is required. Therefore, even if the top gate structure is adopted in another embodiment of the present disclosure, the number of steps for forming the thin film transistor TR1c can be reduced, and the number of deposited layers can be reduced, thereby reducing the number of contact holes, thereby reducing the manufacturing cost and reducing the occupied size of the thin film transistor.

[0208] According to another embodiment of the present disclosure, even if a top gate structure is adopted, the aperture ratio of the display device 700 may be improved.

[0209] Fig.15 is along Fig.13 A cross-sectional view taken along line V-V'.

[0210] Reference Fig.15 The light shielding layer LS is connected to the gate electrode G by using the connection electrode BRL2. A contact hole CHL3 is provided to connect the light shielding layer LS to the gate electrode G.

[0211] The light shielding layer LS is connected to the gate electrode G, which can prevent the light shielding layer LS from being in an unstable floating state. In addition, the light shielding layer LS is connected to the gate electrode G, which can produce the effect that occurs when the gate electrodes are provided on both sides of the active layer A, thereby increasing the on-current of the thin film transistor TR1c.

[0212] Fig.16 is a plan view illustrating a pixel of a display device 800 according to another embodiment of the present disclosure. Fig.17 is along Fig.16 A cross-sectional view taken along line VI-VI'.

[0213] Reference Fig.16 and Fig.17 , a first electrode 371 corresponding to a pixel electrode is disposed on the protective layer 350 , an interlayer insulating layer 360 is disposed on the first electrode 371 , and a second electrode 372 of the display device may be disposed on the interlayer insulating layer 360 .

[0214] In the following, reference will be made to FIG. 18A to FIG. 18G Describing a method of manufacturing a display device 100 according to an embodiment of the present disclosure

[0215] FIG. 18A to FIG. 18G is a cross-sectional view illustrating a method of manufacturing a display device according to one embodiment of the present disclosure.

[0216] First, refer to Fig.18A , light shielding layers LS1, LS2 and signal lines DL, PL are provided on a substrate 310. Some portions of the second light shielding layer LS2 may be used as a first capacitor electrode C11 of a first capacitor. The light shielding layers LS1, LS2 and the signal lines DL, PL may be manufactured together using the same material and through the same process. In this case, a mask process using an optical mask may be performed.

[0217] Reference Fig.18B A buffer layer 220 is disposed on the light shielding layers LS1, LS2 and the signal lines DL, PL, and active layers A1, A2 are disposed on the buffer layer 220. The active layers A1, A2 include an oxide semiconductor material. A mask process for forming the active layers A1, A2 is performed.

[0218] Reference Fig. 18C , a gate insulating film 230 is formed on the active layers A1 and A2 , and gate electrodes G1 and G2 are formed on the gate insulating film 230 .

[0219] The gate insulating film 230 is disposed on the entire upper surface of the substrate 210 including the upper surfaces of the active layers A1, A2. The gate insulating film 230 is not patterned.

[0220] A mask process for forming the gate electrodes G1 and G2 is performed.

[0221] Reference Fig. 18C , the active layers A1 and A2 are selectively provided with conductivity by a doping process using the gate electrodes G1 and G2 as masks, thereby selectively becoming conductive regions. Portions of the active layers A1 and A2 overlapping with the gate electrodes G1 and G2 are not provided with conductivity, thereby becoming channel regions 31. Portions of the active layers A1 and A2 that do not overlap with the gate electrodes G1 and G2 become conductive regions 32 and 33.

[0222] Reference Fig.18D A passivation layer 240 is formed on the gate electrodes G1 and G2, and a protective layer 250 is formed on the passivation layer 240. Contact holes CH1, CH2, CH3, and CH4 are formed in the protective layer 250. The contact holes CH1, CH2, CH3, and CH4 may penetrate the protective layer 250 and may penetrate at least one of the passivation layer 240, the gate insulating film 230, and the buffer layer 220.

[0223] A mask process for forming contact holes CH1, CH2, CH3, and CH4 is performed.

[0224] According to one embodiment of the present disclosure, the process for forming the source electrode and the drain electrode on the passivation layer 240 may be omitted. Thus, according to one embodiment of the present disclosure, at least one mask process for forming the source electrode and the drain electrode may be omitted. As a result, the process of manufacturing the display device 100 may be further simplified.

[0225] Reference Fig.18E , a first electrode 711 of the display device 710 is formed on the protective layer 250. The connecting electrodes BR1, BR2, BR3 and the first electrode 711 of the display device 710 may be manufactured at the same time.

[0226] The connection electrodes BR1, BR2, BR3 and the first electrode 711 may be formed of the same material and may be disposed on the same layer. The connection electrodes BR1, BR2, BR3 and the first electrode 711 may be manufactured by the same process. A mask process for forming the connection electrodes BR1, BR2, BR3 and the first electrode 711 of the display device 710 is performed.

[0227] The signal lines DL, PL and the active layers A1, A2 may be connected to each other by using the connection electrodes BR1, BR3.

[0228] Reference Fig.18D and Fig.18E , the connection electrode may be formed in at least some portions of the contact hole penetrating some portions of the protection layer 250 , the gate insulating film 230 , and the buffer layer 220 .

[0229] In more detail, a first contact hole CH1 is formed penetrating some portions of each of the protective layer 250, the passivation layer 240, the gate insulating film 230 and the buffer layer 220 to expose at least some portions of the driving power line PL and the second active layer A2, and a conductive film of the same material as the first electrode 711 of the display device 710 is disposed in at least some portions of the first contact hole CH1, thereby forming a first connection electrode BR1, and the first connection electrode BR1 is configured to connect the driving power line PL and the second active layer A2 to each other.

[0230] A fourth contact hole CH4 is formed penetrating some portions of each of the protective layer 250, the passivation layer 240, the gate insulating film 230 and the buffer layer 220 to expose at least some portions of the data line DL and the first active layer A1, and a conductive film of the same material as the first electrode 711 is disposed in at least some portions of the fourth contact hole CH4, thereby forming a third connection electrode BR3, which is configured to connect the data line DL and the first active layer A1 to each other.

[0231] The first electrode 711 extends to at least a portion of the second contact hole CH2 penetrating the protection layer 250 , the gate insulating film 230 , and the buffer layer 220 , and then the first electrode 711 may be directly connected to the light shielding layer LS2 and the active layer A2 .

[0232] In more detail, a second contact hole CH2 is formed through a portion of each of the protective layer 250, the passivation layer 240, the gate insulating film 230 and the buffer layer 220 to expose at least a portion of the second light-shielding layer LS2 and at least a portion of the second active layer A2, and the first electrode 711 extends to the second contact hole CH2, so that the first electrode 711 can be directly connected to the second light-shielding layer LS2 and the second active layer A2.

[0233] Reference Fig.18F , a bank layer 750 is disposed on the edge of the first electrode 711. A mask process for forming the bank layer 750 is performed.

[0234] Reference Figure 18G , a light-emitting layer 712 and a second electrode 713 are sequentially disposed on the first electrode 711 , thereby forming a display device 710 .

[0235] In the display device according to one embodiment of the present disclosure, the light shielding layer and the signal line are provided in the same layer and manufactured through the same process. Therefore, it is not necessary to provide an additional mask process for forming the light shielding layer for the manufacturing process of the display device.

[0236] In addition, according to one embodiment of the present disclosure, the signal line and the active layer of the thin film transistor can be connected by using a connection electrode formed by a process for forming the first electrode of the display device. Thus, in the manufacturing process of the display device, it is not necessary to perform an additional mask process for forming the source electrode and the drain electrode of the thin film transistor.

[0237] Thus, according to the embodiments of the present disclosure, a display device having a simplified structure and a method of manufacturing the display device using a simplified process may be provided.

[0238] It is obvious to those skilled in the art that the above disclosure is not limited by the above embodiments and drawings, and that various substitutions, modifications and changes may be made in the disclosure without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the disclosure.

Claims

1. A display device, include: substrate; A light shielding layer and a signal line on the substrate; The light shielding layer and the buffer layer on the signal line; an active layer on the buffer layer; a gate insulating film on the active layer; a gate electrode on the gate insulating film; a protective layer on the gate electrode; a first electrode of the display device on the protective layer; and a connection electrode configured to connect the signal line and the active layer to each other, The light shielding layer and the signal line are arranged on the same layer, wherein the connecting electrode and the first electrode are formed of the same material, and The connection electrode contacts an upper surface of the signal line and a side surface of the active layer. 2 . The display device according to claim 1 , wherein the connection electrode is provided on the same layer as the first electrode. 3 . The display device according to claim 2 , wherein the light shielding layer is formed of the same material as that of the signal line. 4 . The display device according to claim 1 , wherein the signal line comprises at least one of a data line and a driving power line. The display device according to claim 1 , wherein the light shielding layer is connected to the signal line. The display device according to claim 1 , wherein the light shielding layer and the signal line are formed as one body. 7 . The display device according to claim 1 , wherein the gate insulating film is provided on an upper surface of the substrate including an upper surface of the active layer. 8 . The display device according to claim 1 , wherein the active layer is provided between the gate electrode and the substrate. 9 . The display device according to claim 1 , wherein the active layer comprises an oxide semiconductor material.

10. The display device according to claim 1, wherein the active layer include: a first oxide semiconductor layer on the buffer layer; and A second oxide semiconductor layer is formed on the first oxide semiconductor layer. 11 . The display device according to claim 1 , further comprising a light emitting layer provided on the first electrode. 12 . The display device according to claim 11 , further comprising a capacitor connected to the first electrode, wherein any one electrode of the capacitor is formed integrally with the light shielding layer. 13 . The display device according to claim 12 , wherein the first electrode is directly connected to the light shielding layer and the active layer.

14. The display device according to claim 1, further comprising a liquid crystal layer disposed on the first electrode. 15 . The display device according to claim 7 , wherein the gate insulating film is provided on the entire upper surface of the substrate including an upper surface of the active layer.

16. A method of manufacturing a display device, include: forming a light shielding layer and a signal line on a substrate; forming a buffer layer on the light shielding layer and the signal line; forming an active layer on the buffer layer; forming a gate insulating film on the active layer; forming a gate electrode on the gate insulating film; selectively providing conductivity to the active layer by using the gate electrode as a mask to selectively realize a conductive region in the active layer; forming a protective layer on the gate electrode; forming a first electrode of a display device on the protective layer; and forming a connection electrode configured to connect the signal line and the active layer to each other, wherein the light shielding layer and the signal line are manufactured using the same material and through the same process, wherein the connecting electrode and the first electrode are manufactured using the same material and through the same process, and The connection electrode contacts an upper surface of the signal line and a side surface of the active layer.

17. The method of claim 16, wherein the step of selectively realizing a conductive region in the active layer is performed by a doping process. 18 . The method according to claim 16 , wherein the connection electrode is formed in at least some portions of a contact hole penetrating some portions of each of the protection layer, the gate insulating film, and the buffer layer.

19. The method according to claim 16, wherein the first electrode extends to at least some portions of a contact hole penetrating some portions of each of the protection layer, the gate insulating film, and the buffer layer, and the first electrode is directly connected to the light shielding layer and the active layer.

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