Power device including a metal layer

Abstract

This disclosure relates to a power device including a metal layer. The power semiconductor device includes: a substrate having an edge; an insulating layer disposed above the substrate; a metal layer disposed above the insulating layer and including a first portion and a second portion; a coating layer disposed above the metal layer; and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness, and the second portion has a second thickness greater than the first thickness, and the second portion is disposed further away from the edge of the substrate than the first portion.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to U.S. nonprovisional application No. 16 / 714249, filed December 13, 2019, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to power semiconductor devices, and more particularly to power devices including metal layers. Background Technology

[0004] Power semiconductor devices are used in many different industries. Some of these industries, such as telecommunications, computing, and billing systems, are developing rapidly.

[0005] Power semiconductor devices may have package structures to protect integrated circuits (ICs) from physical or chemical corrosion. For example, such package structures include a substrate, one or more insulating layers, a metal layer, and an encapsulation layer. Mismatches in the coefficients of thermal expansion (CTE) between the constituent materials of this package structure can cause thermal deformation and stress, which can degrade the yield, lifespan, and reliability of the power semiconductor device. For example, during the manufacturing process of a power semiconductor device, tensile stresses can be generated in one or more insulating layers of the package structure, leading to cracks in these insulating layers and reducing the yield of the power semiconductor device. Summary of the Invention

[0006] Embodiments of this application relate to a power semiconductor device including a substrate and a metal layer, wherein the substrate has an edge and the metal layer includes a first portion and a second portion. The second portion is configured to be further away from the edge of the substrate than the first portion. The first portion of the metal layer has a first thickness that is smaller than the second thickness of the second portion, and thus reduces the stress applied to the first portion during thermal processes.

[0007] In one embodiment, the power semiconductor device includes: a substrate having an edge, an insulating layer disposed above the substrate, a metal layer disposed above the insulating layer and including a first portion and a second portion, a coating layer disposed above the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness greater than the first thickness, and the second portion is disposed further away from the edge of the substrate than the first portion.

[0008] In an embodiment of the above device, the first thickness of the first portion is in the range of 1 μm to 2 μm, and the second thickness of the second portion is in the range of 4 μm to 5 μm.

[0009] In the implementation of the above-described device, the first part and the second part form a single integrated body.

[0010] In the implementation of the above device, the distance between the outer edge of the first part and the outer edge of the second part is equal to or greater than 20 μm.

[0011] In the implementation of the above-described device, the first part and the second part are spaced apart by a distance ranging from 4μm to 8μm.

[0012] In the embodiments of the above-described device, the coating layer has a thickness greater than 9 μm.

[0013] In an embodiment of the above-described device, the coating layer comprises multiple portions, wherein adjacent pairs of the multiple portions are spaced apart by a distance ranging from 20 μm to 40 μm.

[0014] In the embodiment of the above device, the protective layer has a diameter of 3.4*10. -6 / ℃ to 8.0*10 -6 The substrate has a coefficient of thermal expansion (CTE) in the range of / ℃, and has a coefficient of thermal expansion of 4.2*10. -6 / ℃ to 4.4*10 -6 CTE within the range of / ℃.

[0015] In one embodiment, a method for forming a power semiconductor device includes: forming an insulating layer over a substrate, forming a first metal material layer over the insulating layer, forming a second metal material layer over the first metal material layer, etching the second metal material layer to form a second metal pattern, and etching the first metal material layer to form the first metal pattern. The outer edge of the second metal pattern is configured to be further away from the edge of the substrate than the outer edge of the first metal pattern.

[0016] In an embodiment of the above method, the method further includes: forming an etch stop material layer between a first metal material layer and a second metal material layer, and etching the etch stop material layer to form an etch stop layer. The first metal pattern has a thickness in the range of 1 μm to 2 μm, and the total thickness of the first metal pattern, the etch stop layer, and the second metal pattern is in the range of 4 μm to 5 μm. Attached Figure Description

[0017] Figure 1A and Figure 1B A power semiconductor device including a metal layer according to an embodiment is shown.

[0018] Figure 2A , Figure 2B , Figure 2C and Figure 2D The process of forming a power semiconductor device according to an embodiment is shown.

[0019] Figure 3 A power semiconductor device including a metal layer according to an embodiment is shown.

[0020] Figure 4 A power semiconductor device including a metal layer according to an embodiment is shown. Detailed Implementation

[0021] Embodiments of this application relate to a power semiconductor device comprising a substrate and a metal layer. The metal layer includes a first portion and a second portion, the second portion being disposed further away from the edge of the substrate than the first portion. The first portion of the metal layer has a first thickness less than the second thickness of the second portion, and the stress applied to the first portion during thermal processes can be reduced. For example, the first portion has a thickness in the range of 1 μm to 2 μm, and the second portion has a thickness in the range of 4 μm to 5 μm. In an embodiment, the first and second portions form a single integrated body, thereby deforming to absorb a portion of the stress applied to the metal layer in the form of elastic energy. The distance between the outer edge of the first portion and the outer edge of the second portion is relatively long to further reduce the stress applied to the second portion during thermal processes. In an embodiment, the metal layer comprises a material with relatively high hardness to make the metal layer more resistant to stress applied thereto. For example, the metal layer comprises an alloy of Al, Cu, and W.

[0022] The power semiconductor device further includes a coating layer disposed above a metal layer and a protective layer covering the substrate, the metal layer, and the coating layer. The coating layer has a relatively thick thickness to reduce stress applied to the metal layer. For example, the thickness of the coating layer is equal to or greater than 9 μm. The protective layer has one or more material properties similar to those of the substrate to reduce stress generated in the upper portion of the power device. For example, the protective layer has a thickness of 3.4 × 10⁻⁶. -6 / ℃ to 8.0*10 -6 The coefficient of thermal expansion (CTE) is within the range of / ℃, while the CTE of this substrate (e.g., SiC substrate) is 4.2*10. -6 / ℃ to 4.4*10 -6 Within the range of / ℃.

[0023] Detailed embodiments are provided below with reference to the accompanying drawings. The scope of this disclosure is limited only by the claims and covers many alternatives, modifications, and equivalents. Although the steps of various methods are presented in a given order, the embodiments are not necessarily limited to being performed in the listed order. In some embodiments, certain operations may be performed simultaneously in a different order than described, or not at all.

[0024] Numerous specific details are set forth in the following description. These details are provided to facilitate a thorough understanding of the scope of this disclosure through specific examples, and to allow for the practice of embodiments according to the claims without some of these specific details. Therefore, the specific embodiments of this disclosure are illustrative and not intended to be exclusive or limiting. For clarity, technical materials known in the art related to this disclosure have not been described in detail so as not to unnecessarily obscure this disclosure.

[0025] Figure 1A and Figure 1B A power semiconductor device 100 according to an embodiment of the present disclosure is shown. Figure 1A This is a plan view of the power semiconductor device 100, and Figure 1B It is along Figure 1A A sectional view of line A-A'.

[0026] exist Figure 1A and Figure 1B In the illustrated embodiment, power device 100 is a power metal-oxide-semiconductor field-effect transistor (MOSFET) device. For example, such a MOSFET device may have a horizontal channel structure or a vertical channel structure. In other embodiments, power device 100 may be other power devices, such as diode devices, insulated-gate bipolar transistor (IGBT) devices, etc.

[0027] Power device 100 includes a semiconductor substrate 102. In embodiments, substrate 102 includes a semiconductor compound, such as a group IV compound semiconductor substrate, a group III-V compound semiconductor substrate, or a group II-VI oxide semiconductor substrate. For example, substrate 102 includes a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0028] A gate dielectric layer (not shown) is disposed between each of one or more gate electrodes 104 and the semiconductor substrate 102. A first insulating layer 106 is disposed over the semiconductor substrate 102 and the gate electrode 104, and comprises an oxide or nitride. A second insulating layer 108 is disposed over the first insulating layer 106, and comprises an oxide or nitride. The first insulating layer 106 and the second insulating layer 108 insulate the gate electrode 104 from the metal layer 110. Although Figure 1B The illustrated embodiment includes two insulating layers 106 and 108, but the embodiments disclosed herein are not limited thereto. For example, a single insulating layer (not shown) may replace the first insulating layer 106 and the second insulating layer 108.

[0029] The metal layer 110 includes a first portion 110-1 and a second portion 110-2. The second portion 110-2 is positioned further away from the edge of the substrate 102 than the first portion 110-1. Figure 1B In the embodiment shown, the outer edge of the first portion 110-1 is relative to Figure 1B The outer edge of the first portion 110-1 is spaced apart from the edge of the substrate 102 by a first distance L0 in the horizontal direction, and the outer edge of the second portion 110-2 is spaced apart from the outer edge of the first portion 110-1 by a second distance L1 in the horizontal direction. For example, the first distance L0 is equal to or greater than 30 μm, and the second distance L1 is in the range of equal to or greater than 20 μm. Furthermore, the thickness T1 of the first portion 110-1 is less than the thickness T2 of the second portion 110-2. For example, the thickness T1 of the first portion 110-1 may be in the range of 20% to 60% of the thickness T2 of the second portion 110-2, and the height difference LD between the thickness T1 of the first portion 110-1 and the thickness T2 of the second portion 110-2 may be in the range of 40% to 80% of the thickness T2 of the second portion 110-2. Figure 1B In the embodiment shown, the thickness T1 of the first part 110-1 is relative to Figure 1B The distance between the upper surface 152 and the lower surface 154 of the first portion 110-1 in the vertical direction of its orientation. In an embodiment, the lower surface 154 contacts the top of the barrier layer 114, and the upper surface 152 is along... Figure 1B The horizontal direction has a similar profile to the lower surface 154. Figure 1B Three thicknesses T1, T1', and T1'" are shown at the outer edge of the first portion 110-1, in the recessed portion of the first portion 110-1, and at the inner edge of the first portion 110-1, respectively, and these thicknesses T1, T1', and T1'" of the first portion 110-1 may be substantially the same. For example, the difference between the maximum and minimum values ​​of the thicknesses T1, T1', and T1'" of the first portion 110-1 may be equal to or less than 5% of the minimum value. The thickness T2 of the second portion 110-2 is the distance between the upper surface 160 and the lower surface 162 of the second portion 110-2. Similarly, the second portion 110-2 along... Figure 1B The horizontal direction has essentially the same thickness T2.

[0030] A barrier layer 114 is disposed between the metal layer 110 and the second insulating layer 108 and serves to substantially block the migration of metal ions from the metal layer 110 to the second insulating layer 108, or to improve the adhesion properties of the metal layer 110, or both. For example, the barrier layer 114 comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), or a combination thereof.

[0031] Despite Figure 1BThe embodiment is not shown, but a conductive layer (not shown) may be disposed between the metal layer 110 and the substrate 102 to electrically couple one or more portions (e.g., source or drain regions) of the metal layer 110 and the substrate 102. For example, such a conductive layer is a silicide layer and includes multiple portions, each serving as a source electrode or a drain electrode. Furthermore, although in Figure 1B The implementation is not shown, but the etch stop layer (e.g., Figure 2D The etch stop layer 232' in the middle can be set in the second part 110-2.

[0032] A passivation layer 116 is disposed over the second insulating layer 108 and the metal layer 110. In an embodiment, the passivation layer 116 comprises the same material as the first insulating layer 106 or the second insulating layer 108, or both. For example, the passivation layer 116 comprises an oxide or a nitride.

[0033] The coating layer 120 is disposed between the passivation layer 116 and the protective layer 140, and is used to reduce chip stress and substantially block ions from migrating from the protective layer 140 to the chip circuitry of the power device 100. For example, the coating layer 120 covers the passivation layer 116 and a first portion 110-1 and a second portion 110-2 of the metal layer 110, and includes polyimide.

[0034] The protective layer 140 covers the substrate 102, the first insulating layer 106, the second insulating layer 108, the metal layer 110, the passivation layer 116, and the coating layer 120, and is used to protect the chip circuitry of the power device 100 from physical or chemical corrosion. In an embodiment, the protective layer 140 comprises an epoxy molding compound (EMC) material, and the EMC material includes silicon dioxide, epoxy resin, hardener, flame retardant, catalyst, stress relaxation additive, etc.

[0035] As mentioned above, Figure 1B The power device 100 has a package structure to protect the chip circuitry of the power device 100 from physical or chemical corrosion. When thermal processes are performed on such a package structure, thermal deformation and stress may occur in the power device 100, and therefore the integrity and reliability of the package structure of the power device 100 may deteriorate. For example, when a cooling process is performed on the protective layer 140, the protective layer 140 contracts to apply compressive stress to the side surfaces of the coating layer 120 and compressive and shear stresses to the top surface of the coating layer 120. These stresses can propagate through the coating layer 120, and the propagated stresses can be applied to the metal layer 110 to cause the metal layer 110 to be in a specific direction (e.g., relative to...). Figure 1B The orientation is shifted to the right, thereby generating tensile stress in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116. The propagated stress can also be in a specific direction (e.g., relative to the orientation). Figure 1B A bending moment is generated in the clockwise direction of the orientation of the metal layer 110, which pulls the bottom surface of the metal layer 110 away from the top surface of the second insulating layer 108. These tensile stresses and bending moments can cause cracks to appear in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116.

[0036] When a heating process is performed on the package structure under reliability testing of the power device 100, the substrate 102 has a higher coefficient of thermal expansion (CTE) than each of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116, and therefore the substrate 102 expands more than these layers 106, 108, and 116. The metal layer 110 also has a higher CTE than each of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116, and therefore the metal layer 110 expands more than layers 106, 108, and 116. Consequently, tensile stresses are generated in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116. These tensile stresses can cause cracks to appear in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116.

[0037] In one embodiment, the coating layer 120 has a relatively thick thickness T3 to reduce the stress propagated through the coating layer. Due to the reduced stress applied to the metal layer 110, the displacement of the metal layer 110 can be reduced, and the tensile stress generated in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116 can be reduced. The bending moment required to pull the metal layer 110 away from the second insulating layer 108 can also be reduced.

[0038] In an embodiment, the thickness T1 of the first portion 110-1 of the metal layer 110 is thick enough to suitably serve as an electrical connector, but the thickness T1 of the first portion 110-1 is also thin enough to minimize the vertical cross-sectional area of ​​the first portion 110-1 on which stress propagating through the coating layer 120 is applied. For example, the thickness T1 of the first portion 110-1 is in the range of 1 μm to 2 μm. Because the first portion 110-1 of the metal layer 110 has a relatively thin thickness T1, the vertical cross-sectional area on which the propagated stress is applied can be reduced, thereby reducing the force applied to the vertical cross-sectional area of ​​the first portion 110-1. Therefore, the displacement of the first portion 110-1 during thermal processes can be reduced, thereby reducing the tensile stress generated in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116. The bending moment for pulling the metal layer 110 away from the second insulating layer 108 can also be reduced.

[0039] Similarly, the thickness T2 of the second portion 110-2 can be thin enough to minimize the vertical cross-sectional area of ​​the second portion 110-2 on which stress propagating through the coating layer 120 is applied. On the other hand, the thickness T2 of the second portion 110-2 can be large enough to suitably serve as a heating pad when a wire bonding process is performed on the second portion 110-2. For example, the thickness T2 of the second portion 110-2 is in the range of 4 μm to 5 μm. Furthermore, the distance L1 between the outer edge of the first portion 110-1 and the outer edge of the second portion 110-2 is relatively long to further reduce the stress applied to the second portion 110-2. For example, the distance L1 is equal to or greater than 20 μm. Therefore, the displacement of the second portion 110-2 during the thermal process can be reduced, thereby reducing the tensile stress generated in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116. The bending moment for pulling the metal layer 110 away from the second insulating layer 108 can also be reduced.

[0040] In one embodiment, the first portion 110-1 and the second portion 110-2 form a single integrated body, which deforms to absorb a portion of the stress applied thereon in the form of elastic energy. Therefore, displacement of the metal layer 110 during thermal processes can be reduced, thereby reducing the tensile stress generated in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116. The bending moment required to pull the metal layer 110 away from the second insulating layer 108 can also be reduced.

[0041] In this embodiment, the protective layer 140 has one or more material properties similar to those of the substrate 102. For example, the CTE of the protective layer 140 is 3.4 x 10⁻⁶. -6 / ℃ to 8.0*10 -6 The CTE of substrate 102 is within the range of / ℃, while the CTE of substrate 102 is 4.2*10 -6 / ℃ to 4.4*10 -6 Within the range of / ℃. Since the protective layer 140 has material properties similar to those of the substrate 102, the stress generated in the upper portion of the power device 100 (e.g., the first insulating layer 106, the second insulating layer 108, and the passivation layer 116) due to the difference in material properties between the protective layer 140 and the substrate 120 during the thermal process can be further reduced.

[0042] In an embodiment, the metal layer 110 comprises a material with relatively high hardness. For example, the metal layer 110 comprises an alloy of Al, Cu, and W having a hardness in the range of 0.63 GPa to 0.67 GPa. When the material in the metal layer 110 has relatively high hardness, the material may also have a relatively high elastic modulus. Since the hardness and elastic modulus of a material indicate its resistance to localized plastic deformation and its resistance to elastic deformation, respectively, the metal layer 110 can be more resistant to stresses applied thereto. Therefore, displacement of the metal layer 110 during thermal processes can be reduced, thereby reducing tensile stresses generated in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116.

[0043] As described above, in the power device 100 according to an embodiment of the present disclosure, the tensile stress generated in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116 can be reduced. Therefore, the tensile stress generated when a thermal process is performed on the power device 100 can become sufficiently low to substantially prevent cracking in one or more of the first insulating layer 106, the second insulating layer 108, and the passivation layer 116. Furthermore, the bending moment that pulls the metal layer 110 away from the second insulating layer 108 can be reduced, thereby further reducing the likelihood of such cracking.

[0044] Figure 2A , Figure 2B , Figure 2C and Figure 2D Aspects of a method for forming a semiconductor power device (e.g., power device 100 in FIG. 1) according to embodiments of the present disclosure are illustrated. More specifically, Figures 2A to 2D The formation of a metal layer according to an embodiment is shown (e.g., Figure 1A and Figure 1B The process of forming the metal layer 110 in the process is described below. For the sake of brevity, the description of the remaining processes for forming the power device is omitted.

[0045] exist Figure 2AIn this structure, a first metal material layer 230, an etch stop material layer 232, and a second metal material layer 236 are formed over a structure including a substrate 202, one or more gate electrodes 204, a first insulating layer 206, a second insulating layer 208, and a barrier material layer 214. Each of the first metal material layer 230 and the second metal material layer 236 comprises a conductive material for transmitting electrical signals therethrough. In embodiments, the material includes aluminum (Al), copper (Cu), tungsten (W), platinum (Pt), tantalum (Ta), silicon (Si), or combinations thereof. For example, each of the first material layer 230 and the second material layer 236 may comprise 0.1% Cu, 0.5% W, and 99.4% Al, or comprise 0.5% Cu, 0.8% Si, and 98.7% Al. For example, each of the first metal material layer 230 and the second metal material layer 236 may be deposited using a physical vapor deposition method (e.g., evaporation, DC sputtering, or RF sputtering) or a chemical vapor deposition method (e.g., low-pressure CVD or plasma-enhanced CVD). The first material layer 230 and the second material layer 236 may be formed such that each of the first material layer 230 and the second material layer 236 is aligned with respect to... Figure 2A The orientation of the horizontal direction has essentially the same thickness.

[0046] An etch stop material layer 232 is formed between a first metal material layer 230 and a second metal material layer 236. In an embodiment, the etch stop material layer 232 comprises titanium (Ti) or titanium nitride (TiN). For example, the etch stop material layer 232 can be deposited using physical vapor deposition methods (e.g., sputtering deposition, cathodic arc deposition, or electron beam heating) or chemical vapor deposition methods. Although Figure 2A Although not shown, a conductive layer may be formed between the first metal material layer 230 and the substrate 202 to electrically couple the first metal material layer 230 to one or more portions (e.g., source or drain regions) of the substrate 202.

[0047] exist Figure 2B In this process, a first mask pattern 250 is formed over the second metal material layer 236, and then a first etching process is performed to form a second metal pattern 236' using the first mask pattern 250. In an embodiment, a wet etching process is performed on the second metal material layer 236 using the first mask pattern 250 comprising a photoresist material. The etching rate of the second metal material layer 236 is higher than the etching rate of the etch stop material layer 232, and the first etching process is performed until a portion of the etch stop material layer 232 is exposed.

[0048] exist Figure 2CIn this process, a second etching process is performed to remove the exposed portion of the etch stop material layer 232, thereby forming an etch stop layer 232'. In another embodiment, a dry etching process is performed on the exposed portion of the etch stop material layer 232 to form the etch stop layer 232'. Subsequently, a second mask pattern 260 is formed over the first metal material layer 230 and the second metal pattern 236'.

[0049] exist Figure 2D In one embodiment, a third etching process is performed on the first metal material layer 230 to form a first metal pattern 230' using a second mask pattern 260. In another embodiment, a wet etching process is performed on the first metal material layer 230 using the second mask pattern 260 until a portion of the barrier material layer 214 is exposed. Subsequently, a fourth etching process is performed on the exposed portion of the barrier material layer 214 to remove the exposed portion of the barrier material layer 214, thereby forming a barrier layer 214'. In yet another embodiment, a dry etching process is performed on the exposed portion of the barrier material layer 214 to form the barrier layer 214'. Thus, a metal layer 210 comprising a first metal pattern 230', an etch stop layer 232', and a second metal pattern 236' can be formed. The metal layer 210 may include a first portion comprising the outer portion of the first metal pattern 230' and having a first thickness (e.g., Figure 1B The first thickness T1). The metal layer 210 may further include a second portion, which includes the inner portion of the first metal pattern 230', the etch stop layer 232' and the second metal pattern 236' and has a second thickness greater than the first thickness (e.g., Figure 1B The second thickness T2 in the middle.

[0050] Figure 3 A power semiconductor device 300 according to an embodiment of the present disclosure is shown. The power device 300 includes a semiconductor substrate 302, an insulating layer 308, a passivation layer 316, a first metal layer 310A, a second metal layer 310B, a coating layer 320, and a protective layer 340. For simplicity, some elements of the power device 300 (e.g., a barrier layer, one or more gate electrodes, a gate dielectric layer, and a silicide layer) are not shown. Figure 3 As shown in the image. Although Figure 3 The embodiment shown includes a single insulating layer 308, but embodiments of this disclosure are not limited thereto. For example, the power semiconductor device 300 may include two or more insulating layers (e.g., Figure 1B The first insulating layer 106 and the second insulating layer 108 are used instead of a single insulating layer 308.

[0051] Power device 300 includes a first metal layer 310A and a second metal layer 310B spaced apart from each other by a given distance. Because the first metal layer 310A and the second metal layer 310B are spaced apart from each other, they are compatible with coating layers (e.g., Figure 1B The coating layer 120 is formed in two portions (e.g.,) that are coupled to each other. Figure 1B A single metal layer (e.g., the first part 110-1 and the second part 110-2) in the first part 110-1 and the second part 110-2) Figure 1B Compared to when the first metal layer 310A and the second metal layer 310B are above the metal layer 110, the height difference in the upper surface of the coating layer 320 can be reduced. In an embodiment, the distance between the first metal layer 310A and the second metal layer 310B is large enough to minimize the height difference in the upper surface of the coating layer 320. For example, the distance L2 between the first metal layer 310A and the second metal layer 310B is in the range of 4 μm to 8 μm. In an embodiment, the distance L2 between the first metal layer 310A and the second metal layer 310B is about 6 μm, for example, in the range of 5.9 μm to 6.1 μm. Therefore, the maximum height difference in the upper surface of the coating layer 320 can be equal to or less than 1.5 μm.

[0052] Because the height difference in the upper surface of the coating layer 320 is relatively small, the stress applied to the upper surface of the coating layer 320 during the thermal process becomes more uniform compared to when a relatively large height difference in the upper surface of the coating layer 320 would lead to stress concentration in the upper surface. Therefore, the displacement of the first metal layer 310A during the thermal process can be reduced, thereby reducing the tensile stress generated in the insulating layer 308 or the passivation layer 316, or both. The bending moment required to pull the first metal layer 310A away from the insulating layer 308 can also be reduced. Therefore, according to Figure 3 The embodiment shown can substantially prevent cracks from appearing in the insulating layer 308, or the passivation layer 316, or both, in the power device 300.

[0053] Figure 4 A power semiconductor device 400 according to an embodiment of the present disclosure is shown. The power device 400 includes a semiconductor substrate 402, an insulating layer 408, a passivation layer 416, a first metal layer 410A, a second metal layer 410B, a coating layer 420, and a protective layer 440. For simplicity, some elements of the power device 400 (e.g., a barrier layer, one or more gate electrodes, a gate dielectric layer, and a silicide layer) are not shown. Figure 4 As shown in the image. Although Figure 4 The embodiment shown includes a single insulating layer 408, but embodiments of this disclosure are not limited thereto. For example, the power semiconductor device 400 may include two or more insulating layers (e.g., Figure 1B The first insulating layer 106 and the second insulating layer 108 are used instead of a single insulating layer 408.

[0054] The coating layer 420 includes a plurality of vertical portions spaced apart from each other. In an embodiment, the coating layer 420 has a honeycomb structure comprising an array of hollow cells formed between adjacent vertical portions. For example, when viewed in a top view, each hollow cell may have a specific cross-section (e.g., hexagonal, square, or rectangular) and extend in a direction perpendicular to that cross-section. A protective layer 440 fills the hollow cells between adjacent vertical portions of the coating layer 420.

[0055] In the embodiment, the distance L3 between adjacent vertical portions of the coating layer 420 is in the range of 20 μm to 40 μm. Because these adjacent vertical portions of the coating layer 420 are spaced apart from each other, the coating layer 420 can effectively absorb the stress exerted by the protective layer 440 during thermal processes. Therefore, compared with coating layers that do not include one or more hollow units (e.g., Figure 1B The thickness of the coating layer 120 in the middle (e.g., Figure 1B Compared to the thickness T3 in the coating layer 420, the thickness T4 of each of the multiple portions of the coating layer 420 can be reduced. For example, the thickness T4 of each of the multiple vertical portions of the coating layer 420 is in the range of 6 μm to 9 μm.

[0056] A1. Embodiments of this disclosure relate to power semiconductor devices, said power semiconductor devices comprising:

[0057] A substrate with edges;

[0058] An insulating layer disposed above the substrate;

[0059] A metal layer disposed above the insulating layer and comprising a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, the second portion being disposed further away from the edge of the substrate than the first portion;

[0060] A coating layer, the coating layer being disposed above the metal layer; and

[0061] A protective layer that covers the substrate, the insulating layer, the metal layer, and the coating layer.

[0062] A2. The device according to A1, wherein the first thickness of the first portion is in the range of 20% to 60% of the second thickness of the second portion.

[0063] A3. The device according to A1, wherein the first thickness is the distance between the upper surface of the first portion and the lower surface of the first portion at the outer edge of the first portion, and the second thickness is the distance between the upper surface of the second portion and the lower surface of the second portion at the outer edge of the second portion.

[0064] A4. The device according to A1, wherein the metal layer comprises Al, Cu and W.

[0065] A5. The device according to A1, wherein the coating layer comprises a plurality of portions, adjacent pairs of the plurality of portions being spaced apart by a distance in the range of 20 μm to 40 μm, and wherein the coating layer has a honeycomb structure.

[0066] A6. The device according to A1, wherein the coating layer comprises a plurality of portions, adjacent pairs of the plurality of portions being spaced apart by a distance in the range of 20 μm to 40 μm, and wherein the coating layer has a thickness in the range of 6 μm to 9 μm.

[0067] A7. The device according to A1, wherein the insulating layer is a first insulating layer, the device comprising:

[0068] A second insulating layer is disposed between the substrate and the first insulating layer; and

[0069] A passivation layer is disposed above the first insulating layer and the metal layer.

[0070] A8. The device according to A1, wherein the substrate is a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0071] A9. Embodiments of this disclosure relate to power semiconductor devices, said power semiconductor devices comprising:

[0072] A substrate with edges;

[0073] A first insulating layer is disposed above the substrate;

[0074] A second insulating layer is disposed above the first insulating layer;

[0075] A metal layer disposed above the second insulating layer and comprising a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, the second portion being disposed further away from the edge of the substrate than the first portion;

[0076] A passivation layer is disposed above the second insulating layer and the metal layer;

[0077] A coating layer, the coating layer being disposed above the passivation layer; and

[0078] A protective layer covering the substrate, the first insulating layer, the second insulating layer, the metal layer, the passivation layer, and the coating layer.

[0079] A10. The device according to A9, wherein the first thickness of the first portion is in the range of 20% to 60% of the second thickness of the second portion.

[0080] Various aspects of this disclosure have been described together with specific embodiments presented as examples. Many substitutions, modifications, and variations may be made to the embodiments described herein without departing from the scope of the claims set forth below. Therefore, the embodiments described herein are intended to be illustrative rather than restrictive.

Claims

1. A power semiconductor device, the power semiconductor device comprising: A substrate with edges; An insulating layer disposed above the substrate; A metal layer disposed above the insulating layer and comprising a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, the upper surface of the first portion being at a different level from the upper surface of the second portion, the second portion being disposed further away from the edge of the substrate than the first portion, and the second portion having a second thickness sufficiently large to serve as a pad for performing a wire bonding process thereon. A coating layer disposed above the metal layer; as well as A protective layer that covers the substrate, the insulating layer, the metal layer, and the coating layer.

2. The power semiconductor device of claim 1, wherein the first thickness of the first portion is in the range of 1µm to 2µm, and the second thickness of the second portion is in the range of 4µm to 5µm.

3. The power semiconductor device of claim 1, wherein the first portion and the second portion form a single integrated body.

4. The power semiconductor device of claim 3, wherein the distance between the outer edge of the first portion and the outer edge of the second portion is equal to or greater than 20µm.

5. The power semiconductor device of claim 1, wherein the first portion and the second portion are spaced apart by a distance in the range of 4µm to 8µm.

6. The power semiconductor device of claim 1, wherein the coating layer has a thickness greater than 9 µm.

7. The power semiconductor device of claim 1, wherein the coating layer comprises a plurality of portions, wherein adjacent pairs of the plurality of portions are spaced apart by a distance in the range of 20µm to 40µm.

8. The power semiconductor device according to claim 1, wherein the protective layer has a thickness of 3.4 x 10⁻⁶ mm. -6 / ℃ to 8.0*10 -6 The substrate has a coefficient of thermal expansion (CTE) in the range of / ℃, and the substrate has a coefficient of thermal expansion of 4.2*10. -6 / ℃ to 4.4*10 -6 The coefficient of thermal expansion within the range of / ℃.

9. A method for forming a power semiconductor device, the method comprising: An insulating layer is formed above the substrate; A first metallic material layer is formed over the insulating layer; A second metal material layer is formed above the first metal material layer; Etch the second metal material layer to form a second metal pattern; as well as The first metal material layer is etched to form a first metal pattern having a first thickness, the outer edge of the second metal pattern is configured to be further away from the edge of the substrate than the outer edge of the first metal pattern, and the second metal pattern has a second thickness greater than the first thickness, and the second thickness of the second metal pattern is large enough to serve as a pad for performing a wire bonding process thereon.

10. The method according to claim 9, wherein the method further comprises: An etch stop material layer is formed between the first metal material layer and the second metal material layer; as well as Etch the etch stop material layer to form an etch stop layer. The first metal pattern has a thickness in the range of 1µm to 2µm, and the total thickness of the first metal pattern, the etch stop layer and the second metal pattern is in the range of 4µm to 5µm.

11. A power semiconductor device, comprising: A substrate with edges; An insulating layer disposed above the substrate; A metal layer disposed above the insulating layer and comprising a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, the second portion being disposed further away from the edge of the substrate than the first portion, and the second portion being configured as a pad for performing a wire bonding process thereon; A coating layer disposed above the metal layer and having a third thickness greater than the second thickness, wherein a first portion of the metal layer is disposed between the edge of the substrate and the second portion of the metal layer; as well as A protective layer that covers the substrate, the insulating layer, the metal layer, and the coating layer.

12. The power semiconductor device of claim 11, wherein the first portion is spaced apart from the second portion.

13. The power semiconductor device of claim 11, wherein the coating layer has a honeycomb structure.

14. A power semiconductor device, comprising: A substrate with edges; A first insulating layer is disposed above the substrate; A second insulating layer is disposed above the first insulating layer; A metal layer disposed above the second insulating layer and comprising a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, the second portion being disposed further away from the edge of the substrate than the first portion, and the second thickness of the second portion being sufficiently large to serve as a pad for performing a wire bonding process thereon; A passivation layer is disposed above the second insulating layer and the metal layer; A coating layer disposed above the passivation layer and having a third thickness greater than the second thickness, wherein a first portion of the metal layer is disposed between the edge of the substrate and the second portion of the metal layer; as well as A protective layer covering the substrate, the first insulating layer, the second insulating layer, the metal layer, the passivation layer, and the coating layer.

15. A power semiconductor device, comprising: A substrate with edges; An insulating layer disposed above the substrate; A metal layer disposed above the insulating layer and comprising a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, and the second thickness of the second portion being sufficiently large to serve as a pad for performing a wire bonding process thereon, the second portion being spaced apart from the first portion and being disposed further away from the edge of the substrate than the first portion; A coating layer disposed above the metal layer and having a third thickness greater than the second thickness, wherein a first portion of the metal layer is disposed between the edge of the substrate and the second portion of the metal layer; as well as A protective layer that covers the substrate, the insulating layer, the metal layer, and the coating layer.

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