A preparation method for improving single particle performance of VDMOS

Abstract

This invention discloses a method for fabricating VDMOS single-event performance, belonging to the field of power semiconductor devices. This invention innovatively designs a buried oxide layer (BOX) in the VDMOS power chip. On one hand, this buried oxide layer BOX effectively reduces the amount of electron-hole pairs generated in the Si during single-event incidence, thereby improving the VDMOS power chip's resistance to single-event bombardment. On the other hand, the large number of electron-hole pairs generated during the single-event incidence path, under the action of a high electric field, results in electrons being rapidly collected by the drain end and holes being absorbed by the source and gate ends. The newly added buried oxide layer BOX blocks single-event incidence, providing significant hole charge blocking and mitigation. It also alters the hole charge collection path, ensuring all holes are absorbed at the bottom of the source region, preventing them from reaching the bottom of the gate and causing gate breakdown or parasitic transistor activation and burnout. This invention can improve the single-event performance of VDMOS power chips without adding any new process steps.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a method for preparing VDMOS single-particle devices. Background Technology

[0002] In recent years, with the rapid advancement of commercial satellite construction, the demand for radiation-resistant semiconductor chips has been continuously increasing. Chips must be able to withstand various ionizing radiations, high-energy particles, and cosmic rays in space for extended periods. Therefore, devices used in the aerospace field should possess resistance to TID (Total Ionizing Dose) and SEE (Single Event Effect).

[0003] In VDMOS devices, single-event effects mainly manifest in two forms: SEB (single event burnout) and SEGR (single event gaterupture). When a high-energy particle enters the VDMOS device, it ionizes upon collision with lattice atoms, generating a large number of electron-hole pairs. Under a fixed electric field, holes flow towards the source, while electrons are drawn away from the drain. A VDMOS device consists of an N+ source region, a Pwell body region, and an N- type drift region, inevitably containing a parasitic NPN transistor. When the source-drain current flows through the Pwell body region, a voltage drop occurs. When this voltage drop exceeds the turn-on voltage of the parasitic transistor's emitter junction, the transistor conducts and enters the amplification region. The resulting electrothermal positive feedback from the continuously increasing current causes single-event burnout. Meanwhile, single-event gaterupture, in power MOSFETs, refers to the destructive burning caused by heavy ions penetrating the gate dielectric layer, forming a conductive path within the layer—essentially gate oxide breakdown. Under the influence of an applied electric field, holes continuously accumulate below the Si-SiO2 gate oxide, thus forming a transient high electric field. When the critical electric field for gate oxide breakdown is reached, single-particle gate breakdown will occur.

[0004] Therefore, power chips with single-event immunity have become an urgent need in the current commercial aerospace industry. Summary of the Invention

[0005] The purpose of this invention is to provide a method for preparing VDMOS single-particle performance to solve the problems in the background art.

[0006] To address the aforementioned technical problems, this invention provides a method for preparing VDMOS single-particle performance, comprising: Fabricate power chip cells and terminals on a substrate and an epitaxial layer; Photolithography, implantation, and high-temperature oxidation annealing are performed on the VDMOS power chip to form a buried oxide layer BOX that enhances the single particle of VDMOS in order to suppress the generation of electron-hole pairs during single particle incident. Photolithography, implantation, and high-temperature annealing of P-wells are performed on the cell and terminal regions of the power chip to form the conventional withstand voltage of the withstand voltage rings of the cell and terminal regions. After forming the P-well, SiO2 dielectric field oxygen is grown in the cell region and terminal of the power chip to form the cell region and terminal of the VDMOS single-particle performance power chip. The gate oxide SiO2 dielectric is grown by oxidation, and the polycrystalline control region is deposited and etched to form a polycrystalline field plate that serves as the gate control terminal and the edge boost terminal in the middle of the VDMOS power chip, which plays a switching control role. N+ lithography and implantation are performed in the source region, and P+ lithography and implantation are performed in the body region to form the ohmic contact between the source and body ends of the VDMOS power chip. After the SiO2 dielectric layer PMD is fully deposited, photolithography and dry etching of the contact hole CT are performed to finally form the contact hole CT of the source control end and the body control end, and the metal layer is brought out. Metal deposition, photolithography, and etching are performed to form the metal bonding region between the gate and the source; then a passivation dielectric layer is chemically deposited, photolithographically etched, and etched to protect the chip. Finally, TiNiAg drain metal is sputtered onto the back of the wafer to complete the fabrication of the power chip that enhances the single-event performance of VDMOS.

[0007] In one embodiment, the buried oxide layer BOX is formed to the desired morphology through photolithography, implantation, and high-temperature oxidation. The thickness of the buried oxide layer BOX is 0.1 μm to 0.4 μm, and the width is greater than 1 μm. The implanted impurity of the buried oxide layer BOX is O. + The implantation energy is 150keV~200keV, and the implantation dose is 1E17~2E18 ions / cm². The annealing temperature of the buried oxide layer BOX is 1300°C~1400°C to repair lattice damage and eliminate amorphization and defects caused by implantation. At the same time, the silicon atoms in the oxygen-rich region react chemically with oxygen atoms to form stoichiometric silicon dioxide SiO2.

[0008] In one embodiment, the P-well design of the cell and terminal is carried out by photolithography followed by P-well implantation. The implanted impurity of the P-well is one or more P-type impurities of B / BF2 / BF3. The implantation energy of the P-well is 50keV~100keV, and the implantation dose is 1E13~5E14 ions / cm², forming the cell and terminal in one step.

[0009] In one embodiment, the thickness of the SiO2 dielectric field oxygen is 100nm~600nm, forming the cell region and terminal of the power chip.

[0010] In one embodiment, the thickness of the gate oxide SiO2 dielectric is 30 nm to 150 nm, and the thickness of the polycrystalline material is 0.35 μm to 1.0 μm.

[0011] In one embodiment, the N-type impurity implanted for N+ is one or more N-type impurities from As / P, the N-type impurity implantation energy is 40 keV~80 keV, and the implantation dose is 1E15-1E16 ions / cm²; the P-type impurity implanted for P+ is one or more impurities from B / BF2 / BF3, the P-type impurity implantation energy is 20 keV~60 keV, and the implantation dose is 1E15-5E15 ions / cm², forming an ohmic contact with the metal layer.

[0012] In one embodiment, the SiO2 dielectric layer PMD is grown by chemical deposition, the thickness of the SiO2 dielectric layer PMD is 0.6μm~0.8μm, and the design size of the contact hole CT is 150nm~300nm, for the metal layer to contact.

[0013] In one embodiment, the thickness of the metal is 4μm~6μm, and the gate control terminal, source control terminal, and body control terminal of the VDMOS power chip are led out from the contact hole for subsequent bonding; at the same time, the thickness of the passivation medium is 0.5μm~1.0μm, which completes the device isolation and protection, and the passivation medium is SiO2 or SiO2+Si3N4.

[0014] In one embodiment, the thickness of the drain metal TiNiAg is 0.1 μm to 2 μm.

[0015] This invention provides a method for preparing VDMOS single-particle performance, which has the following beneficial effects: (1) No new manufacturing processes were introduced; (2) Innovatively, a buried oxide layer BOX was proposed to be fabricated in VDMOS power chip. The number of electron-hole pairs generated on the single-event incident path was greatly reduced. At the same time, the changes in the current-free characteristics and electric field distribution of the buried oxide layer BOX played a role in charge guidance, which solved the two problems of SEB and SEGR in single-event effect and improved the high reliability performance of VDMOS power chip. (3) The production method is conventional, simple, effective and operable. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a method for preparing VDMOS single-particle performance improved according to the present invention; Figure 2 This is a schematic diagram of fabricating an enhanced single-particle buried oxide layer (BOX) on the epitaxial layer of a substrate; Figure 3 This is a schematic diagram of P-well fabrication on the cell and terminal. Figure 4 This is a schematic diagram of the active and field regions of a power chip. Figure 5 This is a schematic diagram of the fabrication of the polycrystalline gate control terminal and the polycrystalline field plate; Figure 6 This is a schematic diagram of the ohmic contacts at the source and body ends of a power chip. Figure 7 This is a schematic diagram of the contact holes for the source control terminal and the body control terminal; Figure 8 This is a schematic diagram of the fabrication of the metal AlSiCu contact, the passivation layer SiO2 dielectric protection, and the back TiNiAg contact; Figure 9 This is a schematic diagram of a single-particle incident event without elevation. Figure 10 This is a schematic diagram of single-particle lifting incident according to the present invention. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for fabricating VDMOS single-particle performance according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0018] This invention provides a method for preparing VDMOS single-particle performance, the process of which is as follows: Figure 1 As shown, it includes the following steps: Step S11: Fabricate a buried oxide layer 4 BOX to enhance single-particle performance; Step S12: Create the cell region and the Pwell on the terminal. Step S13: Perform photolithographic etching of the active region on the power chip to fabricate field region oxidation; Step S14: Perform polycrystalline photolithography etching to form the polycrystalline gate control terminal and the polycrystalline field plate; Step S15: Photolithography implantation is used to form ohmic contacts with the metal at the source and body ends of the power chip. Step S16: Photolithographic etching of the contact holes for the deposited dielectric layer, source control terminal, and body control terminal; Step S17: Fabricate the front metal, passivation layer dielectric, and back drain metal.

[0019] The specific steps and processes are as follows: First, a buried oxide layer 4 BOX is fabricated on the epitaxial layer 2 (N-EPI) of the Si substrate 1 (N+SUB). The thickness of the buried oxide layer 4 BOX is 0.1μm~0.4μm, and the width is greater than 1μm. The implanted impurity of the buried oxide layer 4 BOX is O. + The injection energy is 150keV~200keV, and the injection dose is 1E17~2E18 ions / cm². The buried oxide layer 4 BOX requires an annealing temperature much higher than the conventional annealing temperature, 1300°C~1400°C, such as... Figure 2 The diagram shown is a cross-sectional view of the completed step.

[0020] After photolithography of the cell and terminal regions, P-well 5 is fabricated by implantation. The implanted impurities in the P-well 5 are one or more combinations of P-type impurities such as B / BF2 / BF3. The implantation energy of the P-well 5 is 50keV~100keV, and the implantation dose is 1E13~5E14 ions / cm². The P-well 5 of the cell and terminal regions is formed in one step. Figure 3 This is a cross-sectional view after completing this step.

[0021] A SiO2 dielectric field oxygen layer with a thickness of 100nm~600nm is grown on the surface to form the cell region and terminal of the power chip, such as... Figure 4 This is a cross-sectional view after completing this step.

[0022] A gate oxide SiO2 dielectric 7 with a thickness of 30nm~150nm is prepared on the surface, and a polycrystalline 8 control region with a thickness of 0.35μm~1.0μm is deposited and etched to form a polycrystalline field plate for the chip gate control terminal and edge enhancement terminal voltage withstand. Figure 5 The diagram shown is a cross-sectional view after this step is completed.

[0023] In P-well 5, source region 9 N+ implantation is performed, with one or more N-type impurities such as As / P implanted. The N-type impurity implantation energy is 40 keV~80 keV, and the implantation dose is 1E15-1E16 ions / cm². In the body region, 10 P+ implantation is performed, with one or more P-type impurities such as B / BF2 / BF3 implanted. The P-type impurity implantation energy is 20 keV~60 keV, and the implantation dose is 1E15-5E15 ions / cm², forming an ohmic contact with the metal layer. Figure 6 The diagram shown is a cross-sectional view after this step is completed.

[0024] A SiO2 dielectric layer 11 PMD (Pre-Metal Dielectric) was grown using chemical deposition to provide full coverage as an isolation layer. The thickness of the SiO2 dielectric layer 11 PMD (Pre-Metal Dielectric) was 0.6μm~0.8μm. Contact holes 12 were then formed using photolithography and dry etching. The contact hole design size was 150nm~300nm, providing contact for the metal layer. Figure 7 The diagram shown is a cross-sectional view after this step is completed.

[0025] Metal 13, with a thickness of 4μm~6μm, is prepared and used to bring out the gate control terminal, source control terminal, and body control terminal of the VDMOS power chip from the contact hole for subsequent bonding. Simultaneously, a passivation medium 14, with a thickness of 0.5μm~1.0μm, is deposited to complete device isolation and protection. The passivation medium is SiO2 or SiO2+Si3N4. Meanwhile, drain metal 15, TiNiAg, with a thickness of 0.1μm~2μm, is deposited on the back side, completing the entire process to improve the single-particle performance of the VDMOS. Figure 8 The diagram shown is a cross-sectional view.

[0026] The above main design methods have led to a method for fabricating power devices with improved VDMOS single-event performance. This achieves improved VDMOS power chip single-event performance without introducing any new processes or procedures. Figure 9 He Ru Figure 10In comparison, the innovative design of the buried oxide layer BOX is significant because the average ionization energy of Si (~3.6eV) is much lower than that of SiO2 (~18eV). Therefore, the number of electron-hole pairs generated by a single particle in SiO2 is only 1 / 5 that in Si, greatly reducing the number of electron-hole pairs generated on the single particle incident path and acting as a barrier to single particle incident. This effectively reduces the generation of electron-hole pairs during the single particle incident path. At the same time, the buried oxide layer BOX has almost no current path, which changes the electric field distribution and diverts the generated electron-hole charge current, thereby completely eliminating the SEB and SEGR problems in single-event effects, improving the single-event resistance of VDMOS power chips, and realizing a single-event immune VDMOS power chip.

[0027] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for preparing VDMOS single-particle performance, characterized in that, include: Fabricate power chip cells and terminals on a substrate and an epitaxial layer; Photolithography, implantation, and high-temperature oxidation annealing are performed on the VDMOS power chip to form a buried oxide layer BOX that enhances the single particle of VDMOS in order to suppress the generation of electron-hole pairs during single particle incident. Photolithography, implantation, and high-temperature annealing of P-wells are performed on the cell and terminal regions of the power chip to form the conventional withstand voltage of the withstand voltage rings of the cell and terminal regions. After forming the P-well, SiO2 dielectric field oxygen is grown in the cell region and terminal of the power chip to form the cell region and terminal of the VDMOS single-particle performance power chip. The gate oxide SiO2 dielectric is grown by oxidation, and the polycrystalline control region is deposited and etched to form a polycrystalline field plate that serves as the gate control terminal and the edge boost terminal in the middle of the VDMOS power chip, which plays a switching control role. N+ lithography and implantation are performed in the source region, and P+ lithography and implantation are performed in the body region to form the ohmic contact between the source and body ends of the VDMOS power chip. After the SiO2 dielectric layer PMD is fully deposited, photolithography and dry etching of the contact hole CT are performed to finally form the contact hole CT of the source control end and the body control end, and the metal layer is brought out. Metal deposition, photolithography, and etching are performed to form the metal bonding region between the gate and the source; then a passivation dielectric layer is chemically deposited, photolithographically etched, and etched to protect the chip. Finally, TiNiAg drain metal is sputtered onto the back of the wafer to complete the fabrication of the power chip that enhances the single-event performance of VDMOS.

2. The method for preparing VDMOS single-particle performance as described in claim 1, characterized in that, The buried oxide layer BOX is formed to the desired morphology through photolithography, implantation, and high-temperature oxidation. The thickness of the buried oxide layer BOX is 0.1 μm to 0.4 μm, and the width is greater than 1 μm. The implanted impurity of the buried oxide layer BOX is O. + The implantation energy is 150keV~200keV, and the implantation dose is 1E17~2E18 ions / cm². The annealing temperature of the buried oxide layer BOX is 1300°C~1400°C to repair lattice damage and eliminate amorphization and defects caused by implantation. At the same time, the silicon atoms in the oxygen-rich region react chemically with oxygen atoms to form stoichiometric silicon dioxide SiO2.

3. The method for preparing VDMOS single-particle performance as described in claim 1, characterized in that, The cell and terminal are designed with P-wells and fabricated by photolithography followed by P-well implantation. The implanted impurities in the P-wells are one or more P-type impurities of B / BF2 / BF3. The implantation energy of the P-wells is 50keV~100keV, and the implantation dose is 1E13~5E14 ions / cm². The cell and terminal are formed in one step.

4. The method for preparing VDMOS single-particle performance as described in claim 1, characterized in that, The thickness of the SiO2 dielectric oxygen field is 100nm~600nm, forming the cell region and terminal of the power chip.

5. The method for preparing VDMOS single-particle performance as described in claim 1, characterized in that, The thickness of the gate oxide SiO2 dielectric is 30nm~150nm, and the thickness of the polycrystalline material is 0.35μm~1.0μm.

6. The method for preparing VDMOS single-particle performance as described in claim 1, characterized in that, The N-type impurity implanted for N+ is one or more N-type impurities from As / P, with an implantation energy of 40 keV to 80 keV and an implantation dose of 1E15-1E16 ions / cm²; the P-type impurity implanted for P+ is one or more impurities from B / BF2 / BF3, with an implantation energy of 20 keV to 60 keV and an implantation dose of 1E15-5E15 ions / cm², forming an ohmic contact with the metal layer.

7. The method for preparing VDMOS single-particle performance as described in claim 1, characterized in that, The SiO2 dielectric layer PMD is grown by chemical deposition, and the thickness of the SiO2 dielectric layer PMD is 0.6μm~0.8μm. The design size of the contact hole CT is 150nm~300nm, which is used for contact with the metal layer.

8. The method for preparing VDMOS single-particle performance as described in claim 1, characterized in that, The metal has a thickness of 4μm to 6μm and leads out the gate control terminal, source control terminal, and body control terminal of the VDMOS power chip from the contact hole for subsequent bonding. Meanwhile, the passivation medium has a thickness of 0.5μm to 1.0μm to complete device isolation and protection. The passivation medium is SiO2 or SiO2+Si3N4.

9. The method for preparing VDMOS with improved single-particle performance as described in claim 1, characterized in that, The thickness of the drain metal TiNiAg is 0.1 μm to 2 μm.

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