Electronic devices

Abstract

An electronic device may include a semiconductor memory, and the semiconductor memory may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure, which includes a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers can be configured to produce antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0166562, filed on December 13, 2019, entitled “Electronic device,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] The patent document relates to a memory circuit or a memory device and its application in an electronic device or a system. Background Art

[0004] Recently, as electronic devices or appliances tend toward miniaturization, low power consumption, high performance, and multi-functions, etc., there is an increased demand for electronic devices capable of storing information in various electronic devices or appliances such as computers, portable communication devices, etc., and research and development of such electronic devices have been conducted. Examples of such electronic devices include electronic devices capable of storing data using a characteristic of switching between different resistance states according to an applied voltage or current, and can be implemented in various configurations, for example, RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), electric fuses, etc. Summary of the invention

[0005] The technology disclosed in this patent document includes storage circuits or storage devices and their applications in electronic devices or systems, as well as embodiments of various electronic devices, wherein the electronic devices include semiconductor memories that can improve the characteristics of variable resistance elements that exhibit different resistance states to store data.

[0006] In one aspect, an electronic device may include a semiconductor memory, and the semiconductor memory may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure, which includes a first ferromagnetic layer, a second ferromagnetic layer and a spacer layer, wherein the spacer layer is inserted between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, and the n non-magnetic layers and the n-1 magnetic layers are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers can be configured to produce antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer.

[0007] On the other hand, an electronic device may include a semiconductor memory, and the semiconductor memory may include: a magnetic tunnel junction (MTJ) structure, which includes a free layer, a pinned layer and a tunnel barrier layer, the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, and the tunnel barrier layer is inserted between the free layer and the pinned layer; and an intermediate layer, which is inserted between the tunnel barrier layer and the pinned layer, wherein any one or more of the free layer and the pinned layer may include a multilayer synthetic antiferromagnetic structure, the multilayer synthetic antiferromagnetic structure includes a spacer layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers alternately stacked, wherein n represents an odd number equal to or greater than 3, wherein the non-magnetic layer and the magnetic layer may have an fcc (111) structure, and the intermediate layer may have a bcc (001) structure.

[0008] These and other aspects, embodiments and associated advantages are described in more detail in the drawings, the description and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view showing an example of a variable resistance element.

[0010] Figure 2 is a cross-sectional view showing an example of a variable resistance element according to some embodiments of the disclosed technology.

[0011] Figure 3 is a cross-sectional view showing another example of a variable resistance element according to some embodiments of the disclosed technology.

[0012] Figure 4 is a cross-sectional view showing another example of a variable resistance element according to some embodiments of the disclosed technology.

[0013] Figure 5 is a cross-sectional view showing another example of a variable resistance element according to some embodiments of the disclosed technology.

[0014] Figure 6 : are graphs showing Ms*t values ​​of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0015] Figure 7 are graphs showing MH magnetization curves of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0016] Figure 8 are graphs showing Hshift values ​​of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0017] Fig. 9 are graphs showing exchange coupling strengths of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0018] Fig. 10A is a cross-sectional view showing an example of a memory device manufactured according to a method based on some embodiments of the disclosed technology.

[0019] Fig. 10B is a cross-sectional view showing another example of a memory device manufactured according to a method based on some embodiments of the disclosed technology.

[0020] Fig.11 is a diagram showing an example configuration of a microprocessor including a storage circuit according to an embodiment of the disclosed technology.

[0021] Fig.12 is a diagram of an example configuration of a processor including a storage circuit according to an embodiment of the disclosed technology.

[0022] Fig.13 is a diagram showing an example configuration of a system including a storage circuit according to an embodiment of the disclosed technology.

[0023] Fig.14 is a diagram of an example configuration of a data storage system including a storage circuit based on an embodiment of the disclosed technology.

[0024] Fig.15 is a diagram showing an example configuration of a memory system including a memory circuit according to an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0025] Various examples and implementations of the disclosed technology are described in detail below with reference to the accompanying drawings.

[0026] The drawings may not necessarily be drawn to scale, and in some cases, the scale of at least some of the substrates in the drawings may have been exaggerated to illustrate certain features of the described examples or implementations. When specific examples with two or more layers in a multi-layer substrate are presented in the drawings or the description, the relative positioning relationship of these layers or the order in which these layers are arranged reflects the specific implementation of the described or illustrated examples, and there may be different relative positioning relationships or the order in which these layers are arranged.

[0027] Figure 1 is a cross-sectional view showing an example of a variable resistance element.

[0028] refer to Figure 1An example of the variable resistance element 10 may include a magnetic tunnel junction (MTJ) structure including: a free layer 17 having a variable magnetization direction; a pinned layer 14 having a fixed magnetization direction; and a tunnel barrier layer 16 interposed between the free layer 17 and the pinned layer 14.

[0029] The free layer 17 may have a variable magnetization direction, which causes the MTJ structure to have a variable resistance value. The free layer 17 may also be referred to as a storage layer.

[0030] The pinned layer 14 may have a fixed magnetization direction that remains unchanged when the magnetization direction of the free layer 17 changes. For this reason, the pinned layer 14 may be referred to as a reference layer.

[0031] Depending on the voltage or current applied to the variable resistance element 10, the magnetization direction of the free layer 17 can be changed due to spin torque transfer. When the magnetization directions of the free layer 17 and the pinned layer 14 are parallel to each other, the variable resistance element 10 can be in a low resistance state, and this can indicate a digital data bit "0". On the contrary, when the magnetization directions of the free layer 17 and the pinned layer 14 are anti-parallel to each other, the variable resistance element 10 can be in a high resistance state, and this can indicate a digital data bit "1". That is, the variable resistance element 10 can be used as a memory cell to store a digital data bit based on the orientation of the free layer 17.

[0032] The free layer 17 and the pinned layer 14 may have a single-layer or multi-layer structure including a ferromagnetic material. The magnetization direction or polarity of the free layer 17 may change or flip between a downward direction and an upward direction. The magnetization direction of the pinned layer 14 may be fixed in a downward direction.

[0033] The tunnel barrier layer 16 may allow electrons to tunnel to change the magnetization direction of the free layer 17. The tunnel barrier layer 16 may include a dielectric oxide.

[0034] The variable resistance element 10 may further include a shift canceling layer 12 and a spacer layer 13 .

[0035] The shift compensation layer 12 can be used to offset or reduce the influence of the stray magnetic field generated by the pinned layer 14. The magnetization direction of the shift compensation layer 12 can be antiparallel to the magnetization direction of the pinned layer 14. The shift compensation layer 12 can have a single-layer or multi-layer structure including a ferromagnetic material.

[0036] The spacer layer 13 may be interposed between the pinned layer 14 and the shift canceling layer 12 and provide antiferromagnetic exchange coupling therebetween.

[0037] That is, the pinned layer 14 and the shift canceling layer 12 are antiferromagnetically exchange-coupled with each other through the spacer layer 13 to form a synthetic antiferromagnetic structure (SAF).

[0038] The variable resistance element 10 may further include one or more layers that perform various functions to improve the characteristics of the MTJ structure. For example, the variable resistance element 10 may further include: a lower layer 11 that is disposed below the MTJ structure; an intermediate layer 15 that is interposed between the tunnel barrier layer 16 and the pinning layer 14; and an upper layer 18 that is disposed above the MTJ structure.

[0039] In order to maintain strong antiferromagnetic exchange coupling between the pinned layer 14 and the shift compensation layer 12 forming the SAF structure, the characteristics of the spacer layer 13 should be fully ensured. In the variable resistance element 10, the spacer layer 13 may have a single-layer structure, which includes a conductive material such as Ru. However, the spacer layer 13 having a single-layer structure is very susceptible to process damage such as IBE damage, and therefore has a problem of rapid deterioration during scale-down. Therefore, due to the degradation of the characteristics of the spacer layer 13, the antiferromagnetic exchange coupling between the pinned layer 14 and the shift compensation layer 12 is weakened, which may lead to the degradation of the exchange coupling characteristics (including the exchange field (Hex)) of the variable resistance element 10.

[0040] The variable resistance element has such a structure that it exhibits different resistance states or resistance values, and can be switched between different resistance states in response to an applied bias (e.g., current or voltage). The resistance state of this variable resistance element can be changed by applying a voltage or current of sufficient size (i.e., threshold) in a data write operation. The different resistance states of the different resistance values ​​of the variable resistance element can be used to represent different data for data storage. Therefore, the variable resistance element can store different data according to the resistance state. The variable resistance element can be used as a storage unit. The storage unit may further include a selection element, which is coupled to the variable resistance element and controls access to the variable resistance element. Such a storage unit can be arranged in various ways to form a semiconductor memory.

[0041] In some embodiments, the variable resistance element can be implemented to include a magnetic tunnel junction (MTJ) structure, which includes: a free layer with a variable magnetization direction, a pinned layer with a fixed magnetization direction, and a tunnel barrier layer interposed therebetween. In response to a voltage or current of sufficient magnitude applied to the variable resistance element, the magnetization direction of the free layer can be changed to a direction parallel or antiparallel to the magnetization direction of the pinned layer. Therefore, the variable resistance element can switch between a low resistance state and a high resistance state, thereby storing different data based on different resistance states. The disclosed technology and its embodiments can be used to provide an improved variable resistance element that can meet or enhance the various characteristics required for the variable resistance element. For example, a variable resistance element is provided that can prevent the rapid degradation of the spacer layer to ensure scalability and improve exchange coupling characteristics by including a multilayer synthetic antiferromagnetic structure in the SAF structure included in the MTJ structure instead of a spacer layer having a single-layer structure.

[0042] Figure 2 is a cross-sectional view showing an example of a variable resistance element according to some embodiments of the disclosed technology.

[0043] In some embodiments, the variable resistance element 100 may include an MTJ structure including a free layer 170 having a variable magnetization direction, a pinned layer 140 having a fixed magnetization direction, and a tunnel barrier layer 160 interposed between the free layer 170 and the pinned layer 140 .

[0044] The free layer 170 may have one of different magnetization directions or one of different electron spin directions to switch the polarity of the free layer 170 in the MTJ structure, thereby causing a change in resistance value. In some embodiments, when a voltage or current signal (e.g., a drive current above a certain threshold) is applied to the MTJ structure, the polarity of the free layer 170 changes or flips. As the polarity of the free layer 170 changes, the free layer 170 and the pinned layer 140 have different magnetization directions or different electron spin directions, which allows the variable resistance element 100 to store different data or represent different data bits. The free layer 170 may also be referred to as a storage layer. The magnetization direction of the free layer 170 may be substantially perpendicular to the surfaces of the free layer 170, the tunnel barrier layer 160, and the pinned layer 140. In other words, the magnetization direction of the free layer 170 may be substantially parallel to the stacking direction of the free layer 170, the tunnel barrier layer 160, and the pinned layer 140. Therefore, the magnetization direction of the free layer 170 may change between a downward direction and an upward direction. The change in the magnetization direction of the free layer 107 may be caused by a spin transfer torque generated by an applied current or voltage.

[0045] The free layer 170 may have a single-layer or multi-layer structure, which may include a ferromagnetic material. For example, the free layer 170 may include an alloy based on at least one of Fe, Ni or Co, such as a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy or a Co-Fe-B alloy, or may include a metal stack such as Co / Pt or Co / Pd, etc.

[0046] The tunnel barrier layer 160 can allow the tunneling of electrons in both data reading and data writing operations. In a write operation for storing new data, a high write current can be directed through the tunnel barrier layer 160 to change the magnetization direction of the free layer 170, thereby changing the resistance state of the MTJ to write a new data bit. In a read operation, a low read current can be directed through the tunnel barrier layer 160 without changing the magnetization direction of the free layer 170 to measure the existing resistance state of the MTJ under the existing magnetization direction of the free layer 170, thereby reading the data bit stored in the MTJ. The tunnel barrier layer 160 may include a dielectric oxide such as MgO, CaO, SrO, TiO, VO or NbO, etc.

[0047] The pinned layer 140 may have a fixed magnetization direction that remains unchanged when the magnetization direction of the free layer 170 changes. The pinned layer 140 may be referred to as a reference layer. In some embodiments, the magnetization direction of the pinned layer 140 may be fixed in a downward direction. In some embodiments, the magnetization direction of the pinned layer 140 may be fixed in an upward direction.

[0048] The pinning layer 140 may have a single-layer or multi-layer structure, which may include a ferromagnetic material. For example, the pinning layer 140 may include an alloy based on at least one of Fe, Ni, or Co, such as a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, or a Co-Fe-B alloy, or may include a metal stack such as Co / Pt or Co / Pd.

[0049] In some embodiments of the disclosed technology, the pinned layer 140 may form an antiferromagnetic exchange coupling with the shift compensation layer 120 through the spacer layer 130 , which will be described below.

[0050] If voltage or current is applied to the variable resistance element 100, the magnetization direction of the free layer 170 may change due to spin torque transfer. In some embodiments, when the magnetization directions of the free layer 170 and the pinned layer 140 are parallel to each other, the variable resistance element 100 may be in a low resistance state, and this may indicate a digital data bit "0". Conversely, when the magnetization directions of the free layer 170 and the pinned layer 140 are anti-parallel to each other, the variable resistance element 100 may be in a high resistance state, and this may indicate a digital data bit "1". In some embodiments, the variable resistance element 100 may be configured to store a data bit "1" when the magnetization directions of the free layer 170 and the pinned layer 140 are parallel to each other, and to store a data bit "0" when the magnetization directions of the free layer 170 and the pinned layer 140 are anti-parallel to each other.

[0051] In some embodiments, the variable resistance element 100 may further include one or more layers that perform various functions to improve the characteristics of the MTJ structure. For example, the variable resistance element 100 may further include at least one of a buffer layer 110, a shift compensation layer 120, a spacer layer 130 (which may be a multi-layer composite layer), an intermediate layer 150, or a capping layer 180.

[0052] The buffer layer 110 may be disposed below other layers (e.g., the shift compensation layer 120) and on top of the substrate. The buffer layer 110 may be used as a buffer between the substrate and the layer disposed above the buffer layer 110. The buffer layer 110 may promote the crystal growth of the layer disposed above the buffer layer 110, thereby improving the characteristics of the layer disposed above the buffer layer 110. The buffer layer 110 may have a single-layer or multi-layer structure, which may include a metal, a metal alloy, a metal nitride or a metal oxide, or a combination thereof. In addition, the buffer layer 110 may be formed of or include a material having good compatibility with the bottom electrode (not shown) to solve the lattice constant mismatch between the bottom electrode and the layer disposed above the buffer layer 110. For example, the buffer layer 110 may include tantalum (Ta).

[0053] The cover layer 180 can protect the variable resistance element 100 and can be used as a hard mask for patterning the variable resistance element 100. In some embodiments, the cover layer 180 may include various conductive materials, such as metals. In some embodiments, the cover layer 180 may include a metallic material that has almost no pin holes or a small number of pin holes and has high resistance to wet and / or dry etching. In some embodiments, the cover layer 180 may include a metal, a nitride or an oxide or a combination thereof. For example, the cover layer 180 may include a noble metal, such as ruthenium (Ru).

[0054] In some embodiments, the cover layer 180 may have a single layer or a multi-layer structure. For example, the cover layer 180 may have a multi-layer structure including an oxide, a metal, or a combination thereof. In some embodiments, the cover layer 180 may have a multi-layer structure including an oxide layer, a first metal layer, or a second metal layer.

[0055] The shift-compensation layer 120 can be used to offset or reduce the influence of the stray magnetic field generated by the pinned layer 104. Due to the presence and operation of the shift-compensation layer 120, the influence of the stray magnetic field of the pinned layer 140 can be reduced, and thus the bias magnetic field in the free layer 170 can be reduced. The shift-compensation layer 120 can invalidate the shift of magnetization inversion of the free layer 170 caused by the stray field generated by the pinned layer 140. The shift-compensation layer 120 can be a magnetic layer that generates magnetization to generate a magnetic field at the free layer 170 along a magnetization direction that is antiparallel to the magnetization direction of the pinned layer 140. In the embodiment, when the pinned layer 140 has a downward magnetization direction, the shift-compensation layer 120 can have an upward magnetization direction. Conversely, when the pinned layer 104 has an upward magnetization direction, the shift-compensation layer 120 can have a downward magnetization direction. The shift compensation layer 120 may be a ferromagnetic structure, and in certain embodiments, may have a single-layer or multi-layer structure, which may include one or more ferromagnetic materials.

[0056] A material layer (not shown) may be interposed between the pinned layer 140 and the shift compensation layer 120, which is used to address the lattice structure difference and lattice constant mismatch between the pinned layer 140 and the shift compensation layer 120. For example, the material layer may be amorphous and may include metal, metal nitride, or metal oxide.

[0057] In the described embodiment, the shift-compensating layer 120, the spacer layer 130, and the pinned layer 140 may form a multi-layer synthetic antiferromagnetic (Multi SAF) structure.

[0058] The spacer layer 130 may be a multi-composite layer, and may be interposed between the shift-compensating layer 120 and the pinning layer 140 and used as a buffer between the shift-compensating layer 120 and the pinning layer 140. The spacer layer 130 may be used to generate a strong antiparallel exchange coupling between adjacent ferromagnetic layers. The spacer layer 130 may have a multi-layer structure, which includes a first non-magnetic layer 130A, a first magnetic layer 130B, a second non-magnetic layer 130C, a second magnetic layer 130D, and a third non-magnetic layer 130E. The spacer layer 130 having a multi-layer structure may be more resistant to process damage and has a strong bearing capacity. Therefore, compared with Figure 1Compared with the case of a single-layer spacer shown in FIG. 1 , the spacer layer 130 can generate strong anti-parallel exchange coupling between adjacent ferromagnetic layers. According to this embodiment, the shift compensation layer 120 can be anti-ferromagnetically coupled with the first magnetic layer 130B through the first non-magnetic layer 130A, the first magnetic layer 130B can be anti-ferromagnetically coupled with the second magnetic layer 130D through the second non-magnetic layer 130C, and the second magnetic layer 130D can be anti-ferromagnetically coupled with the pinned layer 140 through the third non-magnetic layer 130E. Therefore, when the variable resistance element is scaled down, strong anti-parallel exchange coupling can be generated and scalability can be ensured.

[0059] In order to generate strong exchange coupling between adjacent ferromagnetic layers compared to a single spacer layer, the spacer layer 130 should include: n non-magnetic layers and n-1 magnetic layers alternately stacked, where n may be an odd number equal to or greater than 3. Therefore, each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers. In the embodiment, the spacer layer 130 may have a multi-layer structure including a first non-magnetic layer 130A, a first magnetic layer 130B, a second non-magnetic layer 130C, a second magnetic layer 130D, and a third non-magnetic layer 130E. Figure 2 In the illustrated embodiment, the spacer layer 130 shows three non-magnetic layers and two magnetic layers (eg, n is 3). However, Figure 2 The embodiments shown in are merely examples, and other embodiments are possible as long as n is an odd number equal to or greater than 3. For example, the spacer layer 130 may include 5 non-magnetic layers and 4 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 130 may include 7 non-magnetic layers and 6 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 130 may include 9 non-magnetic layers and 8 magnetic layers that are alternately stacked.

[0060] In this way, the variable resistance element 100 may include a spacer layer 130, which includes n non-magnetic layers 130A, 130C and 130E and n-1 magnetic layers 130B and 130D that are alternately stacked. According to the embodiment, each of the pinned layer 140, the n-1 magnetic layers 130B and 130D, and the shift compensation layer 120 can form a strong exchange coupling between them through three or more non-magnetic layers 130A, 130C and 130E. Therefore, the stable exchange coupling characteristics (including exchange field (Hex)) of the variable resistance element 100 can be ensured, and thus the rapid degradation of the exchange coupling characteristics during scaling down can be prevented.

[0061] In some embodiments, to form a Multi SAF structure and exhibit strong exchange coupling characteristics, the nonmagnetic layers 130A, 130C, and 130E may have an fcc (111) structure, and thus the magnetic layers 130B and 130D may have an fcc (111) structure.

[0062] In some embodiments, the non-magnetic layers 130A, 130C, and 130E may include Ru, Ir, Rh, or Cr, or a combination thereof. Preferably, the non-magnetic layers 130A, 130C, and 130E may include Ir or an alloy including Ir.

[0063] As described above, the shift-compensating layer 120 may be antiferromagnetically coupled to the first magnetic layer 130B through the first non-magnetic layer 130A, the first magnetic layer 130B may be antiferromagnetically coupled to the second magnetic layer 130D through the second non-magnetic layer 130C, and the second magnetic layer 130D may be antiferromagnetically coupled to the pinned layer 140 through the third non-magnetic layer 130E. Each of the layers that have been antiferromagnetically coupled may have magnetization directions that are antiparallel to each other. For example, the shift-compensating layer 120 may have a magnetization direction that is antiparallel to the magnetization direction of the first magnetic layer 130B, the first magnetic layer 130B may have a magnetization direction that is antiparallel to the magnetization direction of the second magnetic layer 130D, and the second magnetic layer 130D may have a magnetization direction that is antiparallel to the magnetization direction of the pinned layer 140. For example, when the pinned layer 140 has a downward magnetization direction, the shift-compensating layer 120 and the second magnetic layer 130D may have an upward magnetization direction, while the first magnetic layer 130B may have a downward magnetization direction. When the pinned layer 140 has an upward magnetization direction, the shift-compensating layer 120 and the second magnetic layer 130D may have a downward magnetization direction, while the first magnetic layer 130B may have an upward magnetization direction.

[0064] According to an embodiment including a Multi SAF structure, the pinned layer 140 and the second magnetic layer 130D may be strongly coupled in opposite directions, and the first magnetic layer 130B and the shift compensation layer 120 may be strongly coupled in opposite magnetization directions. As a result, the size dependence of the exchange coupling characteristics may be improved and the MTJ scalability may be ensured compared to the conventional SAF structure.

[0065] The Multi SAF structure includes an odd number of non-magnetic layers to form a strong antiferromagnetic coupling between the pinned layer 140 and the second magnetic layer 130D and between the first magnetic layer 130B and the shift compensation layer 120. Figure 1 Compared with the spacer layer of the reference numeral 10), this Multi SAF structure can prevent the degradation of exchange coupling characteristics and improve scalability. Figures 6 to 9 Let's describe it in more detail.

[0066] Figure 2 The relative positions of the pinning layer 140 and the displacement compensation layer 120 shown in FIG. 1 may be interchanged.

[0067] The intermediate layer 150 may be interposed between the tunnel barrier layer 160 and the pinned layer 140. The intermediate layer 150 may be disposed adjacent to the spacer layer 130 and the tunnel barrier layer 160. Since the spacer layer 130 includes the non-magnetic layers 130A, 130C, and 130E and the magnetic layers 130B and 130D having an fcc (111) structure, the intermediate layer 150 may be a texture decoupled from the spacer layer 130 and have a bcc (001) structure to improve magnetoresistance (MR).

[0068] In some embodiments, the intermediate layer 150 may include at least one of Co, Fe, Ni, B, or other noble metals, or may include a combination thereof.

[0069] exist Figure 2 In the embodiment, the free layer 170 may be formed above the pinned layer 140. In another embodiment, the free layer 170 may be formed below the pinned layer 140. This will refer to Figure 3 Give a description.

[0070] Figure 3 is a cross-sectional view showing another example of a variable resistance element based on some embodiments of the disclosed technology. The description will focus on Figure 2 The characteristics discussed differ from one another.

[0071] refer to Figure 3 , the variable resistance element 200 according to the embodiment may include a buffer layer 210 , a lower layer 220 , a free layer 230 , a tunnel barrier layer 240 , an intermediate layer 250 , a pinned layer 260 , a spacer layer 270 , a shift compensation layer 280 , and a capping layer 290 . Figure 3 The variable resistance element 200 shown in FIG. Figure 2 The difference between the variable resistance elements 100 shown is that: Figure 3 In the variable resistance element 200 shown, the pinned layer 260 is located above the free layer 230 .

[0072] In the described embodiment, the shift compensation layer 280, the spacer layer 270, and the pinning layer 260 may form a MultiSAF structure.

[0073] A spacer layer 270 may be inserted between the pinned layer 260 and the shift compensation layer 280, and the spacer layer 270 may be a multi-layer composite layer. The spacer layer 270 may have a multi-layer structure, which includes a first non-magnetic layer 270A, a first magnetic layer 270B, a second non-magnetic layer 270C, a second magnetic layer 270D, and a third non-magnetic layer 270E, and the multi-layer structure is used to generate a strong anti-parallel exchange coupling between adjacent ferromagnetic layers. The spacer layer 270 with a multi-layer structure can be more resistant to process damage and has a strong bearing capacity. Therefore, Figure 1 Compared to the case of a single-layer spacer shown in FIG. 1 , the spacer layer 270 can generate strong anti-parallel exchange coupling between adjacent ferromagnetic layers. According to this embodiment, the pinned layer 260 can be anti-ferromagnetically coupled to the first magnetic layer 270B through the first non-magnetic layer 270A, the first magnetic layer 270B can be anti-ferromagnetically coupled to the second magnetic layer 270D through the second non-magnetic layer 270C, and the second magnetic layer 270D can be anti-ferromagnetically coupled to the shift compensation layer 280 through the third non-magnetic layer 270E. Therefore, when the variable resistance element is scaled down, strong anti-parallel exchange coupling can be generated and scalability can be ensured.

[0074] In order to generate strong exchange coupling between adjacent ferromagnetic layers compared to the case of a single spacer layer, the spacer layer 270 should include n non-magnetic layers and n-1 magnetic layers alternately stacked. n may be an odd number of 3 or more. In the embodiment, the spacer layer 270 may have a multilayer structure including a first non-magnetic layer 270A, a first magnetic layer 270B, a second non-magnetic layer 270C, a second magnetic layer 270D, and a third non-magnetic layer 270E. Figure 3 In the illustrated embodiment, the spacer layer 270 shows three non-magnetic layers and two magnetic layers (eg, n is 3). However, Figure 3 The embodiments shown in are merely examples, and other embodiments are possible as long as n is an odd number equal to or greater than 3. For example, the spacer layer 270 may include 5 non-magnetic layers and 4 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 270 may include 7 non-magnetic layers and 6 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 270 may include 9 non-magnetic layers and 8 magnetic layers that are alternately stacked.

[0075] According to the embodiment, each of the pinned layer 260, the n-1 magnetic layers 270B and 270D, and the shift compensation layer 280 can form a strong exchange coupling therebetween through three non-magnetic layers 270A, 270C, and 370E or more non-magnetic layers. Therefore, the stable exchange coupling characteristics (including the exchange field (Hex)) of the variable resistance element 200 can be ensured, and thus the rapid degradation of the exchange coupling characteristics during scaling down can be prevented.

[0076] In some embodiments, to form a Multi SAF structure and exhibit strong exchange coupling characteristics, the nonmagnetic layers 270A, 270C, and 270E may have an fcc (111) structure, and thus the magnetic layers 270B and 270D may have an fcc (111) structure.

[0077] In some embodiments, the non-magnetic layers 270A, 270C, and 270E may include Ru, Ir, Rh, or Cr, or a combination thereof. Preferably, the non-magnetic layers 270A, 270C, and 270E may include Ir or an alloy including Ir.

[0078] The lower layer 220 may be used to improve the perpendicular magnetic anisotropy of the free layer 230. The lower layer 220 may have a single-layer or multi-layer structure, which may include metal, metal alloy, metal nitride, metal oxide, or a combination thereof.

[0079] The description of the buffer layer 210, the free layer 230, the tunnel barrier layer 240, the intermediate layer 250, the pinned layer 260, the spacer layer 270, the displacement compensation layer 280 and the capping layer 290 is similar to that of Figure 2 Those in the illustrated embodiments are substantially similar.

[0080] In this embodiment, the pinned layer 260, the spacer layer 270, and the shift compensation layer 280 may form a Multi SAF structure having strong antiferromagnetic coupling. Therefore, the size dependence of the exchange coupling characteristics may be improved, and the scalability of the MTJ may be ensured.

[0081] exist Figure 2 and Figure 3 In the embodiment shown, the pinned layer 140 or 260 forms a Multi SAF structure with the spacer layer 130 or 270 and the displacement compensation layer 120 or 280. However, there may be another embodiment in which the free layer forms a Multi SAF structure. Figure 4 and Figure 5 Describe this.

[0082] Figure 4 is a cross-sectional view showing another example of a variable resistance element based on some embodiments of the disclosed technology. The description will focus on Figure 2 The characteristics discussed differ from one another.

[0083] refer to Figure 4, the variable resistance element 300 according to the embodiment may include a buffer layer 310, a lower layer 320, a pinned layer 330, an intermediate layer 340, a tunnel barrier layer 350, a free layer 360, and a capping layer 370. The free layer 360 may include a first sublayer 362, a spacer layer 364, and a second sublayer 366. The first sublayer 362, the spacer layer 364, and the second sublayer 366 may be used for a Multi SAF structure. Figure 4 The variable resistance element 300 shown is Figure 2 The variable resistance element 100 shown is different in that the Figure 4 The variable resistance element 300 of the Multi SAF structure shown is a free layer 360 .

[0084] The spacer layer 364 (which may be a multi-layer composite layer) may include n non-magnetic layers and n-1 magnetic layers alternately stacked. n may be an odd number of 3 or more. In the embodiment, the spacer layer 364 may have a multi-layer structure including a first non-magnetic layer 364A, a first magnetic layer 364B, a second non-magnetic layer 364C, a second magnetic layer 364D, and a third non-magnetic layer 364E. Figure 4 In the illustrated embodiment, the spacer layer 364 shows three non-magnetic layers and two magnetic layers (eg, n is 3). However, Figure 4 The embodiments shown in are examples only, and other embodiments are possible as long as n is an odd number equal to or greater than 3. For example, the spacer layer 364 may include 5 non-magnetic layers and 4 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 364 may include 7 non-magnetic layers and 6 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 364 may include 9 non-magnetic layers and 8 magnetic layers that are alternately stacked.

[0085] In the described embodiment, the spacer layer 364 can be used to generate strong antiparallel exchange coupling between adjacent ferromagnetic layers. The spacer layer 364 with a multilayer structure can be more resistant to process damage and has a strong tolerance. Therefore, compared with the case of a single-layer spacer, the spacer layer 364 can generate strong antiparallel exchange coupling between adjacent ferromagnetic layers.

[0086] In this embodiment, the first sublayer 362 may be antiferromagnetically coupled to the first magnetic layer 364B through the first nonmagnetic layer 364A, the first magnetic layer 364B may be antiferromagnetically coupled to the second magnetic layer 364D through the second nonmagnetic layer 364C, and the second magnetic layer 364D may be antiferromagnetically coupled to the second sublayer 366 through the third nonmagnetic layer 364E. Therefore, when the variable resistance element is scaled down, strong anti-parallel exchange coupling may be generated and scalability may be ensured.

[0087] The first sublayer 362 and the second sublayer 366 may have a single-layer or multi-layer structure, which may contain a ferromagnetic material. For example, the first sublayer 362 and the second sublayer 366 may include an alloy based on at least one of Fe, Ni or Co, for example, a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy or a Co-Fe-B alloy, or may include a metal stack such as Co / Pt or Co / Pd, etc.

[0088] In the Multi SAF structure according to the embodiment, the first sublayer 362 that substantially contributes to MR may have a bcc (001) structure in order to improve MR. Therefore, the first sublayer 362, which is a magnetic layer close to the tunnel barrier layer 350, is crystallized along the bcc (001) direction, thereby ensuring sufficient exchange coupling energy and improving MR.

[0089] A material layer (not shown) for solving the lattice structure difference and lattice constant mismatch between the first sublayer 362 and the second sublayer 366 may be interposed between the first sublayer 362 and the second sublayer 366. For example, the material layer may be amorphous and may include metal, metal nitride, or metal oxide.

[0090] In some embodiments, in order to form a Multi SAF structure and exhibit strong exchange coupling characteristics, the non-magnetic layers 364A, 364C, and 364E may have an fcc (111) structure. In some embodiments, the magnetic layers 364B and 364D may have an fcc (111) structure.

[0091] In some embodiments, the non-magnetic layers 364A, 364C, and 364E may include Ru, Ir, Rh, or Cr, or a combination thereof. Preferably, the non-magnetic layers 364A, 364C, and 364E may include Ir or an alloy including Ir.

[0092] In the embodiment, since the free layer 360 forms a Multi SAF structure, the size dependency of the exchange coupling characteristic can be improved and the scalability of the MTJ can be ensured compared to the conventional SAF structure.

[0093] exist Figure 4 In the variable resistance element 300 shown, the free layer 360 is disposed above the pinned layer 330. In another embodiment, the free layer 360 may be disposed below the pinned layer 330. This will be referred to as Figure 5 Further description.

[0094] Figure 5is a cross-sectional view showing another example of a variable resistance element based on some embodiments of the disclosed technology. The description will focus on Figure 3 and Figure 4 The characteristics discussed differ from one another.

[0095] refer to Figure 5 , the variable resistance element 400 according to the embodiment may include a buffer layer 410, a lower layer 420, a free layer 430, a tunnel barrier layer 440, an intermediate layer 450, a pinned layer 460, a shift compensation layer 470, and a capping layer 480. The free layer 430 may include a first sublayer 432, a spacer layer 434, and a second sublayer 436. The first sublayer 432, the spacer layer 434, and the second sublayer 436 may be used for a Multi SAF structure. Figure 5 The variable resistance element 400 shown is Figure 4 The variable resistance element 300 shown is different in that Figure 5 In the variable resistance element 400 shown, the free layer 430 is disposed below the pinned layer 460. In addition, Figure 5 The variable resistance element 400 shown is Figure 3 The variable resistance element 200 shown is different in that Figure 5 In the resistance change element 400 shown, the free layer 430 forms a Multi SAF structure.

[0096] The spacer layer 434 may include n non-magnetic layers and n-1 magnetic layers alternately stacked. n may be an odd number of 3 or more. In the embodiment, the spacer layer 434 may have a multilayer structure including a first non-magnetic layer 434A, a first magnetic layer 434B, a second non-magnetic layer 434C, a second magnetic layer 434D, and a third non-magnetic layer 434E. Figure 5 In the illustrated embodiment, the spacer layer 434 shows three non-magnetic layers and two non-magnetic layers (eg, n is 3). However, Figure 5 The embodiments shown in are examples only, and other embodiments are possible as long as n is an odd number equal to or greater than 3. For example, the spacer layer 434 may include 5 non-magnetic layers and 4 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 434 may include 7 non-magnetic layers and 6 magnetic layers that are alternately stacked. In some embodiments, the spacer layer 434 may include 9 non-magnetic layers and 8 magnetic layers that are alternately stacked.

[0097] In the described embodiment, the spacer layer 434 can be used to generate strong antiparallel exchange coupling between adjacent ferromagnetic layers. The spacer layer 434 with a multilayer structure can be more resistant to process damage and has a strong bearing capacity. Therefore, compared with the case of a single-layer spacer, the spacer layer 434 can generate strong antiparallel exchange coupling between adjacent ferromagnetic layers.

[0098] In this embodiment, the first sublayer 432 may be antiferromagnetically coupled to the first magnetic layer 434B through the first nonmagnetic layer 434A, the first magnetic layer 434B may be antiferromagnetically coupled to the second magnetic layer 434D through the second nonmagnetic layer 434C, and the second magnetic layer 434D may be antiferromagnetically coupled to the second sublayer 436 through the third nonmagnetic layer 434E. Therefore, when the variable resistance element is scaled down, strong anti-parallel exchange coupling may be generated, and scalability may be ensured.

[0099] In some embodiments, in order to exhibit strong exchange coupling characteristics, the non-magnetic layers 434A, 434C, and 434E may have an fcc (111) structure. In some embodiments, the magnetic layers 434B and 434D may have an fcc (111) structure.

[0100] In the Multi SAF structure according to the embodiment, the second sublayer 436 that substantially contributes to MR may have a bcc (001) structure in order to improve MR. Therefore, the second sublayer 436, which is a magnetic layer close to the tunnel barrier layer 440, is crystallized along the bcc (001) direction, thereby ensuring sufficient exchange coupling energy and improving MR.

[0101] In the embodiment, since the free layer 430 forms a Multi SAF structure, the size dependency of the exchange coupling characteristics can be improved and the MTJ scalability can be ensured compared to the conventional SAF structure.

[0102] Will refer to Figures 6 to 9 The effects exhibited by the embodiment are described.

[0103] Figure 6 : are graphs showing Ms*t values ​​of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0104] exist Figure 6 , Ms represents saturation magnetization, t represents the thickness of the multilayer structure, and the arrow represents the magnetization direction in each magnetic layer (Co layer) included in the multilayer structure. Each multilayer structure is as follows:

[0105] (a) Co / [Pt / Co]5

[0106] (b)Co / [Ir / Co]5

[0107] (c)Co / [Ir / Co]3

[0108] (d)Co / [Ir / Co]1

[0109] In the multilayer structure, the number indicates the number of times the thin films are stacked. For example, Co / [Pt / Co]5 includes a Co layer and 5 Pt / Co layers disposed below the Co layer. In the multilayer structures (a) to (d), the Co layers have the same thickness as each other, and the Ir layers have the same thickness as each other.

[0110] refer to Figure 6 , in a multilayer structure including Pt (i.e., (a) Co / [Pt / Co]5), each magnetic layer may have a magnetization direction parallel to each other to show a large Ms*t value. In a multilayer structure including Ir represented by a dotted ellipse (i.e., (b) Co / [Ir / Co]5), the magnetization directions of two adjacent magnetic layers above and below the Ir layer may be antiparallel to each other, so that the magnetization moment of each magnetic layer may be offset, and the Ms*t value may be determined only as Figure 6 The difference in magnetizing moment of the upper two magnetic layers shown. Therefore, the Ms*t value of (b) Co / [Ir / Co]5 can show a smaller Ms*t value than that of (a) Co / [Pt / Co]5. As for (c) Co / [Ir / Co]3, although the number of [Ir / Co] layers is reduced compared to (b) Co / [Ir / Co]5, it shows an Ms*t value close to that of (b) Co / [Ir / Co]5. This may mean that strong antiferromagnetic coupling is formed between the adjacent Co layers (magnetic layers) above and below the Ir layer (non-magnetic layer). For (d) Co / [Ir / Co]1 including two Co layers and an Ir layer interposed therebetween, although the Co layers can be antiferromagnetically coupled to each other, the characteristics of the Ir single layer may be significantly degraded during the scaling down of the variable resistance element, which may cause the exchange field (Hex) to decrease rapidly.

[0111] Figure 7 are graphs showing MH magnetization curves of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0112] exist Figure 7, the horizontal axis represents the magnetic field intensity (H), and the vertical axis represents the magnetization intensity (M). Example 1 represents a variable resistance element including a Multi SAF structure including a shift compensation layer / first non-magnetic layer / first magnetic layer / second non-magnetic layer / second magnetic layer / third non-magnetic layer / pinning layer, Example 2 represents a variable resistance element including a Multi SAF structure including a shift compensation layer / first non-magnetic layer / first magnetic layer / second non-magnetic layer / pinning layer, and the comparative example represents a variable resistance element including a SAF structure including a shift compensation layer / spacer layer / pinning layer.

[0113] refer to Figure 7 , the Multi SAF structures according to Examples 1 and 2 show a steeper slope in the MH magnetization curve than the SAF structure according to the comparative example. Therefore, according to the embodiment, better perpendicular magnetic anisotropy characteristics can be exhibited.

[0114] Figure 8 are graphs showing Hshift values ​​of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0115] exist Figure 8 , the horizontal axis represents the size (diameter) of the variable resistance element, and the vertical axis represents the Hshift value. The example represents a variable resistance element including a Multi SAF structure including a shift compensation layer / first non-magnetic layer / first magnetic layer / second non-magnetic layer / second magnetic layer / third non-magnetic layer / pinning layer, and the comparative example represents a SAF structure including a shift compensation layer / spacer layer / pinning layer.

[0116] Hshift may be an indicator of how the magnetization reversal characteristics of the free layer are shifted due to the stray magnetic field originating from the intermediate layer and the pinned layer. In the SAF structure, if each magnetic layer does not form a complete antiferromagnetic coupling, the Hshift value may increase.

[0117] refer to Figure 8 In the Multi SAF structure according to the example, the shift compensation layer can be strongly antiferromagnetically coupled with the first magnetic layer through the first nonmagnetic layer, the first magnetic layer can be strongly antiferromagnetically coupled with the second magnetic layer through the second nonmagnetic layer, and the second magnetic layer can be strongly antiferromagnetically coupled with the pinned layer through the third nonmagnetic layer. Therefore, it can be seen that when the variable resistance element is scaled down, the Hshift value can be kept from increasing and scalability can be easily ensured.

[0118] Fig. 9 are graphs showing exchange coupling strengths of structures based on some embodiments of the disclosed technology and comparative examples, respectively.

[0119] exist Fig. 9 , the horizontal axis represents the size (diameter) of the variable resistance element, and the vertical axis represents the exchange field (Hex). The example represents a variable resistance element including a Multi SAF structure, which includes a shift compensation layer / first non-magnetic layer / first magnetic layer / second non-magnetic layer / pinning layer, and comparative examples 1 to 4 represent SAF structures, which include a shift compensation layer / spacer layer / pinning layer, wherein each spacer layer has a different thickness from each other. The first non-magnetic layer, the second non-magnetic layer, and the spacer layer are formed of or include the same material as each other. The thickness of the spacer layer of comparative examples 1 to 4 is as follows: comparative example 1 < comparative example 2 < comparative example 3 < comparative example 4. The thickness of the first non-magnetic layer and the second non-magnetic layer of the example is the same as the thickness of comparative example 3.

[0120] The exchange coupling strength characteristic is sensitive to the thickness of the spacer layer. When the thickness of the spacer layer is thick, the exchange coupling strength may deteriorate rapidly, and the exchange coupling strength may deteriorate more rapidly during scaling down of the variable resistance element.

[0121] refer to Fig. 9 , compared with Comparative Examples 1 to 4 (particularly compared with Comparative Example 3, which includes a spacer layer having the same thickness as the first non-magnetic layer and the second non-magnetic layer included in the example structure), the curve graph of the example has the smallest slope, and it can be seen that there is almost no degradation in the exchange coupling strength due to the size reduction. The dotted line represents the simulation characteristics when the thickness of the first non-magnetic layer and the second non-magnetic layer of the example is the same as the thickness of the spacer layer of Comparative Example 2. From the curve graph with the dotted line, it can also be confirmed that the Multi SAF structure according to the embodiment has significantly excellent scalability compared with Comparative Examples 1 to 4.

[0122] The semiconductor memory device as disclosed in this document may include a cell array of variable resistance elements 100, 200, 300, and 400. The semiconductor memory may further include various components such as lines, elements, etc. to drive or control each of the variable resistance elements 100, 200, 300, and 400. Fig. 10A and Fig. 10B This is explained by way of example. Fig. 10A and Fig. 10B In, it is explained Figure 2The variable resistance element 100 shown in FIG. Figures 3 to 5 Variable resistance elements 200, 300 and 400 are shown.

[0123] Fig. 10A sectional views for explaining an example of a memory device and an example of a method of manufacturing the memory device according to some embodiments of the disclosed technology.

[0124] refer to Fig. 10A , the memory device of this embodiment may include: a substrate 400; a lower contact 420 formed above the substrate 400; a variable resistance element 100 formed above the lower contact 420; and an upper contact 450 formed above the variable resistance element 100. For each variable resistance element 100, a specific structure (such as a switch or a switching circuit / element, for example, a transistor) for controlling access to a specific variable resistance element 100 may be provided above the substrate 400 to control the variable resistance element 100, wherein the switch may be opened to select the variable resistance element 100, or the switch may be closed to deselect the variable resistance element 100. The lower contact 420 may be provided above the substrate 400, and may couple the lower end of the variable resistance element 100 to a portion of the substrate 400, for example, as a drain of a transistor of a switching circuit for the variable resistance element 100. The upper contact 450 may be provided above the variable resistance element 100, and may couple the upper end of the variable resistance element 100 to a specific line (not shown), for example, a bit line. In Fig. 10A , two variable resistance elements 100 are shown as examples of elements in the array of the variable resistance elements 100 .

[0125] First, a substrate 400 in which a transistor is formed may be provided, and then a first interlayer dielectric layer 410 may be formed over the substrate 400. Then, a lower contact 420 may be formed by selectively etching the first interlayer dielectric layer 410 to form a hole H exposing a portion of the substrate 400, and filling the hole H with a conductive material. Then, a variable resistance element 100 may be formed by forming a material layer for the variable resistance element 100 over the first interlayer dielectric layer 410 and the lower contact 420, and selectively etching the material layer. The etching process for forming the variable resistance element 100 may include an ion beam etching (IBE) method having a strong physical etching characteristic. Then, a second interlayer dielectric layer 430 may be formed to cover the variable resistance element 100. Then, a third interlayer dielectric layer 440 may be formed over the variable resistance element 100 and the second interlayer dielectric layer 430 , and an upper contact 450 may be formed that passes through the third interlayer dielectric layer 440 and is coupled to an upper end of the variable resistance element 100 .

[0126] In the memory device according to this embodiment, all layers forming the variable resistance element 100 may have side walls aligned with each other. This is because the variable resistance element 100 is formed by an etching process using one mask.

[0127] Different from Fig. 10A In an embodiment of the present invention, a portion of the variable resistance element 100 may be patterned separately from other portions. Fig. 10B The process is shown in FIG.

[0128] Fig. 10B 1 is a cross-sectional view for explaining a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure. Fig. 10A The characteristics discussed differ from one another.

[0129] refer to Fig. 10B , the memory device based on this embodiment may include a variable resistance element 100, a sidewall of a portion of the variable resistance element 100 (eg, the buffer layer 110) is not aligned with sidewalls of other layers thereof. Fig. 10B As shown, the buffer layer 110 may have sidewalls aligned with the lower contacts 520 .

[0130] It can be manufactured by the following process Fig. 10B storage device in the .

[0131] First, a first interlayer dielectric layer 510 may be formed over the substrate 500, and then selectively etched to form a hole H exposing a portion of the substrate 500. Then, a lower contact 520 may be formed to fill the lower portion of the hole H. For example, the lower contact 520 may be formed by a series of processes: forming a conductive material to cover the resulting structure having the hole formed therein, and removing a portion of the conductive material by an etch-back process until the conductive material has a desired thickness. Then, a buffer layer 110 may be formed to fill the remaining portion of the hole H. For example, the buffer layer 110 may be formed by the following steps: forming a material layer for forming the buffer layer 110, which covers the resulting structure having the lower contact 520 formed therein, and then performing a planarization process, such as CMP (chemical mechanical planarization), until the top surface of the first interlayer dielectric layer 510 is exposed. Then, the remaining portion of the variable resistance element 100 may be formed by forming a material layer over the lower contact 520 and the first interlayer dielectric layer 510 , the material layer being used to form the remaining layers of the variable resistance element 100 except the buffer layer 110 .

[0132] Subsequent processes and Fig. 10A The process shown is essentially the same.

[0133] In this embodiment, the height to be etched once required to form the variable resistance element 100 can be reduced, which makes it possible to reduce the difficulty of the etching process.

[0134] Although the buffer layer 110 is buried in the hole H in this embodiment, other portions of the variable resistance element 100 may be buried as needed.

[0135] The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a range of devices or systems. Figures 11 to 15 Some examples of devices or systems implementing the memory circuits disclosed herein are provided.

[0136] Fig.11 is a diagram of an example configuration of a microprocessor including a storage circuit based on the disclosed technology.

[0137] refer to Fig.11 , the microprocessor 1000 may perform a series of processing tasks for controlling and adjusting the reception of data from various external devices, processing the data, and outputting the processing results to the external devices. The microprocessor 1000 may include a storage unit 1010, an operation unit 1020, and a control unit 1030, etc. The microprocessor 1000 may be various data processing circuits such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0138] The storage unit 1010 is a part that stores data in the microprocessor 1000, such as a processor, a register. The storage unit 1010 may include a data register, an address register, a floating point register, etc. In addition, the storage unit 1010 may include various registers. The storage unit 1010 may perform the following functions: temporarily storing data to be operated by the operation unit 1020, the result data of the operation, and the address where the data for performing the operation is stored.

[0139] The memory cell 1010 may include one or more of the semiconductor devices described above based on the embodiments. For example, the memory cell 1010 may include a multilayer synthetic antiferromagnetic (Multi SAF) structure including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer, wherein the spacer layer is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers may be configured to generate antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. In this way, the data storage characteristics of the memory cell 1010 may be improved. As a result, the operating characteristics of the microprocessor 1000 may be improved.

[0140] The operation unit 1020 may perform four arithmetic operations or logic operations according to the result of decoding the command by the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU) and the like.

[0141] The control unit 1030 may receive signals from the storage unit 1010 , the operation unit 1020 , and external devices of the microprocessor 1000 , perform extraction and decoding of commands, and control input and output of signals of the microprocessor 1000 , and execute processing represented by a program.

[0142] The microprocessor 1000 according to this embodiment may further include a cache memory unit 1040 that may temporarily store data to be input from an external device other than the storage unit 1010 or data to be output to an external device. In this case, the cache memory unit 1040 may exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0143] Fig.12 is a diagram of an example configuration of a processor including a storage circuit according to an embodiment of the disclosed technology.

[0144] refer to Fig.12, the processor 1100 can improve performance and realize multi-functions by including various functions in addition to the functions of a microprocessor, which performs tasks for controlling and adjusting a series of processes for receiving data from various external devices, processing data, and outputting processing results to external devices. The processor 1100 may include: a core unit 1110 used as a microprocessor, a cache memory unit 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various systems on chip (SoCs), such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0145] The core unit 1110 of this embodiment is operable to perform an arithmetic logic operation on data input from an external device, and may include a storage unit 1111 , an operation unit 1112 , and a control unit 1113 .

[0146] The storage unit 1111 is operable to store data in the processor 1100, such as a processor register or registers, etc. The storage unit 1111 may include a data register, an address register, a floating point register, etc. In addition, the storage unit 1111 may include various registers. The storage unit 1111 may perform the following functions: temporarily store data to be operated by the operation unit 1112, result data of the operation, and the address where the data for performing the operation is stored. The operation unit 1112 is configured to perform operations in the processor 1100. The operation unit 1112 may perform four arithmetic operations, logic operations, etc. according to the result of the control unit 1113 decoding the command. The operation unit 1112 may include at least one arithmetic logic unit (ALU), etc. The control unit 1113 may receive signals from the storage unit 1111, the operation unit 1112, and the external device of the processor 1100, perform extraction and decoding of commands, control the input and output of signals of the processor 1100, and perform processing represented by the program.

[0147] The cache memory unit 1120 is operable to temporarily store data to compensate for the difference in data processing speed between the core unit 1110 operating at a high speed and the external device operating at a low speed. The cache memory unit 1120 may include a main storage unit 1121, a secondary storage unit 1122, and a tertiary storage unit 1123. Typically, the cache memory unit 1120 includes a main storage unit 1121 and a secondary storage unit 1122, and may include a tertiary storage unit 1123 in the case where a high storage capacity is required. If necessary, the cache memory unit 1120 may include a greater number of storage units. That is, the number of storage units included in the cache memory unit 1120 may be changed according to the design. The speeds at which the main storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 store and distinguish data may be the same or different. In the case where the speeds of the respective storage units 1121, 1122, and 1123 are different, the speed of the main storage unit 1121 may be the largest. At least one of the main storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 of the cache memory unit 1120 may include one or more of the semiconductor devices described above based on the embodiments. For example, the cache memory unit 1120 may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer, wherein the spacer layer is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers may be configured to generate antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. In this way, the data storage characteristics of the cache memory unit 1120 can be improved. As a result, the operating characteristics of the processor 1100 can be improved.

[0148] Despite Fig.1211 shows that the main storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 are all configured inside the cache memory unit 1120, but it should be noted that the main storage unit 1121, the secondary storage unit 1122, and the tertiary storage unit 1123 of the cache memory unit 1120 can all be configured outside the core unit 1110, and the difference in data processing speed between the core unit 1110 and the external device can be compensated. In addition, it should be noted that the main storage unit 1121 of the cache memory unit 1120 can be set inside the core unit 1110, and the secondary storage unit 1122 and the tertiary storage unit 1123 can be configured outside the core unit 1110 to enhance the function of compensating for the difference in data processing speed. In another embodiment, the main storage unit 1121 and the secondary storage unit 1122 can be set inside the core unit 1110, and the tertiary storage unit 1123 can be set outside the core unit 1110.

[0149] The bus interface 1130 is operable to connect the core unit 1110 , the cache unit 1120 , and external devices, and allows efficient transfer of data.

[0150] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the above-described configuration of the core unit 1110. In the case where the processor 1100 includes a plurality of core units 1110, a main storage section 1121 of the cache memory unit 1120 may be configured in each core unit 1110 corresponding to the number of the plurality of core units 1110, and a secondary storage section 1122 and a tertiary storage section 1123 may be configured outside the plurality of core units 1110 in a manner of being shared through the bus interface 1130. The processing speed of the main storage section 1121 may be greater than the processing speeds of the secondary storage section 1122 and the tertiary storage section 1123. In another embodiment, the primary storage unit 1121 and the secondary storage unit 1122 may be configured in each core unit 1110 corresponding to the number of the plurality of core units 1110 , and the tertiary storage unit 1123 may be configured outside the plurality of core units 1110 in a manner shared through the bus interface 1130 .

[0151] The processor 1100 according to this embodiment may further include: an embedded storage unit 1140 that stores data; a communication module unit 1150 that can send data to an external device and receive data from an external device in a wired or wireless manner; a memory control unit 1160 that drives an external storage device; and a media processing unit 1170 that processes data processed in the processor 1100 or data input from an external input device, and outputs the processed data to an external interface device, etc. In addition, the processor 1100 may include a plurality of various modules and devices. In this case, the additional plurality of modules may exchange data with the core unit 1110 and the cache memory unit 1120 and exchange data with each other through the bus interface 1130.

[0152] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. Volatile memory may include DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory), and memory having functions similar to the above memories, etc. Non-volatile memory may include ROM (read-only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memory having similar functions.

[0153] The communication module unit 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, or both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, a wireless sensor network, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0154] The memory control unit 1160 manages and processes data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, such as IDE (Integrated Device Circuit), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC) and Compact Flash (CF) Card, etc.

[0155] The media processing unit 1170 may process data processed in the processor 1100 or data input from an external input device in the form of images, voices, and others, and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), and a high-definition multimedia interface (HDMI) controller, etc.

[0156] Fig.13 is a diagram showing an example configuration of a system including a storage circuit according to an embodiment of the disclosed technology.

[0157] refer to Fig.13 , the system 1200 as a device for processing data can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems operated using a processor, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a recorder, telematics, an audio-visual (AV) system, and a smart TV, etc.

[0158] The processor 1210 may decode input commands, process operations and comparisons for data stored in the system 1200, and control these operations. The processor 1210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single / multi-core processor, a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and the like.

[0159] The main memory device 1220 is a storage device that can temporarily store, call and execute program code or data from the auxiliary memory device 1230 when the program is executed, and can save the stored content even when the power is cut off. The main memory device 1220 may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure, which includes a first ferromagnetic layer, a second ferromagnetic layer and a spacer layer, wherein the spacer layer is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers may be configured to generate antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. In this way, the data storage characteristics of the main memory device 1220 can be improved. As a result, the operating characteristics of the system 1200 can be improved.

[0160] In addition, the main memory device 1220 may also include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type, etc., in which all contents are erased when the power is cut off. Different from this, the main memory device 1220 may not include the semiconductor device according to the embodiment, but may include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type, etc., in which all contents are erased when the power is cut off.

[0161] The auxiliary memory device 1230 is a memory device for storing program code or data. Although the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 is capable of storing a larger amount of data. The auxiliary memory device 1230 may include one or more of the above-mentioned semiconductor devices based on the embodiment. For example, the auxiliary memory device 1230 may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure, which includes a first ferromagnetic layer, a second ferromagnetic layer and a spacer layer, wherein the spacer layer is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers may be configured to generate antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. In this way, the data storage characteristics of the auxiliary memory device 1230 can be improved. As a result, the operating characteristics of system 1200 may be improved.

[0162] In addition, the auxiliary storage device 1230 may also include a data storage system (see Fig.14 1300), such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disk using both magnetism and optics, a solid state disk (SSD), a USB memory (Universal Serial Bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card. Different from this, the auxiliary memory device 1230 may not include the semiconductor device according to the embodiment, but may include a data storage system (see Fig.14 1300 in the reference numeral 1300), such as a magnetic tape, a magnetic disk, an optical laser disk, a magneto-optical disk utilizing both magnetic and optical properties, a solid-state disk (SSD), a USB memory (Universal Serial Bus memory), a Secure Digital (SD) card, a mini Secure Digital (mSD) card, a micro Secure Digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a Memory Stick card, a Smart Media (SM) card, a MultiMedia Card (MMC), an embedded MMC (eMMC), and a Compact Flash (CF) card.

[0163] The interface device 1240 can perform the exchange of commands and data between the system 1200 of this embodiment and the external device. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-computer interaction devices (HIDs) and communication devices, etc. The communication device may include a module that can be connected to a wired network, a module that can be connected to a wireless network, or may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, a wireless sensor network (Zigbee), a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0164] Fig.14 is a diagram of an example configuration of a data storage system including a storage circuit based on an embodiment of the disclosed technology.

[0165] refer to Fig.14 , the data storage system 1300 may include: a storage device 1310 having a non-volatile characteristic as a component for storing data; a controller 1320 for controlling the storage device 1310; an interface 1330 for connecting with an external device; and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disk read-only memory (CDROM), a digital versatile disk (DVD), and a solid state disk (SSD), etc., and may be a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (MSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0166] The storage device 1310 may include a nonvolatile memory that stores data semi-permanently. The nonvolatile memory may include ROM (Read Only Memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM).

[0167] The controller 1320 may control data exchange between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing operations such as processing a command input from the outside of the data storage system 1300 through the interface 1330.

[0168] The interface 1330 performs the exchange of commands and data between the data storage system 1300 and the external device. In the case where the data storage system 1300 is a card type, the interface 1330 can be compatible with the interface used in the following devices: such as USB memory (universal serial bus memory), secure digital (SD) card, mini secure digital (MSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC) and compact flash (CF) card, etc., or, it can be compatible with the interface used in a device similar to the above-mentioned device. In the case where the data storage system 1300 is a disk type, the interface 1330 can be compatible with the following interfaces: such as IDE (integrated device circuit), SATA (serial advanced technology attachment), SCSI (small computer system interface), eSATA (external SATA), PCMCIA (personal computer memory card international association) and USB (universal serial bus), etc., or, it can be compatible with an interface similar to the above-mentioned interface. The interface 1330 can be compatible with one or more interfaces having different types from each other.

[0169] The temporary storage device 1340 can temporarily store data according to the diversity and high performance of the interface with the external device, the controller and the system, so as to effectively transmit data between the interface 1330 and the storage device 1310. The temporary storage device 1340 for temporarily storing data may include one or more of the above-mentioned semiconductor devices based on the implementation. The temporary storage device 1340 may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure, which includes a first ferromagnetic layer, a second ferromagnetic layer and a spacer layer, wherein the spacer layer is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers may be configured to generate antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. In this way, the data storage characteristics of the storage device 1310 or the temporary storage device 1340 can be improved. As a result, the operation characteristics and data storage characteristics of the data storage system 1300 can be improved.

[0170] Fig.15 is a diagram showing an example configuration of a memory system including a memory circuit according to an embodiment of the disclosed technology.

[0171] refer to Fig.15 , the storage system 1400 may include: a memory 1410 having a non-volatile characteristic as a component for storing data; a memory controller 1420 controlling the memory 1410; and an interface 1430 for connecting with an external device, etc. The storage system 1400 may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (MSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0172] The memory 1410 for storing data may include one or more of the above-mentioned semiconductor devices based on the embodiments. For example, the memory 1410 may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure, which includes a first ferromagnetic layer, a second ferromagnetic layer and a spacer layer, wherein the spacer layer is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers may be configured to generate antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. In this way, the data storage characteristics of the memory 1410 can be improved. As a result, the operating characteristics and data storage characteristics of the storage system 1400 can be improved.

[0173] In addition, according to this embodiment, the memory 1410 may also include ROM (read-only memory) with non-volatile characteristics, NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM) and magnetic random access memory (MRAM), etc.

[0174] The memory controller 1420 may control data exchange between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing the following operations: processing a command input from the outside of the memory system 1400 through the interface 1430.

[0175] The interface 1430 performs the exchange of commands and data between the storage system 1400 and the external device. The interface 1430 may be compatible with interfaces used in the following devices: such as USB memory (Universal Serial Bus memory), secure digital (SD) card, mini secure digital (MSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC), compact flash (CF) card, etc., or may be compatible with interfaces used in devices similar to the above devices. The interface 1430 may be compatible with one or more interfaces having different types from each other.

[0176] The memory system 1400 according to the embodiment may further include a buffer memory 1440 for efficiently transmitting data between the interface 1430 and the memory 1410 according to the diversification and high performance of the interface with the external device, the memory controller, and the memory system. For example, the buffer memory 1440 for temporarily storing data may include one or more of the above-mentioned semiconductor devices based on the embodiment. The buffer memory 1440 may include a multi-layer synthetic antiferromagnetic (Multi SAF) structure, which includes a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer, wherein the spacer layer is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n-1 magnetic layers, which are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, wherein the n-1 magnetic layers and the n non-magnetic layers may be configured to generate antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer. By doing so, it is possible to improve the data storage characteristics of the buffer memory 1440. As a result, it is possible to improve the operation characteristics and data storage characteristics of the memory system 1400.

[0177] In addition, the buffer memory 1440 according to the present embodiment may further include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics, etc. Different from this, the buffer memory 1440 may not include the semiconductor device according to the embodiment, but may include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics, etc.

[0178] Based on the memory device disclosed in this document Figures 11 to 15 The features of the above examples of electronic devices or systems in the present invention can be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or portable computers, game consoles, smart TVs, TV set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, watches or other wearable devices with wireless communication capabilities.

[0179] Although the patent document contains many details, these details should not be interpreted as limitations on any invention scope or the scope that can be claimed, but rather as descriptions of specific features of specific embodiments of specific inventions. Certain features described in the context of different embodiments in this patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. Moreover, although the features may be described as working in certain combinations and even initially claimed in this way, one or more features of the combination may be deleted from the claimed combination in some cases, and the claimed combination may be directed to a variant of a sub-combination or a sub-combination.

[0180] Similarly, although operations are depicted in a particular order in the drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order or that all of the operations shown be performed in order to obtain the desired results. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0181] Only some implementations and examples are described. Other implementations, enhancements, and variations can be made based on what is described and illustrated in this patent document.

Claims

1. An electronic device comprising a semiconductor memory, wherein: The semiconductor memory comprises: a multilayer synthetic antiferromagnetic structure, the multilayer synthetic antiferromagnetic structure comprising a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer, the spacer layer being interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer includes n non-magnetic layers and n-1 magnetic layers, the n non-magnetic layers and the n-1 magnetic layers are arranged so that each of the n non-magnetic layers is alternately stacked with each of the n-1 magnetic layers, wherein n represents an odd number equal to or greater than 3, The first ferromagnetic layer, the second ferromagnetic layer and the n-1 magnetic layers form an antiferromagnetic exchange coupling through the n non-magnetic layers.

2. The electronic device according to claim 1, wherein: At least one of the n non-magnetic layers has an fcc (111) structure.

3. The electronic device according to claim 1, wherein: At least one of the n non-magnetic layers includes: Ru, Ir or Cr or a combination thereof.

4. The electronic device according to claim 1, wherein: At least one of the n-1 magnetic layers has an fcc (111) structure.

5. The electronic device according to claim 1, wherein: The first ferromagnetic layer and the second ferromagnetic layer have fixed magnetization directions that are antiparallel to each other.

6. The electronic device according to claim 1, wherein: The first ferromagnetic layer and the second ferromagnetic layer include a single-layer or multi-layer structure, and the first ferromagnetic layer and the second ferromagnetic layer include ferromagnetic materials.

7. The electronic device according to claim 1, wherein: The first ferromagnetic layer includes a pinned layer having a fixed magnetization direction, and the second ferromagnetic layer includes a shift-compensating layer configured to cancel or reduce a stray magnetic field generated by the pinned layer. 8 . The electronic device according to claim 1 , further comprising an intermediate layer adjacent to the spacer layer and having a bcc (001) structure.

9. The electronic device according to claim 8, wherein: The intermediate layer includes Co, Fe, Ni, B or a noble metal or a combination thereof.

10. The electronic device of claim 1, further comprising a material layer interposed between the first ferromagnetic layer and the second ferromagnetic layer and configured to resolve a lattice structure difference and a lattice constant mismatch between the first ferromagnetic layer and the second ferromagnetic layer.

11. The electronic device according to claim 9, wherein: At least one of the first ferromagnetic layer and the second ferromagnetic layer has a bcc (001) structure.

12. The electronic device according to claim 1, further comprising a microprocessor, the microprocessor comprising: a control unit, the control unit comprising an input port for receiving a signal including a command from an external device, and performing at least one of the following: extracting, decoding the command, or controlling a signal input from or a signal output to the microprocessor; an operation unit, the operation unit comprising an input port coupled to the control unit to receive the decoded command, so as to perform an operation based on the decoded command; and a storage unit coupled to the operation unit and configured to store data used to perform the operation, data corresponding to a result of performing the operation, or an address where data associated with the operation is stored, The semiconductor memory is a part of the storage unit in the microprocessor.

13. The electronic device according to claim 1, further comprising a processor, the processor comprising: a core unit configured to perform an operation corresponding to a command by using data based on a command input from an external device communicating with the processor; a cache memory unit coupled to the core unit and configured to store data used to perform the operation, data corresponding to a result of performing the operation, or an address of data on which the operation is performed; and a bus interface coupled between the core unit and the cache memory unit to transmit data between the core unit and the cache memory unit; Wherein, the cache memory unit includes the semiconductor memory.

14. The electronic device according to claim 1, further comprising a data storage system, the data storage system comprising: a storage device configured to store data and retain the stored data in the absence of power; a controller coupled to the storage device and configured to control data transmission to and from the storage device according to a command input from an external device; a temporary storage device coupled to the storage device and the controller and configured to temporarily store data transmitted between the storage device and the external device; and an interface configured to perform communication between at least one of the storage device, the controller, the temporary storage device, and the external device, Wherein, at least one of the storage device or the temporary storage device includes the semiconductor memory.

15. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: A magnetic tunnel junction structure, the magnetic tunnel junction structure comprising a free layer, a pinned layer and a tunnel barrier layer, the free layer having a changeable magnetization direction, the pinned layer having a fixed magnetization direction, and the tunnel barrier layer being interposed between the free layer and the pinned layer; and an intermediate layer interposed between the tunnel barrier layer and the pinning layer, wherein at least one of the free layer and the pinned layer comprises a multi-layer synthetic antiferromagnetic structure, the multi-layer synthetic antiferromagnetic structure comprising a first ferromagnetic layer, a second ferromagnetic layer and a spacer layer, the spacer layer being interposed between the first ferromagnetic layer and the second ferromagnetic layer, The spacer layer includes n non-magnetic layers and n-1 magnetic layers alternately stacked, wherein n represents an odd number equal to or greater than 3, The first ferromagnetic layer, the second ferromagnetic layer and the n-1 magnetic layers form an antiferromagnetic exchange coupling through the n non-magnetic layers. The non-magnetic layer and the magnetic layer have an fcc (111) structure, and the intermediate layer has a bcc (001) structure.

16. The electronic device according to claim 15, wherein: At least one of the n non-magnetic layers includes: Ru, Ir or Cr or a combination thereof.

17. The electronic device according to claim 15, wherein: The intermediate layer includes Co, Fe, Ni, B or a noble metal or a combination thereof.

18. The electronic device according to claim 15, wherein: At least one of the first ferromagnetic layer and the second ferromagnetic layer has a bcc (001) structure.

19. The electronic device of claim 15, further comprising a material layer interposed between the first ferromagnetic layer and the second ferromagnetic layer and configured to resolve a lattice structure difference and a lattice constant mismatch between the first ferromagnetic layer and the second ferromagnetic layer.

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