Electronic devices

Abstract

An electronic device may include a semiconductor memory, and the semiconductor memory may include: a magnetic tunnel junction (MTJ) structure, which includes a free layer, a pinned layer and a tunnel barrier layer, the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, and the tunnel barrier layer is inserted between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL), which includes a homogeneous material with Fe-O bonds.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0166407, filed on December 13, 2019, entitled “Electronic device,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] This patent document relates to a memory circuit or a memory device and its application in an electronic device or a system. Background Art

[0004] Recently, as electronic devices or appliances tend to be miniaturized, low-power, high-performance, and multifunctional, etc., there is an increasing demand for electronic devices that can store information in various electronic devices or appliances such as computers, portable communication devices, etc. Such electronic devices are being extensively researched and developed. Examples of such electronic devices include electronic devices that can store data using a characteristic of switching between different resistance states according to an applied voltage or current, and can be implemented in various configurations, for example, RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), electric fuses, etc. Summary of the invention

[0005] The technology disclosed in this patent document includes memory circuits or memory devices, and their applications in electronic devices or systems. The technology disclosed in this patent document also includes various embodiments of electronic devices including semiconductor memories that can improve the characteristics of variable resistance elements that exhibit different resistance states to store data.

[0006] According to one aspect of the present invention, an electronic device is provided, which includes a semiconductor memory. The semiconductor memory may include: a magnetic tunnel junction (MTJ) structure, which includes a free layer, a pinned layer and a tunnel barrier layer, the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, the tunnel barrier layer is inserted between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL), which includes a homogeneous material with an Fe-O bond.

[0007] According to another aspect of the present invention, an electronic device is provided, which includes a semiconductor memory. The semiconductor memory may include: a substrate; memory cells formed above the substrate, each memory cell including a magnetic layer and a thermal stability enhanced layer (TSEL) in contact with the magnetic layer; and a switching element formed above the substrate and coupled to the memory cells, respectively, to select or deselect the memory cells, wherein the TSEL may include a homogeneous material having an Fe-O bond and is configured to enhance a perpendicular magnetic anisotropy field.

[0008] According to another aspect of the present invention, a semiconductor memory is provided. The semiconductor memory may include: a free layer having a changeable magnetization direction; a pinned layer having a fixed magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe-O bond.

[0009] These and other aspects, embodiments and associated advantages are described in more detail in the detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view showing an example of a variable resistance element.

[0011] Figure 2 is a cross-sectional view showing an example of a variable resistance element based on some embodiments of the disclosed technology.

[0012] Figure 3 is a cross-sectional view showing another example of a variable resistance element based on some embodiments of the disclosed technology.

[0013] Figure 4 is a graph showing the perpendicular magnetic anisotropy field (Hk) as a function of Ms*t value for structures of embodiments and comparative examples based on the disclosed technology.

[0014] Figure 5 is a graph of X-ray photoelectron spectroscopy (XPS) showing the structures of some embodiments and comparative examples based on the disclosed technology.

[0015] Fig. 6A and Figure 6B is a graph showing normalized Kerr rotation angles as a function of applied magnetic field for structures based on some embodiments and comparative examples of the disclosed technology.

[0016] Figure 7 is a graph showing the damping constant as a function of the perpendicular magnetic anisotropy field (Hk) for structures based on some embodiments and comparative examples of the disclosed technology.

[0017] Figure 8 is a graph showing WER as a function of normalized Vw / Vc ratio for structures based on some embodiments and comparative examples of the disclosed technology.

[0018] Fig. 9A are cross-sectional views illustrating an example of a memory device based on some embodiments of the disclosed technology and an example method for manufacturing the memory device.

[0019] Fig. 9B is a cross-sectional view illustrating another example of a memory device and a method for manufacturing the memory device based on some embodiments of the disclosed technology.

[0020] Fig.10 is a diagram of an example configuration of a microprocessor including a memory circuit based on an embodiment of the disclosed technology.

[0021] Fig.11 is an example configuration diagram of a processor including a memory circuit based on an embodiment of the disclosed technology.

[0022] Fig.12 is a diagram of an example configuration of a system including a memory circuit based on an embodiment of the disclosed technology.

[0023] Fig.13 is a diagram of an example configuration of a data storage system including a memory circuit based on an embodiment of the disclosed technology.

[0024] Fig.14 is a diagram of an example configuration of a memory system including a memory circuit based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0025] Various examples and embodiments of the disclosed technology are described in detail below with reference to the accompanying drawings.

[0026] The drawings may not necessarily be drawn to scale, and in some cases, the scale of at least some of the substrates in the drawings may have been exaggerated to illustrate certain features of the examples or embodiments of the invention being described. When specific examples with two or more layers in a multilayer structure are presented in the drawings or the description, the relative positional relationship of the layers or the arrangement order of the layers shown reflects the specific embodiment of the example being described or illustrated, and there may be different relative positional relationships or the arrangement order of the layers.

[0027] It should be understood that the drawings are simplified schematic diagrams of the devices being described and may not include well-known details in order to avoid obscuring aspects of the invention.

[0028] It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the present invention.

[0029] Figure 1 is a cross-sectional view showing an example of the variable resistance element 10 .

[0030] refer to Figure 1 The variable resistance element 10 may include a magnetic tunnel junction (MTJ) structure including: a free layer 14 having a variable magnetization direction; a pinned layer 12 having a fixed magnetization direction; and a tunnel barrier layer 13 interposed between the free layer 14 and the pinned layer 12.

[0031] The free layer 14 may have a variable magnetization direction, which causes the MTJ structure to have a variable resistance value. The free layer 14 may also be referred to as a storage layer.

[0032] The pinned layer 12 may have a fixed magnetization direction that remains unchanged when the magnetization direction of the free layer 14 changes. For this reason, the pinned layer 12 may be referred to as a reference layer.

[0033] Depending on the voltage or current applied to the variable resistance element 10, the magnetization direction of the free layer 14 can be changed due to the spin torque transfer. When the magnetization directions of the free layer 14 and the pinned layer 12 are parallel to each other, the variable resistance element 10 can be in a low resistance state, and this can indicate a digital data bit "0". On the contrary, when the magnetization directions of the free layer 14 and the pinned layer 12 are anti-parallel to each other, the variable resistance element 10 can be in a high resistance state, and this can indicate a digital data bit "1". That is, the variable resistance element 10 can be used as a memory cell to store a digital data bit based on the orientation of the free layer 14.

[0034] The free layer 14 and the pinned layer 12 may each have a single layer or a multilayer structure. The free layer 14 and the pinned layer 12 may each be a ferromagnetic material or include a ferromagnetic material. The magnetization direction or polarity of the free layer 14 may change or flip between a downward direction and an upward direction. The magnetization direction of the pinned layer 12 may be fixed to a downward direction.

[0035] The tunnel barrier layer 13 may allow tunneling of electrons to change the magnetization direction of the free layer 14. The tunnel barrier layer 13 may include a dielectric oxide.

[0036] The variable resistance element 10 may further include one or more layers performing various functions to improve characteristics of the MTJ structure. For example, the variable resistance element 10 may further include a lower layer 11 disposed below the MTJ structure and an upper layer 15 disposed above the MTJ structure.

[0037] The upper layer 15 may include an oxide capping layer. Generally, MgO may be used as the oxide capping layer included in the upper layer 15.

[0038] In order to ensure the characteristics of the variable resistance element 10, the oxide capping layer should meet some requirements. That is, the oxide capping layer 1) should not increase the damping constant (α) of the free layer 14; 2) should not deteriorate the interface characteristics between the free layer 14 and the upper layer 15 and the interface characteristics between the free layer 14 and the tunnel barrier layer 13; 3) should not cause the dispersion and deterioration of the characteristics of the free layer 14, including the coercive force (Hc), the switching current (Ic) and the thermal stability (Δ); and 4) should minimize the parasitic resistance (Rpara) of the oxide to improve the magnetoresistance (MR).

[0039] MgO, which may be used as an oxide capping layer included in the upper layer 15, has a heterogeneous amorphous structure, and for this reason, the oxide layer including MgO may have limitations in maintaining thermal stability (Δ) when scaled down. In addition, characteristics including coercive force (Hc), switching current (Ic), and thermal stability (Δ) and the degree of dispersion of these characteristics may be highly dependent on the oxide capping layer formed on the free layer 14. Therefore, an oxide capping layer such as MgO may deteriorate the characteristics of the variable resistance element 10 including the MTJ structure.

[0040] The variable resistance element has such a structure that it exhibits different resistance states or resistance values, and can be switched between different resistance states in response to an applied bias (e.g., current or voltage). The resistance state of this variable resistance element can be changed by applying a voltage or current of sufficient size (i.e., threshold value) in a data write operation. The different resistance states of the different resistance values ​​of the variable resistance element can be used to represent different data for data storage. Therefore, the variable resistance element can store different data according to the resistance state. The variable resistance element can be used as a storage unit. The storage unit may further include a selection element, which is coupled to the variable resistance element and controls access to the variable resistance element. Such a storage unit can be arranged in various ways to form a semiconductor memory.

[0041] In some embodiments, the variable resistance element can be implemented to include a magnetic tunnel junction (MTJ) structure, which includes: a free layer with a variable magnetization direction, a pinned layer with a fixed magnetization direction, and a tunnel barrier layer interposed therebetween. In response to a voltage or current of sufficient magnitude applied to the variable resistance element, the magnetization direction of the free layer can be changed to a direction parallel or antiparallel to the magnetization direction of the pinned layer. Therefore, the variable resistance element can be switched between a low resistance state and a high resistance state to store different data based on different resistance states. The disclosed technology and embodiments thereof can be used to provide an improved variable resistance element that can meet or enhance the various characteristics required for the variable resistance element. The variable resistance element according to the invention disclosed in the present invention can improve the thermal stability of the free layer and the discreteness of the device characteristics. The variable resistance element according to the invention disclosed in the present invention can provide improved scalability and write error rate (WER).

[0042] Figure 2 is a cross-sectional view showing an example of a variable resistance element 100 based on some embodiments of the disclosed technology.

[0043] refer to Figure 2 The variable resistance element 100 may include an MTJ structure including: a free layer 107 having a variable magnetization direction; a pinned layer 104 having a fixed magnetization direction; and a tunnel barrier layer 106 interposed between the free layer 107 and the pinned layer 104 .

[0044] The free layer 107 may have one of different magnetization directions or one of different electron spin directions to switch the polarity of the free layer 107 in the MTJ structure, thereby causing a change in resistance value. In some embodiments, after a voltage or current signal (e.g., a drive current above a certain threshold) is applied to the MTJ structure, the polarity of the free layer 107 changes or flips. As the polarity of the free layer 107 changes, the free layer 107 and the pinned layer 104 have different magnetization directions or different electron spin directions, which allows the variable resistance element 100 to store different data or represent different data bits. The free layer 107 may also be referred to as a storage layer. The magnetization direction of the free layer 107 may be substantially perpendicular to the surfaces of the free layer 107, the tunnel barrier layer 106, and the pinned layer 104. In other words, the magnetization direction of the free layer 107 may be substantially parallel to the stacking direction of the free layer 107, the tunnel barrier layer 106, and the pinned layer 104. Therefore, the magnetization direction of the free layer 107 may change between a downward direction and an upward direction. The change in the magnetization direction of the free layer 107 may be caused by a spin transfer torque generated by an applied current or voltage.

[0045] The free layer 107 may have a single layer or a multilayer structure. The free layer 107 may include a ferromagnetic material. For example, the free layer 107 may include an alloy based on Fe, Ni or Co, for example, a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy or a Co-Fe-B alloy, or may include a metal stack, such as a stack of a cobalt layer and a platinum layer (Co / Pt stack) or a stack of a cobalt layer and a palladium layer (Co / Pd stack).

[0046] The tunnel barrier layer 106 can allow the tunneling of electrons in both data reading and data writing operations. In a write operation for storing new data, a high write current can be directed through the tunnel barrier layer 106 to change the magnetization direction of the free layer 107, thereby changing the resistance state of the MTJ to write a new data bit. In a read operation, a low read current can be directed through the tunnel barrier layer 106 without changing the magnetization direction of the free layer 107 to measure the existing resistance state of the MTJ under the existing magnetization direction of the free layer 107, thereby reading the data bit stored in the MTJ. The tunnel barrier layer 106 may include a dielectric oxide such as MgO, CaO, SrO, TiO, VO or NbO.

[0047] The pinned layer 104 may have a fixed magnetization direction that remains unchanged when the magnetization direction of the free layer 107 changes. The pinned layer 104 may be referred to as a reference layer. In some embodiments, the magnetization direction of the pinned layer 104 may be fixed to a downward direction. In some embodiments, the magnetization direction of the pinned layer 104 may be fixed to an upward direction.

[0048] The pinning layer 104 may have a single layer or a multilayer structure. The pinning layer 104 may include a ferromagnetic material. For example, the pinning layer 104 may include an alloy based on Fe, Ni or Co, for example, a Fe-Pt alloy, a Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, a Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy or a Co-Fe-B alloy, or may include a metal stack, such as a stack of a cobalt layer and a platinum layer (Co / Pt stack) or a stack of a cobalt layer and a palladium layer (Co / Pd stack).

[0049] In addition, the pinned layer 104 may form an antiferromagnetic exchange coupling with the offset cancellation layer 102 via the spacer layer 103, which will be described below.

[0050] If a voltage or current is applied to the variable resistance element 100, the magnetization direction of the free layer 107 may change due to the spin torque transfer. In some embodiments, when the magnetization directions of the free layer 107 and the pinned layer 104 are parallel to each other, the variable resistance element 100 may be in a low resistance state, and this may indicate a digital data bit "0". On the contrary, when the magnetization directions of the free layer 107 and the pinned layer 104 are anti-parallel to each other, the variable resistance element 100 may be in a high resistance state, and this may indicate a digital data bit "1". In some embodiments, the variable resistance element 100 may be configured to store a data bit "1" when the magnetization directions of the free layer 107 and the pinned layer 104 are parallel to each other, and may store a data bit "0" when the magnetization directions of the free layer 107 and the pinned layer 104 are anti-parallel to each other.

[0051] In some embodiments, the variable resistance element 100 may further include at least one layer that performs various functions to improve the characteristics of the MTJ structure. For example, the variable resistance element 100 may further include at least one of a buffer layer 101, an offset cancellation layer 102, a spacer layer 103, an intermediate layer 105, a thermal stability enhancement layer (TSEL) 108, and a capping layer 109.

[0052] The buffer layer 101 may be disposed below the offset elimination layer 102. The buffer layer 101 may be disposed immediately below the offset elimination layer 102. The buffer layer 101 may serve as a buffer between a substrate and a layer disposed above the buffer layer 101. The buffer layer 101 may promote crystal growth in a layer disposed above the buffer layer 101 to improve the characteristics of the layer disposed above the buffer layer 101. The buffer layer 101 may have a single-layer or multi-layer structure. The buffer layer 101 may include a metal, a metal alloy, a metal nitride, or a metal oxide, or a combination thereof. In addition, the buffer layer 101 may be formed of or include a material having good compatibility with a bottom electrode (not shown) to resolve a lattice constant mismatch between the bottom electrode and the layer disposed above the buffer layer 101. For example, the buffer layer 101 may include tantalum (Ta).

[0053] The capping layer 109 can protect the variable resistance element 100 and can be used as a hard mask for patterning the variable resistance element 100. In some embodiments, the capping layer 109 may include various conductive materials, such as metals. In some embodiments, the capping layer 109 may include a metallic material that has almost no pin holes or a small number of pin holes and has high resistance to wet and / or dry etching. In some embodiments, the capping layer 109 may include a metal, a nitride, or an oxide, or may include a combination thereof. For example, the capping layer 109 may include a noble metal, such as ruthenium (Ru).

[0054] In some embodiments, the capping layer 109 may include a multi-layer structure including a first metal layer and a second metal layer including metals different from each other.

[0055] The offset cancellation layer 102 can offset or reduce the influence of the stray magnetic field generated by the pinned layer 104, thereby reducing the bias magnetic field in the free layer 107. The offset cancellation layer 102 can eliminate the magnetization inversion shift of the free layer 107 caused by the stray field generated by the pinned layer 104. The magnetization direction of the offset cancellation layer 102 can be antiparallel to the magnetization direction of the pinned layer 104. In one embodiment, when the pinned layer 104 has a downward magnetization direction, the offset cancellation layer 102 can have an upward magnetization direction. Conversely, when the pinned layer 104 has an upward magnetization direction, the offset cancellation layer 102 can have a downward magnetization direction. The offset cancellation layer 102 can be exchange-coupled with the pinned layer 104 via the spacer layer 103 to form a synthetic antiferromagnetic (SAF) structure. The offset cancellation layer 102 can have a single-layer or multi-layer structure. The offset cancellation layer 102 can include a ferromagnetic material.

[0056] A material layer (not shown) may be provided between the pinned layer 104 and the offset cancellation layer 102 to address the lattice structure difference and lattice constant mismatch between the pinned layer 104 and the offset cancellation layer 102. For example, the material layer may be amorphous and may include metal, metal nitride, or metal oxide.

[0057] The spacer layer 103 may be interposed between the offset cancellation layer 102 and the pinned layer 104. The spacer layer 103 may serve as a buffer between the offset cancellation layer 102 and the pinned layer 104. The spacer layer 103 may implement antiferromagnetic exchange coupling between the pinned layer 104 and the offset cancellation layer 102. The spacer layer 103 may include a noble metal, such as ruthenium (Ru).

[0058] Figure 2 The relative positions of the pinned layer 104 and the offset cancellation layer 102 shown may be interchanged.

[0059] The intermediate layer 105 may be interposed between the tunnel barrier layer 106 and the pinned layer 104. The intermediate layer 105 may be a magnetic layer closest to the tunnel barrier layer 106. The intermediate layer 105 may have a body-centered cubic (bcc 001) structure to improve magnetoresistance (MR).

[0060] In some embodiments, the intermediate layer 105 may include Co, Fe, Ni, B, other precious metals, or combinations thereof. In some embodiments, the intermediate layer 105 may include a FeCoB alloy, i.e., a Fe and Co alloy containing boron. In one embodiment, both the free layer and the intermediate layer may include a FeCoB alloy.

[0061] The thermal stability enhancement layer (TSEL) 108 can improve the characteristics of the free layer 107 and the degree of dispersion of these characteristics. For example, the TSEL 108 can improve the thermal stability and perpendicular anisotropy of the free layer 107. The TSEL 108 can improve the interface characteristics, ensure scalability, and improve the writing performance of the free layer 107. To this end, Figure 1 Unlike the oxide capping layer including MgO included in the illustrated upper layer 15, the TSEL 108 may include a homogeneous material having a greater number of Fe-O bonds.

[0062] In some embodiments, the TSEL 108 may include an alloy based on Fe, O, and X, for example, a Fe-OX alloy, where X may include Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Ir, Mg, Sr, Ba, or combinations thereof.

[0063] In some embodiments, the Fe—OX alloy included in the TSEL 108 may be an amorphous alloy.

[0064] In the case of forming a homogeneous Fe—OX alloy layer as the TSEL 108 , the homogeneous Fe—OX alloy layer may be formed through a physical deposition process (eg, a sputtering process) using an alloy target and an oxidation process.

[0065] In another embodiment, after the Fe layer is deposited and the X layer is deposited on the Fe layer, an oxidation process can be performed on the resulting structure. Then, a homogeneous Fe-OX layer can be formed by reaction via heat treatment. Here, the stacking order of the Fe layer and the X layer can be reversed.

[0066] In another embodiment, after a plurality of Fe layers and a plurality of X layers are alternately deposited, an oxidation process may be performed on the resulting structure. Then, a homogeneous Fe-OX layer may be formed by heat treatment.

[0067] In yet another embodiment, the homogeneous Fe—OX layer may be formed by a physical deposition process using a Fe target and an X target, for example, a co-sputtering process, and then performing an oxidation process.

[0068] In yet another embodiment, a homogeneous Fe—OX layer may be formed by performing an oxidation process on the free layer 107 including Fe and X and performing a heat treatment on the resulting structure. That is, Fe and X of the Fe—OX layer as the TSEL 108 may be derived from the material included in the free layer 107 .

[0069] In another embodiment, the TSEL 108 may include an alloy based on Fe, O, or X, such as a Fe-Ir-O-X alloy, where X may include Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Mg, Sr, Ba, or a combination thereof.

[0070] In some embodiments, the Fe—Ir—OX alloy included in the TSEL 108 may be a crystalline alloy.

[0071] In the case of forming a homogeneous Fe—Ir—OX alloy layer as the TSEL 108 , the homogeneous Fe—Ir—OX alloy layer may be formed by a physical deposition process (eg, a sputtering process) using an alloy target and an oxidation process.

[0072] In another embodiment, after depositing the Fe layer, depositing the Ir layer on the Fe layer, and depositing the X layer on the Ir layer, an oxidation process may be performed on the resulting structure. Then, a homogeneous Fe-Ir-OX layer may be formed by reaction via heat treatment. Here, the stacking order of the Fe layer, the Ir layer, and the X layer may be reversed.

[0073] In yet another embodiment, after a plurality of Fe layers, a plurality of Ir layers, and a plurality of X layers are alternately deposited, an oxidation process may be performed on the resulting structure. Then, a homogeneous Fe-Ir-OX layer may be formed by heat treatment.

[0074] In yet another embodiment, a homogeneous Fe—Ir—OX layer may be formed through a physical deposition process using a Fe target, an Ir target, and an X target, for example, a co-sputtering process, and then performing an oxidation process.

[0075] In yet another embodiment, a homogeneous Fe-Ir-OX layer may be formed by forming an Ir layer on the free layer 107 including Fe and X, performing an oxidation process, and performing a heat treatment on the resulting structure. That is, Fe and X of the Fe-Ir-OX layer as the TSEL 108 may be derived from the material included in the free layer 107.

[0076] In another embodiment, a homogeneous Fe-Ir-OX layer may be formed by sputtering Ir and oxidizing the free layer 107 containing Fe and X, and then performing a heat treatment. That is, Fe and X of the Fe-Ir-OX layer as the TSEL 108 may be derived from the material included in the free layer 107.

[0077] Since the Fe-O bonds in the variable resistance element 100 contribute to the perpendicular magnetic anisotropy field (Hk) of the free layer 107, it may be important to increase the number of Fe-O bonds to improve the perpendicular magnetic anisotropy field (Hk). According to an embodiment, the TSEL 108 can promote the perpendicular magnetic anisotropy field (Hk) by including a homogeneous material having more Fe-O bonds. In addition, the TSEL 108 can increase the number of Fe-O bonds in the variable resistance element 100 (for example, at the interface between the free layer 107 and the TSEL 108). Therefore, the thermal stability (Δ) and the perpendicular magnetic anisotropy field (Hk) of the free layer 107 can be enhanced, and the characteristics of the free layer 107, such as coercive force (Hc), switching current (Ic) and thermal stability (Δ), and the degree of discreteness of these characteristics can be improved. In addition, the interface characteristics between the TSEL 108 and the free layer 107 and the interface characteristics between the free layer 107 and the tunnel barrier layer 106 can be improved, thereby improving WER and write performance. Furthermore, since sufficient thermal stability can be exhibited when scaled down, the overall thickness of the variable resistance element 100 can be reduced, thereby ensuring scalability.

[0078] In some embodiments, a magnetic layer closest to the tunnel barrier layer 106 among magnetic layers included in the variable resistance element 100 may have a bcc (001) structure to improve MR.

[0079] exist Figure 2 In the embodiment, the free layer 107 may be formed above the pinned layer 104. In another embodiment, the free layer 107 may be formed below the pinned layer 104. This will refer to Figure 3 Give a description.

[0080] Figure 3 is a cross-sectional view showing another example of a variable resistance element based on some embodiments of the disclosed technology. This description will focus on Figure 2 The characteristics discussed differ from one another.

[0081] refer to Figure 3 According to the embodiment, the variable resistance element 200 may include a buffer layer 201, a lower layer 202, a thermal stability enhanced layer (TSEL) 203, a free layer 204, a tunnel barrier layer 205, an intermediate layer 206, a pinned layer 207, a spacer layer 208, an offset cancellation layer 209 and a capping layer 210. Figure 3 The variable resistance element 200 shown in FIG. Figure 2 The difference between the variable resistance elements 100 shown is that: Figure 3In the variable resistance element 200 shown, the pinned layer 207 is located above the free layer 204, and the TSEL 203 is located below the free layer 204. That is, in the variable resistance element 200, the pinned layer 207 formed above the free layer 204 can be antiferromagnetically exchange-coupled with the offset cancellation layer 209 via the spacer layer 208 to form a SAF structure, and the TSEL 203 can be formed below the free layer 204.

[0082] The lower layer 202 may improve the perpendicular magnetic anisotropy of the free layer 204. The lower layer 202 may have a single layer or a multi-layer structure. The lower layer 202 may include metal, metal alloy, metal nitride, metal oxide, or a combination thereof.

[0083] The description of the buffer layer 201, the free layer 204, the tunnel barrier layer 205, the intermediate layer 206, the pinned layer 207, the spacer layer 208, the offset cancellation layer 209 and the capping layer 210 will not be repeated because they are basically similar to those described above. Figure 2 The embodiment shown.

[0084] In this embodiment, the TSEL 203 may be disposed below the free layer 204 . Figure 1 The upper layer 15 shown in FIG. 2 may include a heterogeneous amorphous material such as MgO, while the TSEL 203 may include a homogeneous material having more Fe—O bonds.

[0085] In some embodiments, TSEL 203 may include an alloy based on Fe, O, or X, for example, a Fe-OX alloy, where X may include Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Ir, Mg, Sr, Ba, or a combination thereof. The Fe-OX alloy included in TSEL 203 may be an amorphous alloy.

[0086] In the case of forming a homogeneous Fe—OX alloy layer as the TSEL 203 , the homogeneous Fe—OX alloy layer may be formed through a physical deposition process (eg, a sputtering process) using an alloy target and an oxidation process.

[0087] In another embodiment, after the Fe layer is deposited and the X layer is deposited on the Fe layer, an oxidation process can be performed on the resulting structure. Then, a homogeneous Fe-OX layer can be formed by reaction via heat treatment. Here, the stacking order of the Fe layer and the X layer can be reversed.

[0088] In another embodiment, after a plurality of Fe layers and a plurality of X layers are alternately deposited, an oxidation process may be performed on the resulting structure. Then, a homogeneous Fe-OX layer may be formed by heat treatment.

[0089] In yet another embodiment, the homogeneous Fe—OX layer may be formed by a physical deposition process using a Fe target and an X target, for example, a co-sputtering process, and then performing an oxidation process.

[0090] In another embodiment, the TSEL 203 may include an alloy based on Fe, O, or X, such as a Fe-Ir-OX alloy, where X may include Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Mg, Sr, Ba, or a combination thereof. The Fe-Ir-OX alloy included in the TSEL 203 may be a crystalline alloy.

[0091] In the case of forming a homogeneous Fe—Ir—OX alloy layer as the TSEL 203 , the homogeneous Fe—Ir—OX alloy layer may be formed through a physical deposition process (eg, a sputtering process) using an alloy target and an oxidation process.

[0092] In another embodiment, after depositing the Fe layer, depositing the Ir layer on the Fe layer, and depositing the X layer on the Ir layer, an oxidation process may be performed on the resulting structure. Then, a homogeneous Fe-Ir-OX layer may be formed by reaction via heat treatment. Here, the stacking order of the Fe layer, the Ir layer, and the X layer may be reversed.

[0093] In another embodiment, after a plurality of Fe layers, a plurality of Ir layers, and a plurality of X layers are alternately deposited, an oxidation process may be performed on the resulting structure. Then, a homogeneous Fe-Ir-OX layer may be formed by heat treatment.

[0094] In yet another embodiment, a homogeneous Fe—Ir—OX layer may be formed through a physical deposition process (eg, a co-sputtering process) using a Fe target, an Ir target, and an X target, and then performing an oxidation process.

[0095] Since the Fe-O bonds in the variable resistance element 200 contribute to the perpendicular magnetic anisotropy field (Hk) of the free layer 204, it may be important to increase the number of Fe-O bonds to improve the perpendicular magnetic anisotropy field (Hk). According to an embodiment, the TSEL 203 can promote the perpendicular magnetic anisotropy field (Hk) by including a homogeneous material having more Fe-O bonds. In addition, the TSEL 203 can increase the number of Fe-O bonds in the variable resistance element 200 (for example, at the interface between the free layer 204 and the TSEL 203). Therefore, the thermal stability (Δ) and the perpendicular magnetic anisotropy field (Hk) of the free layer 204 can be enhanced, and the characteristics of the free layer 204, such as coercive force (Hc), switching current (Ic) and thermal stability (Δ), and the degree of discreteness of these characteristics can also be improved. In addition, the interface characteristics between the TSEL 203 and the free layer 204 and the interface characteristics between the TSEL 203 and the tunnel barrier layer 205 can be improved, thereby improving WER and write performance. Furthermore, since sufficient thermal stability can be exhibited when scaled down, the overall thickness of the variable resistance element 200 can be reduced, thereby ensuring the scalability of the device.

[0096] In some embodiments, a magnetic layer closest to the tunnel barrier layer 205 among magnetic layers included in the variable resistance element 200 may have a bcc (001) structure to improve MR.

[0097] Will refer to Figures 4 to 8 The effects according to the embodiment are described in detail.

[0098] Figure 4 is a graph showing the perpendicular magnetic anisotropy field (Hk) as a function of Ms*t value for structures of embodiments and comparative examples based on the disclosed technology.

[0099] exist Figure 4 In the equation, Ms represents the saturation magnetization and t represents the thickness of the free layer. Example 1 represents Figure 2 The variable resistance element 100 shown in FIG. 1 is a TSEL 108 including FeOX (X including Co or CoB). Example 2 represents Figure 2 The variable resistance element 100 shown, in which the TSEL 108 includes FeIrOX (X includes Co or CoB), and the comparative example represent a variable resistance element including a general MgO cap layer and not including the TSEL 108 such as in the variable resistance element 100 .

[0100] like Figure 4As shown, Examples 1 and 2 including TSEL 108 containing FeOX or FeIrOX show significantly improved perpendicular magnetic anisotropy field (Hk) compared to the comparative example including the MgO capping layer. The perpendicular magnetic anisotropy field (Hk) can be improved by increasing the number of Fe-O bonds by using TSEL 108 including FeOX or FeIrOX. Therefore, according to this embodiment, the thermal stability of the free layer can be significantly improved. For reference, the thermal stability can be expressed by equation (1):

[0101] [Equation 1]

[0102]

[0103] Where S represents the area of ​​the free layer, k B represents the Boltzmann constant, and T represents the temperature.

[0104] Referring to equation (1), since the thermal stability is proportional to the Hk value of the free layer, if the Hk value increases, the thermal stability also increases.

[0105] Figure 5 is a graph of X-ray photoelectron spectroscopy (XPS) showing the structures of some embodiments and comparative examples based on the disclosed technology.

[0106] exist Figure 5 In the example, Figure 2 The variable resistance element 100 shown in FIG. 1 , in which the TSEL 108 includes FeOX (X includes Co or CoB), and the comparative example represents a variable resistance element including a general MgO capping layer and not including the TSEL 108 such as in the variable resistance element 100 .

[0107] like Figure 5 As shown, according to the example including the TSEL 108 containing FeOX, the number of Fe-O bonds increases compared to the comparative example. Thus, by using the TSEL 108 containing FeOX, thermal stability and perpendicular magnetic anisotropy field are improved, thereby ensuring sufficient thermal stability when scaling down.

[0108] Fig. 6A and Figure 6B are graphs showing normalized Kerr rotation angles as a function of applied magnetic field for structures of some embodiments and comparative examples based on the disclosed technology, respectively.

[0109] exist Fig. 6A and Figure 6B, the horizontal axis represents the applied magnetic field (kOe), the vertical axis represents the normalized Kerr rotation angle (θ), and σHk represents the standard deviation. The Kerr rotation angle (θ) may be a value indicating the magnitude of the rotation angle when the polarization angle of light is reflected from the optically active magnetic medium. The Kerr rotation angle (θ) may be proportional to the magnetization intensity (M). Fig. 6A Indicates an example and Figure 6B Denotes a comparative example, wherein the example represents Figure 2 The variable resistance element 100 shown, in which the TSEL 108 includes FeOX (X includes Co or CoB), and the comparative example represent a variable resistance element including a general MgO capping layer and not including the TSEL 108 such as in the variable resistance element 100 .

[0110] like Fig. 6A and Figure 6B As shown, according to the example including the TSEL 108 containing FeOX, the free layer thereof exhibits excellent magnetization reversal property and has a smaller standard deviation of the perpendicular magnetic anisotropy field thereof than the comparative example including the MgO cap layer.

[0111] Figure 7 is a graph showing the damping constant as a function of the perpendicular magnetic anisotropy field (Hk) for structures based on some embodiments and comparative examples of the disclosed technology.

[0112] exist Figure 7 In the example, the horizontal axis represents the perpendicular magnetic anisotropy field (Hk) of the free layer, and the vertical axis represents the damping constant of the free layer. Figure 2 The variable resistance element 100 shown in FIG. 1 , in which the TSEL 108 includes FeOX (X includes Co or CoB), and the comparative example represents a variable resistance element including a general MgO capping layer and not including the TSEL 108 such as in the variable resistance element 100 .

[0113] like Figure 7 As shown, according to the example including the TSEL 108 containing FeOX, the damping constant can be significantly reduced and the perpendicular magnetic anisotropy field can be improved compared to the comparative example.

[0114] Figure 8 is a graph showing WER as a function of normalized Vw / Vc ratio for structures based on some embodiments and comparative examples of the disclosed technology.

[0115] exist Figure 8In the example 1, the horizontal axis represents the normalized Vw / Vc value, and the vertical axis represents WER. Vw represents the write voltage, Vc represents the critical voltage, and WER represents the write error rate. Figure 2 The variable resistance element 100 shown in FIG. 1, wherein the TSEL 108 comprises FeOX (X comprises Co or CoB), Example 2 represents Figure 2 The variable resistance element 100 shown, in which the TSEL 108 includes FeIrOX (X includes Co or CoB), and the comparative example represent a variable resistance element including a general MgO cap layer and not including the TSEL 108 such as in the variable resistance element 100 .

[0116] like Figure 8 As shown, Examples 1 and 2 including the TSEL 108 containing FeOX or FeIrOX show significantly improved WER and write performance compared to the comparative example including the MgO capping layer.

[0117] pass Figures 4 to 8 As shown in the results, a variable resistance element with significantly improved characteristics can be achieved by using a TSEL including a homogeneous material having more Fe-O bonds, compared to a comparative example including heterogeneous amorphous MgO. That is, according to one embodiment, the thermal stability (Δ) and the perpendicular magnetic anisotropy field (Hk) of the free layer can be enhanced, and the characteristics of the free layer, such as coercive force (Hc), switching current (Ic) and thermal stability (Δ), and the degree of discreteness of these characteristics can be improved. In addition, the interface characteristics can be improved, thereby improving WER and write performance. Moreover, since sufficient thermal stability can be exhibited when scaled down, the overall thickness of the variable resistance element can be reduced, thereby ensuring scalability.

[0118] Figure 3 The variable resistance element 200 shown may have Figure 2 The same effect is achieved as that of the variable resistance element 100 shown.

[0119] The semiconductor memory device as disclosed herein may include a cell array of variable resistance elements 100 and 200. The semiconductor memory may further include various components such as lines, elements, etc. to drive or control each variable resistance element 100 and 200. Fig. 9A and Fig. 9B To describe an example. Fig. 9A and Fig. 9B Although the Figure 2 Variable resistance element 100, but it should be understood that it is also possible to use Figure 3 The variable resistance element 200 in the embodiment replaces the variable resistance element 100.

[0120] Fig. 9Ais a cross-sectional view of an example of a memory device based on some embodiments of the disclosed technology.

[0121] refer to Fig. 9A , a memory device according to an embodiment may include: a substrate 400; lower contacts 420 formed over the substrate 400; corresponding variable resistance elements 100, each formed over a corresponding one of the lower contacts 420; and upper contacts 650, each formed over a corresponding variable resistance element 100. For each variable resistance element 100, a specific structure (such as a switch or a switching circuit / element, e.g., a transistor) for controlling access to a specific variable resistance element 100 may be provided over the substrate 400, thereby controlling the variable resistance element 100, wherein the switch may be turned on to select the variable resistance element 100, or the switch may be turned off to deselect the variable resistance element 100. Each lower contact 420 may be provided over the substrate 400, and may couple the lower end of the corresponding variable resistance element 100 to a corresponding portion of the substrate 400, e.g., as a drain of a transistor of a switching circuit for the variable resistance element 100. Each upper contact 650 may be disposed above a corresponding variable resistance element 100 and may couple an upper end of the variable resistance element 100 to a specific line (not shown), such as a bit line. Fig. 9A , although two variable resistance elements 100 are shown as an example of elements in the array of the variable resistance elements 100 , the number of the variable resistance elements 100 may be changed.

[0122] The method for manufacturing the device may include providing a substrate 400 in which a transistor is formed. Then, a first interlayer dielectric layer 410 may be formed over the substrate 400. The lower contact 420 may be formed by selectively etching the first interlayer dielectric layer 410 to form a plurality of spaced holes H, each of which penetrates the first interlayer dielectric layer 410, thereby exposing a corresponding portion of the substrate 400. The hole H may be filled with a conductive material. Then, the variable resistance element 100 may be formed by forming a material layer for the variable resistance element 100 over the first interlayer dielectric layer 410 and the lower contact 420. The material layer may be selectively etched to form a plurality of variable resistance elements 100. Each variable resistance element 100 may be located over the corresponding lower contact 420. The etching process for forming the variable resistance element 100 may include an ion beam etching (IBE) method having strong physical etching characteristics. Then, a second interlayer dielectric layer 430 may be formed to cover the space between the variable resistance elements 100 over the first dielectric layer 410. Then, a third interlayer dielectric layer 440 can be formed above the variable resistance element 100 and the second interlayer dielectric 430, and then an upper contact 450 can be formed using a process step similar to the above-mentioned step of forming the lower contact 420. The upper contact 450 passes through the third interlayer dielectric layer 440 and is coupled to the upper end of the corresponding variable resistance element 100.

[0123] exist Fig. 9A In the memory device of FIG. 1 , all layers forming the variable resistance element 100 may have sidewalls aligned with each other. This is because the variable resistance element 100 is formed by an etching process using a single mask.

[0124] Different from Fig. 9A In an embodiment of the present invention, a portion of each variable resistance element 100 may be patterned separately from other portions. Fig. 9B The process is shown in FIG.

[0125] Fig. 9B is a cross-sectional view for describing a memory device and a method for manufacturing the memory device according to another embodiment of the present disclosure. Fig. 9A The characteristics of different characteristics.

[0126] refer to Fig. 9B , a memory device according to an embodiment may include a variable resistance element 100, a sidewall of a portion of the variable resistance element 100 (eg, the buffer layer 101) being not aligned with sidewalls of other layers of the variable resistance element 100. Fig. 9B As shown, the buffer layer 101 may have sidewalls aligned with sidewalls of the lower contact 520 .

[0127] It can be manufactured by the following process Fig. 9B The structure shown in .

[0128] First, a first interlayer dielectric layer 510 may be formed over the substrate 500, and then selectively etched to form a plurality of holes H penetrating the first interlayer dielectric layer 510 to expose corresponding portions of the substrate 500. Then, a lower contact 520 may be formed by filling only the lower portion of the hole H. For example, the lower contact 520 may be formed by a series of processes: forming a conductive material to cover the resulting structure in which the hole is formed, and removing a portion of the conductive material by an etch-back process until the conductive material has a desired thickness. Then, a buffer layer 101 may be formed to fill the remaining portion of each hole H. For example, the buffer layer 101 may be formed by the following steps: forming a material layer for forming the buffer layer 101, which covers the resulting structure in which the lower contact 520 is formed, and then performing a planarization process such as CMP (chemical mechanical planarization) until the top surface of the first interlayer dielectric layer 510 is exposed. Then, the remaining portion of the variable resistance element 100 may be formed by forming a material layer for forming the remaining layers of the variable resistance element 100 except the buffer layer 101 over the lower contact 520 and the first interlayer dielectric layer 510 .

[0129] Subsequent processes and Fig. 9A The process shown is essentially the same.

[0130] In this embodiment, the height of one etching required to form the variable resistance element 100 can be reduced, which reduces the difficulty of the etching process.

[0131] Although the buffer layer 101 of the variable resistance element 100 is buried in the corresponding hole H in this embodiment, other portions of the variable resistance element 100 may be buried as needed.

[0132] The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a range of devices or systems. Figures 10 to 14 Some examples of devices or systems implementing the memory circuits disclosed herein are provided.

[0133] Fig.10 is a diagram of an example configuration of a microprocessor 1000 including a memory circuit based on the disclosed technology.

[0134] refer to Fig.10, the microprocessor 1000 may perform a series of processing tasks for controlling and adjusting receiving data from various external devices, processing the data, and outputting the processing results to the external devices. The microprocessor 1000 may include a storage unit 1010, an operation unit 1020, a control unit 1030, and a cache memory unit 1040. The microprocessor 1000 may be various data processing circuits such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0135] The storage unit 1010 is a part for storing data in the microprocessor 1000, such as a processor register. The storage unit 1010 may include a data register, an address register, a floating point register, etc. In addition, the storage unit 1010 may include various registers. The storage unit 1010 may perform the following functions: temporarily storing data to be operated by the operation unit 1020, result data from performing the operation, and the address where the data for performing the operation is stored.

[0136] The memory cell 1010 may include one or more of the above-mentioned semiconductor devices. For example, the memory cell 1010 may include: a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhancement layer (TSEL) including a homogeneous material having an Fe-O bond. In this way, the data storage characteristics of the memory cell 1010 may be improved. As a result, the operating characteristics of the microprocessor 1000 are improved.

[0137] The operation unit 1020 may perform four arithmetic operations or logic operations according to the result of decoding the command from the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU).

[0138] The control unit 1030 may receive signals from the storage unit 1010 , the operation unit 1020 , and external devices of the microprocessor 1000 , perform extraction and decoding of commands, and control input and output of signals of the microprocessor 1000 , and execute processing represented by a program.

[0139] The cache unit 1040 may temporarily store data to be input from or output to an external device other than the storage unit 1010. In this case, the cache unit 1040 may exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0140] Fig.11is an example configuration diagram of a processor including a memory circuit based on an embodiment of the disclosed technology.

[0141] refer to Fig.11 , the processor 1100 can improve performance and realize multi-functions by including various functions in addition to a microprocessor, which performs tasks for controlling and adjusting a series of processes for receiving data from various external devices, processing data, and outputting processing results to external devices. The processor 1100 may include: a core unit 1110 used as a microprocessor, a cache memory unit 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various systems on chip (SoCs), such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0142] The core unit 1110 of this embodiment is operable to perform an arithmetic logic operation on data input from an external device, and may include a storage unit 1111 , an operation unit 1112 , and a control unit 1113 .

[0143] The storage unit 1111 is operable to store data in the processor 1100 as a processor register or register, etc. The storage unit 1111 may include a data register, an address register, a floating point register, etc. In addition, the storage unit 1111 may include various registers. The storage unit 1111 may perform the following functions: temporarily store data to be operated by the operation unit 1112, the result data of the operation, and the address where the data for performing the operation is stored. The operation unit 1112 is configured to perform operations in the processor 1100. The operation unit 1112 may perform four arithmetic operations, logical operations, etc. according to the result of decoding the command from the control unit 1113. The operation unit 1112 may include at least one arithmetic logic unit (ALU), etc. The control unit 1113 may receive signals from the storage unit 1111, the operation unit 1112, and the external device of the processor 1100, perform extraction and decoding of commands, control the input and output of signals of the processor 1100, and perform processing represented by the program.

[0144] The cache memory unit 1120 is operable to temporarily store data to compensate for the difference in data processing speed between the core unit 1110 operating at a high speed and the external device operating at a low speed. The cache memory unit 1120 may include a primary storage part 1121, a secondary storage part 1122, and a tertiary storage part 1123. Generally, the cache memory unit 1120 includes the primary storage part 1121 and the secondary storage part 1122, and may include a tertiary storage part 1123 in the case where a high storage capacity is required. If necessary, the cache memory unit 1120 may include more storage parts. That is, the number of storage parts included in the cache memory unit 1120 may be changed according to the design. The speeds of storing and distinguishing data in the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 may be the same or different. In the case where the speeds of the respective storage parts 1121, 1122, and 1123 are different, the speed of the primary storage part 1121 may be the largest. At least one of the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory unit 1120 may include one or more of the above-mentioned semiconductor devices based on the embodiments of the present invention. For example, the cache memory unit 1120 may include: a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhancement layer (TSEL) including a homogeneous material having an Fe-O bond. In this way, the data storage characteristics of the cache memory unit 1120 can be improved. As a result, the operating characteristics of the processor 1100 are improved.

[0145] Despite Fig.111120, it is shown that the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 are all configured inside the cache memory unit 1120, but it should be noted that part or all of the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory unit 1120 can be configured outside the core unit 1110, and the difference in data processing speed between the core unit 1110 and the external device can be compensated. In addition, it should be noted that the primary storage part 1121 of the cache memory unit 1120 can be set inside the core unit 1110, and the secondary storage part 1122 and the tertiary storage part 1123 can be configured outside the core unit 1110 to enhance the function of compensating for the difference in data processing speed. In another embodiment, the primary storage part 1121 and the secondary storage part 1122 can be set inside the core unit 1110, and the tertiary storage part 1123 can be set outside the core unit 1110.

[0146] The bus interface 1130 is operative to connect the core unit 1110 , the cache unit 1120 , and external devices, and allows efficient transfer of data.

[0147] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the configuration of the core unit 1110 described above. In the case where the processor 1100 includes a plurality of core units 1110, a primary storage portion 1121 of the cache memory unit 1120 may be configured in each core unit 1110 corresponding to the number of the plurality of core units 1110, and a secondary storage portion 1122 and a tertiary storage portion 1123 may be configured outside the plurality of core units 1110 in a manner of being shared through the bus interface 1130. The processing speed of the primary storage portion 1121 may be greater than the processing speeds of the secondary storage portion 1122 and the tertiary storage portion 1123. In another embodiment, the primary storage part 1121 and the secondary storage part 1122 can be configured in each core unit 1110 corresponding to the number of multiple core units 1110, and the tertiary storage part 1123 can be configured outside the multiple core units 1110 in a manner shared through the bus interface 1130.

[0148] The processor 1100 according to this embodiment may further include: an embedded storage unit 1140 that stores data; a communication module unit 1150 that can send data to an external device and receive data from an external device in a wired or wireless manner; a memory control unit 1160 that drives an external storage device; and a media processing unit 1170 that processes data processed in the processor 1100 or data input from an external input device, and outputs the processed data to an external interface device, etc. The processor 1100 may include a plurality of various modules and devices. In this case, the added plurality of modules may exchange data with the core unit 1110 and the cache memory unit 1120 and with each other through the bus interface 1130.

[0149] The embedded storage unit 1140 may include not only a volatile memory but also a non-volatile memory. The volatile memory may include a DRAM (dynamic random access memory), a mobile DRAM, an SRAM (static random access memory), and a memory having functions similar to those of the above memories, etc. The non-volatile memory may include a ROM (read-only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), or a memory having similar functions.

[0150] The communication module unit 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, or a combination of the two. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0151] The memory control unit 1160 manages and processes data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, such as devices that can control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC) and Compact Flash (CF) Card, etc.

[0152] The media processing unit 1170 may process data processed in the processor 1100 or data input from an external input device in the form of images, voices, and other types, and output the data to an external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), and a high-definition multimedia interface (HDMI) controller, etc.

[0153] Fig.12 is a diagram of an example configuration of a system 1200 including a memory circuit based on an embodiment of the disclosed technology.

[0154] refer to Fig.12 , the system 1200 as a device for processing data can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems operated using a processor, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a recorder, telematics, an audio-visual (AV) system, and a smart TV, etc.

[0155] The processor 1210 may decode input commands, process operations (e.g., comparison, etc.) for data stored in the system 1200, and may control these operations. The processor 1210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single / multi-core processor, a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and the like.

[0156] The main memory device 1220 is a storage device that can temporarily store, call and execute program code or data from the auxiliary memory device 1230 when the program is executed, and can save the stored content even when the power is cut off. The main memory device 1220 may include: a magnetic tunnel junction (MTJ) structure, which includes a free layer, a pinned layer and a tunnel barrier layer, the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, and the tunnel barrier layer is inserted between the free layer and the pinned layer; and a thermal stability enhancement layer (TSEL) including a homogeneous material having an Fe-O bond. In this way, the data storage characteristics of the main memory device 1220 can be improved. As a result, the operating characteristics of the system 1200 are improved.

[0157] In addition, the main memory device 1220 may also include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type, etc., in which all contents are erased when the power is cut off. Different from this, the main memory device 1220 may not include the semiconductor device according to the embodiment, but may include a static random access memory (SRAM) and a dynamic random access memory (DRAM) of a volatile memory type, etc., in which all contents are erased when the power is cut off.

[0158] The auxiliary memory device 1230 is a memory device for storing program code or data. Although the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 is capable of storing a larger amount of data. Based on the embodiment, the auxiliary memory device 1230 may include one or more of the above-mentioned semiconductor devices. For example, the auxiliary memory device 1230 may include: a magnetic tunnel junction (MTJ) structure, which includes a free layer, a pinned layer and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, and the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhancement layer (TSEL), which includes a homogeneous material having an Fe-O bond. In this way, the data storage characteristics of the auxiliary memory device 1230 can be improved. As a result, the operating characteristics of the system 1200 are improved.

[0159] In addition, the auxiliary storage device 1230 may also include a data storage system (see Fig.131300), such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disk using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card. Different from this, the auxiliary memory device 1230 may not include the semiconductor device according to the embodiment, but may include a data storage system (see Fig.13 Reference mark 1300), such as a magnetic tape, a magnetic disk, an optical laser disk, a magneto-optical disk using both magnetic and optical properties, a solid state disk (SSD), a USB memory (Universal Serial Bus memory), a Secure Digital (SD) card, a mini Secure Digital (mSD) card, a micro Secure Digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a Memory Stick card, a Smart Media (SM) card, a MultiMedia Card (MMC), an embedded MMC (eMMC) and a Compact Flash (CF) card, etc.

[0160] The interface device 1240 can perform the exchange of commands and data between the system 1200 and the external device. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-computer interaction devices (HIDs), and communication devices, etc. The communication device may include a module that can be connected to a wired network, a module that can be connected to a wireless network, or may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0161] Fig.13 is a diagram of an example configuration of a data storage system 1300 including a storage circuit based on an embodiment of the disclosed technology.

[0162] refer to Fig.13, the data storage system 1300 may include: a storage device 1310, which has a non-volatile characteristic as a component for storing data; a controller 1320, which controls the storage device 1310; an interface 1330, which is used to connect with an external device; and a temporary storage device 1340, which is used to temporarily store data. The data storage system 1300 may be a disk type and a card type, the disk type such as a hard disk drive (HDD), a compact disk read-only memory (CDROM), a digital versatile disk (DVD), and a solid state disk (SSD), etc., and the card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (MSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0163] The storage device 1310 may include a nonvolatile memory that stores data semi-permanently. The nonvolatile memory may include ROM (Read Only Memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM).

[0164] The controller 1320 may control data exchange between the storage device 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing operations such as processing a command input from the outside of the data storage system 1300 through the interface 1330, and the like.

[0165] The interface 1330 performs the exchange of commands and data between the data storage system 1300 and the external device. In the case where the data storage system 1300 is a card type, the interface 1330 can be compatible with the interface used in the following devices: such as USB memory (universal serial bus memory), secure digital (SD) card, mini secure digital (MSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC) and compact flash (CF) card, or the interface 1330 can be compatible with the interface used in the device similar to the above-mentioned device. In the case where the data storage system 1300 is a disk type, the interface 1330 can be compatible with the following interfaces: such as IDE (integrated device electronics), SATA (serial advanced technology attachment), SCSI (small computer system interface), eSATA (external SATA), PCMCIA (personal computer memory card international association) and USB (universal serial bus), or can be compatible with an interface similar to the above-mentioned interface. The interface 1330 can be compatible with one or more interfaces of different types from each other.

[0166] The temporary storage device 1340 can temporarily store data, and effectively transmit data between the interface 1330 and the storage device 1310 according to the diversity and high performance of the interface with external devices, controllers and systems. The temporary storage device 1340 for temporarily storing data may include one or more of the above-mentioned semiconductor devices based on the embodiment. The temporary storage device 1340 may include: a magnetic tunnel junction (MTJ) structure, which includes a free layer, a pinned layer and a tunnel barrier layer, the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, and the tunnel barrier layer is interposed between the free layer and the pinned layer; and a thermal stability enhancement layer (TSEL) including a homogeneous material having an Fe-O bond. In this way, the data storage characteristics of the storage device 1310 or the temporary storage device 1340 can be improved. As a result, the operating characteristics and data storage characteristics of the data storage system 1300 are improved.

[0167] Fig.14 is a diagram of an example configuration of a memory system 1400 including a memory circuit based on an embodiment of the disclosed technology.

[0168] refer to Fig.14, the storage system 1400 may include: a memory 1410 having a non-volatile characteristic as a component for storing data; a memory controller 1420 that controls the memory 1410; and an interface 1430 for connecting with an external device, etc. The storage system 1400 may be a card type such as a solid state disk (SSD), a USB memory (Universal Serial Bus memory), a secure digital (SD) card, a mini secure digital (MSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, etc.

[0169] The memory 1410 for storing data may include one or more of the above-mentioned semiconductor devices based on the embodiments. For example, the memory 1410 may include: a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhancement layer (TSEL) including a homogeneous material having an Fe-O bond. In this way, the data storage characteristics of the memory 1410 can be improved. As a result, the operating characteristics and data storage characteristics of the storage system 1400 are improved.

[0170] In addition, according to this embodiment, the memory 1410 may also include ROM (read-only memory) with non-volatile characteristics, NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM) and magnetic random access memory (MRAM), etc.

[0171] The memory controller 1420 may control data exchange between the memory 1410 and the interface 1430. To this end, the memory controller 1420 may include a processor 1421 for performing the following operations: processing a command input from the outside of the memory system 1400 through the interface 1430.

[0172] The interface 1430 may perform the exchange of commands and data between the storage system 1400 and an external device. The interface 1430 may be compatible with interfaces used in the following devices: such as USB memory (universal serial bus memory), secure digital (SD) card, mini secure digital (MSD) card, micro secure digital (micro SD) card, secure digital high capacity (SDHC) card, memory stick card, smart media (SM) card, multimedia card (MMC), embedded MMC (eMMC), compact flash (CF) card, etc., or may be compatible with interfaces used in devices similar to the above devices. The interface 1430 may be compatible with one or more interfaces of different types from each other.

[0173] The storage system 1400 according to this embodiment may further include a buffer memory 1440, which is used to efficiently transmit data between the interface 1430 and the memory 1410 according to the diversification and high performance of the interface with the external device, the memory controller and the storage system. For example, the buffer memory 1440 for temporarily storing data may include one or more of the above-mentioned semiconductor devices based on the embodiment. The buffer memory 1440 may include: a magnetic tunnel junction (MTJ) structure, which includes a free layer, a pinned layer and a tunnel barrier layer, the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, and the tunnel barrier layer is disposed between the free layer and the pinned layer; and a thermal stability enhancement layer (TSEL) including a homogeneous material having an Fe-O bond. In this way, the data storage characteristics of the buffer memory 1440 can be improved. As a result, the operating characteristics and data storage characteristics of the storage system 1400 are improved.

[0174] In addition, the buffer memory 1440 according to the present embodiment may further include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics, etc. Different from this, the buffer memory 1440 may not include the semiconductor device according to the embodiment, but may include SRAM (static random access memory) and DRAM (dynamic random access memory) with volatile characteristics, etc., and phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), and magnetic random access memory (MRAM) with non-volatile characteristics, etc.

[0175] Based on the above-mentioned memory device disclosed in this document Figures 10 to 14The features of the examples of electronic devices or systems can be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or portable computers, game consoles, smart TVs, TV set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, watches or other wearable devices with wireless communication capabilities.

[0176] Although the patent document contains many details, these details should not be interpreted as limitations on any invention scope or the scope that can be claimed, but rather as descriptions of specific features of specific embodiments of specific inventions. Certain features described in the context of separate embodiments in this patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination, respectively. Moreover, although the features may be described above as acting in certain combinations and even initially claimed as such, one or more features may be deleted from the claimed combination in some cases, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0177] Similarly, although operations are depicted in a particular order in the drawings, this should not be understood as requiring that these operations should be performed in the particular order shown or in a sequential order or that all illustrated operations should be performed in order to obtain the desired results. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0178] Only some embodiments and examples are described. Other embodiments, enhancements, and variations can be made based on what is described and illustrated in this patent document.

[0179] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: A magnetic tunnel junction MTJ structure, comprising a free layer, a pinned layer and a tunnel barrier layer, wherein the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, and the tunnel barrier layer is interposed between the free layer and the pinned layer; and a thermal stability enhanced layer TSEL comprising a homogeneous material having Fe-O bonds, wherein the TSEL comprises an Fe-OX alloy, and X comprises Co, B, Mn, Cu, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Ir, Sr, Ba, or a combination thereof, The TSEL and the free layer are disposed separately from each other.

2. The electronic device according to claim 1, wherein: The semiconductor memory includes a synthetic antiferromagnetic SAF structure, the SAF structure is disposed above the tunnel barrier layer, and the TSEL is disposed below the free layer.

3. The electronic device according to claim 1, wherein: The semiconductor memory includes a synthetic antiferromagnetic SAF structure, the SAF structure is disposed below the tunnel barrier layer, and the TSEL is disposed above the free layer.

4. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: A magnetic tunnel junction MTJ structure, comprising a free layer, a pinned layer and a tunnel barrier layer, wherein the free layer has a variable magnetization direction, the pinned layer has a fixed magnetization direction, and the tunnel barrier layer is interposed between the free layer and the pinned layer; and a thermal stability enhanced layer TSEL comprising a homogeneous material having Fe-O bonds, wherein the TSEL comprises a Fe-Ir-OX alloy, and X comprises Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Mg, Sr, Ba, or a combination thereof, The TSEL and the free layer are disposed separately from each other.

5. The electronic device according to claim 1, in, The semiconductor memory further includes: an intermediate layer having a body-centered cubic (001) structure and interposed between the tunnel barrier layer and the pinning layer.

6. The electronic device according to claim 5, wherein: The intermediate layer includes Co, Fe, Ni, B, a noble metal or a combination thereof.

7. The electronic device according to claim 1, wherein: The semiconductor memory further comprises: an offset cancellation layer having a magnetization direction antiparallel to the pinned layer; and a spacer layer interposed between the pinning layer and the offset cancellation layer, The pinned layer and the offset cancellation layer form an antiferromagnetic exchange coupling via the spacer layer to form a synthetic antiferromagnetic SAF structure.

8. The electronic device according to claim 1, further comprising a data storage system comprising: a storage device configured to store data and retain the stored data in the absence of power; a controller coupled to the storage device and configured to control data transmission to and from the storage device according to a command input from an external device; a temporary storage device coupled to the storage device and the controller and configured to temporarily store data transferred between the storage device and the external device; and an interface configured to perform communication between at least one of the storage device, the controller, the temporary storage device and the external device, Wherein, at least one of the storage device or the temporary storage device includes the semiconductor memory.

9. The electronic device according to claim 1, further comprising a storage system comprising: a memory configured to store data and retain the stored data in the absence of power; a memory controller coupled to the memory and configured to control data transfer to and from the memory according to a command input from an external device; a buffer memory configured to temporarily store data moving between the memory and the external device; and an interface configured to perform communication between at least one of the memory, the memory controller, the buffer memory and the external device, Wherein, at least one of the memory or the buffer memory includes the semiconductor memory.

10. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: substrate; A memory cell formed above the substrate, each memory cell comprising a magnetic layer, a thermal stability enhancement layer TSEL in contact with the magnetic layer, a free layer with a changeable magnetization direction, a pinned layer with a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and switching elements formed over the substrate and respectively coupled to the memory cells to select or deselect the memory cells, wherein the TSEL comprises a homogeneous material having Fe-O bonds and is configured to enhance a perpendicular magnetic anisotropy field, wherein the TSEL comprises an Fe-OX alloy, and X comprises Co, B, Mn, Cu, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Ir, Sr, Ba, or a combination thereof, The TSEL and the free layer are disposed separately from each other.

11. The electronic device according to claim 10, wherein: Each storage unit includes: an offset cancellation layer having a magnetization direction antiparallel to the pinned layer; and a spacer layer interposed between the pinning layer and the offset cancellation layer, The pinned layer and the offset cancellation layer form an antiferromagnetic exchange coupling via the spacer layer to form a synthetic antiferromagnetic SAF structure.

12. The electronic device according to claim 11, wherein: The SAF structure is disposed above the tunnel barrier layer, and the TSEL is disposed below the free layer.

13. The electronic device according to claim 11, wherein: The SAF structure is disposed below the tunnel barrier layer, and the TSEL is disposed above the free layer.

14. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: substrate; Memory cells are formed over the substrate, each memory cell comprising a magnetic layer and a thermal stability enhancing layer TSEL in contact with the magnetic layer, and a free layer having a changeable magnetization direction; and switching elements formed over the substrate and respectively coupled to the memory cells to select or deselect the memory cells, wherein the TSEL comprises a homogeneous material having Fe-O bonds and is configured to enhance a perpendicular magnetic anisotropy field, wherein the TSEL comprises a Fe-Ir-OX alloy, and X comprises Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Mg, Sr, Ba, or a combination thereof, The TSEL and the free layer are disposed separately from each other.

15. The electronic device according to claim 10, in, Each memory cell further includes: an intermediate layer including a material having a body-centered cubic (001) structure and interposed between the tunnel barrier layer and the pinning layer.

16. The electronic device according to claim 15, wherein: The intermediate layer includes Co, Fe, Ni, B, a noble metal or a combination thereof.

17. The electronic device according to claim 10, wherein: Each memory cell further includes: a cover layer having a multi-layer structure, and wherein each layer included in the multi-layer structure has a material different from each other.

18. A semiconductor memory comprising: The free layer has a variable magnetization direction, The pinned layer has a fixed magnetization direction. a tunnel barrier layer interposed between the free layer and the pinned layer; and a thermal stability enhanced layer TSEL comprising a homogeneous material having Fe-O bonds, wherein the TSEL comprises a Fe-Ir-OX alloy, and X comprises Co, B, Mn, Cu, Al, Si, Ti, V, Cr, Ni, Ga, Ge, Zr, Nb, Mo, Pd, Ag, Hf, Ta, Ru, Pt, Rh, Mg, Sr, Ba, or a combination thereof, The TSEL and the free layer are disposed separately from each other.

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