Managing read voltage levels of data cells in memory devices using programming time proximity

Abstract

The present disclosure relates to managing read voltage levels of data cells in a memory device using programming time proximity. A processing device operably coupled to the memory device is configured to receive a read request identifying data stored in a data cell of the memory device. The processing device further identifies a data cell group to which the data cell is associated, the data cell group being one of a plurality of data cell groups, and each data cell in the data cell group being programmed within a time period associated with the data cell group. The processing device also determines a read voltage level for the data cell group, each of the plurality of data cell groups having a separate read voltage level. The processing device further uses the read voltage level of the data cell group to perform a read operation on the data cell of the memory device.

Description

Technical Field

[0001] The present disclosure relates generally to memory subsystems, and more particularly, to managing read voltage levels of data cells in a memory device using programming time proximity of the data cells. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] According to some embodiments of the present disclosure, a system is described. The system includes: a memory device; and a processing device, which is operably coupled to the memory device to perform operations including: receiving a read request to identify data stored in a data cell of the memory device; identifying a data cell group associated with the data cell, wherein the data cell group is one of a plurality of data cell groups, and wherein each data cell in the data cell group is programmed within a time period associated with the data cell group; determining a read voltage level of the data cell group, wherein each of the plurality of data cell groups has a separate read voltage level; and performing a read operation on the data cell of the memory device using the read voltage level of the data cell group.

[0004] A method is described according to some embodiments of the present disclosure. The method includes: receiving a read request identifying data stored in a data cell; identifying a data cell group associated with the data cell, wherein the data cell group is one of a plurality of data cell groups, and wherein each data cell in the data cell group is programmed within a time period associated with the data cell group; determining whether a read voltage level is assigned to the data cell group; in response to determining that a read voltage level is not assigned to the group of cells: performing a first read operation on the data stored in the data cell using a default read voltage level; and in response to determining that the first read operation fails: performing a read error handling operation to determine a second read voltage level, and assigning the second read voltage level to the data cell group; and performing a second read operation on the data stored in the data cell using the second read voltage level.

[0005] According to some embodiments of the present disclosure, a non-transitory computer-readable storage medium is described. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing device, cause the processing device to: receive a read request identifying data stored in a data unit of the memory device; identify a data unit group associated with the data unit, wherein the data unit group is one of a plurality of data unit groups, and wherein each data unit in the data unit group is programmed within a time period associated with the data unit group; determine a read voltage level for the data unit group, wherein each of the plurality of data unit groups has a separate read voltage level; and perform a read operation on the data unit of the memory device using the read voltage level of the data unit group. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood through the detailed description given below and through the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system for supporting multiple read voltage levels for data cells in a memory subsystem is shown in accordance with some embodiments of the present disclosure.

[0008] Figure 2 is a block diagram illustrating allocation of data units in a memory device to data unit groups according to some embodiments of the present disclosure.

[0009] Figure 3 An example timeline is shown for creating data cell groups and assigning data cells to data cell groups in a process supporting read voltage level management according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method of managing multiple read voltage level values ​​for a group of data cells in a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of an example method of determining a read voltage level of a data cell group in a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 6 is a flow chart of an example method of performing a read operation using different read voltage level values ​​from a group of data cells in a memory subsystem according to some embodiments of the present disclosure.

[0013] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure relate to managing separate read voltage levels when performing a read operation on data stored in a memory device of a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory devices that store data. The host system may provide data to be stored in the memory subsystem and may request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may include a plurality of memory devices that may store data from the host system. The memory devices may be non-volatile memory devices. Non-volatile memory devices are packages of one or more dies. Examples of non-volatile memory devices include NAND type memory devices. Figure 1 Other examples of non-volatile memory devices are described. The die in a package can be assigned to one or more channels for communicating with a memory subsystem controller. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a set of physical blocks, which are groupings of memory cells for storing data. A cell is an electronic circuit that stores information.

[0016] When data is written to a memory cell of a memory device and / or erased therefrom, the memory cell may be damaged to a certain extent. As the number of write operations and / or erase operations performed on the memory cell increases, the probability that the data stored in the memory cell contains errors increases, and the memory cell is increasingly damaged. More and more read and write operations may result in a higher error rate for the data stored in the memory cell. This may increase the use of error recovery operations, which include but are not limited to a read error handling module (REH), which can recover data and determine the pass read voltage level of the memory cell being read. The pass read voltage level may refer to a read voltage level that generates an error indicator within an acceptable range when used in a read operation, thereby resulting in a successful read operation. In addition, memory cells that are programmed at significantly different times may require different read voltage levels to successfully read the data stored in the memory cell. Therefore, when the memory subsystem processes read operations from various memory cells, the memory subsystem may trigger the REH module more frequently to obtain the pass read voltage level of the memory cell being read. Increasing the use of error recovery operations may result in a decrease in the performance of conventional memory subsystems. In addition, as the error rate continues to increase, it may even exceed the error recovery capability of the memory subsystem, resulting in irreparable data loss. In addition, as more resources of the memory subsystem are used to perform error recovery operations, fewer resources are available to perform other read operations or write operations.

[0017] For some memory types (i.e., for memory subsystems that employ certain types of storage media), the error rate may vary over time. In particular, some non-volatile memories have a threshold voltage (Vt) distribution that moves as a function of time. At a given read level (i.e., the voltage applied to the memory cell as part of a read operation), if the Vt distribution moves, certain reliability statistics will also be affected. An example of a reliability statistic is the raw bit error rate (RBER). The RBER can be defined as the ratio of the number of error bits to the number of all data bits stored in a data cell of the memory subsystem, where the data cell can be the entire memory subsystem, a die of a memory device, a set of code words, a set of memory device pages, a set of memory device blocks, or any other meaningful part of the memory subsystem. For any Vt distribution at a certain moment in time, there may be an optimal read voltage level (or read level range) that minimizes the expected RBER. In particular, the Vt distribution and the RBER may be a function of the time since the data cell was programmed (i.e., the time period that has passed since the data was written to the data cell). Due to the time-varying nature of the RBER and other noise mechanisms in the memory, a single read voltage level may not be sufficient to achieve an error rate that meets certain system reliability goals.

[0018] Therefore, some memory subsystems may require multiple pre-programmed read voltage levels, each corresponding to a group of data cells that are programmed close in time to each other, in order to minimize the execution of error recovery operations. This is particularly desirable in memory devices (e.g., replacement gate NAND memory devices) where the voltage distribution of the data cells changes frequently, by which the read voltage level can vary significantly based on the time when the data cells are programmed. For example, a first read voltage level can be used to read data having a first time range since programming, while a second read voltage level can be used to read data having a second time range since programming.

[0019] Various aspects of the present disclosure address the above and other deficiencies by assigning a separate read voltage level to each data cell group that is programmed within a predetermined time period. In this case, the memory subsystem may have multiple data cell groups, and each data cell group may have a dedicated read voltage level that can be used to perform a read operation on the data stored at the data cells of each group. In an embodiment, data cells that are programmed close to each other in time may be included in or assigned to the same data cell group, and thus the same read voltage level may be used to perform a read operation on the data stored at the data cells. Conversely, if two data cells are programmed at two different times that are far apart, the two data cells may be assigned to two different data cell groups. Therefore, different read voltage levels associated with each corresponding data cell group may be used to perform a read operation on the data stored at each data cell.

[0020] In some embodiments, the memory subsystem may create a data cell group at the time of data cell programming, and may maintain a data cell group as the current data cell group for a predetermined period of time (e.g., two hours). Any data cell programmed within the predetermined period of time may be assigned to the current data cell group. When the predetermined period of time has passed, the memory subsystem may create a new data cell group, and may begin assigning data cells programmed within a second period of time to the new data cell group, and so on. In some embodiments, when erasing data stored at a data cell (e.g., in order to enable rewriting of the data cell), the data cell may be removed from the data cell group to which the data cell was assigned when the data cell was programmed.

[0021] When a data cell group is created, it can be associated with one or more data cells. When a data read operation requesting storage at a data cell in the data cell group is received, a read voltage level can be assigned to the data cell group. In this case, when a read operation is received, the memory subsystem can check whether the data cell group has an associated read voltage level. If the data cell group does not yet have an associated read voltage level, the memory subsystem can determine the read voltage level of the data cell group and can assign the determined read voltage level to the data cell group. Subsequent read operations for data cells associated with the data cell group can use the read voltage level assigned to the group to perform read operations on data of the data cells stored in the data cell group.

[0022] In one embodiment, the read voltage level assigned to a data cell group may cause a read operation to fail, for example, due to a shift in the voltage distribution of the memory cells of the data cell. When such a shift in the voltage distribution occurs for a data cell, the read voltage level associated with the data cell may be updated to reflect the passed read voltage level of the data cell group. In an embodiment, the memory subsystem may use an error handling module to obtain a new read voltage level value. The new read voltage level value may then be assigned to the data cell group to replace the previous read voltage level. Then, when performing a read operation, subsequent read operations of the data cells associated with the data cell group may use the new read voltage level.

[0023] The technology described herein for supporting multiple read voltage levels for multiple data cell groups in a memory subsystem enables improved overall performance of the memory subsystem. In a memory device where the voltage distribution of the memory cells changes frequently (e.g., a gate NAND memory device replaced), the pass read voltage level can vary significantly based on the time when the data cell is programmed. Therefore, by having each data cell group that is programmed close to each other in time (e.g., within a predetermined time period) have a separate read voltage level, the read operation of the data cell can reuse the pass read voltage level without having to trigger a time-consuming read error handling module to frequently correct the read voltage level. Since the memory subsystem no longer uses a single read voltage level value for the entire memory device, the need to execute an expensive read error handling module can be significantly reduced as more data cell groups are created within the memory subsystem. Therefore, the technology described herein for supporting a separate read voltage level for each data cell group reduces the overhead of frequently executing the read error handling module, which improves the overall performance of the memory subsystem.

[0024] Figure 1An exemplary computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such memory devices.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device including a memory and a processing device.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0028] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses, for example, the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0029] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the component (memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM) such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A 3D cross-point memory device is a cross-point array of non-volatile memory cells that can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, in which non-volatile memory cells can be programmed without having to erase the non-volatile memory cells in advance. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each memory device 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of a memory device for storing data. With some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of nonvolatile memory cell, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), ferroelectric transistor random access memory (FeTRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or, for simplicity, the controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The exemplary memory subsystem 110 in FIG. 1 is shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., control provided by an external host, or by a processor or controller separate from the memory subsystem).

[0037] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The memory subsystem 110 includes a read voltage level component 113 that can be used to support separate read voltage levels for separate data cell groups based on the proximity of the programming time of the data cells. In an embodiment, the read voltage level component 113 can create multiple data cell groups of the memory devices 130-140. Each data cell group can have an associated read voltage level that can be used to perform a read operation on the data stored at the data cells of each group. In an embodiment, data cells that are programmed close to each other in time can be included in or assigned to the same data cell group, and thus the same read voltage level can be used to perform a read operation on the data stored at the data cells. Conversely, if two data cells are programmed at two different times that are far apart (e.g., programmed at times on opposite sides of a threshold time), the two data cells can be assigned to two different data cell groups. Therefore, different read voltage levels associated with each corresponding data cell group can be used to perform a read operation on the data stored at each data cell. In an embodiment, the memory subsystem can store the read voltage level associated with each data cell group in a memory subsystem controller 115 of the memory subsystem 110.

[0041] In some embodiments, the read voltage level component 113 can create a data cell group at the data cell programming time, and can keep one data cell group as the current data cell group for a predetermined time period. Any data cell programmed within the predetermined time period can be assigned to the current data cell group. For example, when the memory subsystem 110 is powered on, the read voltage level component 113 can create a first data cell group. The first group can be a designated current data cell group for a predetermined time period, which can be determined based on the specifications of the memory subsystem 110 (e.g., four hours). In this case, each data cell programmed within four hours from powering on the memory subsystem to the end of the predetermined time period can be assigned to the first data cell group. After four hours, the memory subsystem can create a new data cell group and can begin to assign data cells programmed in the second period of four hours to the new data cell group, and so on. In some embodiments, when erasing data stored at a data cell (e.g., in order to achieve rewriting of the data cell), the data cell can be removed from the data cell group to which the data cell was assigned when the data cell was programmed.

[0042] When a data cell group is created, it may be associated with one or more data cells. When a data read operation requesting storage at a data cell in the data cell group is received, a read voltage level may be assigned to the data cell group. In this case, when a read operation is received, the read voltage level component 113 may check whether the data cell group has an associated read voltage level. If the data cell group already has an associated read voltage level, the read voltage level component 113 may perform the read operation using the read voltage level associated with the data cell group. On the other hand, if the data cell group does not yet have an associated read voltage level, the read voltage level component 113 may perform the read operation using a default read voltage level. In some embodiments, since the voltage distribution of the data cells changes over time, the default read voltage level may cause the read operation to fail (e.g., the read operation will generate a read bit error rate (RBER) above a certain threshold). When a read operation performed using a default read voltage error fails, the read voltage level component 113 may trigger a read error handling (REH) module to recover the data and determine a new read voltage error value that is more suitable for the specific data cell being read. Subsequently, the read voltage level component 113 may perform a read operation again using the new read voltage level determined by the REH module. If the read operation is successfully performed, the read voltage level component 113 may assign the new read voltage level to the data cell group to which the read data cells have been assigned. Subsequent read operations for data cells associated with the data cell group may perform read operations on data of the data cells stored in the data cell group using the read voltage level assigned to the group.

[0043] In one embodiment, the read voltage level assigned to a data cell group may cause a read operation to fail, for example, due to a shift in the voltage distribution of the memory cells that make up the data cell. The shift in the voltage distribution of the memory cell may be caused by many factors, including temperature, repeated programming / erase operations, and the time that has passed since the memory cell was programmed. When such a shift in the voltage distribution occurs for a data cell, the read voltage level associated with the data cell (via the data cell group to which the data cell is assigned) may no longer be valid. In this case, a read operation on the data cell using the associated read voltage level may fail. As explained above, a failed read operation can trigger the REH module to obtain a new read voltage level value. The read operation can then be performed again using the new read voltage level value. When the second read operation is successfully performed, the read voltage level component 113 can assign the new read voltage level to the data cell group, thereby replacing the previous read voltage level. Then, when performing a read operation, subsequent read operations of the data cells associated with the data cell group can use the new read voltage level.

[0044] In some embodiments, in order to maintain a manageable number of data cell groups, the read voltage level component 113 can merge the data cell groups together so that data cells belonging to multiple groups can be merged together under only one data cell group. In an embodiment, older data cell groups (e.g., created a few months ago) can have similar read voltage level values ​​and can therefore be merged together into one data cell group. For example, the read voltage level component 113 can determine that data cell groups with read voltage level values ​​within a certain proximity to each other can be merged into one group. In an illustrative example, if the difference between the read voltage level values ​​of two data cell groups is small enough to meet a threshold condition, the read voltage level component 113 can merge the data cells in the two groups into one data cell group, thereby covering all data cells in the two groups. In this case, the read voltage level component 113 can assign the read voltage level of a data cell group before the merge to the data cell group obtained after the merge.

[0045] Figure 2 is a block diagram 200 illustrating the allocation of data units in a memory device to data unit groups according to some embodiments of the present disclosure. In one implementation, the memory device 130 may contain data units 210-215, and each data unit may be programmed at a different time. Figure 1 Each memory device 130-140 may contain hundreds of data cells. A data cell may refer to a unit of a memory device for storing data, and may include one or more memory pages, one or more memory blocks, one or more memory cells, or one or more word lines.

[0046] In one embodiment, a plurality of data cell groups 230 - 250 may be defined in the memory subsystem 110 , and each data cell group 230 - 250 may contain a separate read voltage level 231 , 241 , and 251 . Figure 2 An example is shown in which there are three data unit groups 230-250. Depending on the time when each data unit is programmed, each data unit 210-215 can be assigned to only one of the data unit groups 230-250. In one embodiment, the processing logic can create the data unit group 230, for example, when the memory subsystem 110 is powered on, and the data unit group 230 can be designated as the current group within a predetermined time period (e.g., two hours). All data units programmed during the time period when the data unit group 230 is the current group will be assigned to the data unit group 230 (e.g., data units 210 and 213). Similarly, the data unit group 240 can be created at different time points and can be designated as the current data unit group for the same time period (e.g., two hours). The data unit programmed when the data unit group 240 is the current group will be assigned to the data unit group 240 (e.g., data unit 214). The data unit group 250 can be further created at another time point and can be designated as the current data unit group within one-third of the 2 hours. Data cells programmed within a third period of two hours will be assigned to data cell group 250 (eg, data cells 211 and 215), and so on.

[0047] refer to Figure 2 , data cell 210 and data cell 213 are assigned to data cell group 230, indicating that data cells 210 and 213 are programmed closer to each other in time. Therefore, when a read operation for data stored at data cell 210 or data cell 213 is received at memory subsystem 110, memory subsystem 110 may perform the read operation using read voltage level 231 of group 230. For example, when memory subsystem 110 receives a read operation for data stored at data cell 210, memory subsystem 110 may search available data cell groups to determine which data cell group is associated with data cell 210. When memory subsystem 110 determines to assign data cell 210 to group 230, memory subsystem 110 may retrieve read voltage level 231 associated with group 230, and may perform the read operation using read voltage level 231.

[0048] The data cell 214 is assigned to the data cell group 240, indicating that the data cell 214 is programmed when the data cell group 240 is the current group. Therefore, when a read operation for the data stored at the data cell 214 is received at the memory subsystem 110, the memory subsystem 110 may perform the read operation using the read voltage level 241 of the group 240. For example, when the memory subsystem 110 receives a read operation for the data stored at the data cell 214, the memory subsystem 110 may search the available data cell groups to determine which data cell group is associated with the data cell 214. When the memory subsystem 110 determines to assign the data cell 214 to the group 240, the memory subsystem 110 may retrieve the read voltage level 241 associated with the group 240, and may perform the read operation using the read voltage level 241.

[0049] Data cell 211 and data cell 215 are assigned to data cell group 250, indicating that data cells 211 and 215 are programmed closer to each other in time. Therefore, when a read operation for data stored at data cell 211 or data cell 215 is received at memory subsystem 110, memory subsystem 110 may perform the read operation using read voltage level 251 of group 250. For example, when memory subsystem 110 receives a read operation for data stored at data cell 215, memory subsystem 110 may search available data cell groups to determine which data cell group is associated with data cell 215. When memory subsystem 110 determines to assign data cell 215 to group 250, memory subsystem 110 may retrieve read voltage level 251 associated with group 250, and may perform the read operation using read voltage level 251.

[0050] Data unit 212 is not associated with a data unit group. In one embodiment, this may indicate that data unit 212 has not been programmed with any data. In this case, data unit 212 will not be assigned to a data unit group. When memory subsystem 110 receives a programming operation for data unit 212, memory subsystem 110 may then perform the programming operation and may assign data unit 212 to the data unit group that is the current group when programming data unit 212.

[0051] Figure 3An exemplary timeline for creating data cell groups and assigning data cells to data cell groups in a process supporting read voltage level management according to some embodiments of the present disclosure is shown. In some embodiments, when the memory subsystem 110 is powered on, the memory subsystem 110 can begin to create data cell groups and begin to assign data cells to multiple data cell groups. The memory subsystem 100 can then designate one data cell group as the current group at a time. The current data cell group continues to be the current group for a predetermined period of time (e.g., two hours), after which another data cell group is created and designated as the current data cell group, and so on. As the data cells are programmed, they are assigned to the current data cell group as they are programmed.

[0052] In an illustrative example, group 320 may be created, for example, when memory system 110 is powered on (e.g., at 9:00 a.m.). Assuming the predetermined time period (T1) is 2 hours, group 320 will be the designated current data unit group until T1 passes, for example, at 11:00 a.m. In this example, memory subsystem 110 may receive three program requests to program data into data units 321A, 321B, and 321C, respectively. The three program requests are received between 9:00 a.m. and 11:00 a.m., during which time group 320 is the current data unit group. Therefore, after performing programming operations on the respective data units, the memory subsystem may assign each data unit 321A-C to group 320. At T1=11:00 a.m., memory subsystem 110 may create a new data unit group 330, and may designate group 330 as the current data unit group until T2=1:00 p.m.

[0053] Similarly, the memory subsystem 110 may receive two program requests for programming data into data cells 331A and 331B. The two program requests are received between 11:00 AM and 1:00 PM, during which time group 330 is the current data cell group. Therefore, each data cell 331A-B is assigned to group 330 when performing its respective programming operation. At T2=1:00 PM, the memory subsystem 110 may create a new data cell group 340 and may designate group 340 as the current data cell group until T3=3:00 PM.

[0054] At T2, the memory subsystem 110 may receive three program requests to program data into data cells 341A, 341B, and 341C, respectively. The three program requests are received between 1:00 PM and 3:00 PM, during which time group 340 is the current data cell group. Therefore, each data cell 341A-C is assigned to group 340 when performing its respective program operation. At T13 = 3:00 PM, the memory subsystem 110 may create a new data cell group (not shown) and may designate the new group as the current data cell group, and so on.

[0055] In an embodiment, when data stored at one of the data cells 321A-C, 331A-B, and 341A-C is erased (e.g., to enable rewriting of the data cell), the erased data cell may be removed from a corresponding one of the data cell groups to which the erased data cell was assigned when the data cell was programmed. Thus, when the erased data cell is programmed again, it may be assigned to a different group of data cells according to the timing of the programming operation.

[0056] Figure 4 400 is a flowchart of an exemplary method for managing multiple read voltage level values ​​for a data unit group in a memory subsystem according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The read voltage level management component 113 is executed. Although shown in a particular order or sequence, unless otherwise stated, the order of the processes can be modified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processing flows are also possible.

[0057] At operation 410, processing logic receives a read request identifying data stored in a data unit of a memory device. In an embodiment, the read request may be received from a host system. In other embodiments, the read request may be received from a memory subsystem controller, for example, to perform a wear leveling operation, a garbage collection operation, etc. To perform the read request, a read operation may be performed using a read voltage level value associated with one of the data unit groups to which the data unit is assigned, as explained in detail herein.

[0058] At operation 420, processing logic identifies a data unit group to which the data unit is associated. The data unit group is one of a plurality of data unit groups within a memory subsystem, and each data unit in the data unit group is programmed within a time period associated with the data unit group. In an embodiment, the data unit group may be identified by matching an identifier of the data unit with a list of identifiers of data units associated with the data unit group.

[0059] At operation 430, the processing device determines a read voltage level for the data cell group. In an embodiment, each of the plurality of data cell groups of the memory subsystem has a separate read voltage level. In some embodiments, a read error handling module may be used to determine a read voltage level for a data cell group, which may then be assigned to the data cell group, as explained in more detail above.

[0060] At operation 440, the processing device performs a read operation on the data cell of the memory device using the read voltage level of the data cell group. In an embodiment, if the read operation fails (e.g., due to a shift in the voltage distribution of the memory cells constituting the data cell), the processing device may trigger the REH module to obtain a new read voltage level value. The read operation may then be performed again using the new read voltage level value. When the second read operation is successfully performed, the processing logic may assign the new read voltage level to the data cell group, thereby replacing the previous read voltage level, as explained in more detail herein.

[0061] Figure 5 500 is a flowchart of an exemplary method for determining a read voltage level of a data unit group in a memory subsystem according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1 The read voltage level management component 113 is executed. Although shown in a particular order or sequence, unless otherwise stated, the order of the processes can be modified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processing flows are also possible.

[0062] At operation 510, processing logic determines a data cell group associated with the data cell, for example, to perform a read operation on the data in the data cell using a read voltage level from the associated data cell group, as explained in detail herein.

[0063] At operation 515, processing logic determines whether the data cell group has an assigned read voltage level. In an embodiment, the data cell group may have an assigned read voltage level when performing a read operation for data stored in any data cell associated with the group, as explained in greater detail herein.

[0064] At operation 530, once it is determined that the group does not have an assigned read voltage level, the processing logic performs a read operation on the data stored in the data cell using a default read voltage level. In an embodiment, the default read voltage level may refer to an initial value of a read voltage level that may be associated with a memory device and is not specific to any particular group of data cells.

[0065] Therefore, at operation 540, the processing logic may determine that the read operation using the default read voltage level has failed. In an embodiment, when the read operation is performed using the default read voltage level, an indicator of the accuracy of the read operation (e.g., a read bit error rate (RBER)) may be above a certain threshold due to the inaccuracy of the default read voltage level. Therefore, the processing logic may trigger a read error handling (REH) module to obtain a passing read voltage level for the data cell, as explained in more detail herein.

[0066] At operation 550, processing logic assigns the pass read level voltage obtained from the REH module to the data cell group. And at operation 560, processing logic performs a read operation on the data cells using the read voltage level of the group. Further read operations on data stored at the data cells associated with the data cell group may be performed using the read voltage level associated with the group.

[0067] Figure 6 600 is a flowchart of an exemplary method for performing a read operation using different read voltage level values ​​from a group of data cells in a memory subsystem according to some embodiments of the present disclosure. Method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 600 is performed by Figure 1The read voltage level management component 113 is executed. Although shown in a particular order or sequence, unless otherwise stated, the order of the processes can be modified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processing flows are also possible.

[0068] At operation 610, processing logic receives a first read request for data stored at data cell U1. Then, at operation 620, processing logic determines a data cell group Set1 associated with data cell U1 to retrieve a read voltage level associated with Set1 to perform a read operation.

[0069] At operation 630, processing logic performs a first read operation using the read voltage level RL1 of Set1, as explained in greater detail herein above. In an embodiment, processing logic may determine the read voltage level of Set1 using the REH module, as previously explained.

[0070] At operation 640, processing logic receives a subsequent read request for data stored at another data cell U2. Similarly, processing logic determines a data cell group Set2 associated with data cell U2. At operation 655, processing logic determines whether Set1 and Set2 are identical, indicating that data cell U1 and data cell U2 belong to the same data cell group. In an embodiment, when performing a read operation on data stored at data cells associated with the same data cell group, processing logic may perform a read operation on each data cell using a read voltage level assigned to the data cell group, as explained in more detail herein above.

[0071] In operation 660 , the processing device determines that data unit U1 and data unit U2 are associated with the same data unit group ( Set1 ), and then the processing logic performs a read operation on the data stored at U2 using RL1 of Set1 .

[0072] On the other hand, at operation 670 , when the processing device determines that data unit U1 and data unit U2 are associated with different groups of data units, the processing logic performs a read operation on the data stored at data unit U2 using another read voltage level RL2 of Set2 .

[0073] Figure 7An example machine of a computer system 700 is shown in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the operation related to the controller). Figure 1 In an alternative embodiment, the machine can be connected (e.g., connected to a local area network (LAN), an intranet, an extranet, and / or the Internet) to other machines. The machine can operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0074] The machine may be a personal computer (PC), a tablet, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a Web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential instructions or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0075] The exemplary computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0076] The processing device 702 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 to communicate via a network 720.

[0077] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. During the execution of the instructions 726 by the computer system 700, the instructions may also reside in whole or in part in the main memory 704 and / or in the processing device 702, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0078] In one embodiment, instruction 726 includes instructions for implementing Figure 1 The machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some parts of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to other persons skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that leads to a desired result. These operations are operations that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Mainly for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0080] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0081] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0082] The algorithms and displays provided herein are not inherently related to any particular computer or other device. Various general purpose systems may be used together with the programs taught herein, or it may prove to be more convenient to construct more specialized equipment to perform the method. As described above, structures for various of these systems will occur. In addition, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0083] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform processing according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0084] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system comprising: Memory device; as well as A processing device operatively coupled to the memory device to perform operations comprising: receiving a read request directed to a first data unit of the memory device; determining that a first group of data cells is programmed within a first time period; identifying that the first data unit group is associated with the first data unit; determining a first pass read voltage level associated with the first group of data cells using a read error handling operation, wherein the first pass read voltage level, when used in a read operation, produces an error indicator within a given range indicating that the read operation was successful; as well as A first read operation is performed on the first data cells of the memory device using the first pass read voltage level associated with the first group of data cells.

2. The system of claim 1, wherein one or more data cells in the first data cell group and one or more data cells in the second data cell group are programmed in separate associated time periods.

3. The system of claim 1, wherein the processing device performs further operations comprising: receiving a programming request identifying data to be stored on the memory device; programming the data to the first data cell of the memory device; and The first data cell is assigned to a current data cell group, wherein the current data cell group includes data cells programmed within a current time period.

4. The system of claim 1 , wherein to determine the first pass read voltage level, the processing device performs further operations comprising: determining whether a voltage level is associated with the first data cell group by reading; In response to determining that the first data cell group is not associated with the read voltage level: performing the first read operation on the data stored in the data cell using a default read voltage level; and In response to determining that the first read operation failed: performing a read error handling operation to determine the first pass read voltage level, and The first pass read voltage level is associated with the first group of data cells.

5. The system of claim 1, wherein the processing device performs further operations comprising: In response to detecting that data stored in the first data unit is erased, the first data unit is separated from the first data unit group.

6. The system of claim 1, wherein the processing device performs further operations comprising: In response to determining that the first read operation using the first pass read voltage level of the first data cell group has failed: performing a read error handling operation to determine a third pass read voltage level, and The third pass read voltage level is associated with the first group of data cells, replacing the first pass read voltage level.

7. The system of claim 6, wherein to determine that the first read operation failed, the processing device performs further operations comprising: It is determined that the first read operation results in a read bit error rate RBER value that meets a threshold condition.

8. The system of claim 1, wherein the processing device performs further operations comprising: receiving a second read request directed to a second data unit of the memory device; determining whether the second data unit matches one or more data units in a second set of data units; and In response to determining that the second data cell matches the one or more data cells in the second data cell group, a second read operation is performed on the second data cell of the memory device using a second pass read voltage level associated with the second data cell group.

9. The system of claim 1, wherein the processing device performs further operations comprising: receiving a third read request directed to a third data unit of the memory device; identifying a third data cell group having a corresponding third pass read voltage level, wherein the third data cell group reflects one or more data cells of the third data cell group being programmed during a third time period, and wherein the third data cell is associated with the third data cell group; obtaining the third pass read voltage level associated with the third data cell group; and A third read operation is performed on the third data cell of the memory device using the third pass read voltage level.

10. A method comprising: receiving a read request directed to a first data unit of a memory device; determining that a first group of data cells is programmed within a first time period; identifying that the first data unit group is associated with the first data unit; determining a first pass read voltage level associated with the first group of data cells using a read error handling operation, wherein the first pass read voltage level, when used in a read operation, produces an error indicator within a given range indicating that the read operation was successful; as well as A first read operation is performed on the first data cells of the memory device using the first pass read voltage level associated with the first group of data cells.

11. The method of claim 10, wherein one or more data cells in the first data cell group and one or more data cells in the second data cell group are programmed in separate associated time periods.

12. The method according to claim 10, further comprising: receiving a programming request identifying data to be stored on the memory device; programming the data into the first data cell of the memory device; as well as The first data unit is assigned to a current data unit group, wherein the current data unit group includes data units programmed within a current time period.

13. The method of claim 10, wherein determining the first pass read voltage level further comprises: determining whether a voltage level is associated with the first data cell group by reading; In response to determining that the first data cell group is not associated with the read voltage level: performing the first read operation on the data stored in the data cell using a default read voltage level; as well as In response to determining that the first read operation failed: performing a read error handling operation to determine the first pass read voltage level, and The first pass read voltage level is associated with the first group of data cells.

14. The method according to claim 10, further comprising: In response to detecting that data stored in the first data unit is erased, the first data unit is separated from the first data unit group.

15. The method of claim 10, wherein determining that the first read operation has failed further comprises: It is determined that the first read operation results in a read bit error rate RBER value that meets a threshold condition.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving a read request directed to a first data unit of a memory device; determining that a first group of data cells is programmed within a first time period; identifying that the first data unit group is associated with the first data unit; determining a first pass read voltage level associated with the first group of data cells using a read error handling operation, wherein the first pass read voltage level, when used in a read operation, produces an error indicator within a given range indicating that the read operation was successful; as well as A first read operation is performed on the data cells of the memory device using the first pass read voltage level associated with the first group of data cells.

17. The non-transitory computer readable storage medium of claim 16, wherein the processing device is further configured to: receiving a programming request identifying data to be stored on the memory device; programming the data to the first data cell of the memory device; and The first data unit is assigned to a current data unit group, wherein the current data unit group includes data units programmed within a current time period.

18. The non-transitory computer readable storage medium of claim 16, wherein the processing device is further configured to: In response to detecting that data stored in the first data unit is erased, the first data unit is separated from the first data unit group.

19. The non-transitory computer readable storage medium of claim 16, wherein the processing device is further configured to: receiving a second read request directed to a second data unit of the memory device; determining whether the second data unit matches one or more data units in the first set of data units or one or more data units in the second set of data units; and In response to determining that the second data cell matches the one or more data cells in the second data cell group, a second read operation is performed on the second data cell of the memory device using a second pass read voltage level associated with the second data cell group.

20. The non-transitory computer readable storage medium of claim 16, wherein the processing device is further configured to: receiving a third read request identifying data stored in a third data unit of the memory device; identifying a third data cell group having a corresponding third pass read voltage level, wherein the third data cell group reflects one or more data cells in the third data cell group being programmed within a third time period, and wherein the third data cell is associated with the third data cell group; obtaining the third pass read voltage level associated with the third data cell group; and A third read operation is performed on the third data cell of the memory device using the third pass read voltage level.

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