Display device

Abstract

A display apparatus is disclosed. The display apparatus includes a display panel, a memory, a dithering processor, and a panel driver. The display panel includes a display surface, and the memory stores a plurality of dithering patterns for at least one spot area included in the display surface. The dithering processor selects a dithering pattern among the plurality of dithering patterns in a predetermined time unit, and outputs a compensation image signal corresponding to the selected dithering pattern. The panel driver outputs a data signal corresponding to the spot area based on the compensation image signal. Each of the plurality of dithering patterns includes a first gray area having a first gray value higher than a first target gray value of the spot area, and a second gray area having a second gray value lower than the first target gray value.

Description

Technical Field

[0001] This disclosure relates to display devices. More specifically, this disclosure relates to display devices with improved display quality. Background Technology

[0002] In recent years, flat panel display devices such as liquid crystal displays, plasma display panels, and organic light-emitting diode displays have been mainly used as image display devices.

[0003] Some image display devices employ speckle compensation schemes to compensate for display spots generated on the display panel when displaying images. Summary of the Invention

[0004] This disclosure provides a display device capable of preventing flickering and improving display quality.

[0005] This disclosure provides a method for driving a display device.

[0006] According to one embodiment, the display device includes a display panel, a memory, a dithering processor, and a panel driver. The display panel includes a display surface. The memory stores a plurality of dithering patterns for at least one spot region included in the display surface. The dithering processor selects a dithering pattern from the plurality of dithering patterns in a first predetermined time unit and outputs a compensated image signal corresponding to the selected dithering pattern. The panel driver outputs a data signal corresponding to the spot region based on the compensated image signal.

[0007] Each of the multiple dithering patterns includes a first grayscale region and a second grayscale region, the first grayscale region having a first grayscale value that is higher than the first target grayscale value of the spot region, and the second grayscale region having a second grayscale value that is lower than the first target grayscale value.

[0008] According to one implementation, the grayscale difference between the first grayscale value of the first grayscale region and the second grayscale value of the second grayscale region can be equal to or greater than 2.

[0009] According to one implementation, the first target grayscale value may correspond to the average of the first grayscale value of the first grayscale region and the second grayscale value of the second grayscale region.

[0010] According to one embodiment, the display surface may further include a non-spotted region, and the non-spotted region may include an uncompensated region and a boundary region between the uncompensated region and the spotted region.

[0011] According to one embodiment, the display device may further include: a boundary memory storing a plurality of boundary jitter patterns for a boundary region; and a boundary jitter processor selecting a boundary jitter pattern from the plurality of boundary jitter patterns in a second predetermined time unit, and outputting a boundary compensation image signal corresponding to the selected boundary jitter pattern. Each of the plurality of boundary jitter patterns may include a third grayscale region and a fourth grayscale region, the third grayscale region having a third grayscale value higher than a second target grayscale value of the boundary region, and the fourth grayscale region having a fourth grayscale value lower than the second target grayscale value.

[0012] According to one implementation, the boundary region may include a boundary jittering region and a non-jittering region. In the boundary jittering region, the boundary jittering processor performs jittering operations using multiple boundary jittering patterns, and in the non-jittering region, the boundary jittering processor does not perform jittering operations.

[0013] According to one implementation, the third grayscale region and the fourth grayscale region may have the same size as the first grayscale region and the second grayscale region.

[0014] According to one implementation, the third and fourth grayscale regions may have larger dimensions than the first and second grayscale regions.

[0015] According to one implementation, the grayscale difference between the third grayscale value of the third grayscale region and the fourth grayscale value of the fourth grayscale region can be equal to or greater than 2.

[0016] According to one implementation, the boundary region may include multiple sub-boundary regions, and the boundary memory may store sub-boundary jitter patterns for the multiple sub-boundary regions.

[0017] According to one embodiment, each of the sub-boundary dithering patterns may include a first sub-boundary grayscale region and a second sub-boundary grayscale region, the first sub-boundary grayscale region having a fifth grayscale value that is higher than a third target grayscale value of each of the plurality of sub-boundary regions, and the second sub-boundary grayscale region having a sixth grayscale value that is lower than the third target grayscale value.

[0018] According to one implementation, each of the plurality of sub-boundary regions may include a sub-boundary jittering region and a non-jittering region. In the sub-boundary jittering region, the boundary jittering processor performs a sub-boundary jittering operation using a sub-boundary jittering pattern. In the non-jittering region, the boundary jittering processor does not perform a sub-boundary jittering operation. The size of the non-jittering region may gradually increase with increasing distance from the spot region.

[0019] According to one implementation, the first sub-boundary grayscale region and the second sub-boundary grayscale region may have the same size as the first grayscale region and the second grayscale region.

[0020] According to one implementation, the grayscale difference between the fifth grayscale value of the first sub-boundary grayscale region and the sixth grayscale value of the second sub-boundary grayscale region can be equal to or greater than 2.

[0021] According to one embodiment, the display device may further include a spot region extractor that extracts spot regions on the display surface of the display panel.

[0022] According to one embodiment, a method for driving a display device includes: extracting at least one spot region on the display surface of a display panel; selecting a dithering pattern among a plurality of dithering patterns for the spot region in a first predetermined time unit; compensating an image signal corresponding to the spot region based on the selected dithering pattern, and outputting a compensated image signal; generating a data signal for the spot region based on the compensated image signal; and providing the data signal to the display panel.

[0023] Each of the multiple dithering patterns includes a first grayscale region and a second grayscale region, the first grayscale region having a first grayscale value that is higher than the first target grayscale value of the spot region, and the second grayscale region having a second grayscale value that is lower than the first target grayscale value.

[0024] According to one implementation, the grayscale difference between the first grayscale value of the first grayscale region and the second grayscale value of the second grayscale region can be equal to or greater than 2.

[0025] According to one implementation, the first target grayscale value may correspond to the average of the first grayscale value of the first grayscale region and the second grayscale value of the second grayscale region.

[0026] According to one embodiment, the display surface may further include a non-spotted region, and the non-spotted region may include an uncompensated region and a boundary region between the uncompensated region and the spotted region.

[0027] According to one embodiment, the method may further include selecting a boundary dithering pattern from a plurality of boundary dithering patterns for a boundary region within a second predetermined time unit. Each of the plurality of boundary dithering patterns may include a first boundary grayscale region and a second boundary grayscale region, the first boundary grayscale region having a third grayscale value higher than a second target grayscale value of the boundary region, and the second boundary grayscale region having a fourth grayscale value lower than the second target grayscale value.

[0028] According to one implementation, the grayscale difference between the third grayscale value of the first boundary grayscale region and the fourth grayscale value of the second boundary grayscale region can be equal to or greater than 2.

[0029] According to one embodiment, a display device includes a display panel, a frequency comparator, a first memory, a second memory, a first dithering processor, a second dithering processor, and a panel driver. The display panel includes a display surface. The frequency comparator compares a driving frequency of the display panel with a predetermined reference frequency. The first memory stores a plurality of global dithering patterns for the entire area of ​​the display surface, and the second memory stores a plurality of local dithering patterns for at least one spot region included in the display surface. In a normal mode, the first dithering processor selects a global dithering pattern from the plurality of global dithering patterns within a predetermined time unit and outputs a first compensated image signal corresponding to the selected global dithering pattern, wherein the driving frequency in the normal mode is equal to or greater than the reference frequency. In a low-frequency mode, the second dithering processor selects a local dithering pattern from the plurality of local dithering patterns within a predetermined time unit and outputs a second compensated image signal corresponding to the selected local dithering pattern, wherein the driving frequency in the low-frequency mode is less than the reference frequency. In the normal mode, the panel driver outputs a global data signal for the entire area based on the first compensated image signal, and in the low-frequency mode, outputs a local data signal for the spot region based on the second compensated image signal.

[0030] Each of the plurality of local dithering patterns includes a first grayscale region and a second grayscale region, the first grayscale region having a first grayscale value higher than the first target grayscale value of the spot region, and the second grayscale region having a second grayscale value lower than the first target grayscale value; and each of the plurality of global dithering patterns includes a third grayscale region and a fourth grayscale region, the third grayscale region including a third grayscale value higher than the second target grayscale value of the entire region, and the fourth grayscale region having a fourth grayscale value lower than the second target grayscale value.

[0031] According to one embodiment, the grayscale difference between the first grayscale value of the first grayscale region and the second grayscale value of the second grayscale region can be equal to or greater than 2, and the grayscale difference between the third grayscale value of the third grayscale region and the fourth grayscale value of the fourth grayscale region can be equal to or greater than 2.

[0032] According to one embodiment, the first target gray value may correspond to the average of the first gray value of the first gray region and the second gray value of the second gray region, and the second target gray value may correspond to the average of the third gray value of the third gray region and the fourth gray value of the fourth gray region.

[0033] According to one embodiment, the display device may further include a spot region extractor for extracting spot regions.

[0034] When a dithering pattern distributed in time and space is used to dither an image signal targeting a spot area (which corresponds to a portion of the display surface), the display device can prevent the spot from being observable on the display surface.

[0035] Furthermore, since dithering can be performed locally on a portion of the display device, rather than on the entire display surface, the display device can prevent flickering that may be caused by dithering. Attached Figure Description

[0036] The above and other beneficial effects of this disclosure will become apparent when considered in conjunction with the accompanying drawings, and by referring to the following detailed description, in which:

[0037] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0038] Figure 2 It shows Figure 1 The equivalent circuit diagram of one pixel is shown below;

[0039] Figure 3 It shows the method for driving. Figure 2 The waveform diagram of the driving signal of the pixel shown;

[0040] Figure 4 This is an internal block diagram of a signal controller according to an exemplary embodiment of the present disclosure;

[0041] Figure 5 It shows Figure 1 A plan view of the display surface of the display panel shown;

[0042] Figure 6 It shows the relationship with Figure 5 The jitter pattern corresponding to the first region A1 shown in the figure;

[0043] Figure 7 It is shown in units of frame period Figure 6 The jitter pattern shown;

[0044] Figure 8A It shows the target in frame period units. Figure 7 The chart of grayscale values ​​for the first part C1 shown;

[0045] Figure 8B It shows the target in frame period units. Figure 7 The graph of grayscale values ​​for the second part C2 shown in the image;

[0046] Figure 9 This is an internal block diagram of a signal controller according to an exemplary embodiment of the present disclosure;

[0047] Figure 10 This is a plan view showing the display surface of a display panel according to an exemplary embodiment of the present disclosure;

[0048] Figure 11A It shows the relationship with Figure 10 An example of the first jitter pattern corresponding to region D1 shown;

[0049] Figure 11B It shows the relationship with Figure 10 An example of the first boundary jitter pattern corresponding to region D2 shown in the figure;

[0050] Figure 11C An example of a first boundary jitter pattern according to another exemplary embodiment of this disclosure is shown;

[0051] Figure 12 This is a plan view showing the display surface of a display panel according to an exemplary embodiment of the present disclosure;

[0052] Figure 13A It shows Figure 12 The first jitter pattern in region E1 shown;

[0053] Figure 13B It shows Figure 12 The first sub-boundary jitter pattern of region E2 shown;

[0054] Figure 13C It shows Figure 12 The second sub-boundary jitter pattern of region E3 shown;

[0055] Figure 14 This is an internal block diagram of a signal controller according to an exemplary embodiment of the present disclosure;

[0056] Figure 15A This is a plan view showing the display surface of the display panel in normal mode; and

[0057] Figure 15B This is a plan view showing the display surface of the display panel in low-frequency mode. Detailed Implementation

[0058] In this disclosure, it will be understood that when an element or layer is referred to as being “on”, “connected to” or “attached to” another element or layer, it may be directly on, directly connected to or directly attached to the other element or layer, or there may be one or more intermediate elements or layers.

[0059] Throughout this disclosure, the same reference numerals refer to the same elements. In the accompanying drawings, the thickness, scale, and dimensions of components may be exaggerated to effectively describe the technical content.

[0060] As used herein, the term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0061] It will be understood that while terms such as first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of this disclosure, the first element, first component, first region, first layer, or first part discussed below may be referred to as a second element, second component, second region, second layer, or second part. As used herein, the singular forms such as “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0062] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “up” may be used in this document to describe the relationship between one element or feature and another element(s) as shown in the accompanying figures.

[0063] Unless otherwise specified, the terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0064] It will also be understood that, when used in this disclosure, the terms “comprising” and / or “including” specify the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0065] The present disclosure will be described in detail below with reference to the accompanying drawings.

[0066] Figure 1 This is a block diagram illustrating a display device DD according to an exemplary embodiment of the present disclosure. Figure 2 It shows Figure 1 The equivalent circuit diagram of a pixel PX shown in the figure, and Figure 3 It shows the method for driving. Figure 2 The waveform diagram of the driving signal of pixel PX shown.

[0067] refer to Figure 1 The display device DD includes a signal controller 100, a gate driver 200, a data driver 300, a drive voltage generator 400, an initialization voltage generator 500, and a display panel DP.

[0068] The signal controller 100 receives an input image signal (not shown), converts the data format of the input image signal into a data format suitable for the interface to the data driver 300, and generates image data RGB. The signal controller 100 outputs the image data RGB and the data control signal DCS to the data driver 300.

[0069] Gate driver 200 receives gate control signal GCS from signal controller 100. Gate control signal GCS may include a vertical start signal that initiates operation of gate driver 200 and a clock signal that determines the output timing of the signals. Gate driver 200 can generate multiple gate signals and sequentially output them to multiple gate lines GIL1 to GILn and GWL1 to GWLn. Furthermore, gate driver 200 can generate multiple light emission control signals in response to gate control signal GCS and output these signals to multiple light emission control lines EL1 to ELn.

[0070] exist Figure 1 The diagram shows the gate driver 200 outputting a gate signal and a light emission control signal; however, this disclosure should not be limited thereto. In one embodiment of this disclosure, the driving circuit for generating and outputting the gate signal and the driving circuit for generating and outputting the light emission control signal may be provided separately.

[0071] The data driver 300 receives a data control signal DCS and image data RGB from the signal controller 100. The data driver 300 converts the image data RGB into a data signal and outputs the data signal to multiple data lines DL1 to DLm. The data signal can be an analog voltage corresponding to the grayscale value of the image data RGB.

[0072] According to an exemplary embodiment, the gate driver 200 and the data driver 300 can be collectively referred to as a panel driver for driving the display panel DP.

[0073] The drive voltage generator 400 receives a power supply voltage Vin from a power source (not shown). The drive voltage generator 400 can convert the power supply voltage Vin to generate a first drive voltage ELVDD and a second drive voltage ELVSS having a voltage level lower than that of the first drive voltage ELVDD.

[0074] The drive voltage generator 400 may include a DC-DC converter. The drive voltage generator 400 may include a boost converter that boosts the supply voltage Vin to generate a first drive voltage ELVDD. Furthermore, the drive voltage generator 400 may include a buck converter that bucks the supply voltage Vin to generate a second drive voltage ELVSS.

[0075] The drive voltage generator 400 receives a drive voltage control signal VCS from the signal controller 100. The drive voltage generator 400 can generate a first drive voltage ELVDD and a second drive voltage ELVSS in response to the drive voltage control signal VCS.

[0076] Initialization voltage generator 500 receives a first drive voltage ELVDD and a second drive voltage ELVSS from drive voltage generator 400. Initialization voltage generator 500 can generate an initialization voltage Vint using the first drive voltage ELVDD and the second drive voltage ELVSS. The initialization voltage Vint can have a voltage level different from the voltage level of the first drive voltage ELVDD or the voltage level of the second drive voltage ELVSS.

[0077] The display panel DP includes gate lines GIL1 to GILn and GWL1 to GWLn, light emission control lines EL1 to ELn, data lines DL1 to DLm, and a plurality of pixels PX. The gate lines GIL1 to GILn and GWL1 to GWLn extend in a first direction DR1 and are arranged in a second direction DR2 perpendicular to the first direction DR1. Each of the light emission control lines EL1 to ELn is arranged substantially parallel to the corresponding gate line among the gate lines GIL1 to GILn and GWL1 to GWLn. The data lines DL1 to DLm are insulated from the gate lines GIL1 to GILn and GWL1 to GWLn while intersecting with them.

[0078] Each pixel PX is connected to the corresponding gate line in gate lines GIL1 to GILn and GWL1 to GWLn, the corresponding light emission control line in light emission control lines EL1 to ELn, and the corresponding data line in data lines DL1 to DLm. Figure 1 An example of two gate lines connected to gate lines GIL1 to GILn and GWL1 to GWLn in each pixel PX is shown; however, this disclosure should not be limited thereto or thereby restricted. For example, each pixel PX may be connected to one gate line or three or more gate lines.

[0079] The display panel DP receives a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD is provided to the pixel PX via a first power line PL1. The second driving voltage ELVSS is provided to the pixel PX via an electrode (not shown) formed in the display panel DP and / or a second power line PL2.

[0080] The display panel (DP) receives the initialization voltage Vint. The initialization voltage Vint is provided to the pixel (PX) via the initialization voltage line (VIL).

[0081] refer to Figure 2 A pixel (PX) includes a light-emitting element (LD) and a circuitry (CC) that controls the light emission of the LD. A pixel (PX) included in a display panel (DP) may include red pixels that emit red light, green pixels that emit green light, and blue pixels that emit blue light. The light-emitting elements of the red pixels, green pixels, and blue pixels may include organic light-emitting layers made of materials different from each other.

[0082] The circuit section CC includes multiple transistors T1 to T7 (e.g., thin-film transistors) and a capacitor CP. In response to the data signal and gate signal provided to the pixel PX, the transistors T1 to T7 and the capacitor CP control the amount of current flowing through the light-emitting element LD.

[0083] Each of transistors T1 through T7 includes an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In this disclosure, for ease of explanation, one of the input and output electrodes is referred to as the "first electrode," and the other is referred to as the "second electrode." Hereinafter, for ease of explanation, transistors T1, T2, T3, T4, T5, T6, and T7 are referred to as first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7, respectively.

[0084] The first electrode of the first transistor T1 is connected to the first power line PL1 via the fifth transistor T5. The first drive voltage ELVDD is provided to the first power line PL1. The second electrode of the first transistor T1 is connected to the anode of the light-emitting element LD via the sixth transistor T6.

[0085] In response to the voltage applied to the control electrode of the first transistor T1, the first transistor T1 controls the amount of current flowing through the light-emitting element LD.

[0086] The second transistor T2 is connected between the first data line DL1 and the first electrode of the first transistor T1. The control electrode of the second transistor T2 is connected to the first current gate line GWL1. When a first current gate signal is provided to the first current gate line GWL1, the second transistor T2 is turned on, and the first data line DL1 is electrically connected to the first electrode of the first transistor T1.

[0087] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the first current gate line GWL1. When a first current gate signal is provided to the first current gate line GWL1, the third transistor T3 is turned on, and the second electrode of the first transistor T1 is electrically connected to the control electrode of the first transistor T1, such that the first transistor T1 is connected in a diode configuration.

[0088] The fourth transistor T4 is connected between node ND and the initialization voltage line VIL. The control electrode of the fourth transistor T4 is connected to the first previous gate line GIL1. Node ND is connected to the control electrodes of the fourth transistor T4 and the first transistor T1. When the first previous gate signal is supplied to the first previous gate line GIL1, the fourth transistor T4 is turned on, and the initialization voltage Vint is supplied to node ND.

[0089] The fifth transistor T5 is connected between the first power line PL1 and the first electrode of the first transistor T1. The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode of the light-emitting element LD. The control electrodes of the fifth transistor T5 and the sixth transistor T6 are connected to the first light-emitting control line EL1.

[0090] The seventh transistor T7 is connected between the initialization voltage line VIL and the anode of the light-emitting element LD. The control electrode of the seventh transistor T7 is connected to the first current gate line GWL1. When the first current gate signal is provided to the first current gate line GWL1, the seventh transistor T7 is turned on, and the initialization voltage Vint is provided to the anode of the light-emitting element LD.

[0091] The seventh transistor T7 improves the black level performance of pixel PX. More specifically, when the seventh transistor T7 is turned on, an initialization voltage Vint is provided via the seventh transistor T7, and the parasitic capacitance (not shown) of the light-emitting element LD can discharge. Therefore, when a data signal corresponding to black brightness is received via the first data line DL1, despite leakage current flowing through the first transistor T1, the light-emitting element LD can accurately represent black brightness without emitting light, and thus, pixel PX can have improved black level performance.

[0092] although Figure 2The control electrode of the seventh transistor T7 is shown to be connected to the first current gate line GWL1, but this disclosure should not be limited thereto or thereby restricted. In another embodiment, the control electrode of the seventh transistor T7 may be connected to another gate line, for example, to the second current gate line GWL2 (see reference). Figure 1 The second current gate line GWL2 provides a different gate signal than the first current gate signal.

[0093] The first transistors T1 through the seventh transistor T7 can be implemented as P-type metal-oxide-semiconductor (PMOS) transistors; however, they should not be limited to or restricted by this. In some embodiments, some or all of the first transistors T1 through the seventh transistor T7 can be implemented as N-type metal-oxide-semiconductor (NMOS) transistors.

[0094] A capacitor CP is positioned between the first power line PL1 and node ND. The capacitor CP can be charged with a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on by the first light-emitting control signal provided via the first light-emitting control line EL1, the amount of current flowing through the first transistor T1 is determined by the voltage charged in the capacitor CP.

[0095] The light-emitting element LD is electrically connected to the sixth transistor T6 and the second power line PL2. The anode of the light-emitting element LD is connected to the sixth transistor T6, and the cathode of the light-emitting element LD is connected to the second power line PL2. A second driving voltage ELVSS is applied to the second power line PL2. The second driving voltage ELVSS has a lower voltage level than the first driving voltage ELVDD. Therefore, the light-emitting element LD emits light in response to the voltage difference between the signal transmitted via the sixth transistor T6 and the second driving voltage ELVSS provided via the second power line PL2.

[0096] refer to Figures 1 to 3 The display device DD displays the unit image in each frame period Fk-1, Fk and Fk+1. Figure 1 Each of the pixels PX shown receives a corresponding data signal in each frame period Fk-1, Fk, or Fk+1.

[0097] Figure 3 It shows Figure 2 The frame periods Fk-1, Fk, and Fk+1 of pixel PX are shown. In the following description, the driving signals used to drive pixel PX will be described with focus on the k-th frame period Fk. The k-th frame period Fk includes the scan period Sk and the emission period Ek.

[0098] During the scan cycle Sk, the first previous gate signal GIS1 is applied to the first previous gate line GIL1. Figure 3In the diagram, the signal is shown as being activated when the signal has a low level. Figure 3 A low level of the signal shown may correspond to the on-state voltage of the transistor to which the signal is applied. However, it should be noted that this disclosure is not limited thereto or thereby, and a high level of the signal may also be used to activate the corresponding signal.

[0099] In response to the first prior gate signal GIS1, node ND is initialized to the initialization voltage Vint.

[0100] Following the first previous gate signal GIS1, a first current gate signal GWS1 is applied to the first current gate line GWL1 during the scan cycle Sk. The second transistor T2 and the third transistor T3 are turned on by the first current gate signal GWS1, and the data signal applied to the first data line DL1 is provided to node ND.

[0101] Subsequently, during the emission period Ek, a current path is formed between node ND and the light-emitting element LD by applying the light-emitting control signal ES to the first light-emitting control line EL1. Figure 3 In the diagram, the light emission control signal ES is shown to be low during the emission period Ek. Therefore, the light-emitting element LD emits light during the emission period Ek. The light emission control signal ES may be inactive during the scan period Sk, and the light emission control signal ES may be high during the scan period Sk.

[0102] Figure 4 It shows Figure 1 The internal block diagram of the signal controller 100 shown, and Figure 5 It shows Figure 1 The diagram shows a plan view of the display surface of the display panel DP.

[0103] refer to Figure 4 and Figure 5 According to an exemplary embodiment of the present disclosure, the signal controller 100 includes a speckle region extractor 111, a dithering processor 113, and a memory 115.

[0104] The speckle region extractor 111 receives the input image signal I_DATA from an external device (not shown). The speckle region extractor 111 can then display the input image signal I_DATA on the display panel DP (reference). Figure 1 The speckled regions SA in which speckles appear are extracted from the display surface DS. The display surface DS includes the speckled regions SA in which speckles appear and the non-spotted regions NSA in which no speckles appear.

[0105] Figure 5A spot region SA on the display surface DS is shown; however, this disclosure should not be limited to or construed as such. That is, based on the grayscale information of the displayed image, the spot region extractor 111 can extract one or more spot regions SA on the display surface DS. Furthermore, Figure 5 The dotted region SA shown has a quadrilateral shape; however, the shape of the dotted region SA should not be limited to a quadrilateral shape. As an example, the dotted region SA can have a regular shape such as a circle or a rhombus, or it can have an irregular shape.

[0106] After detecting a blob region SA, the blob region extractor 111 provides the jitter processor 113 with an image signal DATA_S corresponding to the detected blob region SA from the input image signal I_DATA. In the case of detecting multiple blob regions SA, the blob region extractor 111 can provide the jitter processor 113 with an image signal DATA_S corresponding to each blob region SA.

[0107] The jitter processor 113 performs jitter on the image signal DATA_S received from the speckle region extractor 111. When the speckle region extractor 111 does not detect any speckle regions SA, the jitter processor 113 may not perform jitter. That is, when the speckle region extractor 111 does not detect any speckle regions SA, the display surface DS only includes non-speculiar regions NSA, and the jitter processor 113 may not perform jitter.

[0108] The speckle region extractor 111 outputs a compensation control signal CS to control the operation of the jitter processor 113. The jitter processor 113 performs jitter operations in response to the compensation control signal CS. For example, when the speckle region extractor 111 does not detect a speckle region SA, the speckle region extractor 111 provides the jitter processor 113 with a compensation control signal CS in a first state, and the jitter processor 113 does not perform jitter operations in response to the compensation control signal CS in the first state. When the speckle region extractor 111 detects a speckle region SA, the speckle region extractor 111 provides the jitter processor 113 with a compensation control signal CS in a second state, and the jitter processor 113 performs jitter operations in response to the compensation control signal CS in the second state.

[0109] The jitter processor 113 receives a dither pattern (DTP) from the memory 115 to perform jitter operations. The memory 115 may include a lookup table storing the dither pattern DTP corresponding to the image signal DATA_S. In one embodiment, the jitter processor 113 may send a request signal RS to the memory 115, and the memory 115 may provide the jitter pattern DTP corresponding to the image signal DATA_S to the jitter processor 113.

[0110] The jitter processor 113 reflects the jitter pattern DTP received from the memory 115 to the image signal DATA_S and outputs the compensated image signal DATA_D. The signal controller 100 combines the compensated image signal DATA_D corresponding to the speckle region SA and the uncompensated image signal corresponding to the non-speculiar region NSA, and provides the combined signal to the data driver 300. Figure 1 As shown in the figure, this allows the data driver 300 to output a data signal corresponding to the spot region SA.

[0111] Figure 6 It shows the relationship with Figure 5 The jitter pattern corresponding to the first region A1 shown, and Figure 7 It is shown in units of frame period Figure 6 The jittering pattern shown. Figure 8A It shows the target in frame period units. Figure 7 The chart showing the grayscale values ​​of the first part C1, and... Figure 8B It shows the target in frame period units. Figure 7 The chart shows the grayscale values ​​of the second part, C2.

[0112] Figure 6 It shows the relationship with Figure 5 The example shown is a dithering pattern DTP corresponding to a region of the spot region SA (e.g., the first region A1). As an exemplary embodiment of this disclosure, each of the dithering pattern DTPs may include 5 by 5 (5×5) grayscale regions. However, this is merely an example, and the number of grayscale regions included in each dithering pattern DTP should not be limited thereto or thereby restricted. That is, each dithering pattern DTP may include N by N (N×N) grayscale regions, and “N” may be a natural number greater than or equal to 1.

[0113] As an example of this disclosure, a spatially distributed dithering pattern DTP is configured to correspond to a first region A1; however, this disclosure should not be limited thereto or thereby restricted. A dithering pattern DTP may be configured to have a size corresponding to the size of the first region A1. The first region A1 may correspond to regions having the same target grayscale value. The speckle region SA may include multiple regions having target grayscale values ​​different from each other.

[0114] In one embodiment, the grayscale regions arranged in each dithering pattern DTP are divided into a first grayscale region GA1 and a second grayscale region GA2. The first grayscale region GA1 may correspond to a region having a grayscale value higher than the target grayscale value to be displayed in the first region A1, and the second grayscale region GA2 may correspond to a region having a grayscale value lower than the target grayscale value. Therefore, the grayscale difference between the first grayscale region GA1 and the second grayscale region GA2 may be greater than one grayscale value, for example, equal to or greater than two grayscale values. In one embodiment of this disclosure, the average of the grayscale values ​​of the first grayscale region GA1 and the second grayscale region GA2 may be approximately the same as the target grayscale value.

[0115] In this exemplary embodiment, each of the first grayscale region GA1 and the second grayscale region GA2 can correspond to a pixel region, wherein each pixel PX of the display panel DP is disposed in the pixel region. Figure 1 (as shown in the diagram), however, this disclosure should not be limited thereto or thereby restricted. That is, each of the first grayscale region GA1 and the second grayscale region GA2 may correspond to two or more pixel regions.

[0116] The first grayscale region GA1 and the second grayscale region GA2 can be distributed in each dithering pattern DTP. For ease of explanation, in Figure 6 and Figure 7 In the image, the first grayscale region GA1 is indicated by a white region, and the second grayscale region GA2 is indicated by a shaded region.

[0117] refer to Figure 7 The first grayscale region GA1 and the second grayscale region GA2 of the dithering pattern DTP are arranged differently according to a predetermined time. Within a frame period, the first grayscale region GA1 and the second grayscale region GA2 of the dithering pattern DTP can have different arrangements. That is, within a frame period, the dithering pattern DTP can have different patterns.

[0118] The dithering pattern DTP can have different first, second, third, and fourth patterns during consecutive frame periods F1, F2, F3, and F4. Within each frame period from F1 to F4, the dithering pattern DTP can be randomly selected from K different patterns. Here, "K" is a natural number equal to or greater than 2.

[0119] During the first frame period F1, the dither pattern DTP has a first dither pattern. In the first dither pattern, a first portion C1 of the dither pattern DTP is set to a first grayscale region GA1, and a second portion C2 of the dither pattern DTP is set to a second grayscale region GA2.

[0120] During the second frame period F2, the dither pattern DTP can have a second dither pattern that is different from the first dither pattern. In the second dither pattern, the first portion C1 and the second portion C2 of the dither pattern DTP are set to the second grayscale region GA2.

[0121] During the third frame period F3, the dither pattern DTP has a third dither pattern that is different from the first and second dither patterns. In the third dither pattern, the first portion C1 and the second portion C2 of the dither pattern DTP are set to the first grayscale region GA1.

[0122] During the fourth frame period F4, the dither pattern DTP has a fourth dither pattern that is different from the first dither pattern, the second dither pattern, and the third dither pattern. In the fourth dither pattern, the first part C1 of the dither pattern DTP is set to the second grayscale region GA2, and the second part C2 of the dither pattern DTP is set to the first grayscale region GA1.

[0123] Figure 8A and Figure 8B An example is shown where the target grayscale value T-gray of the dithering pattern DTP is 4. A first grayscale region GA1 has a grayscale value higher than the target grayscale value T-gray (e.g., 8), and a second grayscale region GA2 has a grayscale value lower than the target grayscale value T-gray (e.g., 0). In this example, the grayscale difference between the first grayscale region GA1 and the second grayscale region GA2 is 8 grayscale levels.

[0124] refer to Figure 7 as well as Figure 8A and Figure 8B The first part C1 has a grayscale value of 8 during the first frame period F1 and the third frame period F3, and a grayscale value of 0 during the second frame period F2 and the fourth frame period F4. The second part C2 has a grayscale value of 0 during the first frame period F1 and the second frame period F2, and a grayscale value of 8 during the third frame period F3 and the fourth frame period F4.

[0125] When the jitter processor 113 uses the jitter pattern DTP distributed in time and space to analyze the image signal DATA_S of the speckle region SA, Figure 4 When performing a dithering operation (as shown), the display device DD can prevent spots from being observed in the area of ​​the display surface DS that is detected as a spot area SA.

[0126] Figure 9 This is an internal block diagram of a signal controller 105 according to an exemplary embodiment of the present disclosure, and Figure 10 This is a plan view showing the display surface of a display panel DP according to an exemplary embodiment of the present disclosure. Figure 9 In the same figures, the same reference numerals refer to Figure 4 The same elements will be omitted, and detailed descriptions of the same elements will be omitted.

[0127] refer to Figure 9 and Figure 10 The signal controller 105 includes a spot region extractor 111, a jitter processor 113, a first memory 115, a boundary region setting unit 121, a boundary jitter processor 123, and a second memory 125.

[0128] The speckle region extractor 111 and the boundary region setting unit 121 receive the input image signal I_DATA from an external device (not shown). The speckle region extractor 111 can, based on the input image signal I_DATA, set the boundary region on the display panel DP (…). Figure 1 The display surface DS (shown in the figure) includes spot regions SA1 and SA2 in which spots appear, and non-spot regions NSA in which no spots appear. As an example, spot regions SA1 and SA2 include a first spot region SA1 and a second spot region SA2. The first spot region SA1 and the second spot region SA2 may differ from each other in their size and / or shape.

[0129] A non-blobular NSA can include boundary regions BA1 and BA2 surrounding blobular regions SA1 and SA2, respectively. In a non-blobular NSA, the remaining regions besides boundary regions BA1 and BA2 can correspond to the uncompensated region NCA. That is, a non-blobular NSA includes boundary regions BA1 and BA2 and the uncompensated region NCA. Figure 10 As shown, the boundary regions BA1 and BA2 include a first boundary region BA1 surrounding the first spot region SA1 and a second boundary region BA2 surrounding the second spot region SA2.

[0130] When the spot region extractor 111 detects the first spot region SA1 and the second spot region SA2, the spot region extractor 111 provides the jitter processor 113 with the first image signal DATA_S1 corresponding to the first spot region SA1 and the second image signal DATA_S2 corresponding to the second spot region SA2 in the input image signal I_DATA.

[0131] The jitter processor 113 performs jitter operations on the first image signal DATA_S1 and the second image signal DATA_S2 received from the speckle region extractor 111. In this exemplary embodiment, the jitter operation performed on the first speckle region SA1 is referred to as the "first jitter operation", and the jitter operation performed on the second speckle region SA2 is referred to as the "second jitter operation".

[0132] The jitter processor 113 receives a first jitter pattern DTP1 and a second jitter pattern DTP2 from the first memory 115 to perform a first jitter operation and a second jitter operation, respectively. The first memory 115 may include a lookup table storing the first jitter pattern DTP1 for a first image signal DATA_S1 and the second jitter pattern DTP2 for a second image signal DATA_S2. In one embodiment, the jitter processor 113 may send a request signal RS1 to the first memory 115, and the first memory 115 may provide the first jitter pattern DTP1 and the second jitter pattern DTP2 to the jitter processor 113.

[0133] The jitter processor 113 reflects the first jitter pattern DTP1 received from the first memory 115 to the first image signal DATA_S1 and outputs the first compensated image signal DATA_D1. It also reflects the second jitter pattern DTP2 received from the first memory 115 to the second image signal DATA_S2 and outputs the second compensated image signal DATA_D2.

[0134] The speckle region extractor 111 can provide information PI related to the extracted speckle regions SA1 and SA2 to the boundary region setting unit 121. As an example, the information PI may include first information related to the first speckle region SA1 and second information related to the second speckle region SA2. Based on the information PI, the boundary region setting unit 121 sets boundary regions BA1 and BA2 surrounding the speckle regions SA1 and SA2 in the input image signal I_DATA, and outputs image signals corresponding to the boundary regions BA1 and BA2 to the boundary jitter processor 123 as boundary image signals DATA_B1 and DATA_B2. Specifically, the boundary region setting unit 121 outputs a first boundary image signal DATA_B1 corresponding to the first boundary region BA1 and a second boundary image signal DATA_B2 corresponding to the second boundary region BA2 to the boundary jitter processor 123. Furthermore, the boundary region setting unit 121 outputs a boundary compensation control signal BCS to the boundary jitter processor 123.

[0135] The boundary jitter processor 123 performs jitter operations on the boundary image signals DATA_B1 and DATA_B2. In response to the boundary compensation control signal BCS received from the boundary region setting unit 121, the boundary jitter processor 123 performs jitter operations on the boundary regions BA1 and BA2. Here, the jitter operation performed on the first boundary region BA1 is referred to as the "first boundary jitter operation," and the jitter operation performed on the second boundary region BA2 is referred to as the "second boundary jitter operation."

[0136] Boundary jitter processor 123 receives a first boundary jitter pattern BTP1 from second memory 125 to perform a first boundary jitter operation, and receives a second boundary jitter pattern BTP2 from second memory 125 to perform a second boundary jitter operation. Second memory 125 includes a lookup table storing the first boundary jitter pattern BTP1 for a first boundary image signal DATA_B1 and the second boundary jitter pattern BTP2 for a second boundary image signal DATA_B2. In one embodiment, boundary jitter processor 123 may send a request signal RS2 to second memory 125, and second memory 125 may provide the first boundary jitter pattern BTP1 and the second boundary jitter pattern BTP2 to boundary jitter processor 123.

[0137] The boundary jitter processor 123 reflects the first boundary jitter pattern BTP1 received from the second memory 125 to the first boundary image signal DATA_B1 and outputs the first boundary compensation image signal DATA_DB1. It also reflects the second boundary jitter pattern BTP2 received from the second memory 125 to the second boundary image signal DATA_B2 and outputs the second boundary compensation image signal DATA_DB2.

[0138] Signal controller 105 combines the first compensated image signal DATA_D1 and the second compensated image signal DATA_D2 output from jitter processor 113, and the first boundary compensated image signal DATA_DB1 and the second boundary compensated image signal DATA_DB2 output from boundary jitter processor 123 with the uncompensated image signal corresponding to the uncompensated region NCA, and provides the combined signal to data driver 300. Figure 1 (as shown in the image).

[0139] Figure 11A It shows the relationship with Figure 10 An example of the first jitter pattern corresponding to region D1 of the first spot region SA1 shown in the figure. Figure 11B It shows the relationship with Figure 10 An example of the first boundary jitter pattern corresponding to region D2 of the first boundary region BA1 shown, and Figure 11C An example of a first boundary jitter pattern according to another exemplary embodiment of this disclosure is shown.

[0140] Figure 11A It shows the relationship with Figure 10 The example shown is of a first dithering pattern DTP1 corresponding to region D1 of the first spot region SA1. Each of the first dithering patterns DTP1 defines a plurality of grayscale regions. As an example, each of the first dithering patterns DTP1 includes 5 by 5 (5×5) grayscale regions. However, this is merely an example, and the number of grayscale regions should not be limited thereto or thereby restricted. In this exemplary embodiment, region D1 may correspond to regions having the same target grayscale value. The first spot region SA1 may include a plurality of regions having target grayscale values ​​that are different from each other.

[0141] The grayscale region can be divided into a first grayscale region GA1 and a second grayscale region GA2. The first grayscale region GA1 may correspond to a region with a grayscale value higher than the target grayscale value to be displayed in region D1, and the second grayscale region GA2 may correspond to a region with a grayscale value lower than the target grayscale value. Therefore, the grayscale difference between the first grayscale region GA1 and the second grayscale region GA2 can be greater than one grayscale value. In one embodiment of this disclosure, the average of the grayscale values ​​of the first grayscale region GA1 and the second grayscale region GA2 can be approximately the same as the target grayscale value.

[0142] As an example, each of the first grayscale region GA1 and the second grayscale region GA2 can correspond to a region corresponding to a pixel region, wherein a [missing information] is provided in the pixel region. Figure 1 The individual pixels of the display panel DP shown in the diagram.

[0143] Figure 11B It shows the relationship with Figure 10 An example of a first boundary jitter pattern BTP1 corresponding to region D2 of the first boundary region BA1 shown. The first boundary region BA1 includes a boundary jitter region jittered by the first boundary jitter pattern BTP1 and a non-jitter region NDA that is not jittered. The first boundary jitter pattern BTP1 may include multiple boundary grayscale regions. In one embodiment, each of the first boundary jitter patterns BTP1 has approximately the same size as each of the first jitter patterns DTP1. Figure 11B Each of the first boundary dithering patterns BTP1 is shown to include 5 by 5 (5×5) boundary grayscale regions; however, the size of each of the first boundary dithering patterns BTP1 should not be limited by or constrained by this. For example, the size of each of the first boundary dithering patterns BTP1 may be larger or smaller than the size of each of the first dithering patterns DTP1.

[0144] The boundary grayscale regions are divided into a first boundary grayscale region BGA1 and a second boundary grayscale region BGA2. The first boundary grayscale region BGA1 may correspond to a region having a grayscale value higher than the target grayscale value to be displayed in each of the first boundary dithering patterns BTP1, and the second boundary grayscale region BGA2 may correspond to a region having a grayscale value lower than the target grayscale value. Therefore, the grayscale difference between the first boundary grayscale region BGA1 and the second boundary grayscale region BGA2 may be greater than one grayscale value, for example, equal to or greater than two grayscale values. In one embodiment of this disclosure, the average of the grayscale values ​​of the first boundary grayscale region BGA1 and the second boundary grayscale region BGA2 may be approximately the same as the target grayscale value.

[0145] like Figure 11B As shown, each of the first boundary dithering patterns BTP1 has approximately the same size as the first dithering pattern DTP1, and the size of each of the boundary grayscale regions BGA1 and BGA2 can be the same as... Figure 11A The grayscale regions GA1 and GA2 shown are each approximately the same size.

[0146] like Figure 11B As shown, the non-jittering region NDA is disposed between the boundary jittering regions jittered by the first boundary jittering pattern BTP1. Therefore, the density of the first boundary jittering pattern BTP1 in the first boundary region BA1 is less than the density of the first jittering pattern DTP1 in the first spot region SA1. That is, within the same size region, the number of first boundary jittering patterns BTP1 is less than the number of first jittering patterns DTP1.

[0147] Figure 11C The dimensions of each of the boundary grayscale regions BGA1 and BGA2 are larger than those of grayscale regions GA1 and GA2. Figure 11A An exemplary implementation of the dimensions of each of the following (shown in the diagram). In this example, the first boundary grayscale region BGA1 has a larger size than the first dithering pattern DTP1. Figure 11AThe size of the first grayscale region GA1 (shown in the diagram) is 5×5 times larger. That is, each of the first grayscale region GA1 and the second grayscale region GA2 can correspond to one pixel region, but each of the first boundary grayscale region BGA1 and the second boundary grayscale region BGA2 can correspond to 5 by 5 (5×5) pixel regions. In this case, each of the first boundary dithering patterns BTP1 can have a size 5×5 times larger than the size of each of the first dithering patterns DTP1. However, the size and number of pixel regions in each of the first boundary dithering patterns BTP1 should not be limited by this or by it, and can be changed in a variety of ways. As described above, because each of the first boundary dithering patterns BTP1 can have a size larger than the size of the first dithering pattern DTP1, the density of the first boundary dithering patterns BTP1 in the first boundary region BA1 can be less than the density of the first dithering patterns DTP1 in the first spot region SA1.

[0148] Boundary regions BA1 and BA2, which perform boundary dithering operations using boundary dithering patterns BTP1 and BTP2 set at a lower density than the dithering patterns DTP1 and DTP2 of the spot regions SA1 and SA2, are set between the spot regions SA1 and SA2 and the uncompensated region NCA. Therefore, the display device DD can prevent the boundary between the spot regions SA1 and SA2 and the uncompensated region NCA from being observed by the user.

[0149] Figure 12 This is a plan view showing the display surface DS of a display panel DP according to an exemplary embodiment of the present disclosure.

[0150] refer to Figure 12 The surface DS includes a speckled region SA1 in which speckles appear and a non-speckled region NSA in which no speckles appear. The non-speckled region NSA may include a first sub-boundary region SBA1 surrounding the speckled region SA1 and a second sub-boundary region SBA2 surrounding the first sub-boundary region SBA1. In the non-speckled region NSA, the remaining regions besides the first sub-boundary region SBA1 and the second sub-boundary region SBA2 may correspond to the uncompensated region NCA. That is, the non-speckled region NSA includes the first sub-boundary region SBA1, the second sub-boundary region SBA2, and the uncompensated region NCA.

[0151] Figure 12 Two sub-boundary regions, SBA1 and SBA2, surrounding the blob region SA1 are shown; however, the number of sub-boundary regions surrounding the blob region SA1 should not be limited to two. That is, two or more sub-boundary regions can be defined around the blob region SA1.

[0152] Figure 13A It shows Figure 12 The first jitter pattern in region E1 shown, Figure 13B It shows Figure 12 The first sub-boundary jitter pattern of region E2 shown, and Figure 13C It shows Figure 12 The second sub-boundary jitter pattern of region E3 shown.

[0153] Figure 13A It shows the relationship with Figure 12 The example shown is of a dithering pattern DTP corresponding to region E1 of the speckle region SA1. Each dithering pattern DTP defines multiple grayscale regions. As an example, each dithering pattern DTP includes 5 by 5 (5×5) grayscale regions. However, this is merely an example, and the number of grayscale regions should not be limited by this or by this. In this exemplary embodiment, region E1 may correspond to regions having the same target grayscale value. The speckle region SA1 may include multiple regions having target grayscale values ​​different from each other.

[0154] The grayscale region can be divided into a first grayscale region GA1 and a second grayscale region GA2. The first grayscale region GA1 may correspond to a region with a grayscale value higher than the target grayscale value to be displayed in region E1, and the second grayscale region GA2 may correspond to a region with a grayscale value lower than the target grayscale value. Therefore, the grayscale difference between the first grayscale region GA1 and the second grayscale region GA2 can be greater than one grayscale value. In one embodiment of this disclosure, the average of the grayscale values ​​of the first grayscale region GA1 and the second grayscale region GA2 can be approximately the same as the target grayscale value.

[0155] As an example, each of the first grayscale region GA1 and the second grayscale region GA2 can correspond to a region corresponding to a pixel region, wherein a [missing information] is provided in the pixel region. Figure 1 The individual pixels of the display panel DP shown in the diagram.

[0156] Figure 13B It shows the relationship with Figure 12 An example of a first sub-boundary dithering pattern STP1 corresponding to region E2 of the first sub-boundary region SBA1 is shown. The first sub-boundary region SBA1 includes a sub-boundary dithering region dithered by the first sub-boundary dithering pattern STP1 and a first non-dithering region NDA1 that is not dithered. The first sub-boundary dithering pattern STP1 may include multiple sub-boundary grayscale regions. In one embodiment, each of the first sub-boundary dithering patterns STP1 has approximately the same size as the dithering pattern DTP. Figure 13BThe diagram shows that each of the first sub-boundary dithering patterns STP1 comprises 5 by 5 (5×5) sub-boundary grayscale regions; however, the size of the first sub-boundary dithering pattern STP1 should not be limited by or constrained by this. For example, the size of each of the first sub-boundary dithering patterns STP1 may be larger or smaller than the size of each of the dithering patterns DTP.

[0157] The sub-boundary grayscale region is divided into a first sub-boundary grayscale region SGA1 and a second sub-boundary grayscale region SGA2. The first sub-boundary grayscale region SGA1 may correspond to a region with a grayscale value higher than the target grayscale value to be displayed in region E2, and the second sub-boundary grayscale region SGA2 may correspond to a region with a grayscale value lower than the target grayscale value. Therefore, the grayscale difference between the first sub-boundary grayscale region SGA1 and the second sub-boundary grayscale region SGA2 may be greater than one grayscale value, for example, equal to or greater than two grayscale values. In one embodiment of this disclosure, the average of the grayscale values ​​of the first sub-boundary grayscale region SGA1 and the second sub-boundary grayscale region SGA2 may be approximately the same as the target grayscale value.

[0158] like Figure 13B As shown, each of the first sub-boundary dithering patterns STP1 has approximately the same size as the dithering pattern DTP, and the size of each of the sub-boundary grayscale regions SGA1 and SGA2 can be the same as... Figure 13A The grayscale regions GA1 and GA2 shown are each approximately the same size.

[0159] like Figure 13B As shown, the first non-jittering region NDA1 is disposed between the sub-boundary jittering regions jittered by the first sub-boundary jittering pattern STP1. Therefore, the density of the first sub-boundary jittering pattern STP1 in the first sub-boundary region SBA1 is less than the density of the jittering pattern DTP in the spot region SA1. That is, within the same size region, the number of first sub-boundary jittering patterns STP1 is less than the number of jittering patterns DTP.

[0160] Figure 13B The first sub-boundary jitter pattern STP1 and the first non-jitter region NDA1 are shown to have approximately the same size; however, this disclosure should not be limited thereto or thereby restricted. In some embodiments, the size of the first non-jitter region NDA1 may be half the size of each of the first sub-boundary jitter patterns STP1, or may be twice the size of each of the first sub-boundary jitter patterns STP1.

[0161] Figure 13C It shows the relationship with Figure 12The example shown is of a second sub-boundary dithering pattern STP2 corresponding to region E3 of the second sub-boundary region SBA2. The second sub-boundary region SBA2 includes a sub-boundary dithering region dithered by the second sub-boundary dithering pattern STP2 and a second non-dithering region NDA2 that is not dithered. The second sub-boundary dithering pattern STP2 may include multiple sub-boundary grayscale regions. In one embodiment, each of the second sub-boundary dithering patterns STP2 has approximately the same size as the dithering pattern DTP. Figure 13C The diagram shows that each of the second sub-boundary dithering patterns STP2 comprises 5 by 5 (5×5) sub-boundary grayscale regions; however, the size of the second sub-boundary dithering pattern STP2 should not be limited by or constrained by this. For example, the size of each of the second sub-boundary dithering patterns STP2 can be larger or smaller than the size of each of the dithering patterns DTP.

[0162] The second sub-boundary dithering pattern STP2 includes multiple sub-boundary grayscale regions. As an example, each of the second sub-boundary dithering patterns STP2 includes 5 by 5 (5×5) sub-boundary grayscale regions. However, this is merely an example, and the number of sub-boundary grayscale regions included in the second sub-boundary dithering pattern STP2 should not be limited by this or by this limitation.

[0163] The sub-boundary grayscale region is divided into a third sub-boundary grayscale region SGA3 and a fourth sub-boundary grayscale region SGA4. The third sub-boundary grayscale region SGA3 may correspond to a region with a grayscale value higher than the target grayscale value to be displayed in region E3, and the fourth sub-boundary grayscale region SGA4 may correspond to a region with a grayscale value lower than the target grayscale value. Therefore, the grayscale difference between the third sub-boundary grayscale region SGA3 and the fourth sub-boundary grayscale region SGA4 can be greater than one grayscale value, for example, equal to or greater than two grayscale values. In one embodiment of this disclosure, the average grayscale value of the third sub-boundary grayscale region SGA3 and the fourth sub-boundary grayscale region SGA4 can be approximately the same as the target grayscale value.

[0164] like Figure 13C As shown, each of the second sub-boundary dithering patterns STP2 has approximately the same size as each of the dithering patterns DTP, and the size of each of the sub-boundary grayscale regions SGA3 and SGA4 can be the same as... Figure 13A The grayscale regions GA1 and GA2 shown are each approximately the same size.

[0165] like Figure 13CAs shown, the second non-jittering region NDA2 is disposed between the sub-boundary jittering regions jittered by the second sub-boundary jittering pattern STP2. Therefore, the density of the second sub-boundary jittering pattern STP2 in the second sub-boundary region SBA2 is less than the density of the jittering pattern DTP in the spot region SA1. That is, within a region of the same size, the number of second sub-boundary jittering patterns STP2 is less than the number of jittering patterns DTP. Furthermore, the density of the second sub-boundary jittering pattern STP2 in the second sub-boundary region SBA2 is less than the density of the first sub-boundary jittering pattern STP1 in the first sub-boundary region SBA1.

[0166] exist Figure 13C In the middle, the second non-jitter region NDA2 has a larger size than the second sub-boundary jitter pattern STP2. Figure 13B The first non-jitter region NDA1 shown has a larger size than the first non-jitter region NDA1. In one embodiment, the second non-jitter region NDA2 has a size three times larger than the first non-jitter region NDA1. However, this disclosure should not be limited thereto or thereby. In some embodiments, the second non-jitter region NDA2 may have a size 1.5 times, 2 times, or 2.5 times larger than the first non-jitter region NDA1.

[0167] Figure 12 and Figures 13A to 13C An example of two sub-boundary regions SBA1 and SBA2 arranged around the spot region SA1 is shown; however, this disclosure should not be limited to or construed as such. That is, three or more sub-boundary regions may be arranged around the spot region SA1, and the size of the non-jittering regions NDA1 and NDA2 in each of the sub-boundary regions SBA1 and SBA2 may gradually increase with increasing distance from the spot region SA1.

[0168] As described above, sub-boundary regions SBA1 and SBA2 can be positioned between the speckle region SA1 and the uncompensated region NCA, and the density of the sub-boundary dithering patterns STP1 and STP2 in the sub-boundary regions SBA1 and SBA2 gradually decreases with increasing distance from the speckle region SA1. Therefore, the display device DD can effectively improve display quality by preventing the boundary between the speckle region SA1 and the uncompensated region NCA from being observed.

[0169] Figure 14 This is an internal block diagram of a signal controller 107 according to an exemplary embodiment of the present disclosure. Figure 15A This is a plan view of the display surface DS of the display panel DP in normal mode (also referred to herein as N-mode), and Figure 15B This is a plan view of the display surface DS of the display panel DP in low-frequency mode (also referred to herein as L-mode).

[0170] refer to Figure 14 , Figure 15A and Figure 15B The signal controller 107 includes a frequency comparator 131, a first memory 135, a first jitter processor 133, a spot region extractor 141, a second memory 145, and a second jitter processor 143.

[0171] Frequency comparator 131 will display panel DP ( Figure 1 The driving frequency FS (shown in the diagram) is compared with a predetermined reference frequency. For example, the reference frequency is approximately 60 Hz. The frequency comparator 131 determines the operating mode (e.g., normal mode and low-frequency mode) by comparing the driving frequency FS with the reference frequency. For example, if the driving frequency FS is equal to or greater than the reference frequency, the display panel DP is driven in normal mode, and if the driving frequency FS is less than the reference frequency, the display panel DP is driven in low-frequency mode.

[0172] Based on the determination that the display panel DP is driven in normal mode (i.e., N-mode), the frequency comparator 131 provides a first compensation control signal NCS to the first jitter processor 133. The first jitter processor 133 can perform jitter operation on the entire area of ​​the display surface DS. That is, the first jitter processor 133 can perform global jitter operation on the entire input image signal I_DATA in response to the first compensation control signal NCS.

[0173] The first jitter processor 133 may receive a global jitter pattern G_DTP for the entire area of ​​the display surface DS from the first memory 135 and perform a global jitter operation. The first memory 135 may include a lookup table storing the global jitter pattern G_DTP for the input image signal I_DATA. In one embodiment, the first jitter processor 133 sends a first request signal RS3 to the first memory 135, and the first memory 135 provides the global jitter pattern G_DTP to the first jitter processor 133.

[0174] The first jitter processor 133 reflects the global jitter pattern G_DTP received from the first memory 135 to the input image signal I_DATA, and outputs the first compensated image signal DATA_ND. Therefore, in normal mode, the signal controller 107 sends a signal to the data driver 300 ( Figure 1 (As shown in the diagram) provides a first compensated image signal DATA_ND for the entire area of ​​the display surface DS.

[0175] Based on the determination that the display panel DP is driven in a low-frequency mode, the frequency comparator 131 provides a second compensation control signal LCS to the speckle region extractor 141. The speckle region extractor 141 also receives the input image signal I_DATA and, based on the input image signal I_DATA, extracts speckle regions SA on the display surface DS of the display panel DP in which speckles appear. The display surface DS may include speckle regions SA in which speckles appear and non-spot regions NSA in which no speckles appear.

[0176] When the speckle region extractor 141 detects a speckle region SA, it provides the second jitter processor 143 with an image signal DATA_S corresponding to the detected speckle region SA in the input image signal I_DATA. Furthermore, the speckle region SA outputs a third compensation control signal CS to control the operation of the second jitter processor 143. The second jitter processor 143 can perform a local jitter operation in response to the third compensation control signal CS, wherein the local jitter operation jitters the portion of the image signal DATA_S corresponding to the speckle region SA in the input image signal I_DATA.

[0177] The second jitter processor 143 can receive a local jitter pattern L_DTP for the speckle region SA from the second memory 145 and perform local jitter operations. The second memory 145 may include a lookup table storing the local jitter pattern L_DTP for the image signal DATA_S. In one embodiment, the second jitter processor 143 sends a second request signal RS4 to the second memory 145, and the second memory 145 provides the local jitter pattern L_DTP to the second jitter processor 143.

[0178] The second jitter processor 143 reflects the local jitter pattern L_DTP received from the second memory 145 to the image signal DATA_S and outputs the second compensated image signal DATA_LD. Therefore, in low-frequency mode, the signal controller 107 combines the second compensated image signal DATA_LD for the speckle region SA of the display surface DS with the uncompensated image signal corresponding to the non-spot region NSA, and provides the combined signal to the data driver 300. Figure 1 (as shown in the image).

[0179] Because dithering can be performed only on the spot area SA in low-frequency mode, instead of the entire display surface DS, the display panel DP can prevent flickering when correcting spots. Therefore, the display panel DP can improve display quality when operating in low-frequency mode.

[0180] Although exemplary embodiments of this disclosure have been described, it should be understood that this disclosure should not be limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure as claimed herein.

[0181] Therefore, the subject matter disclosed herein should not be limited to any single embodiment described herein, and the scope of the inventive concept should not be determined by the appended claims.

Claims

1. A display device, comprising: Display panel, including display surface; A memory that stores multiple dithering patterns for at least one spot region included in the display surface; A jitter processor receives an image signal corresponding to the spot region, receives a jitter pattern corresponding to the image signal from the memory among the plurality of jitter patterns in a first predetermined time unit, and reflects the selected jitter pattern to the image signal to output a compensation image signal corresponding to the selected jitter pattern. as well as The panel driver outputs a data signal corresponding to the spot region based on the compensated image signal. Each of the plurality of dithering patterns includes a first grayscale region and a second grayscale region, wherein the first grayscale region has a first grayscale value that is higher than the first target grayscale value of the spot region, and the second grayscale region has a second grayscale value that is lower than the first target grayscale value. Wherein, the grayscale difference between the first grayscale value in the first grayscale region and the second grayscale value in the second grayscale region is equal to or greater than 2. The grayscale difference between the first grayscale value and the first target grayscale value is equal to or greater than 1, and the grayscale difference between the second grayscale value and the first target grayscale value is equal to or greater than 1.

2. The display device according to claim 1, wherein, The first target gray value corresponds to the average of the first gray value in the first gray region and the second gray value in the second gray region.

3. The display device according to claim 1, wherein, The display surface also includes a non-spotted region, and the non-spotted region includes an uncompensated region and a boundary region between the uncompensated region and the spotted region.

4. The display device according to claim 3, further comprising: A boundary memory stores multiple boundary jitter patterns for the said boundary region; as well as The boundary jitter processor selects a boundary jitter pattern from the plurality of boundary jitter patterns within a second predetermined time unit, and outputs a boundary compensation image signal corresponding to the selected boundary jitter pattern. Each of the plurality of boundary jitter patterns includes a third grayscale region and a fourth grayscale region, wherein the third grayscale region has a third grayscale value that is higher than the second target grayscale value of the boundary region, and the fourth grayscale region has a fourth grayscale value that is lower than the second target grayscale value.

5. The display device according to claim 4, wherein, The boundary region includes a boundary jitter region and a non-jitter region. In the boundary jitter region, the boundary jitter processor performs jitter operations using the plurality of boundary jitter patterns, and in the non-jitter region, the boundary jitter processor does not perform the jitter operations.

6. The display device according to claim 5, wherein, The third grayscale region and the fourth grayscale region have the same dimensions as the first grayscale region and the second grayscale region.

7. The display device according to claim 4, wherein, The third grayscale region and the fourth grayscale region have a size larger than the first grayscale region and the second grayscale region.

8. The display device according to claim 4, wherein, The grayscale difference between the third grayscale value in the third grayscale region and the fourth grayscale value in the fourth grayscale region is equal to or greater than 2.

9. The display device according to claim 4, wherein, The boundary region includes multiple sub-boundary regions, and the boundary memory stores sub-boundary jitter patterns for the multiple sub-boundary regions.

10. The display device according to claim 9, wherein, Each of the sub-boundary dithering patterns includes a first sub-boundary grayscale region and a second sub-boundary grayscale region, wherein the first sub-boundary grayscale region has a fifth grayscale value that is higher than the third target grayscale value of each of the plurality of sub-boundary regions, and the second sub-boundary grayscale region has a sixth grayscale value that is lower than the third target grayscale value.

11. The display device according to claim 10, wherein, Each of the plurality of sub-boundary regions includes a sub-boundary jittering region and a non-jittering region. In the sub-boundary jittering region, the boundary jittering processor performs a sub-boundary jittering operation using the sub-boundary jittering pattern. In the non-jittering region, the boundary jittering processor does not perform the sub-boundary jittering operation, and the size of the non-jittering region gradually increases with the distance from the spot region.

12. The display device according to claim 11, wherein, The first sub-boundary grayscale region and the second sub-boundary grayscale region have the same size as the first grayscale region and the second grayscale region.

13. The display device according to claim 10, wherein, The grayscale difference between the fifth grayscale value of the first sub-boundary grayscale region and the sixth grayscale value of the second sub-boundary grayscale region is equal to or greater than 2.

14. The display device according to claim 1, further comprising a spot region extractor, the spot region extractor extracting the spot region on the display surface of the display panel.

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