Brass-coated metal in flip-chip redistribution layers

Abstract

This application is entitled "Brass Coated Metal in Flip Chip Redistribution Layers." In some examples, a package (303) includes a die (100) and a redistribution layer (301) coupled to the die. The redistribution layer includes a metal layer (106), a brass layer (110) abutting the metal layer, and a polymer layer (302) abutting the brass layer.

Description

Background Technology

[0001] During manufacturing, semiconductor chips (also commonly referred to as "dies") are typically mounted on die pads of a leadframe and coupled to leads of the leadframe by wire bonding, clipping, or other means. Other devices can be similarly mounted on leadframe pads. The assembly is then covered with a molding compound (such as epoxy) to protect it from potentially damaging heat, physical trauma, moisture, and other harmful factors. The finished assembly is called a semiconductor package or more simply a package. Leads are exposed on the surface of the package and are used to electrically couple the packaged chip to external devices.

[0002] However, other types of packages (such as flip-chip packages) are configured differently from those described above. A flip-chip package includes a die, metal bumps (e.g., solder bumps), and a redistribution layer (RDL) bonded between the die and the metal bumps, allowing signals to be properly routed between the bumps and the active circuitry formed on the die. Examples of such flip-chip packages include wafer-level packages (WCSPs). Summary of the Invention

[0003] In some examples, a package includes a die and a redistribution layer coupled to the die. The redistribution layer includes a metal layer, a brass layer adjacent to the metal layer, and a polymer layer adjacent to the brass layer.

[0004] In some examples, a package includes a die with bonding pads and a redistribution layer coupled to the die. The redistribution layer includes a polymer layer adjacent to the die and a metal layer located at least partially within the polymer layer, the metal layer adjacent to a brass layer.

[0005] In some examples, a method for manufacturing a package includes: positioning a copper layer over a die; positioning a zinc layer on the copper layer; heating the zinc and copper layers to produce a brass layer adjacent to the copper layer; and positioning a polymer layer adjacent to the brass layer. Attached Figure Description

[0006] To provide a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0007] Figures 1A-1D Illustrative techniques for coating copper layers in a redistribution layer (RDL) with brass, according to various examples, are described.

[0008] Figures 2A-2C Illustrative techniques for coating copper layers in an RDL with brass, based on various examples, are described.

[0009] Figures 3A-3EIllustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0010] Figures 4A-4G Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0011] Figures 5A-5H Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0012] Figures 6A-6F Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0013] Figures 7A-7H Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0014] Figures 8A-8H Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0015] Figures 9A-9F Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0016] Figures 10A-10G Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples.

[0017] Figures 11A-11H Illustrative process flow techniques for processing RDLs, including brass-coated copper layers, are described according to various examples. Detailed Implementation

[0018] As explained above, certain types of packages include a die, multiple metal bumps, and a redistribution layer (RDL) positioned between the die and the bumps to properly route signals between the active circuitry on the bumps and the die. Copper is a metal commonly used in the RDL to establish electrical pathways between the bumps and the active circuitry on the die. The RDL typically includes a passivation layer (such as polyimide) to protect the copper from corrosion. However, when the passivation layer is damaged, the copper layer is exposed to moisture, temperature fluctuations, and external contaminants (e.g., chlorine and potassium present in solder flux). This exposure causes the copper layer to undergo electrolytic dissolution, thereby compromising the overall functionality of the package.

[0019] This disclosure describes a technique for protecting a copper layer in an RDL from exposure to harmful effects (such as moisture, temperature fluctuations, and external contaminants mentioned above). Specifically, this disclosure describes various examples of packages having an RDL with a brass-coated copper layer and a passivation layer adjacent to the brass layer. The passivation layer protects the copper layer from the aforementioned harmful effects, but in the event of damage to the passivation layer, the brass layer prevents damage to the copper layer. In this way, the overall functional integrity of the package remains intact.

[0020] This disclosure first describes exemplary techniques that can be used to coat RDL copper layers with brass. Figures 1A-1D and Figures 2A-2C Such techniques are described. The remainder of this disclosure describes exemplary process flow techniques that can be used to manufacture RDLs in conjunction with the aforementioned brass coating techniques. Figure 3A The accompanying figures illustrate this type of technology.

[0021] Figures 1A-1D Illustrative techniques for coating a metal layer (e.g., a copper layer) in a redistribution layer (RDL) with brass, according to various examples, are described. The technique begins with... Figure 1A This depicts a die 100 (e.g., a semiconductor wafer or a portion thereof). Multiple vias 102 facilitate communication between active circuitry on the die 100 and the RDL 101. The RDL 101 includes a seed layer 104 (e.g., titanium or titanium-tungsten) adjacent to a metal layer (e.g., a copper layer) 106, as described in detail below. A connection with... Figure 1A The different configurations shown are included within the scope of this disclosure. Figure 1B The deposition of a zinc layer 108 on a metal layer 106 is depicted. Figure 1B In this embodiment, a zinc layer 108 is deposited using physical vapor deposition (PVD) technology; however, other technologies are conceivable and should be included within the scope of this disclosure. Then, as... Figure 1C As depicted, the technique involves heating a metal layer 106 and a zinc layer 108 to form a brass layer 110. In some examples, temperatures ranging from 100 degrees Celsius to 900 degrees Celsius are applied. Because the formation of brass requires the presence of both copper and zinc, regions in the zinc layer that are not adjacent to a metal layer (e.g., a copper layer) remain zinc. Figure 1D As depicted, these remaining areas of zinc layer 108 were subsequently etched away.

[0022] Figures 2A-2C Alternative techniques for coating metal layers (e.g., copper layers) in a redistribution layer (RDL) with brass, according to various examples, are described. Similar to... Figure 1A , Figure 2A It is depicted that a die 100, a seed layer 104 (e.g., titanium or titanium-tungsten) and a metal layer (e.g., copper layer) 106 are provided. Figure 2B The addition of a zinc layer 108 using an impregnation technique is depicted, but other techniques are contemplated and should be included within the scope of this disclosure. For example... Figure 2C As depicted, the metal layer 106 and the zinc layer 108 are heated as described above to form the brass layer 110.

[0023] exist Figure 1D and Figure 2C In this configuration, brass layer 110 coats metal layer 106, meaning that brass layer 110 is adjacent to metal layer 106. As described in detail below, a polymer layer (e.g., a polyimide layer) is applied to brass layer 110, and brass layer 110 protects metal layer 106 from damage caused by exposure to environmental influences such as moisture and temperature changes, should the integrity of the polymer layer be compromised.

[0024] The remaining figures described below illustrate various exemplary process flow techniques that can be used to manufacture RDLs in certain types of packages, such as flip-chip (e.g., wafer-level package (WCSP), ball grid array (BGA)) packages. Each of the process flow techniques described below may be referenced above. Figures 1A-1D and Figures 2A-2C The described brass coating technique. Although Figures 1A-1D and Figures 2A-2C The use of a die with through-holes is depicted; however, the aforementioned brass coating technique is not limited to such dies and can be used with other dies as described in detail below. The following further describes… Figure 3A And the attached diagram.

[0025] Figures 3A-3E Illustrative process flow techniques for manufacturing RDLs, including brass-coated metal layers, are described according to various examples. Figure 3A A die 100 is depicted having a plurality of through-holes 102 to facilitate communication between active circuitry on the die 100 and an RDL to be fabricated on the die 100. The die 100 may be part of, or singulated from, any suitable type of semiconductor wafer (e.g., silicon). The die 100 and the through-holes 102 may be fabricated using any suitable technique.

[0026] exist Figure 3B In this process, a seed layer 104 comprising a titanium / titanium-tungsten layer and a metal layer (e.g., a copper layer) 105 is deposited. Additionally, a photoresist layer 300 is deposited on the metal layer 105, and the photoresist layer 300 is exposed using a mask and subsequently developed according to a pattern to produce... Figures 3C-3E The structure depicted in the text. For example, according to... Figure 3B The pattern specifically depicted in the image is exposed and developed into a photoresist layer 300.

[0027] exist Figure 3C In the above-mentioned techniques for forming the brass-coated metal layer 106 (e.g., Figures 1A-1D or Figures 2A-2C It is used in parallel with photoresist layer 300 to form metal layer (e.g., copper layer) 106 and brass layer 110. For example, photoresist layer 300 is removed using any suitable etching technique.

[0028] exist Figure 3D In this process, a polymer layer (e.g., a polyimide layer) 302 is deposited, exposed using a mask with a suitable pattern, and subsequently developed to produce the final polymer layer 302 shown. In some examples, as shown, the polymer layer 302 includes apertures located above a portion of the metal layer 106 and the brass layer 110.

[0029] Figure 3E This indicates the completed package 303. Solder balls 304 are dropped into the aforementioned orifices in the polymer layer 302. The solder balls 304 can be used to mount the die 100 and RDL 301 to another electronic device, such as a printed circuit board (PCB). In some examples, the titanium / titanium-tungsten layer 104 has... to The thickness range is advantageous because a thicker seed layer can improve plating uniformity and reduce metal (e.g., copper) diffusion, while a thinner layer reduces cost. In some examples, the metal layer 106 has a thickness ranging from 2 micrometers to 30 micrometers. This thickness range results in lower resistance and higher conductivity when thicker, and reduces cost when thinner. In some examples, the brass layer 110 has a thickness ranging from 0.05 micrometers to 2 micrometers. The thicker end of this range improves protection for the metal layer (e.g., copper layer), while the thinner brass layer 110 reduces cost. In some examples, the polymer layer 302 has a thickness ranging from 3 micrometers to 35 micrometers. This thickness range is advantageous because a thicker polymer layer 302 is more conducive to stress buffering, while a thinner layer can reduce cost.

[0030] Figures 4A-4G This paper describes exemplary process flow techniques for manufacturing RDLs, including brass-coated metal layers, based on various examples. (See above for reference.) Figures 3A-3D The discussion applies to each Figures 4A-4D .

[0031] Figure 4E A seed layer was deposited, comprising a titanium / titanium-tungsten layer 402 and a metal layer 404. Additionally, a photoresist layer 400 was deposited, exposed using a suitable mask, and developed to produce... Figure 4E The pattern depicted in the painting.

[0032] exist Figure 4F In the process, a plating process is performed to... Figure 4E A bump under metallization (UBM) 406 is generated in the area not covered by the photoresist layer 400. Then the photoresist layer 400 and the seed layer (except for the portion of the titanium / titanium-tungsten layer 402 under the UBM 406) are etched away.

[0033] Figure 4G This indicates the completed package 403. As shown, solder balls 408 are dropped onto UBM 406. Solder balls 408 can be used to mount die 100 and RDL 401 to another electronic device, such as a PCB. In some examples, the titanium / titanium-tungsten layer 104 has the features described in the reference above. Figure 3E The same thickness range is described above. In some examples, metal layer 106 has the same thickness range as referenced above. Figure 3E The same thickness range is described above. In some examples, the brass layer 110 has the same thickness range as referenced above. Figure 3E The same thickness range as described above. In some examples, polymer layer 302 has the same thickness range as described above. The benefits of the thickness of these various layers are similar to those mentioned above. Figure 3E Those mentioned above. In some examples, UBM 406 has a thickness range between 3 micrometers and 65 micrometers. These thicknesses are advantageous because thicker layers mitigate electromigration problems, and thinner layers reduce costs.

[0034] Figures 5A to 5H Illustrative process flow techniques for manufacturing RDLs, including brass-coated metal layers, are described according to various examples. Figures 5A-5D respectively with Figures 4A-4D The same, and the above refers to Figures 4A-4D The provided descriptions therefore also apply to each. Figures 5A-5D .exist Figure 5E In the middle, use any suitable etching technique to etch away part 500 of the brass layer 110. Figures 5F-5H The actions depicted in the text are respectively with Figures 4E-4G The same as those described above, and therefore the above refers to... Figures 4E-4G The provided descriptions also apply to the following: Figures 5F-5H In addition to removing a portion of brass 110 (e.g., Figure 5E Apart from the portion depicted in the text (500), Figure 5H The finished package 503 shown (which includes RDL 501) and Figure 4G The packaging components are the same. Remove Figures 5A-5H In the example, this portion of the brass layer may be beneficial because it can improve the contact resistance of the UBM406 to the metal layer 106.

[0035] Figures 6A-6FIllustrative process techniques for manufacturing metal layers including brass coatings are described according to various examples. Figure 6A A die 600 with bonding pads 602 is depicted. The bonding pads 602 facilitate communication between the RDL (described below) and the active circuitry of the die 600. The die 600 can be singulated from any suitable type of semiconductor wafer or be part of that semiconductor wafer.

[0036] exist Figure 6B In this process, a polymer layer (e.g., a polyimide layer) 604 is deposited, exposed and developed using a suitable mask to produce the illustrative pattern. In some examples, as shown, photolithography is used to create apertures above the bonding pads 602.

[0037] exist Figure 6C In this process, a seed layer comprising a titanium / titanium-tungsten layer 606 and a metal layer (e.g., a copper layer) 608 is deposited on the polymer layer 604. Additionally, a photoresist layer 610 is deposited, exposed and developed using a appropriately patterned mask to produce... Figure 6C The photoresist pattern depicted in the image.

[0038] exist Figure 6D middle, Figure 6C The photoresist layer 610 is used to deposit the metal layer (e.g., copper layer) 612. Additionally, the above reference is used, for example... Figures 1A-1D or Figures 2A-2C One of the described techniques forms a brass layer 614. The portion of the photoresist layer 610, metal layer 608, and titanium / titanium-tungsten layer 606 that is not beneath the metal layer 612 is etched away using any suitable etching technique.

[0039] exist Figure 6E In the process, another polymer layer 616 is deposited, exposed, and developed to form the pattern shown. As shown, the apertures in the polymer layer 616 expose the brass layer 614.

[0040] Figure 6FThe completed package 603 is depicted, as shown in the figure, which has a die 600, an RDL 601, and solder balls 618 dropped onto an exposed brass layer 613. The solder balls 618 can be used to mount the package 603 to another electronic device, such as a PCB. Thus, an electrical path can be established between the active circuitry on the die 600 and the electronic device coupled to the solder balls 618. In some examples, the polymer layer 604 has a thickness ranging from 3 micrometers to 35 micrometers, where a thicker polymer layer 604 provides better stress buffering, and a thinner layer reduces cost. In some examples, the titanium / titanium-tungsten layer 606, the metal layer 612, and the brass layer 614 have thicknesses similar to the corresponding layers described above with respect to any of the foregoing figures. In some examples, the polymer layer 616 has a thickness ranging from 3 micrometers to 35 micrometers, which may be advantageous because a thicker layer improves stress buffering, while a thinner layer can reduce cost.

[0041] Figures 7A-7H Illustrative process flow techniques for manufacturing RDLs, including brass-coated metal layers, are described according to various examples. Figures 7A-7E respectively with Figures 6A-6E same. Figure 7F It includes a deposited seed layer comprising a titanium / titanium-tungsten layer 620 and a metal layer (e.g., a copper layer) 622. Figure 7F The photoresist layer 624 is also depicted after deposition, exposure using a suitable patterned mask, and development.

[0042] exist Figure 7G In this process, UBM 626 is deposited over the area not covered by photoresist layer 624. Additionally, the photoresist layer 624 is etched away using any suitable etching process, similar to the seed layer (except for the portion of titanium / titanium-tungsten layer 620 located beneath UBM 626). Figure 7H The completed package 703 is depicted, comprising a die 600, an RDL 701, and solder balls 628 deposited on a UBM 626. The solder balls 628 can be used to mount the package 703 to another electronic device, such as a PCB. In this way, the active circuitry on the die 600 communicates with the electronic device via the RDL 701 and the solder balls 628. The dimensions of the various layers in the package 703 can be similar to those described in the reference above. Figure 6F Those described, except for UBM 626, UBM 626 may have, for example, the same as... Figure 5H The dimensions are similar to those of the UBM406 in the text. The criticality of these dimensions may also be the same as or similar to those given above.

[0043] Figures 8A-8H Illustrative process flow techniques for manufacturing RDLs, including brass-coated metal layers, are described according to various examples. In addition to... Figures 8E-8H Apart from part of the 614 brass layer 805 being etched away, Figures 8A-8H respectively with Figures 7A-7H Similarly. Etching away this portion of the brass layer 164 may be beneficial, as it improves the contact resistance from UBM 626 to the metal layer 612. Figure 8H The dimensions of the various layers (including RDL 801) in the package 803 are similar to those in the reference. Figure 7H Those described. Similarly, the criticality of these dimensions is also related to the reference. Figure 7H The descriptions are the same.

[0044] Figures 9A-9F Illustrative process flow techniques for manufacturing RDLs, including brass-coated metal layers, are described according to various examples. Figures 9A-9D respectively with Figures 4A-4D The same, and therefore the above refers to Figures 4A-4D The provided descriptions also apply to the following: Figures 9A-9D .exist Figure 9E In the process, a seed layer including a titanium / titanium-tungsten layer 402 is applied, followed by the application of a metal layer (e.g., a copper layer) 404. Additionally, a photoresist layer 900 is applied, and then the photoresist layer 900 is exposed and developed according to the pattern shown. Figure 9F As depicted, a metal layer 404 is then plated to form pillar 902 (e.g., a copper pillar). Additionally, the photoresist layer 900 and the seed layer portion not located beneath pillar 902 are etched away using any suitable etching technique. Figure 9F The solder ball 904, which has been dripped onto the top surface of pillar 902, is also depicted. Then it can be... Figure 9F The package 903 (including RDL 901) depicted is mounted to another electronic device, such as a PCB. In this way, the active circuitry on die 100 can communicate with the electronic device via RDL 901 and solder balls 904. Except for pillar 902, the dimensions of the various layers in RDL 901 are similar to those described in the reference above. Figure 4G Those mentioned above. In some examples, the pillar 902 has a thickness ranging from 10 micrometers to 150 micrometers. Thicker pillars 902 mitigate electromigration problems and improve stress buffering, while thinner layers improve cost.

[0045] Figures 10A-10G Illustrative process flow techniques for manufacturing RDLs, including brass-coated metal layers, are described according to various examples. Figure 10A In this embodiment, a die 100 with a through-hole 102 is provided, wherein the die 100 is part of or monolithically derived from any suitable type of semiconductor wafer. Figure 10BIn this process, a seed layer comprising a titanium / titanium-tungsten layer 104 and a metal layer (e.g., a copper layer) 105 is deposited. Additionally, a photoresist layer 300 is deposited on the metal layer 105 according to the pattern shown, exposed using a suitable mask, and developed. Figure 10C In this process, a metal layer 105 is deposited to grow a metal layer (e.g., a copper layer) 1000. In some examples, the metal layer 105 is deposited such that the metal layer 1000 has a thickness approximately equal to that of the photoresist layer 300. Figure 10D In the process, a photoresist layer 1002 is deposited, exposed, and developed to produce the pattern shown. Figure 10E In this process, a metal layer 1000 is plated to create metal pillars (e.g., copper pillars) 1004. Additionally, the exposed areas of the photoresist layer 1002 and the seed layer are etched away using any suitable etching technique. Figure 10F In, for example, using the reference above Figures 1A-1D or Figures 2A-2C Any of the described techniques forms a brass layer 1006. Figure 10G In the process shown, a polymer layer 1010 (e.g., polyimide) is deposited, and solder balls 1008 are dropped onto the top surface of pillar 1004. In some examples, solder balls 1008 are dropped onto a portion of brass layer 1006 on the top surface of pillar 1004. In some examples, a portion of brass layer 1006 on the top surface of pillar 1004 is removed (e.g., using a surface planarization technique), and then solder balls 1008 are dropped onto the top surface of pillar 1004. In some examples, polymer layer 1010 has a thickness ranging from 3 micrometers to 35 micrometers. This range may be advantageous because thicker layers provide improved stress buffering, while thinner layers improve cost. In some examples, pillar 1004 has a thickness ranging from 10 micrometers to 150 micrometers. This thickness range may be advantageous because thicker pillars are more conducive to electromigration and stress buffering, while thinner pillars improve cost. Solder balls 1008 can be used to... Figure 10G The completed package 1003 (including RDL 1001) is mounted on another electronic device (such as a PCB). In this way, communication can occur between the electronic device and the active circuitry on the die 100. In some examples, the top surface of the pillar 1004 retains its brass coating, thereby creating a connection with… Figure 10G It has the same structure as the original structure, but also includes a brass layer on the top surface of the pillar 1004 (and below the solder ball 1008).

[0046] Figures 11A-11H Illustrative process techniques for manufacturing copper layers, including brass coatings, are described according to various examples. Figures 11A-11F respectively with Figures 10A-10F Same. Figure 11GIn this process, a polymer layer 1100 (e.g., polyimide) is applied with an exemplary thickness ranging from 3 micrometers to 150 micrometers. Additionally, in... Figure 11G In this process, for example, a surface planarization technique can be used to remove a portion of the brass layer 1006 on the top surface of the pillar 1004. Figure 11H In this process, the thickness of the polymer layer 1100 and the pillar 1004 is reduced to an exemplary thickness, for example, in the range of 10 to 100 micrometers, using any suitable planarization technique. Solder balls 1008 can then be dropped onto the top surface of the pillar 1004, either directly onto the metal (e.g., copper) of the pillar 1004 or onto the brass layer 1006 covering the top surface of the pillar 1004. Then... Figure 11H The package 1003 (including RDL 1101) can be mounted to another electronic device, such as a PCB. In this way, electronic communication can occur between the active circuitry on die 100 and the electronic device. In some examples, a molding compound can be used instead of the polymer layer 1100. In some examples, Figure 11H The thickness of the pillar 1004 in the finished package 1103 can range from 10 micrometers to 150 micrometers. The benefits of this range can include improved electromigration and stress buffering with thicker values ​​and reduced cost with thinner values. In some examples, the thickness of the polymer layer (or molding compound layer) 1100 can range from 10 micrometers to 150 micrometers. In some examples, in Figure 11D In this step, a second seed layer (including an additional titanium / titanium-tungsten layer and a copper layer) can be deposited on the metal layer 1000, and the copper layer of the second seed layer can be plated to produce the pillar 1004. In this type of example, the final structure is similar to... Figure 11H The structure shown is the same, but in which a titanium / titanium-tungsten layer separates pillar 1004 from metal layer 1000. In such examples, other materials (such as molding compounds) can be used instead of polymer layer 1100.

[0047] The foregoing description involves multiple figures illustrating the steps of a process flow. Any structure depicted in any step of any process flow described above and / or drawn in the figures can be incorporated into the finished product. For example, Figure 4D , Figure 5E , Figure 6E and / or Figure 8E The structure described in the text can be incorporated into the finished manufactured product.

[0048] In the foregoing discussion and claims, the terms “comprising” and “including” are used in an open-ended manner and should therefore be interpreted as meaning “including, but not limited to”. Similarly, the terms “coupled” or “coupled” are intended to mean a direct connection or an indirect connection. Thus, if a first device is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices and connections. Likewise, devices coupled between a first component or location and a second component or location can be either a direct connection or a direct connection via other devices and connections. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding numerical values ​​all mean ±10% of the stated value.

[0049] The foregoing discussion is intended to illustrate the principles and various embodiments of this disclosure. Once fully understood, numerous variations and modifications will become apparent to those skilled in the art. The appended claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. A package comprising: Core; as well as A redistribution layer, coupled to the die, comprising: Metal layer; A brass layer covering the top and side surfaces of the metal layer; and A polymer layer adjacent to a portion of the brass layer.

2. The package according to claim 1, wherein the package is a wafer-level package (WCSP).

3. The encapsulation according to claim 1, wherein the polymer layer comprises a polyimide material.

4. The package of claim 1, wherein the brass layer has a thickness in the range of 0.3 micrometers to 4.0 micrometers.

5. The package according to claim 1, further comprising a bump under metallization layer (UBM) adjacent to the brass layer and solder bumps adjacent to the UBM.

6. The package of claim 1, further comprising a bump under-metallization layer (UBM) attached to the metal layer and solder bumps adjacent to the UBM.

7. The package of claim 1, further comprising solder bumps adjacent to the brass layer.

8. The package of claim 1, further comprising solder bumps attached to the metal layer and the polymer layer.

9. The package according to claim 1, wherein the metal layer is a copper layer.

10. The package of claim 1, further comprising a plurality of metal plugs communicatively coupled to the die and the polymer layer.

11. A package comprising: Die, the die having bonding pads; as well as A redistribution layer, coupled to the die, comprising: A polymer layer adjacent to the die; as well as A metal layer, at least partially located within the polymer layer, adjacent to the brass layer.

12. The package of claim 11, wherein the package comprises a wafer-level package (WCSP).

13. The package of claim 11, further comprising an under-bump metallization layer (UBM) having a first surface adjacent to the solder bumps and a second surface adjacent to the brass layer.

14. The package of claim 11, further comprising an under-bump metallization layer (UBM) having a first surface adjacent to the solder bumps and a second surface attached to the metallization layer.

15. The package of claim 11, wherein the brass layer has a thickness in the range of 0.3 micrometers to 4.0 micrometers.

16. The package of claim 11, wherein the metal layer comprises copper.

17. The package of claim 11, further comprising solder bumps adjacent to the brass layer and the polymer layer.

18. The package of claim 11, further comprising solder bumps attached to the metal layer and the polymer layer.

19. The package of claim 11, further comprising a post attached to the brass layer, the post extending over a plane formed by the surface of the polymer layer.

20. The package of claim 19, wherein the brass layer abuts a surface of the metal layer that is substantially parallel to a surface of the die.

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