Electronic circuits, semiconductor modules and semiconductor devices

Abstract

This invention relates to an electronic circuit, a semiconductor module, and a semiconductor device that suppresses current concentration in a portion of a plurality of semiconductor elements connected in parallel. The electronic circuit is composed of a plurality of diodes connected in parallel, the plurality of diodes including a first diode (SBD1) and a second diode (SBD2) with a forward voltage higher than that of the first diode, wherein the inductance of a first path (P1) from a first terminal (32) through the first diode to a second terminal (31) is greater than the inductance of a second path (P2) from the first terminal to the second terminal through the second diode.

Description

Technical Field

[0001] This invention relates to an electronic circuit, a semiconductor module, and a semiconductor device. Background Technology

[0002] The semiconductor device has a substrate on which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and FWDs (Free Wheeling Diodes) are disposed, and the semiconductor device is used in inverter devices, etc. For example, a specific structure of such a semiconductor device is described in Patent Document 1.

[0003] In the semiconductor device described in Patent Document 1, multiple IGBTs and diodes are connected in parallel. In this semiconductor device, current flows in a distributed manner to each IGBT connected in parallel, thus making the semiconductor device suitable for inverter devices that require high current.

[0004] In the semiconductor device described in Patent Document 1, the metal plate on which the IGBT and diode are mounted is miniaturized. As a result, the parasitic inductance of the metal plate is minimized, and the surge voltage generated during inverter operation is also minimized.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2004-31590 Summary of the Invention

[0008] The problem the invention aims to solve

[0009] Semiconductor components such as IGBTs and diodes exhibit individual manufacturing variations. For example, in Patent Document 1, the forward voltage (VF) of each diode connected in parallel is different, and the turn-on voltage (VF) of each IGBT connected in parallel is also different. ON The individual differences also vary. Due to these individual variations, when the inverter is operating, the current will concentrate in a portion of the diodes or a portion of the IGBTs. The semiconductor element in which the current is concentrated will generate more heat than the other semiconductor elements, and depending on the circumstances, this concentrated semiconductor element may overheat abnormally and break down.

[0010] The present invention was made in view of the aforementioned circumstances, and one of its objectives is to provide an electronic circuit, semiconductor module, and semiconductor device capable of suppressing current concentration in a portion of a plurality of semiconductor elements connected in parallel.

[0011] Solution for solving the problem

[0012] One aspect of the present invention relates to an electronic circuit consisting of a plurality of diodes connected in parallel, the plurality of diodes including a first diode and a second diode having a forward voltage higher than that of the first diode, wherein the inductance of a first path from the first terminal through the first diode to the second terminal is greater than the inductance of a second path from the first terminal through the second diode to the second terminal.

[0013] One aspect of the present invention relates to a semiconductor module having an electronic circuit consisting of a plurality of diodes connected in parallel, the plurality of diodes including a first diode and a second diode having a forward voltage higher than that of the first diode. In this semiconductor module, the inductance of a wiring member forming a first path from a first terminal through the first diode to a second terminal is greater than the inductance of a wiring member forming a second path from the first terminal through the second diode to the second terminal.

[0014] One aspect of the present invention relates to a semiconductor device comprising a plurality of semiconductor modules connected in parallel between a pair of terminals, the semiconductor modules being the aforementioned semiconductor modules. In each path from one terminal of the pair of terminals through the respective semiconductor modules to the other terminal of the pair of terminals, the path through the semiconductor module with the lower forward voltage has a greater inductance.

[0015] Another aspect of the present invention relates to an electronic circuit consisting of a plurality of switching elements connected in parallel, the plurality of switching elements including a first switching element and a second switching element having a higher turn-on voltage than the first switching element, wherein the inductance of a first path from the first terminal through the first switching element to the second terminal is greater than the inductance of a second path from the first terminal through the second switching element to the second terminal.

[0016] The effects of the invention

[0017] According to one aspect of the present invention, it is possible to suppress current concentration in a portion of a plurality of semiconductor elements connected in parallel in electronic circuits, semiconductor modules, and semiconductor devices. Attached Figure Description

[0018] Figure 1 This is a plan view of a semiconductor module involved in one embodiment of the present invention.

[0019] Figure 2 This is an equivalent circuit diagram of a semiconductor module involved in one embodiment of the present invention.

[0020] Figure 3A This is a diagram conceptually illustrating the length relationship of the bonding lines connecting multiple diodes connected in parallel to electrodes on a circuit board in one embodiment of the invention.

[0021] Figure 3B This is a diagram conceptually illustrating the length relationship of the bonding lines connecting multiple diodes connected in parallel to electrodes on a circuit board in one embodiment of the invention.

[0022] Figure 4 This is a diagram conceptually illustrating the length relationship of the bonding lines connecting multiple diodes connected in parallel to electrodes on a circuit board in one embodiment of the invention.

[0023] Figure 5 This is a diagram conceptually illustrating the relationship between the cross-sectional areas of the bonding lines connecting multiple diodes connected in parallel to electrodes on a circuit board in one embodiment of the invention.

[0024] Figure 6 This is a diagram conceptually illustrating the relationship between the cross-sectional areas of the bonding lines connecting multiple diodes connected in parallel to electrodes on a circuit board in one embodiment of the invention.

[0025] Figure 7 It is a diagram that conceptually represents the length relationship of the wiring pattern connected to each of the plurality of diodes in one embodiment of the present invention.

[0026] Figure 8 It is a diagram that conceptually illustrates the relationship between the cross-sectional areas of the wiring patterns connected to each of the plurality of diodes in one embodiment of the present invention.

[0027] Figure 9 It is a diagram that conceptually illustrates the length relationship and cross-sectional area relationship of a wiring pattern connecting various diodes among a plurality of diodes in one embodiment of the present invention.

[0028] Figure 10 This is a diagram conceptually illustrating the length relationship of the bonding lines connecting multiple diodes connected in parallel to electrodes on a circuit board in one embodiment of the invention.

[0029] Figure 11 This is a diagram schematically illustrating a semiconductor device involved in one embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures

[0031] 1: Semiconductor module; 2: Laminated substrate; 10: Base plate; 12: Housing component; 13, 14: Terminal component; 20: Insulating layer; 21: First circuit board; 22: Second circuit board; 23: Third circuit board; 31: P terminal (positive potential point); 32: U terminal (intermediate potential point); 33: N terminal (negative potential point); BD1~BD8: Diodes; BW1~BW8: Bonding wires; L1 A ~L8 A L1 B ~L8 B : Inductor; MOS1~MOS8: Switching element; P1~P8: Path; SBD1~SBD8: Diode; T1~T8: Electrode; W1 A ~W8 A W1 B ~W8 B Wiring components. Detailed Implementation

[0032] The following describes a semiconductor module to which the present invention can be applied. Figure 1 , Figure 2 These are a plan view and an equivalent circuit diagram of the semiconductor module 1 involved in one embodiment of the present invention. Furthermore, the semiconductor module 1 involved in one embodiment of the present invention is merely an example and is not limited thereto; appropriate modifications are permissible.

[0033] like Figure 1 As shown, the semiconductor module 1 is used, for example, in a power module, and includes a substrate 10, a multilayer substrate 2 disposed on the substrate 10, and a housing member 12 for housing the multilayer substrate 2.

[0034] The substrate 10 is, for example, a square-shaped metal plate made of copper, aluminum or their alloys, and functions as a heat sink to dissipate heat from the laminated substrate 2 and the electronic components mounted on the laminated substrate 2 to the outside.

[0035] The housing component 12 is a rectangular resin frame that follows the outline of the base plate 10, and is, for example, bonded to the base plate 10. The space surrounded by the base plate 10 and the housing component 12 is filled with a sealing resin (not shown). Through this sealing resin, the laminated substrate 2 and the electronic components mounted on the laminated substrate 2 are sealed within the aforementioned space.

[0036] The laminated substrate 2 is composed of, for example, a DBA (Direct Bonded Aluminum) substrate, a DBC (Direct Bonded Copper) substrate, or an AMB (Active Metal Brazing) substrate. The laminated substrate 2 has an insulating layer 20, which is formed of an insulator such as ceramic, for example, alumina (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4). A first circuit board 21, a second circuit board 22, and a third circuit board 23 are formed on the upper surface of the insulating layer 20. These circuit boards are metal layers such as copper foil, formed in an island-like manner on the insulating layer 20 in an electrically insulated manner.

[0037] On the first circuit board 21, the second circuit board 22, and the third circuit board 23, P terminals (positive potential points) 31, U terminals (intermediate potential points) 32, and N terminals (negative potential points) 33 are respectively configured (connected) using solder or other bonding materials. P terminals 31, U terminals 32, and N terminals are external connection terminals used for inputting and outputting main current to the semiconductor module 1.

[0038] On the first circuit board 21 and the second circuit board 22, multiple electronic components are arranged using bonding materials such as solder. Specifically, on the first circuit board 21, switching elements MOS1 to MOS4 and diodes SBD1 to SBD4 are arranged using bonding materials. On the second circuit board 22, switching elements MOS5 to MOS8 and diodes SBD5 to SBD8 are arranged using bonding materials.

[0039] The switching elements MOS1 to MOS8 are, for example, semiconductor switching elements made of silicon (Si), silicon carbide (SiC), or gallium carbide (GaN), specifically, power MOSFETs. When MOS1 to MOS8 are power MOSFETs, they have a drain electrode as the main electrode on the back side, and a gate electrode and a source electrode as the main electrode on the surface. MOS1 to MOS8 may include a body diode parasitic on the power MOSFET. The body diode is connected in reverse parallel with the power MOSFET, and has a cathode electrode on the back side and an anode electrode on the surface. MOS1 to MOS8 may also be switching elements with other structures, such as IGBTs. When MOS1 to MOS8 are IGBTs, they have a collector electrode as the main electrode on the back side, and a gate electrode and an emitter electrode as the main electrode on the surface. Furthermore, MOS1 to MOS8 may also be RC (Reverse-Conducting) IGBTs obtained by monolithically combining an IGBT and a diode. In this case, the diode is connected in reverse parallel with the IGBT, and has a cathode electrode on the back side and an anode electrode on the surface.

[0040] Switching elements MOS1 to MOS4 are connected in parallel. The drain electrodes of switching elements MOS1 to MOS4 are disposed on the first circuit board 21 using solder or other bonding materials, thereby being electrically connected to the P terminal 31. In addition, the source electrodes are electrically connected to the second circuit board 22 via bonding wires, thereby being electrically connected to the U terminal 32.

[0041] The gate electrodes of switching elements MOS1 to MOS4 are connected by a junction wire. This junction wire connecting the gate electrodes is electrically connected to a terminal member 13 embedded in the housing member 12. During periods when a voltage exceeding a predetermined threshold is applied to the gate electrodes from the terminal member 13, switching elements MOS1 to MOS4 are turned on, and current flows from the drain electrode to the source electrode. During periods when no voltage exceeding the predetermined threshold is applied to the gate electrodes from the terminal member 13, switching elements MOS1 to MOS4 are turned off, and the current from the drain electrode to the source electrode is interrupted.

[0042] Switching elements MOS5 to MOS8 are also connected in parallel. The drain electrodes of switching elements MOS5 to MOS8 are disposed on the second circuit board 22 using solder or other bonding materials, thereby being electrically connected to the U terminal 32. In addition, the source electrodes are electrically connected to the third circuit board 23 via bonding wires, thereby being electrically connected to the N terminal 33.

[0043] The gate electrodes of switching elements MOS5 to MOS8 are also connected by a bonding wire. This bonding wire, connecting these gate electrodes, is electrically connected to the terminal member 14 embedded in the housing member 12 via a control circuit board. During the period when a voltage exceeding a predetermined threshold is applied to the gate electrode from the terminal member 14, the switching elements MOS5 to MOS8 are turned on, and current flows from the drain electrode to the source electrode. During the period when a voltage exceeding the predetermined threshold is not applied to the gate electrode from the terminal member 14, the switching elements MOS5 to MOS8 are turned off, and the current from the drain electrode to the source electrode is cut off. Furthermore, the wiring between the source electrode and the third circuit board 23, and the wiring between the gate electrode and the control circuit board, are not limited to bonding wires, but can be replaced with other conductive wiring components such as striplines and lead frames.

[0044] Diodes SBD1 to SBD8 are diodes fabricated using SiC, specifically Schottky barrier diodes. Diodes SBD1 to SBD8 can be diodes fabricated using either Si or SiC. Alternatively, some or all of diodes SBD1 to SBD8 can be replaced with diodes with other structures such as JBS (junction barrier Schottky) diodes, MPS (merged PN Schottky) diodes, or PN diodes. Furthermore, diodes SBD1 to SBD8 can also be diodes integrated into an RC-IGBT. That is, diodes SBD1 to SBD8 are not limited to Schottky barrier diodes and can be diodes with different structures. However, it is preferable that the diodes connected in parallel all have the same structure. The cathode electrode, serving as the main electrode, of diodes SBD1 to SBD8 is located on the back side, and the anode electrode, also serving as the main electrode, of diodes SBD1 to SBD8 is located on the surface.

[0045] Diodes SBD1 to SBD4 are multiple diodes, including a first diode connected in parallel and a second diode with a forward voltage higher than that of the first diode. Diodes SBD5 to SBD8 are also multiple diodes, including a first diode connected in parallel and a second diode with a forward voltage higher than that of the first diode. Here, forward voltage refers to the voltage generated when a forward current flows through the diode. For example, it is the voltage generated between the anode and cathode electrodes when a rated current flows from the anode electrode to the cathode electrode.

[0046] Diodes SBD1 to SBD4 are connected in parallel with switching elements MOS1 to MOS4, respectively. More specifically, diodes SBD1 to SBD4 are FWDs (Free Wheeling Diodes), connected in reverse parallel with switching elements MOS1 to MOS4, respectively. The anodes of diodes SBD1 to SBD4 are electrically connected to terminal U 32, and the cathodes of diodes SBD1 to SBD4 are electrically connected to terminal P 31.

[0047] like Figure 2 As shown, the paths from U terminal 32 through diodes SBD1 to SBD4 to P terminal 31 are labeled P1 to P4. Each path P1 to P4 is connected by a wiring component W1 that electrically connects U terminal 32 to the anode electrode of each diode SBD1 to SBD4. A ~W4 A And the wiring components W1 that electrically connect the cathode electrodes of each diode SBD1 to SBD4 to the P terminal 31. B ~W4B constitute.

[0048] For the U terminal 32 parasitic in paths P1 to P4 and between the anode electrodes of each diode SBD1 to SBD4 (in other words, each wiring component W1) A ~W4 A The inductors are labeled L1 and L2 respectively. A ~L4 A For the parasitic connection between the cathode electrode of each diode SBD1 to SBD4 and the P terminal 31 (in other words, between each wiring component W1) B ~W4 B The inductors are labeled L1 and L2 respectively. B ~L4 B .

[0049] Figure 2 The wiring components W1 shown A ~W4 A like Figure 1 That includes wiring patterns on the second circuit board 22 that connect the U terminal 32 to each electrode T1 to T4 on the second circuit board 22, and bonding lines BW1 to BW4 that connect each electrode T1 to T4 to the anode electrode of each diode SBD1 to SBD4. Figure 2 The wiring components W1 shown B ~W4 B like Figure 1 This includes wiring patterns on the first circuit board 21 that connect the cathode electrodes of each diode SBD1 to SBD4 to the P terminal 31. Illustrations of these wiring patterns are omitted to avoid complicating the drawings. Furthermore, the bonding lines BW1 to BW4 can be replaced with other conductive wiring components such as striplines or lead frames.

[0050] Diodes SBD5 to SBD8 are connected in parallel with switching elements MOS5 to MOS8, respectively. More specifically, diodes SBD5 to SBD8 are open-ended diodes (FWDs) and are connected in reverse parallel with switching elements MOS5 to MOS8, respectively. The anode of diodes SBD5 to SBD8 is connected to terminal N 33, and the cathode of diodes SBD5 to SBD8 is connected to terminal U 32.

[0051] like Figure 2 As shown, the paths from N terminal 33 through diodes SBD5 to SBD8 to U terminal 32 are marked with P5 to P8. Each path P5 to P8 is connected by a wiring component W5 that connects N terminal 33 to the anode electrode of each diode SBD5 to SBD8. A ~W8 A And the wiring components W5 that connect the cathode electrodes of each diode SBD5 to SBD8 to the U terminal 32.B ~W8 B constitute.

[0052] For the N terminal 33 parasitic in paths P5 to P8 and between the anode electrodes of each diode SBD5 to SBD8 (in other words, each wiring component W5) A ~W8 A The inductors are marked L5 respectively. A ~L8 A For the parasitic junction between the cathode electrode of each diode SBD5 to SBD8 and the U terminal 32 (in other words, each wiring component W5) B ~W8 B The inductors are marked L5 respectively. B ~L8 B .

[0053] Figure 2 The wiring components W5 shown A ~W8 A like Figure 1 These include wiring patterns on the third circuit board 23 that connect the N terminal 33 to each electrode T5 to T8 on the third circuit board 23, and bonding lines BW5 to BW8 that connect each electrode T5 to T8 to the anode electrode of each diode SBD5 to SBD8. Figure 2 The wiring components W5 shown B ~W8 B like Figure 1 This includes wiring patterns on the second circuit board 22 that connect the cathode electrodes of each diode SBD5 to SBD8 to the U terminal 32. Illustrations of these wiring patterns are omitted to avoid complicating the drawings. Furthermore, the bonding lines BW5 to BW8 can also be replaced with other conductive wiring components such as striplines or lead frames.

[0054] exist Figure 2 In the diagram, BD1 to BD8 are the body diodes parasitic on the switching elements MOS1 to MOS8, respectively. For example... Figure 2 As shown, diodes BD1 to BD8 are connected in reverse parallel to the channels of switching elements MOS1 to MOS8, respectively.

[0055] In a semiconductor module 1 configured as described above, during the switching operations of each switching element MOS1 to MOS8, there is a period during which reverse current flows from the negative potential side to the positive potential side. The forward voltage of the Schottky barrier diodes SBD1 to SBD8, which are connected in reverse parallel with each switching element MOS1 to MOS8, is lower than the forward voltage of the body diodes BD1 to BD8 parasitic on each switching element MOS1 to MOS8. Therefore, as long as the applied voltage does not exceed the forward voltage of diodes BD1 to BD4, the current flows from terminal U 32 to terminal P 31 through diodes SBD1 to SBD4. As long as the applied voltage does not exceed the forward voltage of diodes BD5 to BD8, the current flows from terminal N 33 to terminal U 32 through diodes SBD5 to SBD8.

[0056] For example, consider the case where the switching elements MOS1 to MOS8 are power MOSFETs fabricated using SiC. In this case, the forward voltage of the diodes BD1 to BD8 parasitic on the switching elements MOS1 to MOS8 may increase with the passage of time, leading to current degradation and potential damage to the switching elements MOS1 to MOS8. However, in this embodiment, by connecting the diodes SBD1 to SBD8 with low forward voltages in parallel with the diodes BD1 to BD8, current is less likely to flow to the diodes BD1 to BD8. Therefore, current degradation of the diodes BD1 to BD8 is suppressed, and the long-term reliability of the switching elements MOS1 to MOS8 is improved.

[0057] Although diodes SBD1 through SBD8 have the same structure, they exhibit individual manufacturing differences. Therefore, the forward voltage of diodes SBD1 through SBD8 contains variations.

[0058] When multiple diodes are connected in parallel, the current typically concentrates on the diode with the lowest forward voltage. When the current from terminal U 32 to terminal P 31 concentrates on the diode with the lowest forward voltage among diodes SBD1 to SBD4, this diode heats up more than the others due to the concentrated current, and depending on the situation, may overheat and break. Similarly, when the current from terminal N 33 to terminal U 32 concentrates on the diode with the lowest forward voltage among diodes SBD5 to SBD8, this diode heats up more than the others due to the concentrated current, and depending on the situation, may overheat and break.

[0059] Therefore, the inventors of this invention conceived of the present invention, focusing on the deviation of the forward voltage between multiple diodes. In this embodiment, in order to prevent diode damage caused by abnormal heating as described above, the semiconductor module 1 is designed to suppress the concentration of current to a portion of the diodes.

[0060] More specifically, to obtain the above structure, in this embodiment, the forward voltages of the four Schottky barrier diodes are measured beforehand. The Schottky barrier diode with the lowest forward voltage is placed in path P1, and then the Schottky barrier diodes are placed in paths P2 to P4 in order of increasing forward voltage. That is, the diode with the smaller number marked in diodes SBD1 to SBD4 has the lower forward voltage.

[0061] Furthermore, in the semiconductor module 1 according to this embodiment, the parasitic inductance of the path in the parallel-connected paths P1 to P4 where the Schottky barrier diode with the lower forward voltage is placed is larger. That is, the parasitic inductance of path P1 (in other words, the wiring member W1) is the largest among the paths P1 to P4. A and W1 B Parasitic inductance (inductance L1) A With inductor L1 B The sum, denoted below as "inductance (L1)" A +L1 B The parasitic inductance of other paths is also recorded in the same way. The maximum inductance is then recorded for paths P2 to P4 (in other words, wiring component W2). A and W2 B Wiring component W3 A and W3 B Wiring component W4 A and W4 B The parasitic inductance is arranged in descending order of magnitude. That is, the smaller the number marked in paths P1 to P4, the greater the parasitic inductance of the path.

[0062] In this way, semiconductor module 1 has the following electronic circuit structure: the inductance of the first path (e.g., path P1) from the first terminal (e.g., U terminal 32) through the first diode (e.g., diode SBD1) to the second terminal (e.g., P terminal 31) is greater than the inductance of the second path (e.g., path P2) from the first terminal through the second diode (e.g., diode SBD2) to the second terminal.

[0063] In addition, semiconductor module 1 satisfies at least one of the following conditions (1) to (4) so ​​that the path with the smaller number of the marking in path P1 to P4 has a larger parasitic inductance.

[0064] (1) The total length of the junction line constituting the path (hereinafter referred to as the "first conductive line") is longer than the total length of the junction line constituting the path of the Schottky barrier diode configured with a higher forward voltage compared to the path (hereinafter referred to as the "second conductive line");

[0065] (2) The cross-sectional area of ​​the first conductive wire is smaller than that of the second conductive wire;

[0066] (3) The total length of the wiring pattern constituting the path (hereinafter referred to as "first wiring pattern") is longer than the total length of the wiring pattern constituting the path in which a Schottky barrier diode with a higher forward voltage is configured compared to the path (hereinafter referred to as "second wiring pattern");

[0067] (4) The cross-sectional area of ​​the first wiring pattern is smaller than that of the second wiring pattern.

[0068] Conditions (1) and (2) represent conditions that make the parasitic inductance of the first conductive line greater than that of the second conductive line. Conditions (3) and (4) represent conditions that make the parasitic inductance of the first wiring pattern greater than that of the second wiring pattern.

[0069] Figure 3A , Figure 3B , Figure 4 This is a diagram that conceptually illustrates condition (1). For example... Figure 3A , Figure 3B , Figure 4 As shown, the smaller the number of the markings in the joint lines BW1 to BW4, the longer the total length of the joint line.

[0070] exist Figure 3A In the example shown, diodes SBD1 to SBD4 are arranged in a row in this order on the first circuit board 21. A second circuit board 22 is formed on the side closest to the diode SBD4 with the higher forward voltage. Each diode SBD1 to SBD4 is electrically connected to electrodes T1 to T4 of the second circuit board 22 via bonding lines BW1 to BW4. That is, each diode SBD1 to SBD4 is configured such that the smaller the number marked (the lower the forward voltage), the greater the distance between it and the electrodes T1 to T4 to which it is connected. Therefore, the total length of the bonding lines with smaller marked numbers in BW1 to BW4 is longer. For example, the total length of bonding line BW1 constituting the path P1 where diode SBD1 is arranged is longer than the total length of bonding line BW2 constituting the path P2 where diode SBD2, which has a higher forward voltage than diode SBD1, is arranged. Consequently, the parasitic inductance of the bonding lines with smaller marked numbers in BW1 to BW4 is greater. Therefore, the smaller the number marked in each path P1 to P4 of each junction line BW1 to BW4, the greater the parasitic inductance.

[0071] Figure 3B express Figure 3A A variation of the example shown. In Figure 3B In the example shown, diodes SBD1, SBD3, SBD4, and SBD2 are arranged in a row in this order on the first circuit board 21. Furthermore, a second circuit board 22 is formed at a position slightly offset from the center of the first circuit board 21 towards the diode SBD4. Figure 3B In the example shown, with Figure 3A Similarly, in the example shown, diodes SB1 to SBD4 are configured such that the smaller the number marked (the lower the forward voltage), the farther away they are from the electrodes T1 to T4 at the connection destination. Therefore, the total length of the junction lines BW1 to BW4 with smaller marked numbers is longer, resulting in greater parasitic inductance. Consequently, the parasitic inductance of the paths P1 to P4, which include junction lines BW1 to BW4, is greater with smaller marked numbers.

[0072] exist Figure 4 In the example shown, diodes SBD1 to SBD4 are arranged in a row in this order on the first circuit board 21. Additionally, a second circuit board 22 is formed side-by-side with the first circuit board 21. For example... Figure 4 As shown in the top view, when viewed from above, the distances between each diode SBD1 to SBD4 and each electrode T1 to T4 are equal. On the other hand, as... Figure 4 As shown in the top and side views, the junction lines BW1 to BW4 are routed in a gently curved manner. The smaller the number marked (the lower the forward voltage of the diode), the greater the curvature (smaller the radius of curvature) of the junction line. In other words, the smaller the number marked among the junction lines BW1 to BW4, the more curved the route is, resulting in a longer total length of the junction line and thus a greater parasitic inductance. Consequently, the smaller the number marked on each path P1 to P4, which includes each junction line BW1 to BW4, the greater the parasitic inductance.

[0073] Figure 5 and Figure 6 This is a diagram that conceptually illustrates condition (2). In Figure 5 and Figure 6 In the example shown, with Figure 4 Similarly, on the first circuit board 21, diodes SBD1 to SBD4 are arranged in a single column in this order. Furthermore, a second circuit board 22 is formed side-by-side with the first circuit board 21. Additionally, with... Figure 3A , Figure 3B as well as Figure 4 The examples differ, but the total length of each junction line BW1 to BW4 is the same.

[0074] like Figure 5 and Figure 6 As shown, the smaller the number marked in the joint lines BW1 to BW4, the smaller the cross-sectional area of ​​the joint line. Specifically, in Figure 5 In the example, each junction line BW1 to BW4 is formed by a single line. The smaller the number (the lower the forward voltage of the diode), the thinner the wire diameter, and thus the smaller the cross-sectional area. Figure 6In the example, each bonding line BW1 to BW4 is formed by multiple lines of the same diameter. The smaller the number marked (the lower the forward voltage of the diode), the fewer the number of bonding lines, and thus the smaller the total cross-sectional area. That is, in Figure 5 and Figure 6 In any example, the smaller the number marked on the junction lines BW1 to BW4, the smaller the cross-sectional area and the greater the parasitic inductance. Therefore, the smaller the number marked on each path P1 to P4, which includes each junction line BW1 to BW4, the greater the parasitic inductance.

[0075] Figure 7 This is a diagram that conceptually illustrates condition (3). In Figure 7 In the example, with Figure 4 Similarly, on the first circuit board 21, diodes SBD1 to SBD4 are arranged in a single column in this order. Figure 7 In the example, the distances between each diode SBD1 to SBD4 and the P terminal 31 are different. Specifically, the diodes with smaller marked numbers (diodes with lower forward voltage) among the diodes SBD1 to SBD4 are farther away from the P terminal 31, resulting in a longer wiring pattern between the diodes and the P terminal 31 on the first circuit board 21. Therefore, the total length of the wiring pattern on the first circuit board 21 constituting paths P1 to P4 for the paths of diodes SBD1 to SBD4 with smaller marked numbers is longer, and the parasitic inductance is greater. Consequently, the parasitic inductance is greater for the paths with smaller marked numbers among the paths P1 to P4.

[0076] Figure 8 This is a diagram that conceptually illustrates condition (4). Furthermore, Figure 8 And the following Figure 9 and Figure 10 The arrows shown are for illustrative purposes and do not represent structural elements. Figure 8In this example, the P-terminal 31 is positioned at the center of the first circuit board 21 using a bonding material such as solder. Diodes SBD1 to SBD4 are arranged around the P-terminal 31, with equal distances between each diode SBD1 to SBD4 and the P-terminal 31. Multiple slits 41 to 46 of varying widths are formed on the first circuit board 21. Slits 41 to 44 are formed between each diode SBD1 to SBD4 and the P-terminal 31, with smaller numbers indicating wider slits. Slit 45 is formed between diode SBD1 and diode SBD3, and slit 46 is formed between diode SBD2 and diode SBD4. Slits 45 and 46 are narrower than slit 42 and wider than slit 43. By forming these slits 41 to 46 on the first circuit board 21, the average cross-sectional area of ​​the wiring pattern constituting the path of the diodes SBD1 to SBD4 with smaller numbers between each diode SBD1 to SBD4 and the P-terminal 31 is smaller, resulting in a larger parasitic inductance. Therefore, the smaller the number marked in each path P1 to P4, the greater the parasitic inductance of that path.

[0077] Figure 9 This is a conceptual diagram illustrating the conditions obtained by combining conditions (3) and (4). Figure 9 In the example shown, diodes SBD1, SBD3, SBD4, and SBD2 are arranged in a row on the first circuit board 21 in this order. Additionally, P-terminals 31 are positioned near the center of the first circuit board 21 using solder or other bonding materials. The distance between diode SBD1 and P-terminal 31 is the same as the distance between diode SBD2 and P-terminal 31. The distance between diode SBD3 and P-terminal 31 is equal to the distance between diode SBD4 and P-terminal 31, and shorter than the distances between diodes SBD1 and P-terminal 31 and SBD2 and P-terminal 31. Furthermore, slits 51 to 54 of equal width are formed near each of the diodes SBD1 to SBD4. By forming these slits 51 to 54 on the first circuit board 21, the average cross-sectional area of ​​the wiring pattern forming the path of diode SBD1 or SBD3 is smaller than that of the wiring pattern forming the path of diode SBD2 or SBD4, thereby increasing the parasitic inductance.

[0078] That is, in Figure 9 In the example, although diodes SBD1 and SBD2 are equidistant from terminal P31, the average cross-sectional area of ​​the wiring pattern forming the path where diode SBD1 is located is smaller. Therefore, the parasitic inductance of path P1 where diode SBD1 is located is larger than that of path P2 where diode SBD2 is located.

[0079] The distance between diodes SBD3 and SBD4 and terminal 31 is shorter than the distance between diodes SBD1 and SBD2 and terminal 31. Furthermore, although diodes SBD3 and SBD4 are equidistant from terminal 31, the average cross-sectional area of ​​the wiring pattern forming the path where diode SBD3 is located is smaller. Therefore, the parasitic inductance of path P3, where diode SBD3 is located, is smaller than that of paths P1 and P2, but larger than that of path P4, where diode SBD4 is located.

[0080] Like this, in Figure 9 As shown in the example, the smaller the number marked in each path P1 to P4, the greater the parasitic inductance of the path.

[0081] Figure 1 The path from U terminal 32 to P terminal 31 via diodes SBD1 to SBD4 combines conditions (1) and (3). Similarly, Figure 1 The path from N terminal 33 to U terminal 32 via diodes SBD5-8 also combines conditions (1) and (3).

[0082] Specifically, such as Figure 1 As shown, the smaller the number marked in the connection lines BW1 to BW4, the longer the total length of the connection line, resulting in a larger parasitic inductance. Furthermore, the smaller the number marked in each of the diodes SBD1 to SBD4 (the lower the forward voltage), the greater the distance between them and the P-terminal 31, resulting in a longer wiring pattern between the diodes and the P-terminal 31 formed on the first circuit board 21. Therefore, the total length of the wiring pattern on the first circuit board 21 constituting paths P1 to P4 for the paths containing the smaller-marked diodes SBD1 to SBD4 is longer, resulting in a larger parasitic inductance. Consequently, the smaller the number marked in each of the paths P1 to P4, the larger the parasitic inductance.

[0083] Similarly, for bonding lines BW5 to BW8, the smaller the marked number, the longer the total length of the bonding line, resulting in a larger parasitic inductance. Furthermore, for each diode SBD5 to SBD8, the smaller the marked number (the lower the forward voltage), the greater the distance between it and the P terminal 31, resulting in a longer wiring pattern between the diode and the U terminal 32 on the second circuit board 22. Therefore, the total length of the wiring pattern on the second circuit board 22 constituting paths P5 to P8 for the paths containing diodes SBD5 to SBD8 with smaller marked numbers is longer, resulting in a larger parasitic inductance. Consequently, the paths with smaller marked numbers in each of paths P5 to P8 have a larger parasitic inductance.

[0084] Furthermore, semiconductor module 1 need not be a structure that satisfies all of the conditions (1) to (4). For example, even if the total length of bonding wire BW2 is longer than the total length of bonding wire BW1, the wiring component W1 can be formed in such a way that at least one of the conditions (2) to (4) is satisfied so that the parasitic inductance of path P1 as a whole is greater than that of path P2 as a whole. A W2 A W1 B and W2 B That's all.

[0085] In this way, conditions (1) to (4) are illustrative examples. Semiconductor module 1 can also be a structure that does not satisfy all of the conditions (1) to (4), as long as the parasitic inductance of the path with the smaller marked number is greater.

[0086] The current from terminal U 32 to terminal P 31 flows to the path P1-P4 where the Schottky barrier diode with the lowest forward voltage is located (i.e., path P1). As the current flowing to path P1 changes (increases), a current is generated in path P1 corresponding to the wiring component W1. A and W1 B parasitic inductance (L1) A +L1 B The back electromotive force is directly proportional to the current. Due to this back electromotive force, the current becomes less likely to flow to path P1. In other words, the current becomes more likely to flow to paths P2 to P4.

[0087] Similarly, in path P2, as the current increases, a connection is generated in path P2 with the wiring component W2. A and W2 B parasitic inductance (L2) A +L2 B The back electromotive force is proportional to the current, making it less likely for the current to flow to path P2. Therefore, the current becomes more likely to flow to paths P3 and P4 compared to path P2. The same phenomenon occurs in path P3; as the current increases, the current becomes more likely to flow to path P4 compared to path P3.

[0088] As the rate of change of current flowing through paths P1 to P4 decreases, the back electromotive force generated in each path P1 to P4 also decreases. When the current flowing through each path P1 to P4 converges to a fixed value, the back electromotive force in each path P1 to P4 also becomes zero. In this steady state, the current flows equally through each path P1 to P4.

[0089] In this way, by forming the wiring components of each path in such a way that the parasitic inductance of the path through the Schottky barrier diode with the lower forward voltage is increased, the current from the U terminal 32 to the P terminal 31 is quickly dispersed to the parallel-connected paths P1 to P4, suppressing the concentration of current in a portion of the path (e.g., path P1). Therefore, it is possible to prevent abnormal heating and damage to semiconductor devices such as Schottky barrier diodes caused by current concentration.

[0090] Similarly, for diodes SBD5 to SBD8, the smaller the number on the label, the lower the forward voltage. Likewise, for paths P5 to P8, the smaller the number on the label, the greater the parasitic inductance. Therefore, in paths P5 to P8, similar to paths P1 to P4, the current is rapidly dispersed, suppressing current concentration in a portion of the path.

[0091] By suppressing the abnormal heating of some semiconductor components caused by current concentration, the rated current of semiconductor module 1 can be increased. Furthermore, the more diodes connected in parallel, the more significant the current concentration suppression effect described above can be achieved.

[0092] Next, specific implementation examples will be described. Figure 10 This is a conceptual diagram illustrating the length relationship of the bonding lines connecting multiple diodes connected in parallel to electrodes on a circuit board. In this embodiment, for convenience, only the relationship between path P1 and path P2 is illustrated.

[0093] In this embodiment, paths P1 and P2 only satisfy condition (1) in conditions (1) to (4). That is, paths P1 and P2 involved in this embodiment have the same structure except that the total length of the junction line BW1 is different from the total length of the junction line BW2. In other words, the parasitic inductance of path P1 and the parasitic inductance of path P2 depend only on the difference in the total length of the junction lines BW1 and BW2.

[0094] Let the currents flowing to paths P1 and P2 be “I1” and “I2”, respectively, and let the forward voltages of diodes SBD1 and SBD2 be “VF1” and “VF2”, respectively. Let time be “t”. In this case, the concentration of current in path P1 is suppressed by satisfying the relationship shown in equation (1).

[0095] VF1+(L1 A +L1 B )dI1 / dt=VF2+(L2 A +L2 B )dI2 / dt…(1)

[0096] The forward voltages of diodes SBD1 and SBD2 are set as X±Y (V: volts), and their measured values ​​are set as XY (V) and X+Y (V). In this embodiment, the current α (A: ampere) flows to each path β (ns: nanosecond) of path P1 and path P2. When the values ​​listed here as examples are substituted into the above equation (1), the following equation (2) can be obtained. And, according to the following equation (2), the following equation (3) is obtained.

[0097] -2Y(V)={(L2 A +L2 B )-(L1 A +L1 B )}×α( A ) / β(ns)…(2)

[0098] (L1 A +L1 B )-(L2 A +L2 B )=2Y×β / α(nH:Nahen)…(3)

[0099] As shown in equation (3) above, by making the parasitic inductance of path P1 (L1) A +L1 B The parasitic inductance of path P2 (L2) A +L2 B The value of 2Y×β / α(nH) is increased to suppress the concentration of current in path P1.

[0100] For example, consider parasitic inductance (L2) A +L2 B The case where the inductance is 12nH. In this case, the total length of the junction wire BW2 is made 10% shorter than the total length of the junction wire BW1. Therefore, the parasitic inductance (L1) is... A +L1 B ) becomes more than the parasitic inductance (L2) A +L2 B ) 0.12nH.

[0101] In the above embodiments, the number and arrangement of the switching elements and diodes disposed on the laminated substrate 2 are not limited to the above structure and can be appropriately changed.

[0102] In the above embodiments, the number and layout of the circuit boards on the insulating layer 20 are not limited to the above structure and can be appropriately changed.

[0103] In the above embodiments, the parasitic inductance of all parallel connected paths is specified (specifically, the parasitic inductance increases sequentially in the order of paths P1 to P4 (or P5 to P8), but by specifying the parasitic inductance of only at least two paths (for example, making the parasitic inductance of path P1 larger than that of path P2), it is possible to achieve the effect of suppressing the concentration of current in a portion of the paths.

[0104] In the above embodiment, the structure is configured as follows: using an inductor on the anode electrode side (e.g., L1) A ) and the inductance on the cathode side (e.g., L1) B The sum of the inductances of the diodes in the specified path is used to represent the parasitic inductance of the diodes. In this case, it is preferable that the inductance on the anode side of the diode with the lower forward voltage is higher than the inductance on the anode side of the diode with the higher forward voltage. That is, the inductance on the anode side can also be used to adjust the magnitude of the inductance of each diode connected in parallel in the specified path. In other words, for example, it is also possible that the wiring member W1 electrically connected to the cathode electrode in paths P1 to P4 is... B ~W4 B Inductor L1 B ~L4 B Equal, and for the wiring component W1 electrically connected to the anode electrode A ~W4 A Inductor L1 A ~L4 A The smaller the marked number, the larger the inductance. This is because the anode electrode appears on the surface side of semiconductor module 1, and the inductance can be easily adjusted by changing the wiring length of bonding lines BW1 to BW4. Furthermore, the adjustment of the inductance between each diode is not limited to the wiring components on the anode electrode side, but can also be adjusted using the wiring components on the cathode electrode side.

[0105] Furthermore, similar to diodes SBD1-SBD4, the switching elements MOS1-MOS4 also exhibit a problem where current is concentrated in a portion of the switching elements. Specifically, when multiple switching elements are connected in parallel, the current typically concentrates at the turn-on voltage (V). ON Lower-profile switching elements.

[0106] Therefore, in the above embodiment, the switching element with the lowest turn-on voltage is configured as switching element MOS1, and thereafter, switching elements with low turn-on voltages are sequentially configured as switching elements MOS2 to MOS4. That is, switching elements MOS1 to MOS4 are configured such that the smaller the marked number, the lower the turn-on voltage of the switching element.

[0107] In this structure, where switching elements MOS1 to MOS4 are configured, the wiring components are formed as follows: in each path P1' to P4' from P terminal 31 through each switching element MOS1 to MOS4 to U terminal 32, the path through the switching element with the smaller marked number has a larger parasitic inductance. Therefore, in each path P1' to P4', the current is rapidly dispersed, suppressing current concentration in a portion of the path.

[0108] Alternatively, the switching elements MOS5 to MOS8 can also be configured such that the smaller the number of the marking, the lower the turn-on voltage of the switching element. Furthermore, the paths P5' to P8' from U terminal 32 through each switching element MOS5 to MOS8 to N terminal 33 also exhibit different parasitic inductances, with smaller markings for each path. With this structure, in paths P5' to P8', similar to paths P1' to P4', the current is rapidly dispersed, suppressing current concentration in a portion of the path.

[0109] That is, the semiconductor module 1 can also be configured in such a way as to suppress the concentration of current to a portion of the switching elements: it has an electronic circuit consisting of multiple switching elements connected in parallel, the multiple switching elements including a first switching element (e.g., switching element MOS1) and a second switching element (e.g., switching element MOS2) with a turn-on voltage higher than that of the first switching element. In this electronic circuit, the inductance of the first path from the first terminal (e.g., P terminal 31) through the first switching element to the second terminal (e.g., U terminal 32) is greater than the inductance of the second path from the first terminal through the second switching element to the second terminal.

[0110] In the above embodiment, the wiring component is formed in such a way that the path with the smaller number of the marking in path P1 to P4 has a larger parasitic inductance. However, in another embodiment, inductor elements with different inductances (e.g., inductors with cores with different permeabilities) may be arranged in each path P1 to P4 in such a way that the path with the smaller number of the marking in path P1 to P4 has a larger inductance.

[0111] Figure 11 This is a schematic diagram illustrating a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes semiconductor modules 1A and 1B connected in parallel. Semiconductor modules 1A and 1B have the same structure as the semiconductor module 1 according to the above-described embodiment. Figure 4 For convenience, semiconductor module 1A is represented by a frame with P terminal 31A and N terminal 33A, and semiconductor module 1B is represented by a frame with P terminal 31B and N terminal 33B.

[0112] Terminals P 31A and 31B are electrically connected to the positive potential point 200A (one of the terminals in the pair) on the positive side of the power supply 200. Terminals N 33A and 33B are electrically connected to the negative potential point 200B (the other of the pair) on the negative side of the power supply 200. The path from the positive potential point 200A to the negative potential point 200B via the semiconductor module 1A is marked with P1. A Mark P1 as the path from positive potential point 200A to negative potential point 200B via semiconductor module 1B. B .

[0113] The forward voltage of semiconductor module 1A and the forward voltage of semiconductor module 1B also contain discrepancies. Therefore, there is concern about current concentration in the semiconductor module with the lower forward voltage. Therefore, the semiconductor device 100 has a structure where the inductance through the path of the semiconductor module with the lower forward voltage is greater.

[0114] In this example, the forward voltage of semiconductor module 1A is lower than the forward voltage of semiconductor module 1B. Additionally, path P1... A The parasitic inductance is greater than that of path P1 B The parasitic inductance is large.

[0115] Current begins to flow towards path P1, which is configured with semiconductor module 1A, which has a low forward voltage. A Following the flow path P1 A The change (increase) in current along path P1 A The generation and path P1 A The parasitic inductance of the wiring component is proportional to the back electromotive force. Due to this back electromotive force, current becomes less likely to flow to path P1. A In other words, the current becomes easier to flow to path P1. B That is, the current is rapidly distributed to the parallel-connected path P1. A and path P1 B Suppress current in path P1 A The concentration of current. Therefore, in this example, it is also possible to prevent abnormal heating and damage to semiconductor components such as Schottky barrier diodes caused by current concentration.

[0116] exist Figure 11 The invention illustrates a semiconductor device formed by connecting two semiconductor modules in parallel, but semiconductor devices formed by connecting three or more semiconductor modules in parallel are also within the scope of this invention.

[0117] This embodiment and its variations have been described, but as other embodiments, the above embodiments and variations may be combined in whole or in part.

[0118] Furthermore, this embodiment is not limited to the above-described embodiments and variations, and various changes, substitutions, and modifications can be made without departing from the spirit of the technical concept. Moreover, if the technical concept can be implemented by other methods due to technological advancements or other derived technologies, those methods can also be used. Therefore, the claims cover all embodiments that can be included within the scope of the technical concept.

[0119] The following is a summary of the feature points in the above embodiments.

[0120] The electronic circuit described in the above embodiments is an electronic circuit composed of multiple diodes connected in parallel. The multiple diodes include a first diode and a second diode with a forward voltage higher than that of the first diode. The inductance of the first path from the first terminal through the first diode to the second terminal is greater than the inductance of the second path from the first terminal through the second diode to the second terminal.

[0121] In the electronic circuit described in the above embodiments, in each path from the first terminal through each of the plurality of diodes to the second terminal, the path through the diode with the lower forward voltage has a greater inductance.

[0122] In the electronic circuit described in the above embodiments, the inductor is an inductor on the anode side.

[0123] The semiconductor module described in the above embodiments has an electronic circuit, which is formed by connecting a plurality of diodes in parallel. The plurality of diodes includes a first diode and a second diode with a forward voltage higher than that of the first diode. The inductance of the wiring member forming a first path from the first terminal through the first diode to the second terminal is greater than the inductance of the wiring member forming a second path from the first terminal through the second diode to the second terminal.

[0124] The semiconductor module described in the above embodiments includes a substrate on which the electronic circuit is mounted. The wiring component of the first path includes a first conductive line that connects the first terminal or the second terminal disposed on the substrate to the first diode. The wiring component of the second path includes a second conductive line that connects the first terminal or the second terminal disposed on the substrate to the second diode. The inductance of the first conductive line is greater than the inductance of the second conductive line.

[0125] The semiconductor module described in the above embodiments satisfies at least one of the following conditions (1) to (2):

[0126] (1) The total length of the first conductive line is longer than the total length of the second conductive line;

[0127] (2) The cross-sectional area of ​​the first conductive wire is smaller than that of the second conductive wire.

[0128] The semiconductor module described in the above embodiments includes a substrate on which the electronic circuit is mounted. The wiring component of the first path includes a first wiring pattern that connects the first terminal or the second terminal disposed on the substrate to the first diode. The wiring component of the second path includes a second wiring pattern that connects the first terminal or the second terminal disposed on the substrate to the second diode. The inductance of the first wiring pattern is greater than the inductance of the second wiring pattern.

[0129] The semiconductor module described in the above embodiments satisfies at least one of the following conditions (3) to (4):

[0130] (3) The total length of the first wiring pattern is longer than the total length of the second wiring pattern;

[0131] (4) The cross-sectional area of ​​the first wiring pattern is smaller than that of the second wiring pattern.

[0132] In the semiconductor module described in the above embodiments, the plurality of diodes are diodes having the same structure.

[0133] In the semiconductor module described in the above embodiments, the plurality of diodes are diodes made using silicon carbide (SiC).

[0134] The semiconductor device described in the above embodiments includes a plurality of semiconductor modules connected in parallel between a pair of terminals. The semiconductor modules are the semiconductor modules described above. In each path from one of the terminals in the pair of terminals through each of the plurality of semiconductor modules to the other terminal in the pair of terminals, the path through the semiconductor module with the lower forward voltage has a greater inductance.

[0135] The electronic circuit described in the above embodiments is composed of multiple switching elements connected in parallel. The multiple switching elements include a first switching element and a second switching element whose turn-on voltage is higher than that of the first switching element. The inductance of the first path from the first terminal through the first switching element to the second terminal is greater than the inductance of the second path from the first terminal through the second switching element to the second terminal.

[0136] Industrial availability

[0137] As explained above, the present invention has the effect of suppressing current concentration in a portion of a plurality of semiconductor elements connected in parallel, and is particularly useful for electronic circuits, semiconductor modules and semiconductor devices.

Claims

1. An electronic circuit that is connected in parallel with a plurality of diodes including a first diode and a second diode having a forward voltage higher than that of the first diode, an inductance of a first path from a first terminal to a second terminal via the first diode is larger than an inductance of a second path from the first terminal to the second terminal via the second diode.

2. The electronic circuit according to claim 1, wherein in each path from the first terminal to the second terminal via each diode of the plurality of diodes, an inductance of a path via a diode having a lower forward voltage is larger.

3. The electronic circuit according to claim 1 or 2, wherein the inductance is an inductance on an anode side.

4. A semiconductor module having an electronic circuit that is connected in parallel with a plurality of diodes including a first diode and a second diode having a forward voltage higher than that of the first diode, an inductance of a wiring member forming a first path from a first terminal to a second terminal via the first diode is larger than an inductance of a wiring member forming a second path from the first terminal to the second terminal via the second diode.

5. The semiconductor module according to claim 4, wherein a substrate on which the electronic circuit is mounted is provided, the wiring member of the first path includes a first conductive line connecting the first terminal or the second terminal provided on the substrate and the first diode, the wiring member of the second path includes a second conductive line connecting the first terminal or the second terminal provided on the substrate and the second diode, the inductance of the first conductive line is larger than the inductance of the second conductive line.

6. The semiconductor module according to claim 5, wherein at least one of the following conditions (1) and (2) is satisfied: (1) a total length of the first conductive line is longer than a total length of the second conductive line; (2) a cross-sectional area of the first conductive line is smaller than a cross-sectional area of the second conductive line.

7. The semiconductor module according to claim 4, wherein a substrate on which the electronic circuit is mounted is provided, the wiring member of the first path includes a first wiring pattern connecting the first terminal or the second terminal provided on the substrate and the first diode, the wiring member of the second path includes a second wiring pattern connecting the first terminal or the second terminal provided on the substrate and the second diode, the inductance of the first wiring pattern is larger than the inductance of the second wiring pattern.

8. The semiconductor module according to claim 7, wherein at least one of the following conditions (3) and (4) is satisfied: (3) a total length of the first wiring pattern is longer than a total length of the second wiring pattern; (4) a cross-sectional area of the first wiring pattern is smaller than a cross-sectional area of the second wiring pattern.

9. The semiconductor module according to any one of claims 4 to 8, wherein The plurality of diodes are diodes having the same configuration.

10. The semiconductor module according to any one of claims 4 to 8, characterized in that The plurality of diodes are diodes fabricated using silicon carbide (SiC).

11. A semiconductor device comprising a plurality of semiconductor modules connected in parallel between a pair of terminals, the semiconductor modules being the semiconductor module according to any one of claims 4 to 10, In each path from one of the pair of terminals to the other of the pair of terminals via each of the plurality of semiconductor modules, the inductance of the path via the semiconductor module having the lower forward voltage is greater.

12. An electronic circuit in which a plurality of switching elements are connected in parallel, the plurality of switching elements including a first switching element and a second switching element having a higher on-voltage than the first switching element, The inductance of a first path from a first terminal to a second terminal via the first switching element is greater than the inductance of a second path from the first terminal to the second terminal via the second switching element.

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