Storage device and method of operating the same

Abstract

A memory device includes: a memory cell array including cell strings respectively connected between a string select line and a ground select line; word lines connected to the memory cells; control logic that generates a first voltage supplied to the string select line and a second voltage supplied to the ground select line, and adjusts voltage levels of the first voltage and the second voltage to control a channel boost level of the cell strings; and a row decoder that supplies a read voltage, a read pass voltage, and the first voltage and the second voltage to the memory cell array under the control of the control logic. The control logic generates one of the first voltage and the second voltage as a pre-pulse voltage. The row decoder supplies a third voltage to at least one of the word lines.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0175689, titled "Storage Device and Method of Operating the Same", filed with the Korean Intellectual Property Office on December 26, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments relate to a storage device and a method of operating the same. Background Art

[0004] A storage device including non - volatile memory elements uses a pre - pulse scheme to prevent hot carrier injection (HCI) or soft erasure from occurring during execution of a read operation, a program verification operation, etc. Summary of the Invention

[0005] Embodiments are directed to a storage device, including: a memory cell array including a plurality of cell strings, each cell string including a plurality of memory cells respectively connected between a plurality of string selection lines and a plurality of ground selection lines and a plurality of word lines connected to the plurality of memory cells; control logic configured to generate a first voltage provided to the plurality of string selection lines and a second voltage provided to the plurality of ground selection lines and adjust each voltage level of the first voltage and the second voltage to control a channel boost level of the plurality of cell strings; and a row decoder configured to provide a read voltage, a read - through voltage, the first voltage, and the second voltage to the memory cell array under the control of the control logic. The control logic may generate one of the first voltage and the second voltage as a pre - pulse voltage. The row decoder may provide a third voltage to at least one of the plurality of word lines. The third voltage may have a first level when the pre - pulse voltage has a level higher than or equal to a predetermined first threshold, and may have a second level higher than the first level when the pre - pulse voltage has a level lower than the first threshold.

[0006] Embodiments are also directed to a storage device, including: a plurality of cell strings, each cell string including a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines and connected in series between a plurality of string selection lines and a plurality of ground selection lines; and control logic configured to select at least one of the plurality of cell strings to perform a read operation or a program verification operation and configured to control a pre - pulse voltage such that the pre - pulse voltage is selectively input to a string selection line or a ground selection line connected to an unselected cell string. The value of the pre - pulse voltage may be greater than a predetermined threshold during a period before a predetermined read voltage according to a threshold voltage distribution is input to a selected cell string, and may be less than or equal to the predetermined threshold during a period of inputting the predetermined read voltage.

[0007] The embodiment also relates to a storage device, including: a memory cell array including a plurality of cell strings, each cell string including a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells; control logic configured to control a plurality of string select lines or a plurality of ground select lines connected to the plurality of cell strings to be precharged and adjust at least one of the plurality of word lines to control a potential level of each channel of the plurality of cell strings, thereby performing a read operation and a program verification operation; and a row decoder configured to input a read voltage or a read through voltage to the plurality of word lines under the control of the control logic to control the read operation or the program verification operation. The control logic may select at least one word line connected to a dummy memory cell among the plurality of memory cells as a barrier line and may input a predetermined control voltage to control the potential level of the channel, where the predetermined control voltage has a level lower than the level of the read through voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing example embodiments in detail with reference to the attached drawings, in which:

[0009] Figure 1 A storage device according to an example embodiment is shown.

[0010] Figure 2 is an equivalent circuit diagram of a memory cell array of a storage device according to an example embodiment.

[0011] Figure 3A and Figure 3B A storage device according to an example embodiment is shown.

[0012] Figure 4A and Figure 4B A storage device according to an example embodiment is shown.

[0013] Figure 5 is a circuit diagram of a cell string of a storage device according to an example embodiment.

[0014] Figures 6 to 8 An operation of a storage device according to an example embodiment is shown.

[0015] Figure 9 is a flowchart of an operation method of a storage device according to an example embodiment.

[0016] Figure 10A and Figure 10B is a flowchart of a method of selecting a barrier line in a storage device according to an example embodiment.

[0017] Figures 11 to 12B An operation of a storage device according to an example embodiment is shown.

[0018] Figure 13A and Figure 13B illustrates the operation of a storage device according to an exemplary embodiment.

[0019] Figures 14 to 15B illustrates the operation of a storage device according to an exemplary embodiment.

[0020] Figures 16 to 17B illustrates the operation of a storage device according to an exemplary embodiment.

[0021] Figure 18 is a flowchart showing a method of operating a storage device according to an exemplary embodiment.

[0022] Figure 19 illustrates a mobile system including a storage device according to an exemplary embodiment.

[0023] Figure 20 illustrates a data center including a storage device according to an exemplary embodiment.

[0024] Figure 21 is a diagram showing a storage device according to another exemplary embodiment. DETAILED DESCRIPTION

[0025] Figure 1 illustrates a storage device according to an exemplary embodiment.

[0026] Referring Figure 1 , a storage device 100 according to an exemplary embodiment may include a memory cell array 110, a voltage generator 120, control logic 130, a row decoder 140, and a read / write circuit 150. The memory cell array 110 may include a plurality of memory cells and may be divided into a plurality of blocks.

[0027] The plurality of memory cells may be connected to the row decoder 140 through string selection lines SSL, word lines WL, and ground selection lines GSL, and may be connected to a page buffer PB of the read / write circuit 150 through bit lines BL. As an example, in each of the plurality of blocks included in the memory cell array 110, a plurality of memory cells arranged at the same height from the substrate may be connected to the same word line WL, and a plurality of memory cells arranged at the same position on a plane parallel to the upper surface of the substrate may be provided with a cell string sharing a single channel region.

[0028] The voltage generator 120 may generate various voltages for the operation of the storage device 100 using externally provided power PWR. For example, the voltage generator 120 may generate a read voltage and a read pass voltage provided to the word line WL for read operations and / or program verification operations. Additionally, the voltage generator 120 may generate a control voltage and a pre-pulse voltage provided to the string selection lines SSL and the ground selection lines GSL.

[0029] The control logic 130 may generate various control signals for a programming operation or a read operation based on a command CMD and an address ADDR received from the outside. For example, the control logic 130 may generate a voltage control signal for controlling the level of the voltage generated by the voltage generator 120. In addition, the control logic 130 may provide a row address signal X-ADDR to the row decoder 140 and may provide a column address signal Y-ADDR to the read / write circuit 150.

[0030] The row decoder 140 may select at least one of a plurality of cell strings included in the memory cell array 110 in response to the row address signal X-ADDR and may select at least one word line among a plurality of word lines connected to the selected cell string. As an example, in a read operation, the row decoder 140 may provide a read voltage to the selected word line and may provide a read pass voltage to the unselected word lines. In addition, the row decoder 140 may provide a control voltage for a read operation to the selected string select line and the selected ground select line connected to the selected cell string.

[0031] In an exemplary embodiment, the row decoder 140 may selectively provide a pre-pulse voltage to an unselected string select line or an unselected ground select line connected to an unselected cell string in a read operation. For example, the row decoder 140 may provide a pre-pulse voltage to the unselected string select line and may provide a ground voltage to the unselected ground select line during a setup period of the word line. In another embodiment, the row decoder 140 may provide a ground voltage to the unselected string select line and may provide a pre-pulse voltage to the unselected ground select line during a setup period of the word line.

[0032] The control logic 130 may be configured to control a channel boost level of a cell string to a predetermined level in a read operation and may include a channel boost control unit CBC. The channel boost control unit CBC may output a pre-pulse control signal to the row decoder 140 to selectively provide a pre-pulse voltage to an unselected string select line or an unselected ground select line during a predetermined channel boost period in a read operation. In addition, the channel boost control unit CBC may logically divide a channel region included in an unselected cell string into a plurality of channel regions during a predetermined channel boost period in a read operation and may select at least one of a plurality of unselected word lines as a barrier line to control a channel boost level of each of the plurality of separated channel regions. In Figure 1 FIG., the channel boost control unit CBC is shown as being included in the control logic 130. However, the channel boost control unit CBC may be implemented outside the control logic 130.

[0033] The channel boost control unit CBC can control the row decoder 140 to supply a voltage lower than a predetermined threshold to the barrier line during a channel boost period for adjusting the potentials of a plurality of logically separated channel regions, for example, supply a ground voltage to the barrier line. Additionally, the channel boost control unit CBC can control the row decoder 140 to supply a voltage higher than or equal to the threshold to the barrier line during a readout period when a read voltage is input to a selected word line and the page buffer reads data from selected memory cells connected to the selected word line, for example, supply a voltage identical to the read pass voltage to the barrier line.

[0034] During the channel boost period, under the control of the channel boost control unit CBC, the potential of the channel disposed above the barrier line can be boosted to a first level, and the potential of the channel disposed below the barrier line can be boosted to a second level. The second level can be lower than the first level and can be, for example, a ground level. The above example can correspond to the case where the selected word line is disposed above the barrier line. As an example, when the selected word line is disposed below the barrier line, the potential of the channel disposed above the barrier line can be boosted to the second level, and the potential of the channel disposed below the barrier line can be boosted to the first level.

[0035] When a voltage higher than or equal to a predetermined threshold is input to the barrier line during the readout period, the potentials of the channels disposed above and below the barrier line can be boosted to a third level lower than the first level and higher than the second level. Thus, when the channel boost control unit CBC performs a read operation, the channel potentials of unselected cell strings can be lower than the existing boosted levels. Accordingly, an increase in power consumption can be significantly reduced, and the occurrence of hot carrier injection (HCI) or soft erase can be effectively suppressed.

[0036] The read / write circuit 150 can function as a write driver or a sense amplifier and can include a page buffer PB. For example, in a programming operation, the read / write circuit 150 can function as a write driver to supply a voltage determined depending on data to be stored in the memory cell array 110 to the bit line BL. Additionally, during a read operation, the read / write circuit 150 can operate as a sense amplifier to read data stored in the memory cell array 110.

[0037] The storage device 100 according to an exemplary embodiment can have a multi-stack (or, multi-layer) structure, wherein each of the channel regions passing through a plurality of word lines WL includes a lower channel region and an upper channel region. The lower channel region and the upper channel region can be connected to each other in a direction perpendicular to the substrate. Depending on the degree of integration density of the storage device 100, the number of stacking levels of the plurality of word lines WL can be determined to be 48, 64, 96, etc. In an exemplary embodiment, the number of stacking levels of the plurality of word lines WL can be about 190 or more.

[0038] The storage device 100 according to an exemplary embodiment may have a chip-on-periphery (COP) structure in which a plurality of memory cells are formed and disposed on a peripheral circuit. The peripheral circuit may include a control logic 130, a row decoder 140, and a read / write circuit 150 on a single wafer. In another embodiment, the storage device 100 may have a structure in which the peripheral circuit and the plurality of memory cells are formed on different wafers and then electrically connected to each other using a metal interconnect technology or the like.

[0039] Figure 2 FIG. 4 is an equivalent circuit diagram showing a memory cell array of a storage device according to an exemplary embodiment.

[0040] Referring Figure 2 to FIG. 4, the memory cell array 200 may include a plurality of cell strings S1 to Sn, each cell string including n memory cells MC1 to MCn connected in series with each other. The cell strings S1 to Sn may each include a ground selection transistor GST and a string selection transistor SST connected in series to both ends of the memory cells MC1 to MCn, respectively. The n memory cells MC1 to MCn connected in series with each other may be connected to n word lines WL1 to WLn, respectively. A dummy cell in which no data is stored may be further provided between the ground selection transistor GST and the first memory cell MC1 and / or between the string selection transistor SST and the nth memory cell MCn. The dummy cell may be added differently to positions other than the above positions.

[0041] In the ground selection transistor GST, the gate terminal may be connected to ground selection lines GSL1 to GSLn, and the source terminal may be connected to a common source line CSL. In the string selection transistor SST, the gate terminal may be connected to string selection lines SSL1 to SSLn, and the source terminal may be connected to the drain terminal of the nth memory cell MCn.

[0042] Although Figure 2 FIG. 4 shows a structure in which a single ground selection transistor GST and a single string selection transistor SST are connected to n memory cells MC1 to MCn connected in series with each other, a plurality of ground selection transistors GST and / or a plurality of string selection transistors SST may be connected to the n memory cells MC1 to MCn.

[0043] The drain terminal of the string select transistor SST may be connected to a corresponding one of the bit lines BL1 to BLm. When a signal is input to the gate terminal of the string select transistor SST through the string select lines SSL1 to SSLn, the signals input through the bit lines BL1 to BLm may be sent to the memory cells MC1 to MCn connected in series with each other to perform a programming operation or a read operation. Additionally, a predetermined erase voltage may be input through a well region formed in the substrate so that an erase operation is performed to erase the data written in the memory cells MC1 to MCn.

[0044] In a read operation, a turn-on voltage having a predetermined level may be input to a selected string select line and a selected ground select line connected to a selected cell string. Additionally, a predetermined pre-pulse voltage may be selectively input to an unselected string select line or an unselected ground select line connected to an unselected cell string. Based on at least one selected from a plurality of unselected word lines, a channel provided on one side of a barrier line may have a potential set to a first level, and a channel provided on the other side of the barrier line may have a potential set to a second level different from the first level. During a read period in which a read voltage is input to a selected word line connected to a selected memory cell to read data, the potential of the channel may be set to a third level between the first level and the second level.

[0045] Figure 3A and Figure 3B shows a storage device according to an exemplary embodiment. Figure 3A shows the structure of a storage device according to an exemplary embodiment, and Figure 3B shows the structure of a cell region of a storage device according to an exemplary embodiment.

[0046] First, referring to Figure 3A , a storage device 300 according to an exemplary embodiment may include a cell region C and a peripheral circuit region P stacked in a vertical direction.

[0047] The peripheral circuit region P may be provided below the cell region C and may include a first substrate 301. Additionally, the peripheral circuit region P may include a plurality of circuit elements 303 provided on the first substrate 301, a plurality of wirings 305 connected to the circuit elements 303, an interlayer insulating layer 307 that insulates the circuit elements 303 and the wirings 305 from each other, and the like. The circuit elements 303 included in the peripheral circuit region P may provide circuits for driving the storage device 300 (e.g., page buffers, row decoders, etc.).

[0048] The cell region C may include a second substrate 302 disposed on the first interlayer insulating layer 307. Additionally, the cell region C may include a ground selection line GSL, word lines WL, string selection lines SSL1 and SSL2, and a plurality of insulating layers IL stacked on the second substrate 302. The plurality of insulating layers IL may be stacked alternately with the ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2. The number of the ground selection line GSL and the string selection lines SSL1 and SSL2 may be variously modified with respect to Figure 3A the number shown in

[0049] Additionally, the cell region C may include a channel structure CH extending in a first direction (Z-axis direction) perpendicular to the upper surface of the second substrate 302. The channel structure CH may pass through the ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2 to connect to the second substrate 302. The channel structure CH may include a channel region 310, a buried insulating layer 320 filling the internal space of the channel region 310, a bit line connection layer 330, etc. Each of the channel structures CH may be connected to at least one bit line through the bit line connection layer 330. The ground selection line GSL, word lines WL, string selection lines SSL1 and SSL2, insulating layer IL, and channel structure CH may be defined as a stacked structure.

[0050] At least one gate insulating layer may be disposed outside the channel region 310. In an exemplary embodiment, the gate insulating layer may include a tunneling layer, a charge storage layer, a blocking layer, etc. sequentially disposed from the channel region 310. At least one of the tunneling layer, charge storage layer, and blocking layer may have a shape surrounding the ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2.

[0051] The ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2 may be covered by an interlayer insulating layer 350. Additionally, the ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2 may be divided into a plurality of regions through word line cuts 340. In an exemplary embodiment, the string selection lines SSL1 and SSL2 may be divided into a plurality of regions by an isolation insulating layer 360 between a pair of word line cuts 340 adjacent to each other in a second direction (Y-axis direction) parallel to the upper surface of the second substrate 302.

[0052] In the region where the isolation insulating layer 360 is provided, one or more dummy channel structures DCH having the same structure as the channel structure CH may be provided. Different from the channel structure CH, the dummy channel structure DCH may not be electrically connected to the bit line.

[0053] Reference Figure 3B, the cell region C1 of the memory device 300 according to the exemplary embodiment may include a ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2 stacked on the upper surface of the substrate 302. The ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2 may be divided into a plurality of regions by word line cuts WC, and the string selection lines SSL1 and SSL2 may be divided into a plurality of regions between a pair of word line cuts WC. The number of the ground selection line GSL and the string selection lines SSL1 and SSL2 may be different from Figure 3B the number shown therein. The channel structure CH may pass through the ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2.

[0054] The channel structure CH and the word line cuts WC may extend in a first direction (Z-axis direction), and their widths may not be constant along the first direction. For example, the channel structure CH and the word line cuts WC may have a tapered structure in which the width (e.g., the width along the Y-axis direction) decreases along the first direction toward the substrate 302.

[0055] Unlike Figure 3A and Figure 3B shown therein, in a memory device according to another exemplary embodiment, each of the channel structures CH may have a double-layer stacked structure including an upper channel structure and a lower channel structure, as will be described in detail below with reference to Figure 4A and Figure 4B .

[0056] Figure 4A and Figure 4B show a memory device according to the exemplary embodiment. Figure 4A shows the structure of a memory device according to the exemplary embodiment, and Figure 4B shows the structure of the cell region of a memory device according to the exemplary embodiment.

[0057] Referring to Figure 4A , a memory device 400 according to the exemplary embodiment may include a cell region C and a peripheral circuit region P stacked in a vertical direction. Figure 4A The memory device 400 may have a structure similar to that of the Figure 3A memory device 300, and repeated descriptions may be omitted below.

[0058] The memory device 400 may include a channel structure CH extending in a first direction (Z-axis direction) perpendicular to the upper surface of the second substrate 402 and passing through the ground selection line GSL, word lines WL, and string selection lines SSL1 and SSL2. To overcome process difficulties caused by an increase in the number of word lines WL, after stacking the lower word lines and forming the lower channel structure, the upper word lines may be stacked and the upper channel structure may be formed. Thus, asFigure 4A As shown, each of the channel structures CH may have a double-layer stacked structure including an upper channel structure and a lower channel structure.

[0059] The lower channel structure may extend from the second substrate 402, and the upper channel structure may extend from the lower channel structure to be connected to the bit line through the bit line connection layer 430. In each channel structure CH, the channel region 410 of the upper channel structure and the channel region 410 of the lower channel structure may be connected to each other. The upper channel structure, the lower channel structure, and the word line cut 440 may have a tapered structure, the width of which decreases in the direction from the first direction (Z-axis direction) toward the second substrate 402.

[0060] Reference Figure 4B , in the cell region C2 of the memory device 400 according to the exemplary embodiment, each of the channel structures CH may include a lower channel structure LCH extending from the substrate 402 and an upper channel structure UCH connected to the lower channel structure LCH. The lower channel structure LCH may penetrate the lower word line LWL and may provide a lower memory cell. The upper channel structure UCH may penetrate the upper word line UWL and may provide an upper memory cell. Additionally, an intermediate word line MWL may be disposed at the boundary between the upper channel structure UCH and the lower channel structure LCH connected to each other. In Figure 4B the exemplary embodiment shown, it is assumed that the number of the lower word lines LWL and the number of the upper word lines UWL are the same, but the number of the lower word lines LWL and the number of the upper word lines UWL may be different from each other, and various changes may be made thereto.

[0061] In Figure 4B the exemplary embodiment shown, the word line cuts WC may be formed at once. Accordingly, the height of each of the word line cuts WC may be greater than the height of the lower channel structure LCH or the upper channel structure UCH. The channel structures CH and the word line cuts WC may have different side profiles.

[0062] In reference Figures 3A to 4BIn the storage devices 300 and 400 according to the exemplary embodiments described, at least one of the plurality of word lines WL can be selected as a barrier line while performing a read operation, and the voltage input to the barrier line can be controlled to be different from that of other unselected word lines. Accordingly, the channel potential of the unselected cell string can be controlled. For example, in the storage devices 300 and 400, among the unselected word lines, at least one unselected word line can be selected as a barrier line in a read operation and / or a program verification operation, and the time point at which a read pass voltage is input to the barrier line can be controlled to be after a channel boost period. Accordingly, the channel potential of the unselected cell string can be controlled within a predetermined range. As described above, the channel potential of the unselected cell string can be controlled within a predetermined range during a read operation, so that the occurrence of hot carrier injection (HCI) or soft erasure can be suppressed to improve data reliability. As an example, in Figure 4A and Figure 4B the exemplary embodiment shown, an intermediate word line MWL adjacent to the boundary between the lower channel structure LCH and the upper channel structure UCH can be selected as a barrier line.

[0063] Figure 5 FIG. is a circuit diagram showing a cell string of a storage device according to an exemplary embodiment.

[0064] Referring Figure 5 , a storage device according to an exemplary embodiment can include a plurality of cell strings S1 to S4 included in a memory cell array 500. In Figure 5 FIG., the memory cell array 500 is shown as including four cell strings S1 to S4. However, various changes can be made to the number of cell strings S1 to S4.

[0065] The plurality of cell strings S1 to S4 can be connected to bit lines BL through corresponding string select transistors SST1 to SST4. For example, the first cell string S1 can be connected to the bit line BL through the first string select transistor SST1. Similarly, the fourth cell string S4 can be connected to the bit line BL through the fourth string select transistor SST4. Different from that shown in Figure 5 FIG., at least one of the plurality of cell strings S1 to S4 can be connected to a different bit line BL. The plurality of string select transistors SST1 to SST4 can receive control signals from a row decoder through different string select lines SSL1 to SSL4.

[0066] The cell strings S1 to S4 can be connected to a common source line CSL through corresponding ground selection transistors GST1 to GST4. For example, the first cell string S1 can be connected to the common source line CSL through the first ground selection transistor GST1. Similarly, the fourth cell string S4 can be connected to the common source line CSL through the fourth ground selection transistor GST4. The plurality of ground selection transistors GST1 to GST4 can receive control signals from a row decoder through different ground selection lines GSL1 to GSL4 for operation.

[0067] Each of the cell strings S1 to S4 can include a plurality of memory cells MC1 to MC12 connected in series with each other between corresponding string selection transistors SST1 to SST4 and corresponding ground selection transistors GST1 to GST4. In Figure 5 it, each of the four cell strings S1 to S4 is shown as including 12 memory cells MC1 to MC12. However, various changes can be made to the number of memory cells. Each of the cell strings S1 to S4 can also include at least one dummy memory cell, and the at least one dummy memory cell is disposed between the ground selection transistors GST1 to GST4 and the first memory cell MC1 and / or between the twelfth memory cell MC12 and the string selection transistors SST1 to SST4. In another exemplary embodiment, dummy memory cells can be added to positions different from the above-described exemplary positions.

[0068] Multiple memory cells arranged along the same row can be connected to the same word line. For example, the first memory cell MC1 included in the multiple cell strings S1 to S4 can be commonly connected to the first word line WL1. Similarly, the twelfth memory cell MC12 included in the multiple cell strings S1 to S4 can be commonly connected to the twelfth word line WL12.

[0069] In a storage device, one of the multiple cell strings S1 to S4 can be selected during a read operation and / or a program verification operation, and a read voltage and a read pass voltage can be input to the multiple word lines WL1 to WL12 connected to the selected cell string. For example, a read voltage can be input to the selected word line connected to the selected memory cell to read data, and a read pass voltage can be input to the unselected word lines. Moreover, in a storage device, a predetermined conduction voltage can be input to the selected string selection line and the selected ground selection line connected to the selected cell string. In an exemplary embodiment, the read pass voltage can be about 10V or less, and the conduction voltage can be about 5V to about 8V.

[0070] Figures 6 to 8 An operation of a storage device according to an exemplary embodiment is shown. Figure 6 and Figure 8 are waveform diagrams showing the operation of the storage device, and Figure 7Shows the change in the threshold voltage distribution of the memory device.

[0071] Reference Figure 6 , the read operation and / or the program verification operation of the memory device may include a first period P1, a second period P2, and a third period P3. The first period P1 may be the period between t1 and t2, during which the channel of the unselected cell string is boosted. The second period P2 may be the period between t2 and t3, during which the predetermined read voltages VREAD1 and VREAD2 are input to the selected word line according to the threshold voltage distribution of the selected memory cell. The third period P3 may be the period between t3 and t4, during which a recovery operation is performed.

[0072] During the first period P1 and the second period P2, a voltage equal to or higher than the threshold voltage may be provided to the selected string select transistor and the selected ground select transistor included in the selected cell string through the selected string select line Sel_SSL and the selected ground select line Sel_GSL to turn them on. During the first period P1 and the second period P2, a voltage less than or equal to the threshold voltage may be provided to the unselected string select transistor and the unselected ground select transistor included in the unselected cell string through the unselected string select line Unsel_SSL and the unselected ground select line Unsel_GSL to turn them off.

[0073] In the memory device, during the first period P1 and the second period P2, the read pass voltage VPASS may be input to the unselected word line Unsel_WL. In the memory device, the precharge voltage may be input to the selected word line Sel_WL during the first period P1, and the read voltages VREAD1 and VREAD2 may be input to the selected word line Sel_WL during the second period P2. For example, depending on the threshold voltage distribution of the memory cell, the read voltage, as well as the number and levels of the memory cells, may vary with respect to Figure 6 the case shown. For example, when the memory cell is a triple-level cell (TLC) storing 3-bit data, the memory device may perform a read operation using two or more read voltages having different levels from each other.

[0074] The above operations may cause the channel potential CH of the unselected cell string to be boosted to a predetermined level VBOOST during the first period P1, and soft erase may occur due to the voltage difference L1 between the read voltages VREAD1 and VREAD2.

[0075] As Figure 7 shown, when soft erase occurs, the threshold voltage distribution of the memory cell may change. The higher the threshold voltage of the memory cell, the greater the degree of change in the threshold voltage distribution may be. Compared with Figure 7As shown in [reference], the change in the threshold voltage distribution can have various aspects. For example, the threshold voltage can decrease in the third programming state P3 to the sixth programming state P6, and can increase in the erase state E to the second programming state P2.

[0076] Therefore, at least a part of the threshold voltage distribution of the memory cells can overlap with each other. Therefore, it may not be possible to accurately determine the read voltage, and thus, read failures may occur and the reliability of the memory device may deteriorate.

[0077] To solve the above problems, in the memory device, a pre-pulse voltage can be input to both the unselected string selection line Unsel_SSL and the unselected ground selection line Unsel_GSL during the first period P1 to reduce the degree of boosting the channel potential CH of the unselected cell string. Refer to Figure 8 , during the first period P1, a voltage VPRE higher than or equal to the threshold voltage can be provided to the unselected string selection transistor and the unselected ground selection transistor connected to the unselected cell string through the unselected string selection line Unsel_SSL and the unselected ground selection line Unsel_GSL.

[0078] In the memory device, a read-through voltage VPASS can be input to the unselected word line Unsel_WL during the first period P1 and the second period P2. In the memory device, a pre-charge voltage can be input to the selected word line Sel_WL during the first period P1, and read voltages VREAD1 and VREAD2 can be input to the selected word line Sel_WL during the second period P2.

[0079] The above operations can boost the potential of the channel CH of the unselected cell string to a predetermined boost level VBOOST' during the first period P1. In this case, since the voltage difference L1' between the boost level VBOOST' of the channel CH of the unselected cell string and the read voltages VREAD1 and VREAD2 can be reduced compared to the voltage difference L1 shown in the exemplary embodiment described in Figure 6 reference, the occurrence of soft erasure can be significantly reduced.

[0080] In the operation described in Figure 8 reference, the unselected string selection transistor and the unselected ground selection transistor are turned on during the first period P1, and thus, power consumption and power supply size may increase. Therefore, in the memory device according to the present exemplary embodiment, only a part of the channel of the unselected cell string can be boosted during the first period P1 to reduce the final potential of the channel of the unselected cell string, and soft erasure can be prevented from occurring. In addition, in the memory device according to the present exemplary embodiment, the pre-pulse voltage can be selectively input to the unselected string selection line or the unselected ground selection line to significantly reduce the increase in power consumption and power supply size.

[0081] Figure 9 is a flowchart showing an operation method of a storage device according to an exemplary embodiment.

[0082] Referring Figure 9 , a read operation and / or a program verification operation of a storage device according to an exemplary embodiment may start with selecting at least one of a plurality of word lines connected to a selected cell string as a barrier line (S10). In the storage device, at least one word line among word lines other than the selected word line may be selected as the barrier line. As an example, at least one of dummy word lines may be selected as the barrier line.

[0083] In an exemplary embodiment, a read operation and / or a program verification operation of a storage device may include a first period, a second period, a third period, etc. In the first period, the channel potential of an unselected cell string is boosted. In the second period, a read voltage is input to a selected word line connected to a selected memory cell. In the third period, a recovery operation is performed. In this storage device, a voltage lower than a predetermined threshold (e.g., a ground voltage) may be input to the barrier line during the first period, and a voltage higher than or equal to the predetermined threshold (e.g., a read pass voltage) may be input to the barrier line during the second period.

[0084] In the storage device, a pre-pulse voltage may be input to an unselected string select line or an unselected ground select line included in the unselected cell string during the first period (S20). For example, during the first period, a pre-pulse voltage may be input to the unselected string select line, and a cut-off voltage (e.g., a ground voltage) may be input to the unselected ground select line. In another embodiment, during the first period, a cut-off voltage may be input to the unselected string select line, and a pre-pulse voltage may be input to the unselected ground select line. Thus, during the first period, the channel of the unselected cell string may be divided into: a region where the channel potential is boosted to a first level on one side of the barrier line, and a region where the channel potential is boosted to a second level different from the first level on the other side of the barrier line. When a read pass voltage is input to the barrier line during the second period, the potential of the channel of the unselected cell string may be boosted to a third level between the first level and the second level.

[0085] In the storage device, a predetermined read voltage may be input to the selected word line to perform a read operation (S30). In an exemplary embodiment, since the potential of the channel of the unselected cell string has a third level between the first level and the second level, a change in the threshold voltage distribution of the memory cell due to soft erasure may be reduced, read failure, etc. may be prevented, and the reliability of the storage device may be improved. In addition, since the pre-pulse voltage may be selectively input to the unselected string select line or the unselected ground select line, power consumption and power supply size may be reduced compared to a pre-pulse scheme according to the related art.

[0086] Hereinafter, a method of selecting a barrier line in a memory device according to an exemplary embodiment will be described in further detail.

[0087] Figure 10A and Figure 10B is a flowchart showing a method of selecting a barrier line in a memory device according to an exemplary embodiment.

[0088] Referring to Figure 10A , in a memory device, a read voltage input to a selected memory cell may be determined (S110). The read voltage may be a voltage input to a selected word line connected to the selected memory cell during a read operation, a program verification voltage used in a programming operation using an incremental step pulse programming (ISPP) scheme, an erase verification voltage used during an erase operation, and the like.

[0089] In a memory device, a voltage having a predetermined level so as to significantly reduce the number of memory cells that may experience read failures may be determined as the read voltage. For example, a voltage having a predetermined voltage difference from a reference voltage may be determined as the read voltage. The reference voltage may be set and changed based on the degree of degradation of memory cells such as the program / erase cycle (P / E cycle), high temperature stress (HTS), and the like.

[0090] In an exemplary embodiment, the read voltage may be determined depending on the read page of the selected memory cell. For example, when the selected memory cell is a triple-level cell (TLC) capable of storing 3-bit data, the read voltage may be determined according to the page to be read among the most significant bit (MSB), the center significant bit (CSB), and the least significant bit (LB) of the selected memory cell.

[0091] In a memory device, a channel boost level of an unselected cell string may be determined based on the determined read voltage (S120). For example, a voltage level having a predetermined voltage difference from the determined read voltage may be determined as the channel boost level of the unselected cell string.

[0092] Among a plurality of unselected word lines, at least one word line may be selected as a barrier line based on the determined channel boost level of the unselected cell string (S130). For example, the channel boost level of the unselected cell string may vary depending on the ratio of the number of word lines between the unselected string selection line and the barrier line to the number of word lines between the barrier line and the unselected ground selection line. In addition, the channel boost level of the unselected cell string may vary depending on the level of a read pass voltage input to the unselected word line. Therefore, considering the division ratio of the word lines or the level of the read pass voltage, at least one barrier line that satisfies the channel boost level determined in S120 may be selected among the unselected word lines.

[0093] Referring to Figure 10B, in a memory device, a read voltage to be input to a selected word line connected to a selected memory cell can be determined (S210). Additionally, a channel boost level of an unselected cell string can be determined based on the determined read voltage (S220).

[0094] At least one of a plurality of unselected word lines can be selected as a barrier line candidate based on the determined channel boost level (S230). For example, considering a division ratio of the word lines (a division ratio at which the channel boost level determined in S220 can be obtained) and / or a level of a read-through voltage, at least one unselected word line can be selected as a barrier line candidate.

[0095] Whether there is a dummy word line in the selected barrier line candidate and / or a word line adjacent to the selected barrier line candidate can be determined (S240). A plurality of dummy memory cells that do not store actual data can be connected to the dummy word line.

[0096] When there is a dummy word line in the barrier line candidate and / or a word line adjacent to the barrier line candidate, the dummy word line can be selected as the barrier line (S250). Additionally, when there is no dummy word line in the barrier line candidate and / or a word line adjacent to the barrier line candidate, at least one of the barrier line candidates can be selected as the barrier line (S260). The barrier line selected in S260 can not be a dummy word line.

[0097] Figures 11 to 12B An operation of a memory device according to an exemplary embodiment is illustrated.

[0098] Reference Figure 11 , the memory cell array 600 can include a plurality of cell strings S1 to S4. In Figure 11 , the memory cell array 600 is shown as including a first cell string S1 to a fourth cell string S4, but various modifications can be made to the configuration of the memory cell array 60. Each of the first cell string S1 to the fourth cell string S4 can include a plurality of memory cells MC1 to MC12 connected between string selection lines SSL1 to SSL4 and ground selection lines GSL1 to GSL4.

[0099] During a read operation and / or a program verification operation, data stored in a selected memory cell can be read by selecting at least one of the first cell string S1 to the fourth cell string S4 and inputting a read voltage to at least one selected word line connected to the selected cell string S1 to S4. For example, a read voltage can be input to the twelfth word line WL12 to read data stored in the twelfth memory cell MC12 connected to the first cell string S1. The read voltage can be input during a read operation, as well as during a program verification operation and an erase verification operation.

[0100] Among the multiple unselected word lines WL1 to WL11 connected to the first cell string S1, at least one unselected word line can be selected as the barrier line B_WL. For example, the sixth word line WL6 and the seventh word line WL7 can be selected as the barrier line B_WL.

[0101] The channels of the unselected cell strings S2 to S4 can be logically divided into multiple regions through the barrier line B_WL during the first period P1 of the read operation. In the memory device, a cut-off voltage (e.g., ground voltage) can be input to the barrier line B_WL during the first period P1. Additionally, a conduction voltage (e.g., a voltage equal to the read-through voltage) can be input to the barrier line B_WL during the second period P2. On the other hand, the read-through voltage can be input to the other word lines WL1 to WL5 and WL8 to WL11 among the multiple word lines WL1 - WL12 except for the selected word line WL12 and the barrier line B_WL.

[0102] A conduction voltage can be input to each of the selected string selection line SSL1 and the selected ground selection line GSL1. Additionally, a pre-pulse voltage can be selectively input to any one of the unselected string selection lines SSL2 to SSL4 and the unselected ground selection lines GSL1 to GSL4 during the first period P1.

[0103] To prevent hot carrier injection (HCI) from occurring in the barrier line B_WL due to the rapid change in the potential around the barrier line B_WL, the level of the read-through voltage input to the word lines adjacent to the barrier line B_WL can be adjusted. For example, during the first period P1, the levels of the read-through voltages input to the eighth word line WL8 and the ninth word line WL9 (set above the barrier line B_WL) and the fourth word line WL4 and the fifth word line WL5 (set below the barrier line B_WL) may be lower than the levels of the read-through voltages input to the other word lines. In the exemplary embodiment, the closer the word line is to the barrier line B_WL, the more the level of the read-through voltage can be reduced and then input. For example, during the first period P1, the read-through voltage can be input to the fifth word line WL5 and the eighth word line WL8 closest to the barrier line B_WL after reducing a first value. During the first period P1, after reducing a second value smaller than the first value, the read-through voltage can be input to the fourth word line WL4 and the ninth word line WL9 closest to the barrier line B_WL.

[0104] Hereinafter, reference will be made to Figure 12A and Figure 12B to describe the control signals input to the memory cell array 600 and the resulting changes in the channel potential of the unselected cell strings.

[0105] Reference Figure 12A and Figure 12B, a predetermined conduction voltage can be input to the first string selection line SSL1 (selected string selection line Sel_SSL) and the first ground selection line GSL1 (selected ground selection line Sel_GSL).

[0106] A predetermined cut-off voltage (e.g., ground voltage) can be input to the second string selection line SSL2 to the fourth string selection line SSL4 (unselected string selection line Unsel_SSL). A predetermined pre-pulse voltage can be input to the second ground selection line GSL2 to the fourth ground selection line GSL4 (unselected ground selection line Unsel_GSL). In the exemplary embodiment, the maximum value VPRE of the pre-pulse voltage can be about 3V or more and 4V or less.

[0107] A read-through voltage VPASS can be input to the first word line WL1 to the third word line WL3, the tenth word line WL10, and the eleventh word line WL11 (unselected word line Unsel_WL). A voltage higher than or equal to a predetermined threshold (e.g., read-through voltage VPASS) can be input to the sixth word line WL6 and the seventh word line WL7 selected as the barrier line B_WL.

[0108] During at least a part of the first period P1 and the second period P2, the voltage input to the fifth word line WL5 and the eighth word line WL8 (the word line BN1_WL closest to the barrier line B_WL) can be lower than the read-through voltage VPASS. As an example, at the time point t1 between the first period P1 and the second period P2, the voltage input to the fifth word line WL5 and the eighth word line WL5 can be lower than the read-through voltage VPASS by a first value m1.

[0109] During at least a part of the first period P1 and the second period P2, the voltage input to the fourth word line WL4 and the ninth word line WL9 (the next word line BN2_WL closest to the barrier line B_WL) can be lower than the read-through voltage VPASS. As an example, at the first time point t1 between the first period P1 and the second period P2, the voltage input to the fourth word line WL4 and the ninth word line WL9 can be lower than the read-through voltage VPASS by a second value m2. In the exemplary embodiment, the first value m1 can be greater than the second value m2. Therefore, the time S1 for the voltage input to the fifth word line WL5 and the eighth word line WL8 to reach the read-through voltage VPASS can be longer than the time S2 for the voltage input to the fourth word line WL4 and the ninth word line WL9 to reach the read-through voltage VPASS.

[0110] During the first period P1, a voltage lower than a predetermined threshold can be input to the barrier line B_WL to divide the channel CH logic of the unselected cell strings SSL2 to SSL4 into a first channel CH1 above the barrier line B_WL and a second channel CH2 below the barrier line B_WL.

[0111] In a memory device, a first boosting may be performed during a first period P1 to boost a first channel CH1 and a second channel CH2. Refer to Figure 12A and Figure 12B , during the first period P1, a pre-pulse voltage may be input only to an unselected ground selection line Unsel_GSL among an unselected string selection line Unsel_SSL and an unselected string selection line Unsel_GSL to boost the potential of the first channel CH1 to a predetermined boosting level VBOOST and maintain the potential of the second channel CH2 at a ground level.

[0112] In a memory device, a second boosting may be performed during a second period P2. Refer to Figure 12A and Figure 12B , a voltage (e.g., a read-through voltage VPASS) equal to or higher than a predetermined threshold may be input to a barrier word line B_WL during the second period P2. During the second period, when the read-through voltage VPASS is input to the barrier word line B_WL, the first channel CH1 may be electrically connected to the second channel CH2, and the potential of the channel CH may be boosted to a value VBOOST' between the boosting level VBOOST of the first channel CH1 and the boosting level (ground level) of the second channel CH2.

[0113] In an exemplary embodiment, the boosting level VBOOST' determined to be the potential of the channel CH during the second period may be determined depending on the boosting level VBOOST of the first channel CH1 and the boosting level of the second channel CH2, and a ratio of the number of word lines corresponding to the first channel CH1 to the number of word lines corresponding to the second channel CH2. For example, in Figure 12A , the number of word lines WL8 to WL12 corresponding to the first channel CH1 is five, and the number of word lines WL1 to WL5 corresponding to the second channel CH2 is five. Accordingly, during the second period P2, the boosting level VBOOST' corresponding to the potential of the channel CH may be determined as an intermediate value between the boosting level VBOOST of the first channel CH1 and the boosting level (ground level) of the second channel CH2.

[0114] As referred to above Figures 11 to 12BAs described, in the memory device according to the exemplary embodiment, during the first period P, the channels of the unselected cell strings can be separated using the barrier lines, and a pre-pulse voltage can be selectively input to the unselected string select line or the unselected ground select line. During the second period P2, a voltage greater than or equal to a predetermined value can be input to the barrier lines to electrically connect the channels that are electrically separated from each other. Accordingly, compared to the potential when boosting is performed without selecting and controlling the barrier lines, the potential of the channels of the unselected cell strings can be reduced, and deterioration of the threshold voltage distribution of the memory cells (e.g., due to soft erasure occurring) can be prevented. Further, in the memory device according to the exemplary embodiment, the pre-pulse voltage can be selectively input to the unselected string select line or the unselected ground select line during the first period P1 to minimize an increase in power consumption and thus reduce the power supply size.

[0115] Different from that described with reference Figure 12A and Figure 12B In the memory device, a pre-pulse voltage can be input to the unselected string select line. In this case, when the pre-pulse voltage is input to the unselected string select line, a voltage lower than the pre-pulse voltage (e.g., the ground voltage) can be input to the unselected ground select line. Hereinafter, this will be described with reference Figure 13A and Figure 13B thereof.

[0116] Referring to Figure 13A and Figure 13B , during the first period P1, the potential of the first channel CH1 above the barrier line B_WL can be maintained at the ground level, and the potential of the second channel CH2 below the barrier line B_WL can be boosted to a predetermined boost level VBOOST. During the second period P2, when a voltage higher than a predetermined threshold (e.g., the read-through voltage VPASS) is input to the barrier line B_WL, the first channel CH1 and the second channel CH2 can be electrically reconnected to each other, and the potential of the channel CH of the unselected cell string can be boosted to a boost level VBOOST' that is higher than the boost level of the first channel CH1 and lower than the boost level VBOOST of the second channel CH2. In the exemplary embodiment, the boost level VBOOST' of the potential of the channel CH of the unselected cell string can be determined depending on the boost level of the first channel CH1 and the boost level VBOOST of the second channel CH2, and the ratio of the number of word lines corresponding to the first channel CH1 to the number of word lines corresponding to the second channel CH2.

[0117] Figures 14 to 15B FIG. shows the operation of the memory device according to the exemplary embodiment.

[0118] Referring to Figure 14, the memory cell array 700 may include first to fourth cell strings S1 to S4. Each of the first to fourth cell strings S1 to S4 may include a plurality of memory cells MC1 to MC12 connected between string select lines SSL1 to SSL4 and ground select lines GSL1 to GSL4. In Figure 14 , each of the cell strings S1 to S4 is shown as including twelve memory cells MC1 to MC12, but the configuration of each of the cell strings S1 to S4 may be changed.

[0119] In the memory device, among a plurality of unselected word lines WL1 to WL11 connected to the second cell string S2 (selected cell string), one or more unselected word lines may be selected as a barrier line B_WL. During at least a part of the read operation period, each channel of the unselected cell strings S1, S3, and S4 may be logically divided into a plurality of channels by the barrier line B_WL.

[0120] In the memory device, the boost level of the channels included in each of the unselected cell strings S1, S3, and S4 may be determined based on the read voltage input to the twelfth word line WL12 as the selected word line. For example, a voltage level having a predetermined voltage difference from the read voltage may be determined as the boost level of the channels included in each of the unselected cell strings S1, S3, and S4. At least one of the plurality of unselected word lines WL1 to WL11 may be selected as the barrier line B_WL based on the determined boost level of each channel of the unselected cell strings S1, S3, and S4. For example, in Figure 14 the illustrated exemplary embodiment, the fourth word line WL4 and the fifth word line WL5 may be selected as the barrier line B_WL.

[0121] In this memory device, a conduction voltage may be input to the selected string select line SSL2 and the selected ground select line GSL2. During a first period P1, a cut-off voltage (e.g., ground voltage) may be input to the barrier line B_WL. A conduction voltage (e.g., a voltage equal to the read pass voltage) may be input to the barrier line B_WL during a second period P2. During the first period P1, a pre-pulse voltage may be input to the unselected string select lines SSL2 to SSL4 or the unselected ground select lines GSL2 to GSL4.

[0122] During a first period P1, the channels of the unselected string select lines SSL2 to SSL4 can be electrically separated into a plurality of channels by a barrier line B_WL. The potential of a part of the plurality of channels electrically separated by a selectively input pre-pulse voltage can be increased to a predetermined boost level. When a read-through voltage is input to the barrier line B_WL during a second period P2, the plurality of electrically separated channels can be electrically reconnected to each other. The boost level of the electrically connected channels can be determined depending on, for example, the boost level of each of the channels separated by the barrier line B_WL, the ratio of the number of word lines corresponding to the respective separated channels, and the like. For example, in Figure 14 , since the number of word lines arranged above the barrier line B_WL is 7 and the number of word lines arranged below the barrier line B_WL is 3, the boost level of the channels during the second period P2 can have a value obtained by summing the following at a ratio of 7:3: the boost level of the channels separated based on the barrier line B_WL during the first period P1. As described above, in the memory device according to the exemplary embodiment, the position of the barrier line B_WL can be adjusted to control the boost level of the channels of the unselected string select lines to a desired value.

[0123] Reference Figure 15A and Figure 15B both, a predetermined conduction voltage can be input to the second string select line SSL2 (selected string select line Sel_SSL) and the second ground select line GSL2 (selected ground select line Sel_GSL).

[0124] A cut-off voltage (e.g., a ground voltage) can be input to the first string select line SSL1, the third string select line SSL3, and the fourth string select line SSL4, which are unselected string select lines Unsel_SSL. A pre-pulse voltage can be input to the first ground select line GSL1, the third ground select line GSL3, and the fourth ground select line GSL4, which are unselected ground select lines Unsel_GSL. In the exemplary embodiment, the maximum value VPRE of the pre-pulse voltage can be about 3V or more and 4V or less.

[0125] A read-through voltage VPASS can be input to the first word line WL1 to the third word line WL3 and the sixth word line WL6 to the eleventh word line WL11, which are unselected word lines Unsel_WL. A cut-off voltage (e.g., a ground voltage) can be input to the fourth word line WL4 and the fifth word line WL5 selected as the barrier line B_WL during the first period P1, and a read-through voltage VPASS can be input to the fourth word line WL4 and the fifth word line WL5 during the second period P2.

[0126] During at least a part of the first period P1 and the second period P2, the voltages input to the third word line WL3 and the sixth word line WL6 of the word line BN1_WL closest to the barrier line B_WL can be lower than the read-through voltage VPASS. As an example, at the first time point t2 between the first period P1 and the second period P2, the voltages input to the third word line WL3 and the sixth word line WL6 can be lower than the read-through voltage VPASS by a first value m1.

[0127] During at least a part of the first period P1 and the second period P2, the voltages input to the second word line WL2 and the seventh word line WL7 of the unselected word line BN2_WL next closest to the barrier line B_WL can be lower than the read-through voltage VPASS. As an example, at the first time point t2 between the first period P1 and the second period P2, the voltages input to the second word line WL2 and the seventh word line WL7 can be lower than the read-through voltage VPASS by a second value m2. In the exemplary embodiment, the first value m1 can be greater than the second value m2. Therefore, the time S1 for the voltages input to the third word line WL3 and the sixth word line WL6 to reach the read-through voltage VPASS can be longer than the time S2 for the voltages input to the second word line WL2 and the seventh word line WL7 to reach the read-through voltage VPASS.

[0128] During the first period P1, the channels CH of the unselected cell strings SSL1, SSL3, and SSL4 can be logically divided into a first channel CH1 and a second channel CH2 by the barrier line B_WL. The first channel CH1 can be preliminarily boosted to a first boost level VBOOST, and the second channel CH2 can be maintained at a second boost level lower than the first boost level VBOOST, for example, the ground level (ground state).

[0129] Since the same voltage (e.g., the read-through voltage VPASS) as that of other unselected word lines Unsel_WL is input to the barrier line B_WL during the second period, and the first channel CH1 and the second channel CH2 can be combined into a single channel CH. Therefore, the combined channel CH can be secondarily boosted to an intermediate value VBOOST' between the first boost level VBOOST of the first channel CH1 and the boost level (0V) of the second channel CH2.

[0130] In the exemplary embodiment, the boost level of the combined channel CH can be calculated by summing the boost voltage VBOOST of the first level and the boost level (0V) of the second channel CH2 depending on the ratio of the number of word lines corresponding to the first channel CH1 to the number of word lines corresponding to the second channel CH2. For example, in Figure 15AAmong them, the number of unselected word lines WL6 to WL12 corresponding to the first channel CH1 is seven, and the number of unselected word lines WL1 to WL3 corresponding to the second channel CH2 is three. Therefore, during the second period P2, the boosting level VBOOST' of the combined channel CH can have a value obtained by summing the following items at a ratio of 7:3: the first boosting level VBOOST of the first channel CH1 and the boosting level (0V) of the second channel CH2.

[0131] As opposed to Figures 11 to 15B shown, the barrier lines B_WL can be selected as a plurality of unselected word lines spaced apart from each other. Reference Figures 16 to 17B will describe this in detail.

[0132] Figures 14 to 15B illustrates the operation of a memory device according to an exemplary embodiment.

[0133] Reference Figures 16 to 17B , a memory device according to an exemplary embodiment may include a plurality of word lines WL1 to WL12. Among the plurality of word lines WL1 to WL12, a plurality of word lines spaced apart from each other may be selected as the barrier lines B_WL. For example, in Figure 16 , the eighth word line WL8 may be selected as the first barrier line B_WL1, and the fourth word line WL4 may be selected as the second barrier line B_WL2.

[0134] During the first period P1, the channels of the plurality of unselected cell strings S2 to S4 may be logically divided into first to third channels CH1 to CH3 by the first barrier line B_WL1 and the second barrier line B_WL2.

[0135] During the first period P1, a ground voltage may be input to the unselected string selection lines SSL2 to SSL4, a pre-pulse voltage may be input to the unselected ground selection lines GSL2 to GSL4, and the first channel CH1 may be preliminarily boosted to a first boosting level VBOOST1. The second channel CH2 may be preliminarily boosted to a second boosting level VBOOST2, and the third channel CH3 may be preliminarily boosted to a third boosting level VBOOST3. In the exemplary embodiment, each of the first to third boosting levels VBOOST1 to VBOOST3 may be proportional to the number of word lines corresponding to each of the first to third channels CH1 to CH3.

[0136] During a second period P2, the functions of the first barrier line B_WL1 and the second barrier line B_WL2 can be deactivated to merge the first channel CH1 to the third channel CH3 into a single channel CH. In this case, the boosted level VBOOST' of the merged channel CH can have a value obtained by summing the boosted levels VBOOST1 to VBOOST3 of the first channel CH1 to the third channel CH3 in proportion to the number of its word lines.

[0137] Figure 18 is a flowchart showing an operation method of a memory device according to an exemplary embodiment.

[0138] Refer to Figure 18 , the memory device according to the exemplary embodiment can operate in one of a first mode to a third mode during a read operation and / or a program verification operation.

[0139] The memory device can obtain status information (which can be stored in an external memory, an internal buffer, etc.) in real time or every predetermined period to determine the operation mode (S410). The status information can include information related to the degree of degradation of the memory device, the operation state, etc. For example, the status information of the memory device can include information such as the programming / erasing (P / E) cycle, the number of read retries, the retention time, and the number of error bits in the memory cells. The status information can include environmental information such as the operating temperature or the power level of the external power supply.

[0140] In one embodiment, the status of the memory device can be classified into a first state to a third state depending on a predetermined criterion. As an example, the first state can be the following state: in this state, an operation voltage may not be generated normally due to poor power supply of the memory device. The second state can refer to a state in which the degree of degradation of the memory device is relatively high, and thus read failures or the like may occur. The third state can refer to the following state: in this state, a programming operation, a read operation, etc. can be normally executed.

[0141] It can be determined whether the current state of the memory device is the first state among the first state to the third state (S420). In some examples, it can be determined whether the memory device is in the first state based on the result of comparing the power level of the external power obtained in S410 with a predetermined threshold.

[0142] When the result determined in S420 is that the memory device is in the first state, the first mode can be executed (S430). In the first mode, the barrier line can not be selected and a pre-pulse voltage can not be input to the unselected string selection line and the unselected ground selection line. The operation method of the memory device in the first mode is the same as that described above with reference to Figure 6 as described.

[0143] Since the pre-pulse voltage is not input to both the unselected string select line and the unselected ground select line in the first mode, the power consumption can be significantly reduced. Therefore, the first mode may be effective when the power supply state of the memory device is relatively poor.

[0144] When the result determined in S420 is that the memory device is not in the first state, it can be determined whether the current state of the memory device is the second state (S440). In some examples, it can be determined whether the memory device is in the second state based on whether the P / E cycle obtained in S410 is greater than a predetermined threshold.

[0145] When the result determined in S440 is that the memory device is in the second state, the second mode can be executed (S450). In the second mode, the barrier line can be not selected, and the pre-pulse voltage can be input to the unselected string select line and the unselected ground select line. The operation method of the memory device in the second mode is the same as that described above with reference to Figure 8 as described.

[0146] Since the pre-pulse voltage is input to both the unselected string select line and the unselected ground select line in the second mode, the power consumption may increase. However, the channel potential of the unselected cell string can be further reduced to completely prevent soft erase. Therefore, in terms of reliability, the second mode may be the most effective. The second mode can mainly operate in a state where the degree of deterioration of the memory device is relatively high.

[0147] When the result determined in S440 is that the memory device is not in the second state (for example, in the third state), the third mode can be executed (S460). In the third mode, the barrier line can be selected, and the pre-pulse voltage can be selectively input to the unselected string select line or the unselected ground select line, as described above with reference to Figures 9 to 17B as described. The third mode can mainly operate in a state where the degree of deterioration of the memory device is low to medium.

[0148] In the third mode, the channel potential of the unselected cell string can be limited to a predetermined level to prevent soft erase and ensure the reliability of the memory device. In addition, the pre-pulse voltage can be selectively input to the unselected string select line or the unselected ground select line to significantly reduce the power consumption and the increase in the power supply size. Therefore, the second mode may be effective in a system (such as a mobile system) that requires both low power and high reliability.

[0149] Figure 19 A mobile system including a memory device according to an example embodiment is shown.

[0150] Reference Figure 19, the mobile system 1000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memory devices 2600a and 2600b, input / output (I / O) devices 2700a and 2700b, and an application processor (AP) 2800.

[0151] The mobile system 2000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer (desktop PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. Moreover, the mobile system 2000 may be implemented as a server or a PC.

[0152] The camera 2100 may capture a still image or video under the user's control. In an exemplary embodiment, the camera 2100 may send data such as a still image / video to the AP 2800 according to the D-PHY or C-PHY interface defined in the MIPI standard. The mobile system 2000 may use the still image / video captured by the camera 2100 to obtain specific information, or may convert and store the still image / video into other types of data such as text. In another implementation, the mobile system 2000 may identify a string included in the still image / video captured by the camera 2100, and may provide a text or audio translation corresponding to the string. As described above, the camera 1100 in the mobile system 1000 tends to be used in various application fields.

[0153] The display 2200 may be implemented in various forms, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix organic light emitting diode (AMOLED) display, a plasma display panel (PDP), a field emission display (FED), an electronic paper, etc. In an exemplary embodiment, the display 1200 may provide a touch screen function so that it also serves as an input device of the mobile system 2000. Additionally, the display 2200 may be integrated with a fingerprint sensor or the like to provide a security function for the mobile system 2000.

[0154] The audio processor 2300 may process audio data stored in the flash memory devices 2600a and 2600b, or may process audio data included in content received from the outside through the modem 2400 or the I / O devices 2700a and 2700b. For example, the audio processor 2300 may perform various processes on the audio data, such as encoding / decoding, amplification, and noise filtering, etc.

[0155] The modem 2400 can modulate signals and transmit the modulated signals to send and receive wired / wireless data, and can demodulate externally received signals to restore the original signals. The I / O devices 2700a and 2700b can provide digital input and output, and can include: input devices such as ports capable of connecting to an external recording medium, a touch screen, or mechanical button keys; and output devices capable of outputting vibrations in a tactile manner. In some examples, the I / O devices 1700a and 1700b can be connected to an external recording medium through ports such as USB, Lightning cable, SD card, micro SD card, DVD, network adapter, etc.

[0156] The AP 2800 can control the overall operation of the mobile system 2000. Specifically, the AP 2800 can control the display 2200 to display a part of the content stored in the flash memory devices 2600a and 2600b on the screen. In an exemplary embodiment, the AP 2800 can send the image data to be displayed on the display 2200 to the display 2200 according to the D-PHY or C-PHY interface defined in the MIPI standard. Additionally, when a user input is received through the I / O devices 2700a and 2700b, the AP 2800 can perform a control operation corresponding to the user input.

[0157] The AP 2800 can be set as a system-on-chip (SoC) that drives application programs, an operating system (OS), etc. Additionally, the AP 2800 can be included in a single semiconductor package together with other devices included in the mobile system 1000 (e.g., DRAM 2500a, flash memory 2620, and / or memory controller 2610). For example, the AP 2800 and at least one device can be set in a package form such as package-on-package (PoP), ball grid array (BGA), chip scale package (CSP), system-in-package (SIP), multi-chip package (MCP), wafer-level packaged (WFP), wafer-level processed stacked package (WSP), etc.

[0158] The kernel of the operating system driven on the AP 2800 can include an input / output scheduler and a device driver for controlling the flash memory devices 2600a and 2600b. The device driver can control the access performance of the flash memory devices 2600a and 2600b with reference to the number of synchronization queues managed by the input / output scheduler, or can control the CPU mode, dynamic voltage and frequency scaling (DVFS) levels, etc. inside the SoC.

[0159] In an example embodiment, the AP 2800 may include a processor block that executes operations or drives applications and / or an operating system, and various other peripheral components connected to the processor block via a system block and a system bus. The peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, and the like. The processor block may include one or more cores. When multiple cores are included in the processor block, each of these cores includes a cache memory, and a common cache shared by the cores may be included in the processor block.

[0160] In an example embodiment, the AP 2800 may include an accelerator block 2820, a dedicated circuit for AI data operations. In another implementation, according to an example embodiment, a separate accelerator chip may be provided separately from the AP 2800, and the DRAM 2500b may be additionally connected to the accelerator block 2820 or the accelerator chip. The accelerator block 2820 may be a functional block dedicated to performing specific functions of the AP 2800, and may include a graphics processing unit (GPU) serving as a functional block dedicated to processing graphic data, a neural processing unit (NPU) serving as a functional block dedicated to performing AI calculations and interference, a data processing unit (DPU) serving as a functional block dedicated to sending data, and the like.

[0161] According to an example embodiment, the mobile system 1000 may include multiple DRAMs 2500a and 2500b. In an example embodiment, the AP 2800 may include a controller 2810 for controlling the DRAMs 1500a and 1500b, and the DRAM 2500a may be directly connected to the AP 2800.

[0162] The AP 2800 may set command and mode register set (MRS) commands according to JEDEC standards to control the DRAM, or may set specifications and functions used by the mobile system 2000 (such as low voltage, high speed, and reliability) and a DRAM interface protocol for CRC / ECC to perform communication. For example, the AP 2800 may communicate with the DRAM 2500a via an interface compliant with JEDEC standards (such as LPDDR4, LPDDR5, etc.). In another embodiment, the AP 2800 may set a new DRAM interface protocol to control the DRAM 1500b for the accelerator, where the accelerator block 1820 or the accelerator chip set separately from the AP 1800 has a higher bandwidth than the DRAM 1500a to perform communication.

[0163] In Figure 19Only DRAMs 2500a and 2500b are shown, but the configuration of the mobile system 1000 can be changed. Depending on the bandwidth and response speed, voltage conditions, etc. of the AP 2800 or the accelerator block 2820, the mobile system 2000 may further include memories other than DRAMs 2500a and 2500b. As an example, the controller 2810 and / or the accelerator block 2820 can control various memories, such as PRAM, SRAM, MRAM, RRAM, FRAM, hybrid RAM, etc. Compared with the I / O devices 2700a and 2700b or the flash memory devices 2600a and 2600b, the DRAMs 2500a and 2500b have relatively low latency and high bandwidth. The DRAMs 2500a and 2500b can be initialized at the time when the mobile system 2000 is powered on. When loading the operating system and application data, the DRAMs 2500a and 2500b can be used as a temporary storage for the operating system and application data, or can be used as a space for executing various software codes.

[0164] Data for four basic arithmetic operations (such as addition, subtraction, multiplication, and division), vector operations, address operations, or fast Fourier transform (FFT) operations can be stored in the DRAMs 2500a and 2500b. In another exemplary embodiment, the DRAMs 2500a and 2500b can be set as a processing-in-memory (PIM) with an operation function. As an example, functions used in inference can be executed in the DRAMs 2500a and 2500b. In this case, inference can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm can include a training step in which a model is learned through various data, and an inference step in which data is recognized through the trained model. For example, functions used in inference can include a hyperbolic tangent function, a sigmoid function, a rectified linear unit (ReLU) function, etc.

[0165] As an exemplary embodiment, an image captured by the user through the camera 2100 can be signal-processed and stored in the DRAM 2500b, and the accelerator block 2820 or the accelerator chip can use the data stored in the DRAM 2500b and the functions used in inference to perform AI data operations to recognize the data.

[0166] According to an exemplary embodiment, the mobile system 2000 may include a plurality of storage devices or a plurality of flash memory devices 2600a and 2600b having a capacity greater than the capacity of the DRAMs 2500a and 2500b.

[0167] Flash memory devices 2600a and 2600b may include a memory controller 2610 and flash memory 2620. The memory controller 2610 may receive control commands and data from the AP 2800, and may write the data to the flash memory 2620 in response to the control command, or may read the data stored in the flash memory 2620 and send the read data to the AP 2800. The pre-pulse scheme described with reference to the exemplary embodiment may be applied to the process of verifying a write operation of writing data to the flash memory 2620 or reading data from the flash memory 2620. As an example, the channel boost level of the flash memory 2620 may be reduced to improve the reliability of the flash memory 2620. Additionally, a pre-pulse voltage may be selectively applied to an unselected string select line or an unselected ground select line of the flash memory 2620 to reduce power consumption.

[0168] According to an exemplary embodiment, the accelerator block 2820 or the accelerator chip may use the flash memory devices 2600a and 2600b to perform training steps and AI data operations. In the exemplary embodiment, blocks capable of performing predetermined operations may be implemented in the flash memory devices 2600a and 2600b. Instead of the AP 2800 and / or the accelerator block 2820, the operation logic may use the data stored in the flash memory 2620 to perform at least a part of the training steps and AI data operations performed by the AP 2800 and / or the accelerator module 2820.

[0169] In the exemplary embodiment, the AP 2800 may include an interface 2830. Thus, the flash memory devices 2600a and 2600b may be directly connected to the AP 2800. For example, the AP 2800 may be implemented as a SoC, the flash memory device 2600a may be implemented as a chip independent of the AP 2800, and the AP 2800 and the flash memory device 2600a may be installed in a single package. However, the exemplary embodiment is not limited thereto, and multiple flash memory devices 2600a and 2600b may be electrically connected to the mobile system 2000 through a connection.

[0170] The flash memory devices 2600a and 2600b may store data such as still images / videos captured by the camera 2100, or data received through a communication network and / or ports included in the I / O devices 2700a and 2700b. For example, the flash memory devices 2600a and 2600b may store augmented reality / virtual reality, high definition (HD) or ultra-high definition (UHD) content.

[0171] Figure 20 A data center including a storage device according to an exemplary embodiment is shown.

[0172] Reference Figure 20, The data center 3000 is a facility for collecting various types of data and providing services, and can be referred to as a data storage center. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to an exemplary embodiment, various selections can be made for the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0173] The application server 3100 or the storage server 3200 may include at least one of processors 3110 and 3210 and memories 3120 and 3220. A description will be given by taking the storage server 3200 as an example. The processor 3210 may control the overall operation of the storage server 3200 and may access the memory 3220 to execute instructions and / or data loaded in the memory 3220. According to an exemplary embodiment, various selections can be made for the number of processors 3210 included in the storage server 3200 and the number of memories 322 included in the storage server 3200. In an exemplary embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an exemplary embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. According to an exemplary embodiment, the application server 3100 may not include a storage device 3150. The storage server 3200 may include at least one storage device 3250. According to an exemplary embodiment, various selections can be made for the number of storage devices 3250 included in the storage server 3200.

[0174] The application servers 3100 to 3100n and the storage servers 3200 to 3200m may communicate with each other through the network 3300. The network 3300 may be implemented using a Fibre Channel (FC) or an Ethernet network. In this case, the FC may be a medium used in relatively high-speed data transmission, and an optical switch providing high performance / high availability may be used. Depending on the access method of the network 3300, the storage servers 3200 to 3200m may be set as file storage devices, block storage devices, or object storage devices.

[0175] In an example embodiment, network 1300 may be a storage-only network, such as a storage area network (SAN). As an example, the SAN may be an FC-SAN that uses an FC network and is implemented depending on the FC protocol (FCP). As another example, the SAN may be an IP-SAN that uses a TCP / IP network and is implemented depending on the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In other embodiments, network 1300 may be a general network such as a TCP / IP network. For example, network 1300 may be implemented depending on protocols such as Ethernet over FC (FCoE), network-attached storage (NAS), NVMe over Fabrics (NVMe-oF).

[0176] Hereinafter, the description will be mainly directed to application server 3100 and storage server 3200. The description of application server 3100 may be applied to another application server 3100n, and the description of storage server 3200 may be applied to another storage server 3200m.

[0177] Application server 3100 may store, via network 3300, data requested by a user or client in one of storage servers 3200 to 3200m. Application server 3100 may obtain, via network 3300, data requested by a user or client to be read from one of storage servers 3200 to 3200m. For example, application server 3100 may be implemented as a web server, a database management system (DBMS), etc.

[0178] Application server 3100 may access memory 3120n or storage device 3150n included in another application server 3100n via network 3300, or may access memory 3220 to 3220m or storage device 3250 to 3250m included in storage servers 3200 to 3200m via network 3300.

[0179] Therefore, the application server 3100 can perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 can execute instructions for moving data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m or instructions for copying data. In this case, the data can be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the memories 3120 to 3120n of the application servers 3100 to 3100n through the memories 3220 to 3220m of the storage servers 3200 to 3200m, or can be directly moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the memories 3120 to 3120n of the application servers 3100 to 3100n.

[0180] The storage server 3200 will be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface controller 3240 and the controller 3251. For example, the interface 3254 can be implemented in a direct attached storage (DAS) manner, in which the storage server 3200 is directly connected to the storage device 3250 using a dedicated cable. For example, the interface 3254 can be implemented with various interface protocols, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect Express (PCI Express), PCIe (NVMe), NVMe (NVM Express), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Storage (UFS), CompactFlash (CF) card interface, etc.

[0181] The storage server 3200 may further include a switch 3230 and a network interface controller 3240. The switch 3230 can selectively connect the processor 3210 to the storage device 3250 under the control of the processor 3210, or can selectively connect the network interface controller 3240 to the storage device 3250.

[0182] The network interface controller 3240 can connect the storage server 3200 to a network to perform communication and can be referred to as a network interface card, network adapter, etc. The network interface controller 3240 can be connected to the network 3300 through a wired interface, wireless interface, Bluetooth interface, optical interface, etc. The network interface controller 3240 can include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and can be connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface can be implemented as one of the above examples of the interface 3254. In an example embodiment, the network interface controller 3240 can be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0183] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor can send commands to the storage devices 3250 to 3250m and 3150 to 3150n or the memories 3220 to 3220m and 3120 to 3120n to program or read data. In this case, the data can be error correction data of an error correction code (ECC) engine. The data can be data processed by data bus inversion (DBI) or data masking (DM), and can include cyclic redundancy code (CRC) information.

[0184] The storage devices 3250 to 3250m can send control signals and command / address signals to the NAND flash devices 3252 to 3252m in response to read commands received from the processor. Therefore, when reading data from the NAND flash devices 3252 to 3252m, a read enable (RE) signal can be input as a data output control signal for outputting data to the DQ bus. The RE signal can be used to generate a data strobe DQS. The command and address signals can be latched into the page buffer according to the rising or falling edge of the write enable (WE) signal.

[0185] The controller 3251 can control the overall operation of the storage device 3250. In an example embodiment, the controller 3251 can include a static random access memory (SRAM). The controller 3251 can write data to the NAND flash device 3252 in response to a write command, or can read data from the NAND flash device 3252 in response to a read command. For example, the write command and / or the read command can be provided from the processor 3210 in the storage server 3200, the processor 3210m in another storage server 3200m, or the processors 3110 and 3110n in the application servers 3100 and 3100n.

[0186] The NAND flash device 3252 can be according to the reference Figures 1 to 18A storage device according to various example embodiments described. The NAND flash memory device 3252 may reduce the channel boost level during a write verification operation and / or a read operation to prevent soft erasure from occurring and ensure reliability. Additionally, the NAND flash memory device 3252 may selectively apply a pre-pulse voltage to an unselected string select line or an unselected ground select line to reduce power consumption.

[0187] By summarizing and reviewing, using a pre-pulse scheme can enable a pre-pulse voltage to be input to an unselected string select line and an unselected ground select line before a read voltage is input to a selected word line. In a general pre-pulse scheme, the pre-pulse voltage may be input to both the unselected string select line and the unselected ground select line during a setup period, so that not only power consumption but also the power supply size may increase.

[0188] As described above, in a storage device according to an example embodiment, at least one word line among a plurality of word lines may be used as a barrier line to control the potential level of a channel region. Therefore, soft erasure during a read operation can be prevented.

[0189] Additionally, in a storage device according to an example embodiment, a control signal input to at least one word line adjacent to a barrier line during a channel boost period may be limited to a predetermined level to prevent hot carrier injection that may occur in the barrier line.

[0190] Additionally, in a storage device according to an example embodiment, a pre-pulse voltage may be selectively input to an unselected string select line and an unselected ground select line to significantly reduce an increase in power consumption and the power supply size.

[0191] An embodiment may provide a storage device and an operation method thereof that can prevent deterioration of a threshold voltage distribution of memory cells while significantly reducing an increase in power consumption and the power supply size.

[0192] Figure 21 is a diagram showing a storage device 4000 according to another example embodiment.

[0193] Refer to Figure 21 , the storage device 4000 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by the following operations: manufacturing an upper chip including a cell region CELL on a first wafer; manufacturing a lower chip including a peripheral circuit region PERI on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. For example, the bonding metal may include copper (Cu) using Cu-to-Cu bonding. However, the example embodiment may not be limited thereto. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0194] The peripheral circuit region PERI and the cell region CELL of the memory device 4000 may each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0195] The peripheral circuit region PERI may include a first substrate 4210, an interlayer insulating layer 4215, a plurality of circuit elements 4220a, 4220b, and 4220c formed on the first substrate 4210, first metal layers 4230a, 4230b, and 4230c respectively connected to the plurality of circuit elements 4220a, 4220b, and 4220c, and second metal layers 4240a, 4240b, and 4240c formed on the first metal layers 4230a, 4230b, and 4230c. In an exemplary embodiment, the first metal layers 4230a, 4230b, and 4230c may be formed of tungsten having a relatively high resistivity, and the second metal layers 4240a, 4240b, and 4240c may be formed of copper having a relatively low resistivity.

[0196] In Figure 21 the exemplary embodiment shown, although only the first metal layers 4230a, 4230b, and 4230c and the second metal layers 4240a, 4240b, and 4240c are shown and described, the exemplary embodiment is not limited thereto, and one or more additional metal layers may also be formed on the second metal layers 4240a, 4240b, and 4240c. At least a part of the one or more additional metal layers formed on the second metal layers 4240a, 4240b, and 4240c may be formed of aluminum or the like having a resistivity lower than that of the copper forming the second metal layers 4240a, 4240b, and 4240c.

[0197] The interlayer insulating layer 4215 may be disposed on the first substrate 4210 and cover the plurality of circuit elements 4220a, 4220b, and 4220c, the first metal layers 4230a, 4230b, and 4230c, and the second metal layers 4240a, 4240b, and 4240c. The interlayer insulating layer 4215 may include an insulating material such as silicon oxide, silicon nitride, etc.

[0198] Lower bonding metals 4271b and 4272b may be formed on a second metal layer 4240b in a word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4271b and 4272b in a peripheral circuit area PERI may be electrically bonded to upper bonding metals 4371b and 4372b of a cell area CELL. The lower bonding metals 4271b and 4272b and the upper bonding metals 4371b and 4372b may be formed of aluminum, copper, tungsten, etc. In addition, the upper bonding metals 4371b and 4372b in the cell area CELL may be referred to as first metal pads, and the lower bonding metals 4271b and 4272b in the peripheral circuit area PERI may be referred to as second metal pads.

[0199] The cell area CELL may include at least one memory block. The cell area CELL may include a second substrate 4310 and a common source line 4320. On the second substrate 4310, a plurality of word lines 4331 to 4338 (i.e., 4330) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 4310. At least one string selection line and at least one ground selection line may be disposed above and below the plurality of word lines 4330, respectively, and the plurality of word lines 4330 may be disposed between the at least one string selection line and the at least one ground selection.

[0200] In a bit line bonding area BLBA, a channel structure CH may extend in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 4310 and pass through the plurality of word lines 4330, the at least one string selection line, and the at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to a first metal layer 4350c and a second metal layer 4360c. For example, the first metal layer 4350c may be a bit line contact, and the second metal layer 4360c may be a bit line. In an exemplary embodiment, the bit line 4360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 4310.

[0201] In Figure 21 the exemplary embodiment shown, an area where the channel structure CH, the bit line 4360c, etc. are provided may be defined as a bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line 4360c may be electrically connected to a circuit element 4220c that provides a page buffer 4393 in a peripheral circuit area PERI. The bit line 4360c may be connected to the upper bonding metals 4371c and 4372c in the cell area CELL, and the upper bonding metals 4371c and 4372c may be connected to the lower bonding metals 4271c and 4272c connected to the circuit element 4220c of the page buffer 4393.

[0202] In the word line bonding area WLBA, a plurality of word lines 4330 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 4310 and perpendicular to the first direction, and may be connected to a plurality of cell contact plugs 4341 to 4347 (i.e., 4340). The plurality of word lines 4330 and the plurality of cell contact plugs 4340 may be connected to each other in a pad provided by at least a part of the plurality of word lines 4330 extending with different lengths in the second direction. The first metal layer 4350b and the second metal layer 4360b may be sequentially connected to the upper portions of the plurality of cell contact plugs 4340 connected to the plurality of word lines 4330. The plurality of cell contact plugs 4340 may be connected to the peripheral circuit area PERI through the upper bonding metals 4371b and 4372b of the cell area CELL and the lower bonding metals 4271b and 4272b of the peripheral circuit area PERI in the word line bonding area WLBA.

[0203] The plurality of cell contact plugs 4340 may be electrically connected to the circuit elements 4220b forming the row decoder 4394 in the peripheral circuit area PERI. In an exemplary embodiment, the operating voltage of the circuit elements 4220b of the row decoder 4394 may be different from the operating voltage of the circuit elements 4220c forming the page buffer 4393. For example, the operating voltage of the circuit elements 4220c forming the page buffer 4393 may be greater than the operating voltage of the circuit elements 4220b forming the row decoder 4394.

[0204] The common source line contact plug 4380 may be provided in the external pad bonding area PA. The common source line contact plug 4380 may be formed of a conductive material such as metal, metal compound, polysilicon, etc., and may be electrically connected to the common source line 4320. The first metal layer 4350a and the second metal layer 4360a may be sequentially stacked on the upper portion of the common source line contact plug 4380. For example, the area where the common source line contact plug 4380, the first metal layer 4350a, and the second metal layer 4360a are arranged may be defined as the external pad bonding area PA.

[0205] The input / output pads 4205 and 4305 may be provided in the external pad bonding area PA. Refer to Figure 21, an under-insulating film 4201 covering the lower surface of the first substrate 4210 may be formed under the first substrate 4210, and a first input / output pad 4205 may be formed on the under-insulating film 4201. The first input / output pad 4205 may be connected to at least one of a plurality of circuit elements 4220a, 4220b, and 4220c disposed in the peripheral circuit region PERI through a first input / output contact plug 4203, and may be separated from the first substrate 4210 through the under-insulating film 4201. In addition, a side-insulating film may be disposed between the first input / output contact plug 4203 and the first substrate 4210 to electrically isolate the first input / output contact plug 4203 and the first substrate 4210.

[0206] Reference Figure 21 , an upper-insulating film 4301 covering the upper surface of the second substrate 4310 may be formed on the second substrate 4310, and a second input / output pad 4305 may be formed on the upper insulating layer 4301. The second input / output pad 4305 may be connected to at least one of a plurality of circuit elements 4220a, 4220b, and 4220c disposed in the peripheral circuit region PERI through a second input / output contact plug 4303. In an exemplary embodiment, the second input / output pad 4305 is electrically connected to the circuit element 4220a.

[0207] According to an embodiment, the second substrate 4310 and the common source line 4320 may not be disposed in the region where the second input / output contact plug 4303 is provided. In addition, the second input / output pad 4305 may not overlap with the word line 4330 in the third direction (Z-axis direction). Reference Figure 21 , the second input / output contact plug 4303 may be separated from the second substrate 4310 in a direction parallel to the upper surface of the second substrate 4310, and may pass through the interlayer insulating layer 4315 of the cell region CELL to be connected to the second input / output pad 4305.

[0208] According to an embodiment, the first input / output pad 4205 and the second input / output pad 4305 may be selectively formed. For example, the memory device 4000 may include only the first input / output pad 4205 provided on the first substrate 4210 or the second input / output pad 4305 provided on the second substrate 4310. Alternatively, the memory device 4000 may include both the first input / output pad 4205 and the second input / output pad 4305.

[0209] In each of an external pad bonding region PA and a bit line bonding region BLBA included in the cell region CELL and the peripheral circuit region PERI, respectively, a metal pattern provided on the uppermost metal layer may be set as a dummy pattern, or the uppermost metal layer may not be provided.

[0210] In the external pad bonding region PA, the memory device 4000 may include a lower metal pattern 4273a corresponding to a metal pattern 4372a formed in the top metal layer of the cell region CELL, and in the top metal layer of the peripheral circuit region PERI, having the same cross-sectional shape as the upper metal pattern 4372a of the cell region CELL to be connected to each other. In the peripheral circuit region PERI, the lower metal pattern 4273a formed in the top metal layer of the peripheral circuit region PERI may not be connected to the contact. Similarly, in the external pad bonding region PA, an upper metal pattern 4372a corresponding to the lower metal pattern 4273a formed in the top metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 4273a of the peripheral circuit region PERI may be formed in the top metal layer of the cell region CELL.

[0211] Lower bonding metals 4271b and 4272b may be formed on the second metal layer 4240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 4271b and 4272b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 4371b and 4372b of the cell region CELL through Cu-to-Cu bonding.

[0212] In addition, in the bit line bonding region BLBA, an upper metal pattern 4392 corresponding to a lower metal pattern 4252 formed in the top metal layer of the peripheral circuit region PERI and having the same cross-sectional shape as the lower metal pattern 4252 of the peripheral circuit region PERI may be formed in the top metal layer of the cell region CELL. Contacts may not be formed on the upper metal pattern 4392, and the upper metal pattern 4392 is formed in the top metal layer of the cell region CELL.

[0213] In an exemplary embodiment, corresponding to a metal pattern formed in the top metal layer of one of the cell region CELL and the peripheral circuit region PERI, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern may be formed in the top metal layer within the other of the cell region CELL and the peripheral circuit region PERI. Contacts may not be formed on the reinforcing metal pattern.

[0214] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general descriptive sense and not for purposes of limitation. In some cases, as will be appreciated by those of ordinary skill in the art submitting this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A storage device, comprising: A memory cell array including a plurality of cell strings, each cell string including a plurality of memory cells respectively connected between a plurality of string selection lines and a plurality of ground selection lines, and a plurality of word lines connected to the plurality of memory cells; Control logic configured to generate a first voltage provided to the plurality of string selection lines and a second voltage provided to the plurality of ground selection lines, and adjust each voltage level of the first voltage and the second voltage to control the channel boost level of the plurality of cell strings; And A row decoder configured to provide a read voltage, a read-through voltage, the first voltage, and the second voltage to the memory cell array under the control of the control logic, wherein: The control logic generates one of the first voltage and the second voltage as a pre-pulse voltage to input the pre-pulse voltage to an unselected string selection line or an unselected ground selection line before inputting the read voltage to a selected word line, and The row decoder provides a third voltage to at least one word line among the plurality of word lines, the third voltage having a first level when the pre-pulse voltage has a level higher than or equal to a predetermined first threshold, and having a second level higher than the first level when the pre-pulse voltage has a level lower than the first threshold, wherein, during a period when the pre-pulse voltage has a level higher than or equal to the first threshold, each channel of the plurality of cell strings is divided into a first channel and a second channel based on the word line provided with the third voltage.

2. The storage device according to claim 1, wherein: The control logic selects at least one of the plurality of cell strings as a selected cell string, and The row decoder provides a predetermined conduction voltage to the string selection line and the ground selection line connected to the selected cell string, and provides the first voltage and the second voltage to the string selection line and the ground selection line not connected to the selected cell string, respectively.

3. The storage device according to claim 2, wherein, The level of the pre-pulse voltage is lower than the level of the conduction voltage.

4. The storage device according to claim 1, wherein, The second level is lower than the level of the read-through voltage.

5. The storage device according to claim 1, wherein, During a period when the pre-pulse voltage has a level lower than the first threshold, the first channel and the second channel are combined into one channel.

6. The storage device according to claim 1, wherein: When the first voltage is generated as the pre-pulse voltage, the first channel has a first potential level and the second channel has a second potential level lower than the first potential level, and During a period when the pre-pulse voltage has a level lower than the first threshold, each channel of the plurality of cell strings has a level obtained by summing the first potential level and the second potential level at a predetermined ratio.

7. The storage device according to claim 1, wherein, The control logic controls the row decoder to adjust the level of the read-through voltage and supplies the read-through voltage with the adjusted level to at least one of the plurality of word lines adjacent to the word line supplied with the third voltage.

8. The memory device according to claim 7, wherein, the control logic controls the row decoder to adjust the level of the read-through voltage to be greater when a word line is adjacent to the word line supplied with the third voltage, and supplies the adjusted read-through voltage to the word line.

9. The memory device according to claim 1, wherein, the word line among the plurality of word lines supplied with the third voltage is selected as at least one dummy word line connected to memory cells that do not store data.

10. The memory device according to claim 1, wherein, the word line supplied with the third voltage is selected as at least one word line provided at a boundary between an upper channel structure and a lower channel structure passing through the plurality of word lines.

11. The memory device according to claim 1, wherein, the read-through voltage is 10 V or less, and the first voltage and the second voltage are 3 V or more and 4 V or less.

12. A memory device, comprising: a plurality of cell strings, each cell string including a plurality of memory cells, the plurality of memory cells being disposed at intersections of a plurality of word lines and a plurality of bit lines and connected in series between a plurality of string selection lines and a plurality of ground selection lines; and control logic configured to select at least one of the plurality of cell strings to perform a read operation or a program verification operation, and control a pre-pulse voltage such that the pre-pulse voltage is selectively input to a string selection line or a ground selection line connected to an unselected cell string before a predetermined read voltage is input to a selected word line, wherein the pre-pulse voltage has a value greater than a predetermined threshold during a period before the predetermined read voltage according to a threshold voltage distribution is input to the selected cell string, and has a value less than or equal to the predetermined threshold during a period when the predetermined read voltage is input, wherein the control logic selects at least one of the plurality of word lines as a barrier line, and based on the at least one word line selected as the barrier line, divides a channel of the unselected cell string into a plurality of channels during a period before the predetermined read voltage is input, and the barrier line partially boosts the potential of the divided plurality of channels by preventing potential sharing between the divided plurality of channels.

13. The memory device according to claim 12, wherein, the control logic determines a channel boost level of an unselected cell string based on the predetermined read voltage, and selects at least one word line as a barrier line based on the determined channel boost level of the unselected cell string.

14. The memory device according to claim 12, wherein, the plurality of string selection lines are respectively connected to gate terminals of a plurality of string selection transistors.

15. A memory device, comprising: a memory cell region including a first metal pad; An outer circuit region, including a second metal pad, and vertically connected to the memory cell region through the first metal pad and the second metal pad; A memory cell array, in the memory cell region, including a plurality of cell strings, the plurality of cell strings including a plurality of memory cells; and a plurality of word lines connected to the plurality of memory cells; Control logic, in the outer circuit region, configured to control a plurality of string select lines or a plurality of ground select lines connected to the plurality of cell strings to be precharged, and adjust at least one of the plurality of word lines to control the potential level of each channel of the plurality of cell strings to perform a read operation and a program verification operation; And A row decoder, in the outer circuit region, configured to input a read voltage or a read pass voltage into the plurality of word lines under the control of the control logic to control the read operation or the program verification operation, wherein the control logic selects at least one word line connected to a dummy memory cell among the plurality of memory cells as a barrier line, and inputs a predetermined control voltage to control the potential level of the channel, the level of the predetermined control voltage being lower than the level of the read pass voltage, wherein, during a period before the read voltage is input, based on the at least one word line selected as the barrier line, the channels of the unselected cell strings among the plurality of cell strings are divided into a plurality of channels.

16. The storage device according to claim 15, wherein, The storage device has the following structure: in this structure, a cell region including the memory cell array and an outer circuit region including the control logic and the row decoder are stacked in a direction perpendicular to the substrate.

17. The storage device according to claim 15, wherein, The control logic selects two or more word lines spaced apart from each other among the plurality of word lines as the barrier line.

18. The storage device according to claim 15, wherein, The control logic selects at least one word line provided at a boundary between an upper channel structure and a lower channel structure passing through the plurality of word lines as the barrier line.

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