Display device

Abstract

The present application provides a display device with improved reliability, equipped with: a substrate including a first region and a second region; a plurality of main pixel groups; a plurality of auxiliary pixel groups; a plurality of first signal lines; and a plurality of second signal lines, wherein, on the second region, the distance between the plurality of first signal lines gradually decreases from the center of the second region to the periphery of the second region, and, on the second region, the distance between the plurality of second signal lines gradually decreases from the center of the second region to the periphery of the second region.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a display device with improved product reliability. Background Art

[0002] In recent years, the uses of display devices have become more diverse. In addition, as display devices become thinner and lighter, their use is becoming increasingly widespread.

[0003] As the use of display devices diversifies, there may be various methods of designing the form of the display devices, and functions that can be grafted or linked to the display devices are increasing. Summary of the Invention

[0004] As a method for increasing functionality that can be grafted or linked to a display device, embodiments of the present invention may provide a display device equipped with an area inside the display area where a sensor, etc., can be disposed. However, this technical issue is merely exemplary and does not limit the scope of the present invention.

[0005] According to one aspect of the present invention, a display device is provided, comprising: a substrate including a first area and a second area provided with a transmissive portion; a plurality of main pixel groups arranged on the first area; a plurality of auxiliary pixel groups arranged on the second area; a plurality of first signal lines electrically connecting the plurality of main pixel groups and the plurality of auxiliary pixel groups and extending along a first direction; and a plurality of second signal lines electrically connecting the plurality of main pixel groups and the plurality of auxiliary pixel groups and extending along a second direction intersecting the first direction, wherein, on the second area, the distance between the plurality of first signal lines gradually decreases from the center of the second area to the periphery of the second area, and on the second area, the distance between the plurality of second signal lines gradually decreases from the center of the second area to the periphery of the second area.

[0006] In this embodiment, the distance between the plurality of first signal lines arranged on the first region may be smaller than or equal to the distance between the plurality of first signal lines arranged on the second region.

[0007] In this embodiment, the distance between the plurality of second signal lines arranged on the first region may be less than or equal to the distance between the plurality of second signal lines arranged on the second region.

[0008] In this embodiment, the distances between the plurality of auxiliary pixel groups along the first direction may gradually decrease from the center of the second region toward the periphery of the second region.

[0009] In this embodiment, the distances between the plurality of auxiliary pixel groups along the second direction may gradually decrease from the center of the second region toward the periphery of the second region.

[0010] In this embodiment, the distance between the plurality of primary pixel groups along the first direction may be less than or equal to the distance between the plurality of auxiliary pixel groups along the first direction.

[0011] In this embodiment, the distance between the plurality of primary pixel groups along the second direction may be less than or equal to the distance between the plurality of auxiliary pixel groups along the second direction.

[0012] In this embodiment, each of the plurality of auxiliary pixel groups may include a first auxiliary pixel, a second auxiliary pixel, and a third auxiliary pixel that emit light of different wavelengths.

[0013] In this embodiment, each of the plurality of primary pixel groups may include a first primary pixel, a second primary pixel, and a third primary pixel that emit light of different wavelengths.

[0014] In this embodiment, each of the plurality of second signal lines may include a first conductive line, a second conductive line, and a third conductive line.

[0015] In this embodiment, a portion of the first conductive line may be electrically connected to the first auxiliary pixel, a portion of the second conductive line may be electrically connected to the second auxiliary pixel, and a portion of the third conductive line may be electrically connected to the third auxiliary pixel.

[0016] In this embodiment, the first conductive line may be electrically connected to the first primary pixel, the second conductive line may be electrically connected to the second primary pixel, and the third conductive line may be electrically connected to the third primary pixel.

[0017] In this embodiment, at least one of the plurality of first signal lines may include a first signal line extending along the first direction and being disconnected with the second region interposed therebetween, and the disconnected first signal line is connected by a connecting line meandering along an edge of the second region.

[0018] In this embodiment, at least one of the plurality of second signal lines may include a disconnected second signal line extending along the second direction and having the second region interposed therebetween, and the disconnected second signal lines are connected by a connecting line meandering along an edge of the second region.

[0019] According to another aspect of the present invention, a display device is provided, comprising: a substrate including a first area and a second area provided with a transmissive portion; a plurality of main pixel groups arranged on the first area; a plurality of auxiliary pixel groups arranged on the second area; a plurality of first signal lines electrically connecting the plurality of main pixel groups and the plurality of auxiliary pixel groups and extending along a first direction; a plurality of second signal lines electrically connecting the plurality of main pixel groups and the plurality of auxiliary pixel groups and extending along a second direction intersecting the first direction; and a component arranged below the substrate in a manner corresponding to the second area and including an electronic element that emits or receives light, wherein, on the second area, the distance between the plurality of first signal lines gradually decreases from the center of the second area to the periphery of the second area, and on the second area, the distance between the plurality of second signal lines gradually decreases from the center of the second area to the periphery of the second area.

[0020] In this embodiment, the distance between the plurality of first signal lines arranged on the first region may be smaller than or equal to the distance between the plurality of first signal lines arranged on the second region.

[0021] In this embodiment, the distance between the plurality of second signal lines arranged on the first region may be less than or equal to the distance between the plurality of second signal lines arranged on the second region.

[0022] In this embodiment, the distances between the plurality of auxiliary pixel groups along the first direction may gradually decrease from the center of the second region toward the periphery of the second region.

[0023] In this embodiment, the distances between the plurality of auxiliary pixel groups along the second direction may gradually decrease from the center of the second region toward the periphery of the second region.

[0024] In this embodiment, each of the plurality of auxiliary pixel groups may include a first auxiliary pixel, a second auxiliary pixel, and a third auxiliary pixel that emit light of different wavelengths.

[0025] According to another aspect of the present invention, there is provided a display device comprising: a substrate including a first region and a second region provided with a transmissive portion; a plurality of main pixel groups arranged on the first region along a first direction and a second direction intersecting the first direction; and a plurality of auxiliary pixel groups arranged on the second region along the first direction and the second direction, wherein the distance between the plurality of auxiliary pixel groups gradually decreases from the center of the second region toward the periphery of the second region, and the distance between the plurality of main pixel groups is less than or equal to the distance between the plurality of auxiliary pixel groups.

[0026] Other aspects, features, and advantages besides those described above will become apparent from the following detailed description, claims, and accompanying drawings for carrying out the invention.

[0027] According to one embodiment of the present invention configured as described above, a display device can be realized in which the display area in which components are arranged is expanded and images can be displayed. Of course, the scope of the present invention is not limited to these effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0029] Figure 2 is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0030] Figure 3a and Figure 3b is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0031] Figure 4 FIG. 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.

[0032] Figure 5 and Figure 6 is an equivalent circuit diagram of a pixel that may be included in a display device according to an embodiment of the present invention.

[0033] Figure 7a and 7b is a cross-sectional view of a main pixel and an auxiliary pixel that may be included in a display device according to an embodiment of the present invention.

[0034] Figure 8 FIG. 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.

[0035] Figure 9a and Figure 9b FIG. 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.

[0036] Figure 10a and Figure 10b FIG. 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.

[0037] Description of Reference Numerals

[0038] DA: Display Area 1A: First Area

[0039] 2A: Second area TA: Transmissive part

[0040] GL: Gate line DL: Data line

[0041] 1: Display device 10: Display panel

[0042] 20: Component 100: Substrate DETAILED DESCRIPTION

[0043] The present invention is susceptible to various modifications and embodiments, and specific embodiments are illustrated in the accompanying drawings and described in detail in the detailed description. Figure 1 The effects and features of the present invention and methods for achieving the effects and features will be made clear by the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals and repeated description thereof will be omitted.

[0045] In the following embodiments, the terms "first" and "second" are not used in a limiting sense, but are used to distinguish one component from other components. In addition, as long as the context does not clearly indicate otherwise, the singular expression includes the plural expression.

[0046] In addition, terms such as "including" or "having" indicate the presence of the features or components described in the specification, and do not preclude the possibility of the addition of one or more other features or components. Furthermore, when a portion of a film, region, component, etc. is referred to as being "on" or "above" another portion, this includes not only the situation of being "immediately above" or "immediately above" the other portion, but also the situation of having other films, regions, components, etc. interposed therebetween.

[0047] For the sake of convenience, the sizes of the components in the drawings may be exaggerated or reduced. For example, for the sake of convenience, the sizes and thicknesses of the components shown in the drawings are arbitrarily shown, and the present invention is not necessarily limited to the contents shown in the drawings.

[0048] The x-axis, y-axis, and z-axis are not limited to the three axes in the rectangular coordinate system, and can be interpreted as including a broad meaning thereof. For example, the x-axis, y-axis, and z-axis can also refer to different directions that are not perpendicular to each other, although they can also be perpendicular to each other.

[0049] When an embodiment can be implemented in different ways, a specific process sequence can be performed in a different order than described. For example, two processes described in succession can be performed substantially simultaneously, or in a reverse order to the described order.

[0050] Figure 1 is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0051] Reference Figure 1 The display device 1 includes a display area DA that displays an image and a non-display area NDA that does not display an image. The display area DA includes a first area 1A and a second area 2A equipped with a transmissive portion TA. The display device 1 can provide a primary image using light emitted by a plurality of primary pixels Pm arranged in the first area 1A, and can provide an auxiliary image using light emitted by a plurality of auxiliary pixels Pa arranged in the second area 2A.

[0052] As referenced later Figure 2 As described above, the second region 2A may be an area having components including optical elements disposed thereunder. The second region 2A may include a transmissive portion TA that allows light and / or sound emitted from the components to the outside or transmitted from the outside toward the components to pass through. As one embodiment of the present invention, when infrared light is transmitted through the second region 2A, the transmittance may be approximately 30% or greater, more preferably 50% or greater, or 75% or greater, or 80% or greater, or 85% or greater, or 90% or greater.

[0053] In this embodiment, a plurality of auxiliary pixels Pa may be arranged in the second area 2A, and a predetermined image may be provided using light emitted from the plurality of auxiliary pixels Pa. The image provided in the second area 2A is an auxiliary image, and its resolution may be lower than that of the image provided in the first area 1A. That is, because the second area 2A is provided with a transmissive portion TA that allows light and / or sound to pass through, the number of auxiliary pixels Pa that can be arranged per unit area can be less than the number of primary pixels Pm arranged per unit area in the first area 1A.

[0054] The following description uses an example in which the display device 1 according to one embodiment of the present invention is an organic light-emitting display device. However, the display device of the present invention is not limited thereto. As one embodiment, various display devices such as an inorganic light-emitting display (ILD) and a quantum dot light-emitting display (QDLED) can be used.

[0055] exist Figure 1 The figure shows a case where the second region 2A is arranged above the quadrilateral display area DA, but the present invention is not limited to this. The shape of the display area DA can be circular, elliptical, or polygonal such as a triangle, and the position and number of the second regions 2A can also be varied.

[0056] Figure 2is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0057] Reference Figure 2 The display device 1 may include a display panel 10, an input sensing layer 40 and an optical functional layer 50 disposed on the display panel 10, and these may be covered by a window 60. The window 60 may be bonded to the underlying components (e.g., the optical functional layer 50) via an adhesive layer such as an optically clear adhesive (OCA). The display device 1 may be included in various electronic devices such as mobile phones, tablet PCs, notebooks, and smart watches.

[0058] The display panel 10 may include a plurality of diodes arranged in the display area DA. The input sensing layer 40 may obtain coordinate information based on an external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes and traces connected to the sensing electrodes. The input sensing layer 40 may be arranged on the display panel 10. The input sensing layer 40 may sense external inputs through a mutual capacitance method or a self-capacitance method.

[0059] The input sensing layer 40 may be directly disposed on the display panel 10. Alternatively, the input sensing layer 40 may be bonded to the display panel 10 via an adhesive layer such as an optically clear adhesive (OCA). Figure 2 As shown, the input sensing layer 40 may be disposed immediately above the display panel 10 . In this case, no adhesive layer may be interposed between the input sensing layer 40 and the display panel 10 .

[0060] The optical functional layer 50 may include a reflection prevention layer. The reflection prevention layer may reduce the reflectivity of light (external light) incident from the outside through the window 60 toward the display panel 10. The optical functional layer 50 may include functional layers such as a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include an extended synthetic resin film, and the liquid crystal coating type includes liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer may further include a protective film.

[0061] The optical function layer 50 may include a structure comprising a black matrix and a color filter. The color filters may be arranged according to the color of light emitted from each pixel of the display panel 10. As one embodiment, the optical function layer 50 may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged on different layers. The first reflected light and the second reflected light, respectively reflected by the first reflective layer and the second reflective layer, may destructively interfere with each other, thereby reducing the reflectivity of external light.

[0062] The optical function layer 50 may include a lens layer. The lens layer may improve the light output efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or a plurality of layers having different refractive indices.

[0063] Component 20 may be located in second area 2A. Component 20 may be an electronic element that utilizes light or sound. For example, component 20 may be an optical element, a sensor that receives and utilizes light, such as an infrared sensor, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small light fixture that outputs light, or a speaker that outputs sound.

[0064] In one embodiment, when the display device 1 is used as a smart watch or a vehicle instrument panel, the component 20 may be a part such as a clock hand or a hand indicating predetermined information (eg, vehicle speed).

[0065] As described above, the assembly 20 may include (a plurality of) components that can add predetermined functions to the display device 1 or components such as accessories that enhance the aesthetics of the display panel 10 .

[0066] Figure 3a and Figure 3b is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0067] Reference Figure 3a The display device 1 may include: a display panel 10 including display elements; and a component 20 located below the display panel 10 and arranged corresponding to the second area 2A.

[0068] The display panel 10 may include a substrate 100 , a display element layer 200 disposed on the substrate 100 , and an encapsulation substrate 300 a serving as an encapsulation component for encapsulating the display element layer 200 . Furthermore, the display panel 10 may further include a lower protective film 175 disposed below the substrate 100 .

[0069] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may have flexible, rollable, or bendable properties. The substrate 100 may be a multilayer structure including a layer including the above-mentioned polymer resin and an inorganic layer (not shown).

[0070] The display element layer 200 may include a circuit layer including thin-film transistors (TFT) and TFT'; organic light-emitting diodes (OLED) and OLED', which serve as display elements; and an insulating layer IL therebetween. A primary pixel Pm, including a primary thin-film transistor (TFT) and a connected primary organic light-emitting diode (OLED), may be arranged in the first region 1A. An auxiliary pixel Pa, including an auxiliary thin-film transistor (TFT') and a connected auxiliary organic light-emitting diode (OLED), may be arranged in the second region 2A.

[0071] Furthermore, a transmissive portion TA may be disposed in the second region 2A where no auxiliary thin film transistor TFT' and display elements are disposed. The transmissive portion TA may be understood as a region that transmits signals such as light or sound emitted from the component 20 or incident upon the component 20.

[0072] The display element layer 200 may be covered by an encapsulation substrate 300a. The encapsulation substrate 300a may include a glass material. For example, the encapsulation substrate 300a may include a glass material having SiO2 as a main component. The encapsulation substrate 300a may be arranged to face the substrate 100, and a sealant ST may be arranged between the substrate 100 and the encapsulation substrate 300a. The sealant ST may be located at an edge portion of the substrate 100 and surround the display element layer 200 as a whole between the substrate 100 and the encapsulation substrate 300a. When viewed from a direction perpendicular to the upper surface of the substrate 100 (or, in a plan view), the first region 1A and the second region 2A may be surrounded as a whole by the sealant ST.

[0073] Reference Figure 3b, the display element layer 200 may be covered by a thin film encapsulation layer 300b. The thin film encapsulation layer 300b may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 3b A first inorganic encapsulating layer 310 , a second inorganic encapsulating layer 330 , and an organic encapsulating layer 320 therebetween are shown.

[0074] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. Polymer materials may include acrylic resins, epoxy resins, polyimide, and polyethylene.

[0075] The lower protective film 175 can be attached to the lower portion of the substrate 100 and serve to support and protect the substrate 100. The lower protective film 175 can be provided with an opening 175OP corresponding to the second region 2A. Providing the opening 175OP in the lower protective film 175 can improve the light transmittance of the second region 2A. The lower protective film 175 can be provided with a material including polyethylene terephthalate or polyimide.

[0076] The area of ​​the second region 2A may be larger than the area of ​​the arrangement component 20. Therefore, the area of ​​the opening 175OP provided in the lower protection film 175 may not be consistent with the area of ​​the second region 2A. For example, the area of ​​the opening 175OP may be smaller than the area of ​​the second region 2A.

[0077] Furthermore, the second area 2A may be provided with a plurality of components 20. The plurality of components 20 may have different functions from each other.

[0078] Figure 4 FIG. 1 is a plan view schematically illustrating a display device according to an embodiment of the present invention.

[0079] Reference Figure 4 , various components constituting the display device 1 are arranged on a substrate 100. The substrate 100 includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA includes a first area 1A and a second area 2A. The display area DA can be referred to above. Figure 3a and Figure 3b The packaging component is covered to be protected from the influence of external air or moisture.

[0080] The display device 1 includes a plurality of primary pixels Pm arranged in a first area 1A. Each primary pixel Pm may include a display element such as an organic light-emitting diode (OLED). Each primary pixel Pm may emit, for example, red, green, blue, or white light via the OLED. As described above, the primary pixel Pm in this specification may be understood as a pixel that emits light of any of red, green, blue, or white.

[0081] The second area 2A can be arranged on one side of the first area 1A, and a plurality of auxiliary pixels Pa can be arranged in the second area 2A. The auxiliary pixels Pa can each include a display element such as an organic light-emitting diode. Each auxiliary pixel Pa can emit, for example, red, green, blue, or white light through the organic light-emitting diode. As described above, the auxiliary pixel Pa in this specification can be understood as a pixel that emits light of any color of red, green, blue, or white. In addition, a transmissive portion TA arranged between the auxiliary pixels Pa can be provided in the second area 2A. At least one component 20 can be arranged at the lower portion corresponding to the second area 2A of the display device 1.

[0082] In one embodiment, a primary pixel Pm and an auxiliary pixel Pa may include the same pixel circuit. However, the present invention is not limited thereto. The pixel circuit included in the primary pixel Pm and the pixel circuit included in the auxiliary pixel Pa may also be different from each other.

[0083] Because the second region 2A includes a transmissive portion TA, the resolution of the second region 2A can be lower than that of the first region 1A. For example, the resolution of the second region 2A can be approximately half that of the first region 1A. In some embodiments, the resolution of the first region 1A can be greater than 400 ppi, while the resolution of the second region 2A can be approximately 100 ppi.

[0084] Each pixel Pm and Pa can be electrically connected to a peripheral circuit arranged in the non-display area NDA. A first scan driving circuit 110, a first light emitting driving circuit 115, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power supply wiring 160, and a second power supply wiring 170 can be arranged in the non-display area NDA.

[0085] The first scan driver circuit 110 can provide scan signals to each pixel Pm and Pa via scan lines SL. The first light-emitting driver circuit 115 can provide light-emitting control signals to each pixel Pm and Pa via light-emitting control lines EL. The second scan driver circuit 120 can be positioned between the display area DA and aligned with the first scan driver circuit 110. Some of the pixels Pm and Pa arranged in the display area DA can be electrically connected to the first scan driver circuit 110, while the remaining pixels can be connected to the second scan driver circuit 120. As one embodiment, the second light-emitting driver circuit (not shown) can be positioned between the display area DA and aligned with the first light-emitting driver circuit 115.

[0086] The first light emitting driving circuit 115 may be spaced apart from the first scan driving circuit 110 in the x-direction and disposed on the non-display area NDA. In one embodiment, the first light emitting driving circuit 115 may be alternately disposed with the first scan driving circuit 110 in the y-direction.

[0087] The terminal 140 may be arranged on one side of the substrate 100. The terminal 140 may be exposed without being covered by the insulating layer, thereby being electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display device 1. The printed circuit board PCB transmits signals or power from the control unit (not shown) to the display device 1. The control signals generated by the control unit may be transmitted to the first scan driving circuit 110, the first light-emitting driving circuit 115, and the second scan driving circuit 120 respectively via the printed circuit board PCB. The control unit may provide a first power supply voltage ELVDD and a second power supply voltage ELVSS to the first power supply wiring 160 and the second power supply wiring 170 respectively via the first connection wiring 161 and the second connection wiring 171. The first power supply voltage ELVDD may be provided to each pixel Pm, Pa via the driving voltage line PL connected to the first power supply wiring 160, and the second power supply voltage ELVSS may be provided to the counter electrode of each pixel Pm, Pa connected to the second power supply wiring 170.

[0088] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 can be provided to each pixel Pm, Pa through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151. Figure 4 The data driving circuit 150 is shown as being disposed on the printed circuit board PCB. However, as an embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power supply wiring 160.

[0089] The first power supply wiring 160 may include a first sub wiring 162 and a second sub wiring 163 extending in alignment along the x-direction with the display area DA interposed therebetween. The second power supply wiring 170 may partially surround the display area DA in a ring shape with one side open.

[0090] Figure 5 and Figure 6 is an equivalent circuit diagram of a pixel that may be included in a display device according to an embodiment of the present invention.

[0091] Reference Figure 5 Each pixel Pm, Pa includes a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light emitting diode OLED connected to the pixel circuit PC.

[0092] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and transmits the data signal Dm input through the data line DL to the driving thin film transistor T1 according to the scan signal Sn input through the scan line SL.

[0093] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL and stores a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a first power voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0094] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and controls a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light with a predetermined brightness according to the driving current.

[0095] exist Figure 5 The case where the pixel circuit PC includes two thin film transistors and one storage capacitor is described in the foregoing, but the present invention is not limited thereto. Figure 6 As shown, the pixel circuit PC may include seven thin film transistors and one storage capacitor.

[0096] Reference Figure 6 Each pixel Pm and Pa includes a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include multiple thin-film transistors and storage capacitors. The thin-film transistors and storage capacitors may be connected to signal lines SL, SL-1, EL, DL, an initialization voltage line VL, and a drive voltage line PL.

[0097] exist Figure 6 , each pixel Pm and Pa is connected to the signal lines SL, SL-1, EL, DL, the initialization voltage line VL, and the drive voltage line PL. However, the present invention is not limited to this. As one embodiment, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the drive voltage line PL can be shared by adjacent pixels.

[0098] The plurality of thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , a light emission control thin film transistor T6 and a second initialization thin film transistor T7 .

[0099] The signal lines include a scan line SL that transmits a scan signal Sn, a front scan line SL-1 that transmits a front scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL that transmits an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL that intersects the scan line SL and transmits a data signal Dm. A drive voltage line PL transmits a drive voltage ELVDD to the drive thin film transistor T1, and an initialization voltage line VL transmits an initialization voltage Vint that initializes the drive thin film transistor T1 and the pixel electrode.

[0100] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first storage storage plate Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin film transistor T1 is connected to the lower driving voltage line PL via the operation control thin film transistor T5. The driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the light emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and supplies the driving current I to the organic light emitting diode OLED. OLED .

[0101] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is connected to the lower driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scan signal Sn received via the scan line SL, thereby performing a switching operation to transmit the data signal Dm transmitted to the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0102] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL. The compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the drive drain electrode D1 of the drive thin-film transistor T1 and is connected to the pixel electrode of the organic light-emitting diode OLED via the light-emission control thin-film transistor T6. The compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the first storage storage plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin-film transistor T4, and the drive gate electrode G1 of the drive thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn received via the scan line SL, thereby electrically connecting the drive gate electrode G1 and the drive drain electrode D1 of the drive thin-film transistor T1, thereby diode-connecting the drive thin-film transistor T1.

[0103] A first initialization gate electrode G4 of the first initialization thin-film transistor T4 is connected to the front scan line SL-1. A first initialization source electrode S4 of the first initialization thin-film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin-film transistor T7 and the initialization voltage line VL. A first initialization drain electrode D4 of the first initialization thin-film transistor T4 is connected to the first storage storage plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin-film transistor T3, and the drive gate electrode G1 of the drive thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the front scan signal Sn-1 received via the front scan line SL-1, thereby performing an initialization operation of transmitting the initialization voltage Vint to the drive gate electrode G1 of the drive thin-film transistor T1, thereby initializing the voltage of the drive gate electrode G1 of the drive thin-film transistor T1.

[0104] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the light emitting control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the lower driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0105] The light-emitting control gate electrode G6 of the light-emitting control thin film transistor T6 is connected to the light-emitting control line EL, the light-emitting control source electrode S6 of the light-emitting control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the light-emitting control drain electrode D6 of the light-emitting control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light-emitting diode OLED.

[0106] The operation control thin film transistor T5 and the light emitting control thin film transistor T6 are turned on simultaneously according to the light emitting control signal En received through the light emitting control line EL, thereby transmitting the driving voltage ELVDD to the organic light emitting diode OLED, thereby driving the current I OLED Flow in organic light-emitting diodes OLED.

[0107] A second initialization gate electrode G7 of the second initialization thin-film transistor T7 is connected to the front scan line SL-1. A second initialization source electrode S7 of the second initialization thin-film transistor T7 is connected to the light-emission control drain electrode D6 of the light-emission control thin-film transistor T6 and the pixel electrode of the organic light-emitting diode OLED. A second initialization drain electrode D7 of the second initialization thin-film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin-film transistor T4 and the initialization voltage line VL. The second initialization thin-film transistor T7 is turned on in response to the front scan signal Sn-1 received via the front scan line SL-1, thereby initializing the pixel electrode of the organic light-emitting diode OLED.

[0108] exist Figure 6 The figure shows a case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the front scan line SL-1, but the present invention is not limited to this. As an embodiment, the first initialization thin film transistor T4 can be connected to the front scan line SL-1 and driven according to the front scan signal Sn-1, while the second initialization thin film transistor T7 can be connected to a separate signal line (e.g., the rear scan line) and driven according to the signal transmitted to the signal line.

[0109] The second storage plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common power supply voltage ELVSS. Accordingly, the organic light emitting diode OLED receives the driving current I from the driving thin film transistor T1. OLED It emits light, thus displaying images.

[0110] exist Figure 6 4 shows a case where the compensation thin film transistor T3 and the first initialization thin film transistor T4 have a double gate electrode, but the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have a single gate electrode.

[0111] In this embodiment, the main pixel Pm and the auxiliary pixel Pa can be equipped with the same pixel circuit PC. However, this is not limited to this. The main pixel Pm and the auxiliary pixel Pa can also be equipped with pixel circuits PC of different structures. For example, the main pixel Pm can be equipped with a pixel circuit PC of different structures. Figure 6 The pixel circuit and the auxiliary pixel Pa adopt Figure 5 Various deformations such as pixel circuits.

[0112] Figure 7a and Figure 7b is a cross-sectional view of a main pixel and an auxiliary pixel that may be included in a display device according to an embodiment of the present invention.

[0113] Below, refer to Figure 7a and Figure 7b , a description is given of the stacked structure of a display device according to an embodiment of the present invention.

[0114] Reference Figure 7a The display device 1 may include thin film transistors TFT, TFT' and organic light emitting diodes OLED, OLED' arranged on a substrate 100. The substrate 100 may include a glass material or a polymer resin with SiO2 as a main component. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate, etc. The substrate 100 including the polymer resin may have flexible, rollable or bendable properties. The substrate 100 may be a multilayer structure including a layer containing the above-mentioned polymer resin and an inorganic layer (not shown).

[0115] The buffer layer 101 may be located on the substrate 100 to reduce or block the penetration of foreign matter, moisture, or external air from the lower portion of the substrate 100 and to provide a flat surface on the substrate 100. The buffer layer 101 may include an inorganic substance such as an oxide or a nitride, an organic substance, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic substances. A barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 101 to block the penetration of external air.

[0116] A main thin-film transistor (TFT) and an auxiliary thin-film transistor (TFT') may be arranged on top of the buffer layer 101. The main thin-film transistor (TFT) includes a main semiconductor layer 134a, a main gate electrode 136a, a main source electrode 137a, and a main drain electrode 138a. The auxiliary thin-film transistor (TFT') includes an auxiliary semiconductor layer 134b, an auxiliary gate electrode 136b, an auxiliary source electrode 137b, and an auxiliary drain electrode 138b. The main thin-film transistor (TFT) may be connected to the main organic light-emitting diode (OLED) in the first region 1A to drive the main organic light-emitting diode (OLED). The auxiliary thin-film transistor (TFT') may be connected to the auxiliary organic light-emitting diode (OLED') in the second region 2A to drive the auxiliary organic light-emitting diode (OLED').

[0117] The main semiconductor layer 134a and the auxiliary semiconductor layer 134b may be disposed on the buffer layer 101. The main semiconductor layer 134a may include: a main channel region 131a overlapping with the main gate electrode 136a; a main source region 132a and a main drain region 133a disposed on either side of the main channel region 131a and including a higher concentration of impurities than in the main channel region 131a. The auxiliary semiconductor layer 134b may include: an auxiliary channel region 131b overlapping with the auxiliary gate electrode 136b; an auxiliary source region 132b and an auxiliary drain region 133b disposed on either side of the auxiliary channel region 131b and including a higher concentration of impurities than in the auxiliary channel region 131b. The impurities may include N-type impurities or P-type impurities. The main source region 132a and the auxiliary source region 132b can be electrically connected to the main source electrode 137a of the main thin film transistor TFT and the auxiliary source electrode 137b of the auxiliary thin film transistor TFT', respectively; the main drain region 133a and the auxiliary drain region 133b can be electrically connected to the main drain electrode 138a of the main thin film transistor TFT and the auxiliary drain electrode 138b of the auxiliary thin film transistor TFT', respectively.

[0118] The main semiconductor layer 134a and the auxiliary semiconductor layer 134b may include an oxide semiconductor and / or a silicon semiconductor. When the main semiconductor layer 134a and the auxiliary semiconductor layer 134b are formed using an oxide semiconductor, for example, they may include an oxide of at least one substance selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the main semiconductor layer 134a and the auxiliary semiconductor layer 134b may be ITZO (InSnZnO), IGZO (InGaZnO), etc. When the main semiconductor layer 134a and the auxiliary semiconductor layer 134b are formed using a silicon semiconductor, for example, they may include amorphous silicon (a-Si) or low-temperature polysilicon (LTPS) obtained by crystallizing amorphous silicon (a-Si).

[0119] The main gate electrode 136a and the auxiliary gate electrode 136b can be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The main gate electrode 136a and the auxiliary gate electrode 136b can be connected to a gate line that applies an electrical signal to the main gate electrode 136a and the auxiliary gate electrode 136b.

[0120] A first insulating layer 103 may be disposed between the main semiconductor layer 134a and the main gate electrode 136a and between the auxiliary semiconductor layer 134b and the auxiliary gate electrode 136b. The first insulating layer 103 may include a material selected from silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The first insulating layer 103 may be a single layer or multiple layers including the above inorganic insulators.

[0121] A second insulating layer 105 may be provided on the first insulating layer 103 in a manner covering the main gate electrode 136a and the auxiliary gate electrode 136b. The second insulating layer 105 may include a material selected from silicon oxide (SiO2), silicon nitride (SiN x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The second insulating layer 105 may be a single layer or multiple layers including the above inorganic insulators.

[0122] A main storage capacitor Cst and an auxiliary storage capacitor Cst' may be arranged on the second insulating layer 105. The main storage capacitor Cst may include a main lower electrode 144a and a main upper electrode 146a. The main storage capacitor Cst may overlap with the main thin-film transistor TFT, and the main lower electrode 144a of the main storage capacitor Cst and the main gate electrode 136a of the main thin-film transistor TFT are arranged as a whole. As one embodiment, the main storage capacitor Cst may not overlap with the main thin-film transistor TFT, and the main lower electrode 144a may be an independent component separated from the main gate electrode 136a of the main thin-film transistor TFT. The auxiliary storage capacitor Cst' may include an auxiliary lower electrode 144b and an auxiliary upper electrode 146b. The auxiliary storage capacitor Cst' may overlap with the auxiliary thin-film transistor TFT', and the auxiliary lower electrode 144b of the auxiliary storage capacitor Cst' and the auxiliary gate electrode 136b of the auxiliary thin-film transistor TFT' are arranged as a whole. As an embodiment, the auxiliary storage capacitor Cst′ may not overlap with the auxiliary thin film transistor TFT′, and the auxiliary lower electrode 144 b may be an independent component separated from the auxiliary gate electrode 136 b of the auxiliary thin film transistor TFT′.

[0123] The main upper electrode 146a and the auxiliary upper electrode 146b may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may be a single layer or multiple layers of the above substances.

[0124] The third insulating layer 107 may be formed to cover the main upper electrode 146a and the auxiliary upper electrode 146b. The third insulating layer 107 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), etc.

[0125] The main source electrode 137a, the auxiliary source electrode 137b, the main drain electrode 138a, and the auxiliary drain electrode 138b may be disposed on the third insulating layer 107. The main source electrode 137a, the auxiliary source electrode 137b, the main drain electrode 138a, and the auxiliary drain electrode 138b may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. As an example, the main source electrode 137a, the auxiliary source electrode 137b, the main drain electrode 138a, and the auxiliary drain electrode 138b may have a multilayer structure of Ti / Al / Ti.

[0126] A planarization layer 113 may be disposed to cover the main source electrode 137a, the auxiliary source electrode 137b, the main drain electrode 138a, and the auxiliary drain electrode 138b. The planarization layer 113 may have a flat upper surface so that the pixel electrode disposed thereon can be formed flatly.

[0127] The planarization layer 113 may be formed into a single layer or multiple layers of a film composed of an organic substance or an inorganic substance. Such a planarization layer 113 may include a general polymer of benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer and a blend thereof. In addition, the planarization layer 113 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), etc. After the planarization layer 113 is formed, chemical mechanical polishing may be performed to provide a flat upper surface.

[0128] There may be an opening in the planarization layer 113 that exposes any one of the main source electrode 137a and the main drain electrode 138a of the main thin film transistor TFT, and the main pixel electrode 210a contacts the main source electrode 137a or the main drain electrode 138a through the opening and is electrically connected to the main thin film transistor TFT.

[0129] Furthermore, the planarization layer 113 may include an opening portion that exposes any one of the auxiliary source electrode 137b and the auxiliary drain electrode 138b of the auxiliary thin film transistor TFT', and the auxiliary pixel electrode 210b contacts the auxiliary source electrode 137b or the auxiliary drain electrode 138b through the opening portion and is electrically connected to the auxiliary thin film transistor TFT'.

[0130] In the first area 1A of the substrate 100, a main organic light-emitting diode OLED can be arranged on the planarization layer 113. The main organic light-emitting diode OLED includes a main pixel electrode 210a, a main intermediate layer 220a, and a main counter electrode 230a arranged opposite to the main pixel electrode 210a and with the main intermediate layer 220a interposed therebetween.

[0131] In the second area 2A of the substrate 100, an auxiliary organic light-emitting diode OLED' can be arranged on the planarization layer 113, and the auxiliary organic light-emitting diode OLED' includes an auxiliary pixel electrode 210b, an auxiliary intermediate layer 220b, and an auxiliary counter electrode 230b arranged opposite to the auxiliary pixel electrode 210b and with the auxiliary intermediate layer 220b interposed therebetween.

[0132] A main pixel electrode 210a and an auxiliary pixel electrode 210b may be arranged on the planarization layer 113. The main pixel electrode 210a and the auxiliary pixel electrode 210b may be (semi-) translucent electrodes or reflective electrodes. The main pixel electrode 210a and the auxiliary pixel electrode 210b may be provided with a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may be provided with at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The main pixel electrode 210a and the auxiliary pixel electrode 210b may be provided with a structure stacked with ITO / Ag / ITO.

[0133] A pixel definition film 180 may be disposed on the planarization layer 113. The pixel definition film 180 may have an opening that exposes at least a portion of the primary pixel electrode 210a and an opening that exposes at least a portion of the auxiliary pixel electrode 210b. The pixel definition film 180 can prevent arcing, etc., at the edge of the primary pixel electrode 210a by increasing the distance between the edge of the primary pixel electrode 210a and the primary counter electrode 230a above the primary pixel electrode 210a. It can also prevent arcing, etc., at the edge of the auxiliary pixel electrode 210b by increasing the distance between the edge of the auxiliary pixel electrode 210b and the auxiliary counter electrode 230b above the auxiliary pixel electrode 210b. The pixel definition film 180 can be formed using, for example, an inorganic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), or phenolic resin by spin coating or other methods.

[0134] A main intermediate layer 220a may be disposed on the main pixel electrode 210a, at least a portion of which is exposed through the pixel definition film 180, and an auxiliary intermediate layer 220b may be disposed on the auxiliary pixel electrode 210b. The main intermediate layer 220a and the auxiliary intermediate layer 220b may include a light-emitting layer, and may optionally include functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) below and above the light-emitting layer.

[0135] The light emitting layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light emitting layer may be a low molecular weight organic material or a high molecular weight organic material.

[0136] When the light-emitting layer includes a low-molecular-weight substance, the main intermediate layer 220a and the auxiliary intermediate layer 220b may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite structure. The low-molecular-weight organic substance may include copper phthalocyanine (CuPc), NPB (N,N'-di(napthalene-1-yl)-N,N'-diphenyl-benzidine), Alq3 (tris-8-hydroxyquinoline aluminum), and other organic substances. Such layers may be formed by vacuum deposition.

[0137] When the light-emitting layer comprises a polymer, the main intermediate layer 220a and the auxiliary intermediate layer 220b may generally have a structure including a hole transport layer (HTL) and a light-emitting layer (EML). In this case, the hole transport layer may comprise PEDOT (poly(3,4-ethylenedioxythiophene)), and the light-emitting layer may comprise a polymer such as poly(p-phenylene vinylene) (PPV) or polyfluorene. Such a light-emitting layer can be formed by screen printing, inkjet printing, laser induced thermal imaging (LITI), or the like.

[0138] A main counter electrode 230a may be disposed on the main intermediate layer 220a. The main counter electrode 230a may be disposed on the main intermediate layer 220a and arranged to cover the entirety of the main intermediate layer 220a. The main counter electrode 230a may be disposed above the first region 1A and arranged to cover the entirety of the first region 1A. In other words, the main counter electrode 230a may be formed integrally to cover the plurality of primary pixels Pm disposed in the first region 1A.

[0139] An auxiliary counter electrode 230b may be disposed on the auxiliary intermediate layer 220b. The auxiliary counter electrode 230b may be disposed on the auxiliary intermediate layer 220b and arranged to cover the entirety of the auxiliary intermediate layer 220b. The auxiliary counter electrode 230b may be disposed above the second region 2A and arranged to cover the entirety of the second region 2A. Specifically, the auxiliary counter electrode 230b may be integrally formed to cover the plurality of auxiliary pixels Pa disposed in the second region 2A, and may also be disposed on the transmissive portion TA provided in the second region 2A. Furthermore, the auxiliary counter electrode 230b may also be formed to cover the auxiliary pixels Pa in the second region 2A, but not disposed on the transmissive portion TA provided in the second region 2A.

[0140] As an embodiment, the main counter electrode 230a and the auxiliary counter electrode 230b may be formed as one body. For example, the main counter electrode 230a disposed on the first region 1A may extend toward the second region 2A and also be disposed on the second region 2A.

[0141] The main counter electrode 230a and the auxiliary counter electrode 230b may include a conductive material with a low work function. For example, the main counter electrode 230a and the auxiliary counter electrode 230b may include a (semi-)transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the main counter electrode 230a and the auxiliary counter electrode 230b may further include a layer such as ITO, IZO, ZnO, or In2O3 in addition to the (semi-)transparent layer containing the above-mentioned substances.

[0142] The main organic light emitting diode OLED and the auxiliary organic light emitting diode OLED′ may be covered by an encapsulation substrate 300a. The encapsulation substrate 300a may include a glass material. For example, the encapsulation substrate 300a may include a glass material having SiO2 as a main component. The encapsulation substrate 300a may be arranged to face the substrate 100.

[0143] Figure 7b Examples and Figure 7a The difference between the embodiment of FIG is that the display element layer is covered by the thin film encapsulation layer 300b. Figure 7b In the composition of Figure 7a The description of the same configuration is omitted, and the following description focuses on the differences.

[0144] Reference Figure 7bThe display element layer may be covered by a thin film encapsulation layer 300b. The thin film encapsulation layer 300b may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. As an embodiment, the thin film encapsulation layer 300b may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween.

[0145] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include one or more inorganic insulators. The inorganic insulator may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride. The organic encapsulation layer 320 may include a polymer series of substances. The polymer series of materials may include acrylic resins, epoxy resins, polyimides and polyethylene, etc. For example, the organic encapsulation layer 320 may include an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.).

[0146] In the case where the display panel includes a thin film encapsulation layer 300b as an encapsulation member covering the display element layer, it may have a smaller Figure 7a The thickness of the display panel is described in detail.

[0147] Figure 8 Schematically illustrates a plan view of a display device according to an embodiment of the present invention. Figure 8 The figure shows a situation where seven gate lines and seven data lines are respectively arranged in the second region 2A. However, in practice, the number of gate lines and data lines may not be limited thereto, for example, more than seven or less than seven.

[0148] Reference Figure 8 According to one embodiment, a display device 1 includes: a substrate 100 including a first area 1A and a second area 2A including a transmissive portion TA; a plurality of main pixel groups Pgm arranged on the first area 1A; a plurality of auxiliary pixel groups Pga arranged on the second area 2A; a plurality of first signal lines electrically connecting the plurality of main pixel groups Pgm and the plurality of auxiliary pixel groups Pga and extending along a first direction (x direction); and a plurality of second signal lines electrically connecting the plurality of main pixel groups Pgm and the plurality of auxiliary pixel groups Pga and extending along a second direction (y direction) intersecting the first direction (x direction).

[0149] As one embodiment, the plurality of first signal lines extending along the first direction (x direction) may be gate lines GL1-GL16, and the plurality of second signal lines extending along the second direction (y direction) may be data lines DL1-DL15. Furthermore, the primary pixel group Pgm may include the aforementioned primary pixels Pm, and the auxiliary pixel group Pga may include the aforementioned auxiliary pixels Pa. For example, the gate lines GL1-GL16 extending along the first direction (x direction) may transmit scan signals, pre-scan signals, and light-emitting control signals to the primary pixels Pm and the auxiliary pixels Pa, and the data lines DL1-DL15 may transmit data signals, drive voltages, and the like to the primary pixels Pm and the auxiliary pixels Pa.

[0150] In an existing display device, gate lines extending in a first direction and data lines extending in a second direction are arranged at predetermined intervals on a second area provided with a transmissive portion to form a grid pattern. The grid pattern formed by the gate lines and the data lines functions as a diffraction grating, so that light emitted from a component (e.g., an optical element) passes through the diffraction grating and is diffracted, resulting in a problem of outputting a blurred image.

[0151] The present invention is used to solve the above-mentioned problem. In a second area equipped with a transmissive portion, the intervals between gate lines extending along a first direction and the intervals between data lines extending along a second direction are gradually reduced from the center of the second area toward the periphery of the second area, thereby preventing the gate lines and the data lines from acting as a diffraction grating, thereby providing a display device with improved product reliability.

[0152] The distances between the gate lines GL2, GL4, GL6, GL8, GL10, GL12, and GL14 extending along the first direction (x-direction) in the second region 2A may gradually decrease from the center of the second region 2A toward the periphery of the second region 2A. More specifically, along the second direction (y-direction), the distances between the most adjacent gate lines gradually decrease from the eighth gate line GL8 arranged in the center of the second region 2A toward the second gate line GL2 and the fourteenth gate line GL14 arranged at the periphery of the second region 2A. As one embodiment, along the second direction (y-direction), a first distance d1 between the eighth gate line GL8 and the tenth gate line GL10 arranged in the center of the second region 2A may be greater than a second distance d2 between the tenth gate line GL10 and the twelfth gate line GL12.

[0153] The distances between the data lines DL2, DL4, DL6, DL8, DL10, DL12, and DL14 extending along the second direction (y-direction) in the second region 2A may gradually decrease from the center of the second region 2A toward the periphery of the second region 2A. More specifically, along the first direction (x-direction), the distances between the most adjacent data lines gradually decrease from the eighth data line DL8 arranged in the center of the second region 2A toward the second data line DL2 and the fourteenth data line DL14 arranged at the periphery of the second region 2A. As one embodiment, the third distance d3 between the eighth data line DL8 and the tenth data line DL10 arranged in the center of the second region 2A along the first direction (x-direction) may be greater than the fourth distance d4 between the tenth data line DL10 and the twelfth data line DL12.

[0154] The distance between the plurality of first signal lines arranged in the first region 1A may be less than or equal to the distance between the plurality of first signal lines arranged in the second region 2A. More specifically, the distance between the gate lines GL1-GL16 extending along the first direction (x-direction) in the first region 1A may be less than or equal to the distance between the gate lines GL2, GL4, GL6, GL8, GL10, GL12, and GL14 extending along the first direction (x-direction) in the second region 2A. As one embodiment, a fifth distance d5 between the fifteenth gate line GL15 and the sixteenth gate line GL16 arranged in the first region 1A may be less than the first distance d1 between the eighth gate line GL8 and the tenth gate line GL10 arranged in the center portion of the second region 2A, and less than the second distance d2 between the tenth gate line GL10 and the twelfth gate line GL12.

[0155] The distance between the gate lines arranged in the second area 2A of the display device 1 can gradually decrease from the center of the second area 2A toward the periphery of the second area 2A, and the minimum distance between the gate lines arranged in the second area 2A can be the same as the distance between the gate lines arranged in the first area 1A. Therefore, the distance between the gate lines arranged in the second area 2A can gradually decrease from the center of the second area 2A toward the periphery of the second area 2A in a manner that converges with the distance between the gate lines arranged in the first area 1A.

[0156] The distances between the plurality of second signal lines arranged in the first region 1A may be less than or equal to the distances between the plurality of second signal lines arranged in the second region 2A. More specifically, the distances between the data lines DL1-DL15 extending along the second direction (y-direction) in the first region 1A may be less than or equal to the distances between the data lines DL2, DL4, DL6, DL8, DL10, DL12, and DL14 extending along the second direction (y-direction) in the second region 2A. As one embodiment, a sixth distance d6 between the twelfth data line DL12 and the thirteenth data line DL13 arranged in the first region 1A may be less than a third distance d3 between the eighth data line DL8 and the tenth data line DL10 arranged in the center portion of the second region 2A, and less than a fourth distance d4 between the tenth data line DL10 and the twelfth data line DL12.

[0157] The distance between the data lines arranged in the second area 2A of the display device 1 can gradually decrease from the center of the second area 2A to the periphery of the second area 2A, and the minimum distance between the data lines arranged in the second area 2A can be the same as the distance between the data lines arranged in the first area 1A. Therefore, the distance between the data lines arranged in the second area 2A can gradually decrease from the center of the second area 2A to the periphery of the second area 2A in a manner that converges to the distance between the data lines arranged in the first area 1A.

[0158] As one embodiment, the distance between the gate lines and the distance between the data lines arranged in the first region 1A may be 50 μm to 70 μm, and the distance between the gate lines and the data lines arranged in the center of the second region 2A and their adjacent gate lines and data lines may be 500 μm to 700 μm. The distance between the gate lines and the distance between the data lines arranged in the second region 2A may gradually decrease from the center of the second region 2A toward the periphery of the second region 2A, and the distance between the gate lines and the data lines arranged in the periphery of the second region 2A and their adjacent gate lines and data lines may be 50 μm to 70 μm.

[0159] The plurality of primary pixel groups Pgm arranged in the first area 1A and the plurality of auxiliary pixel groups Pga arranged in the second area 2A can be electrically connected to a plurality of first signal lines extending along a first direction (x direction). Furthermore, the plurality of primary pixel groups Pgm arranged in the first area 1A and the plurality of auxiliary pixel groups Pga arranged in the second area 2A can be electrically connected to a plurality of second signal lines extending along a second direction (y direction).

[0160] The second region 2A is provided with the transmission portion TA, and thus the number of auxiliary pixel groups Pga that can be arranged per unit area may be smaller than the number of main pixel groups Pgm arranged per unit area in the first region 1A.

[0161] Since the distance between the gate lines GL2, GL4, GL6, GL8, GL10, GL12, and GL14 extending along the first direction (x direction) in the second area 2A can gradually decrease from the center of the second area 2A to the periphery of the second area 2A, the distance between the data lines DL2, DL4, DL6, DL8, DL10, DL12, and DL14 extending along the second direction (y direction) in the second area 2A can gradually decrease from the center of the second area 2A to the periphery of the second area 2A, and therefore the distance between the multiple auxiliary pixel groups Pga arranged along the first direction (x direction) and the second direction (y direction) in the second area 2A can gradually decrease from the center of the second area 2A to the periphery of the second area 2A. As one embodiment, when the auxiliary pixel group Pga arranged in the center portion of the second area 2A is referred to as the first auxiliary pixel group Pga1, the auxiliary pixel group Pga adjacent to the first auxiliary pixel group Pga1 in the first direction (x direction) is referred to as the second auxiliary pixel group Pga2, and the auxiliary pixel group Pga adjacent to the second auxiliary pixel group Pga2 in the first direction (x direction) is referred to as the third auxiliary pixel group Pga3, the seventh distance d7 between the first auxiliary pixel group Pga1 and the second auxiliary pixel group Pga2 may be greater than the eighth distance d8 between the second auxiliary pixel group Pga2 and the third auxiliary pixel group Pga3. Moreover, when the auxiliary pixel group Pga adjacent to the first auxiliary pixel group Pga1 arranged in the central portion of the second area 2A in the second direction (y direction) is referred to as the fourth auxiliary pixel group Pga4, and the auxiliary pixel group Pga adjacent to the fourth auxiliary pixel group Pga4 in the second direction (y direction) is referred to as the fifth auxiliary pixel group Pga5, the ninth distance d9 between the first auxiliary pixel group Pga1 and the fourth auxiliary pixel group Pga4 may be greater than the tenth distance d10 between the fourth auxiliary pixel group Pga4 and the fifth auxiliary pixel group Pga5.

[0162] The distance between the plurality of main pixel groups Pgm arranged along the first direction (x direction) may be less than or equal to the distance between the plurality of auxiliary pixel groups Pga arranged along the first direction (x direction). More specifically, when the main pixel group Pgm electrically connected to the fifteenth gate line GL15 and the second data line DL2 is referred to as the first main pixel group Pgm1, and the main pixel group Pgm adjacent to the first main pixel group Pgm1 in the first direction (x direction) is referred to as the second main pixel group Pgm2, an eleventh distance d11 between the first main pixel group Pgm1 and the second main pixel group Pgm2 may be less than or equal to a seventh distance d7 between the first auxiliary pixel group Pga1 and the second auxiliary pixel group Pga2, and an eighth distance d8 between the second auxiliary pixel group Pga2 and the third auxiliary pixel group Pga3.

[0163] The distance between the plurality of main pixel groups Pgm arranged along the second direction (y direction) may be less than or equal to the distance between the plurality of auxiliary pixel groups Pga arranged along the second direction (y direction). More specifically, when the main pixel group Pgm adjacent to the first main pixel group Pgm1 electrically connected to the fifteenth gate line GL15 and the second data line DL2 in the second direction (y direction) is referred to as the third main pixel group Pgm3, the twelfth distance d12 between the first main pixel group Pgm1 and the third main pixel group Pgm3 may be less than or equal to the ninth distance d9 between the first auxiliary pixel group Pga1 and the fourth auxiliary pixel group Pga4 and the tenth distance d10 between the fourth auxiliary pixel group Pga4 and the fifth auxiliary pixel group Pga5.

[0164] Figure 9a and Figure 9b is a plan view schematically illustrating a display device according to an embodiment of the present invention. More specifically, Figure 9a 1 is a diagram illustrating a situation in which at least one of the plurality of first signal lines extending in the first direction (x direction) is disconnected with the second region 2A interposed therebetween and connected by a connecting line meandering along an edge portion of the second region 2A. Figure 9b This is a diagram illustrating a situation where at least one of the plurality of second signal lines extending in the second direction (y direction) is disconnected by placing the second region 2A therebetween and connected by a connecting line meandering along the edge of the second region 2A. Figure 9a The figure shows a situation where three connecting lines meander along the lower edge of the second area 2A. However, in reality, the number of connecting lines meandering along the lower edge of the second area 2A can be more than three, and they can also meander along the upper edge of the second area 2A. In addition, for the convenience of illustration and explanation, Figure 9b The figure shows a situation where three connecting lines meander along the right edge of the second area 2A. However, in reality, the number of connecting lines meandering along the right edge of the second area 2A can be more than three, and they can meander along the left edge of the second area 2A.

[0165] To improve the transmittance of the second region 2A, fewer signal lines can be arranged in the second region 2A than in the first region 1A. That is, to improve the transmittance of the second region 2A, the number of signal lines that can be arranged per unit area in the second region 2A can be less than the number of signal lines arranged per unit area in the first region 1A.

[0166] To this end, at least one of the plurality of first signal lines may include a first signal line extending in the first direction (x direction) and being disconnected with the second region 2A interposed therebetween, and the disconnected first signal lines may be connected by a connecting line meandering along an edge portion of the second region 2A. More specifically, referring to Figure 9aThe gate lines GL9, GL11, and GL13 can extend along the first direction (x direction) and be disconnected with the second region 2A therebetween, and can be connected by connecting lines GL9-C, GL11-C, and GL13-C that meander along the edges of the second region 2A. The gate lines GL9, GL11, and GL13 and the connecting lines GL9-C, GL11-C, and GL13-C can be arranged on different layers and connected via contact holes CNT. Alternatively, the gate lines GL9, GL11, and GL13 and the connecting lines GL9-C, GL11-C, and GL13-C can be arranged on the same layer.

[0167] Furthermore, at least one of the plurality of second signal lines may include a second signal line extending in the second direction (y direction) and being disconnected with the second region 2A interposed therebetween, and the disconnected second signal lines may be connected by a connecting line meandering along an edge portion of the second region 2A. More specifically, referring to Figure 9b The data lines DL9, DL11, and DL13 can extend along the second direction (y-direction) and be disconnected with the second region 2A interposed therebetween. The data lines DL9-C, DL11-C, and DL13-C can be connected by meandering connection lines DL9-C, DL11-C, and DL13-C along the edges of the second region 2A. The data lines DL9, DL11, and DL13 and the connection lines DL9-C, DL11-C, and DL13-C can be arranged on different layers and connected via contact holes CNT. Alternatively, the data lines DL9, DL11, and DL13 and the connection lines DL9-C, DL11-C, and DL13-C can be arranged on the same layer.

[0168] Figure 10a and Figure 10b is a plan view schematically illustrating a display device according to an embodiment of the present invention. More specifically, Figure 10a It is magnified Figure 8 The floor plan of Section A, Figure 10b It is magnified Figure 8 Floor plan of Section B.

[0169] Reference Figure 10a Each of the plurality of auxiliary pixel groups Pga may include a first auxiliary pixel Pa1, a second auxiliary pixel Pa2, and a third auxiliary pixel Pa3 that emit light of different wavelengths, and each of the plurality of second signal lines may include a first conductive line CL1, a second conductive line CL2, and a third conductive line CL3. More specifically, the auxiliary pixel group Pga may include a first auxiliary pixel Pa1 that emits light of a red wavelength, a second auxiliary pixel Pa2 that emits light of a green wavelength, and a third auxiliary pixel Pa3 that emits light of a blue wavelength. The first conductive line CL1 may be electrically connected to the first auxiliary pixel Pa1, the second conductive line CL2 may be electrically connected to the second auxiliary pixel Pa2, and the third conductive line CL3 may be electrically connected to the third auxiliary pixel Pa3.

[0170] exist Figure 10a In the figure, one auxiliary pixel group Pga is shown to include three auxiliary pixels Pa1, Pa2, and Pa3 arranged in one column, but the present invention is not limited thereto. One auxiliary pixel group Pga may include four auxiliary pixels arranged in two columns, or eight auxiliary pixels arranged in four columns.

[0171] Reference Figure 10b Each of the plurality of primary pixel groups Pgm may include a first primary pixel Pm1, a second primary pixel Pm2, and a third primary pixel Pm3 that emit light of different wavelengths, and each of the plurality of second signal lines may include a first conductive line CL1, a second conductive line CL2, and a third conductive line CL3. More specifically, the primary pixel group Pgm may include a first primary pixel Pm1 that emits light of a red wavelength, a second primary pixel Pm2 that emits light of a green wavelength, and a third primary pixel Pm3 that emits light of a blue wavelength. The first conductive line CL1 may be electrically connected to the first primary pixel Pm1, the second conductive line CL2 may be electrically connected to the second primary pixel Pm2, and the third conductive line CL3 may be electrically connected to the third primary pixel Pm3.

[0172] exist Figure 10b In the figure, a primary pixel group Pgm is shown to include three primary pixels Pm1, Pm2, and Pm3 arranged in one column, but the present invention is not limited thereto. A primary pixel group Pgm may include four primary pixels arranged in two columns, or eight primary pixels arranged in four columns.

[0173] According to one embodiment of the present invention, in order to solve the following problem existing in an existing display device, the intervals between gate lines and data lines arranged in an area where components are arranged are gradually reduced from the center to the periphery, so that the gate lines and data lines can be prevented from acting as diffraction gratings, thereby providing a display device with improved product reliability, wherein the problem is that the gate wiring and data wiring regularly arranged in the area where components are arranged act as diffraction gratings, causing light emitted from the components to pass through the diffraction grating and be diffracted, thereby outputting a blurred image.

[0174] The present invention has been described with reference to the embodiments shown in the accompanying drawings. However, this is for illustrative purposes only. A person skilled in the art will readily appreciate that various modifications may be made to the embodiments and equivalent embodiments may be realized. Therefore, the true scope of protection of the present invention should be determined based on the technical concepts of the claims.

Claims

1. A display device comprising: The substrate includes a first region and a second region having a transmissive portion; a plurality of primary pixel groups arranged on the first area; a plurality of auxiliary pixel groups arranged on the second area; a plurality of first signal lines electrically connecting the plurality of main pixel groups and the plurality of auxiliary pixel groups and extending along a first direction; as well as a plurality of second signal lines electrically connecting the plurality of main pixel groups and the plurality of auxiliary pixel groups and extending along a second direction intersecting the first direction; Wherein, in the second area, the distances between the plurality of first signal lines all gradually decrease from the center of the second area to the periphery of the second area, In the second area, the distances between the plurality of second signal lines gradually decrease from the center of the second area to the periphery of the second area. The distances between the plurality of auxiliary pixel groups along the first direction all gradually decrease from the center of the second area to the periphery of the second area, The distances between the plurality of auxiliary pixel groups along the second direction all gradually decrease from the center of the second area to the periphery of the second area. The number of the first signal lines and the second signal lines arranged per unit area in the second region is less than the number of the first signal lines and the second signal lines arranged per unit area in the first region, The plurality of first signal lines are gate lines, and the plurality of second signal lines are data lines.

2. The display device according to claim 1, wherein A distance between the plurality of first signal lines arranged on the first region is smaller than or equal to a distance between the plurality of first signal lines arranged on the second region.

3. The display device according to claim 1, wherein A distance between the plurality of second signal lines arranged on the first region is smaller than or equal to a distance between the plurality of second signal lines arranged on the second region.

4. The display device according to claim 1, wherein A distance between the plurality of main pixel groups along the first direction is less than or equal to a distance between the plurality of auxiliary pixel groups along the first direction.

5. The display device according to claim 4, wherein A distance between the plurality of main pixel groups along the second direction is less than or equal to a distance between the plurality of auxiliary pixel groups along the second direction.

6. The display device according to any one of claims 1 to 5, wherein: Each of the plurality of auxiliary pixel groups includes a first auxiliary pixel, a second auxiliary pixel, and a third auxiliary pixel that emit light of different wavelengths.

7. The display device according to claim 6, wherein: Each of the plurality of primary pixel groups includes a first primary pixel, a second primary pixel, and a third primary pixel that emit light of different wavelengths.

8. The display device according to claim 7, wherein: Each of the plurality of second signal lines includes a first conductive line, a second conductive line, and a third conductive line.

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