Display device and multi-screen display device

Abstract

A display device and a multi-screen display device are disclosed. The display device includes: a display substrate including a plurality of sub-pixels, the plurality of sub-pixels being respectively arranged in a plurality of pixel areas defined by a plurality of data lines and a plurality of gate lines; a line substrate, the line substrate being bonded to the display substrate using a substrate bonding member and including a plurality of data wiring lines; and a side data connection member, the side data connection member being arranged on one side of each of the display substrate and the line substrate to connect the plurality of data lines to the plurality of gate lines in a one-to-one relationship.

Description

[0001] This application is a divisional application of the invention patent application with application number 201711146494.4 (filing date is November 17, 2017, invention name is "display device, multi-screen display device using the same and manufacturing method thereof"). Technical Field

[0002] The present disclosure relates to a display device, a multi-screen display device using the same, and a method of manufacturing the same. Background Art

[0003] The display device is being widely used as a display screen of a notebook computer, a tablet computer, a smart phone, a portable display device, and a portable information device, in addition to a display screen of a monitor of a television (TV).

[0004] Liquid crystal display (LCD) devices and organic light emitting display devices display images by using thin film transistors (TFTs) as switching elements. Since LCD devices cannot emit light by themselves, LCD devices display images by using light emitted from a backlight unit disposed under a liquid crystal display panel. Since the LCD device includes a backlight unit, the design of the LCD device is not limited, and the brightness and response time are reduced. Since the organic light emitting display device includes organic materials, the organic light emitting display device is easily affected by water, resulting in deterioration of reliability and lifespan.

[0005] Recently, research and development of light emitting diode display devices including light emitting devices are being conducted. The light emitting diode display devices have high image quality and high reliability, and thus are attracting attention as next generation display devices.

[0006] The light emitting diode display device of the related art is manufactured by transferring the light emitting device to a thin film transistor (TFT) array substrate, and due to the transfer process time consumed by the transfer process of the light emitting device, the current transfer technology is more conducive to display devices with relatively large sizes than to panels with relatively small sizes.

[0007] However, the related art light emitting diode display device includes a pad portion connected to a pixel driving line of a display substrate and a device for covering a display driving circuit unit attached to the pad portion, and for this reason, a bezel area is increased due to the device.

[0008] In addition, in the case where the light-emitting diode display device of the related art is manufactured in a large size, the number of pixels increases, and for this reason, the transfer error rate of the light-emitting device increases, resulting in a decrease in yield. In order to solve this problem, research and development are being conducted on a multi-screen device, which implements a large-size screen and is implemented by connecting two or more light-emitting diode display devices with relatively small sizes. However, in the multi-screen device, due to the border area of ​​each of the two or more light-emitting diode display devices, there is a gap (or boundary portion) between the display devices connected to each other. When an image is displayed on the entire screen, the boundary portion causes the entire screen to have a discontinuous feeling, resulting in a decrease in the user's immersion when watching. Summary of the invention

[0009] Accordingly, the present disclosure is directed to a display device and a multi-screen display device using the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0010] An aspect of the present disclosure is directed to providing a display device including a minimum bezel area and a multi-screen display device using the display device.

[0011] Another aspect of the present disclosure is directed to providing a multi-screen display device in which a boundary portion between adjacent display devices is minimized.

[0012] Additional advantages and features of the present disclosure will be partially described in the following description, and will become partially apparent to those skilled in the art after reading the following, or may be learned through practice of the present invention. The objects and other advantages of the present disclosure may be realized and obtained through the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0013] To achieve these and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device is provided, comprising: a display substrate comprising a plurality of sub-pixels, the plurality of sub-pixels being respectively arranged in a plurality of pixel areas defined by a plurality of data lines and a plurality of gate lines; a line substrate, the line substrate being bonded to the display substrate using a substrate bonding member and comprising a plurality of data wiring lines; and a side data connection member, the side data connection member being arranged on one side of each of the display substrate and the line substrate to connect the plurality of data lines to the plurality of gate lines in a one-to-one relationship.

[0014] The size of the wire substrate may be equal to or smaller than that of the display substrate, and the one side of the wire substrate may be disposed on the same line as the one side of the display substrate with respect to a thickness direction of the display substrate.

[0015] The display device may also include: a side gating connection member, which is connected to the multiple gating lines, and the multiple gating lines are arranged on the other side of each of the display substrate and the line substrate in a one-to-one relationship, wherein the line substrate may also include a plurality of gating wiring lines, and the plurality of gating wiring lines are connected to the side gating connection member in a one-to-one relationship.

[0016] The display substrate may include: a first display area and a second display area surrounding the first display area; a plurality of first unit pixels, the plurality of first unit pixels are arranged in the first display area and each include a plurality of sub-pixels, the plurality of sub-pixels each include a light-emitting device; and a plurality of second unit pixels, the plurality of second unit pixels are arranged in the second display area, overlap with an edge of the display substrate, the plurality of second unit pixels each include a plurality of sub-pixels and have a size smaller than that of each of the plurality of first unit pixels.

[0017] The plurality of first unit pixels may be arranged at a reference pixel pitch, and a distance between a central portion of each of the plurality of second unit pixels and an outer surface of the display substrate may be half of the reference pixel pitch or less.

[0018] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0020] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0021] Figure 2 is an example Figure 1 Schematic diagram of a wire substrate illustrated in FIG.

[0022] Figure 3 yes Figure 1 A circuit diagram of a unit pixel as illustrated in FIG.

[0023] Figure 4 is an example Figure 1 A cross-sectional view of an edge of the display device illustrated in FIG.

[0024] Figure 5 is an example Figure 1 Schematic diagram of a wire substrate illustrated in FIG.

[0025] Figure 6is a diagram for describing a display device according to an embodiment of the present disclosure;

[0026] Figure 7 Is used to describe Figure 1 and Figure 6 A diagram of a side data connection member of a display device illustrated in FIG.

[0027] Fig. 8A , Figure 8B and Figure 8C It is used to describe manufacturing Figure 7 A diagram of a method of connecting a side data member as illustrated in FIG.

[0028] Fig. 9 is a diagram for describing a display substrate of a display device according to an embodiment of the present disclosure;

[0029] Fig.10 Is used to describe Fig. 9 A cross-sectional view of the structure of a sub-pixel illustrated in FIG.

[0030] Fig.11 Is used to describe Fig.10 A cross-sectional view of the structure of the light emitting device illustrated in FIG.

[0031] Fig.12 is a plan view for describing a concave portion provided in a unit pixel according to an embodiment of the present disclosure;

[0032] Fig.13 It is along Fig.12 A cross-sectional view taken along line II' illustrated in FIG.

[0033] Fig.14 is a diagram for describing a modified embodiment of a recess according to an embodiment of the present disclosure;

[0034] Fig.15 is a diagram for describing a modified embodiment of a recess according to an embodiment of the present disclosure;

[0035] Fig.16 It is along Fig.12 Another cross-sectional view taken along line II' illustrated in FIG.

[0036] Fig.17 It is along Fig.12 Another cross-sectional view taken along line II' illustrated in FIG.

[0037] Fig.18 is a diagram for describing a multi-screen display device according to an embodiment of the present disclosure;

[0038] Fig.19 It is along Fig.18 A cross-sectional view taken along line II-II' illustrated in FIG.

[0039] Fig. 20A and Fig. 20B 1 is a diagram illustrating respective images displayed by a related art multi-screen display device and a multi-screen display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Now, reference will be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0041] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be understood as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0042] The shapes, sizes, ratios, angles, and quantities disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when it is determined that a detailed description of the related known technology unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted.

[0043] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may be added unless “only” is used. Terms in the singular form may include plural forms unless otherwise indicated.

[0044] When understanding the elements, the elements are construed as including the error range although not explicitly described.

[0045] When describing a positional relationship, for example, when the positional relationship between two components is described as "on", "above", "below", and "beside", unless "just" or "exactly" is used, one or more other components may be set between the two components.

[0046] When describing a time relationship, for example, when a time sequence is described as "after," "afterwards," "next," and "before," discontinuity may be included unless "directly" or "exactly" is used.

[0047] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0048] The first horizontal axis direction, the second horizontal axis direction, and the vertical axis direction should not be understood as merely a geometric relationship in which the relationship therebetween is perpendicular, and may represent a wider directivity within the scope of the functional operation of the elements of the present disclosure.

[0049] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of a first item, a second item, and a third item" means all combinations of items listed with two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0050] The features of the various embodiments of the present disclosure may be partially or entirely connected or combined with each other, and may interact with each other in various ways and be driven by technology, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0051] Hereinafter, exemplary embodiments of a display device and a multi-screen display device using the same according to the present disclosure will be described in detail with reference to the accompanying drawings. In the specification, reference numerals are added to the elements in each figure, and it should be noted that, where possible, detailed reference numerals that have been used to represent similar elements in other figures are used for the elements. In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted.

[0052] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 is an example Figure 1 Schematic diagram of a wire substrate illustrated in FIG. Figure 3 yes Figure 1 A circuit diagram of a unit pixel is illustrated in FIG. Figure 4 is an example Figure 1 A cross-sectional view of one edge of a display device illustrated in FIG.

[0053] Reference Figures 1 to 4 , the display device according to the present embodiment may include a display substrate 10 , a line substrate 20 , and a side data connection member 30 .

[0054] The display substrate 10 may be defined as a thin film transistor (TFT) array substrate. The display substrate 10 according to an embodiment may include a first base substrate 100, a plurality of pixel driving lines, and a plurality of sub-pixels SP1 to SP3.

[0055] The first bottom substrate 100 may be formed of a glass or plastic material, and for example, may be formed of a glass material. The first bottom substrate 100 according to an embodiment may include a display area (or active area) AA and a non-display area (or inactive area) IA. The display area AA may be defined as a central area except for the edge of the first bottom substrate 100. The non-display area IA may be defined as surrounding the display area AA and may overlap with the edge of the first bottom substrate 100. The non-display area IA may have a relatively very narrow width and may be defined as a frame area.

[0056] The pixel driving line may be disposed on the front surface 100a of the first base substrate 100 and may supply a signal necessary for each of the plurality of sub-pixels SP1 to SP3. The pixel driving line according to an embodiment may include a plurality of data lines DL, a plurality of gate lines GL, a plurality of driving power lines DPL, and a plurality of common power lines CPL.

[0057] The plurality of data lines DL may be disposed on the front surface 100a of the first base substrate 100, may be arranged at intervals from each other along a first horizontal axis direction X, and may extend in length along a second horizontal axis direction Y. Here, the first horizontal axis direction X may be parallel to a first longitudinal direction X of the display device, for example, a long side length direction or a transverse direction of the display device, and the second horizontal axis direction Y may be parallel to a second longitudinal direction Y of the display device, for example, a short side length direction or a longitudinal direction of the display device.

[0058] A plurality of gate lines GL may be disposed on the front surface 100 a of the first base substrate 100 , cross the plurality of data lines DL, may extend in length along a first horizontal axis direction X, and may be arranged along a second horizontal axis direction Y spaced apart from each other by a certain interval.

[0059] The plurality of driving power lines DPL are disposed on the first base substrate 100 in parallel with the plurality of data lines DL and may be formed together with the plurality of data lines DL. Each of the plurality of driving power lines DPL may supply pixel driving power supplied from the outside to adjacent sub-pixels SP1 to SP3.

[0060] The plurality of common power lines CPL are disposed on the first base substrate 100 in parallel with the plurality of gate lines GL and may be formed together with the plurality of gate lines GL. Each of the plurality of common power lines CPL may supply common power supplied from the outside to adjacent sub-pixels SP1 to SP3.

[0061] The plurality of sub-pixels SP1 to SP3 may be respectively disposed in a plurality of sub-pixel regions defined by intersections of the gate lines GL and the data lines DL. Each of the plurality of sub-pixels SP1 to SP3 may be defined as a region corresponding to a minimum unit from which light is actually emitted.

[0062] At least three adjacent sub-pixels SP1 to SP3 may constitute one unit pixel UP for displaying colors. For example, one unit pixel UP may include red, green, and blue sub-pixels SP1, SP2, and SP3 adjacent to each other along the first horizontal axis direction X, and may further include a white sub-pixel for enhancing brightness.

[0063] Alternatively, each of the driving power lines DPL may be provided in a corresponding unit pixel among the plurality of unit pixels UP. In this case, at least three adjacent sub-pixels SP1 to SP3 constituting each of the unit pixels UP may share one driving power line DPL. Therefore, the number of driving power lines for driving each of the sub-pixels SP1 to SP3 is reduced, and the aperture ratio of each of the unit pixels UP is increased or the size of each of the unit pixels UP is reduced in proportion to the number of reduced driving power lines.

[0064] The plurality of sub-pixels SP1 to SP3 according to the embodiment may each include a pixel circuit PC and a light emitting device 150 .

[0065] The pixel circuit PC may be disposed in a circuit area defined in each sub-pixel SP, and may be connected to the gate line GL, the data line DL, and the driving power line DPL adjacent thereto. The pixel circuit PC may control the current flowing into the light emitting device 150 according to the data signal supplied through the data line DL in response to the scan pulse supplied through the gate line GL based on the pixel driving power supplied through the driving power line DPL. The pixel circuit PC according to the embodiment may include a switching TFT T1, a driving TFT T2, and a capacitor Cst.

[0066] The switching TFT T1 may include a gate electrode connected to the gate line GL, a first electrode connected to the data line DL, and a second electrode connected to the gate electrode N1 of the driving TFT T2. Here, each of the first electrode and the second electrode of the switching TFT T1 may be a source electrode or a drain electrode according to a current direction. The switching TFT T1 may be turned on according to a scan pulse supplied through the gate line GL, and may supply a data signal supplied through the data line DL to the driving TFT T2.

[0067] The driving TFT T2 may be turned on by the voltage supplied through the switching TFT T1 and / or the voltage of the capacitor Cst to control the amount of current flowing from the driving power line DPL to the light emitting device 150. To this end, the driving TFT T2 according to the embodiment may include a gate electrode connected to the second electrode N1 of the switching TFT T1, a drain electrode connected to the driving power line DPL, and a source electrode connected to the light emitting device 150. The driving TFT T2 may control a data current flowing from the driving power line DPL to the light emitting device 150 according to a data signal supplied through the switching TFT T1, thereby allowing the light emitting device 150 to emit light having a brightness proportional to the data signal.

[0068] The capacitor Cst may be disposed in an overlapping region between the gate electrode N1 and the source electrode of the driving TFT T2 , may store a voltage corresponding to a data signal supplied to the gate electrode of the driving TFT T2 , and may turn on the driving TFT T2 with the stored voltage.

[0069] Optionally, the pixel circuit PC may further include at least one compensation TFT for compensating for the threshold voltage shift of the driving TFT T2, and may further include at least one auxiliary capacitor. Compensation power such as an initialization voltage may be additionally supplied to the pixel circuit PC based on the number of TFTs and auxiliary capacitors. Therefore, the pixel circuit PC according to the present embodiment can drive the light emitting device 150 by the same current driving method for each sub-pixel of the organic light emitting display device, and therefore, may be replaced by a pixel circuit of an organic light emitting display device known to those skilled in the art.

[0070] The light emitting device 150 may be disposed in each of the plurality of sub-pixels SP1 to SP3. The light emitting device 150 may be electrically connected to the pixel circuit PC of the corresponding sub-pixel SP and the corresponding common power line CPL, and thus, light may be emitted by a current flowing from the pixel circuit PC (i.e., the driving TFT T2) to the common power line CPL. The light emitting device 150 according to the embodiment may be a light emitting device or a light emitting diode chip that emits one of red light, green light, blue light, and white light. For example, the light emitting device 150 may be a light emitting device or a micro light emitting diode chip. Here, the micro light emitting diode chip may have a scale of 1 μm to 100 μm, but is not limited thereto. In other embodiments, the size of the light emitting diode chip may be smaller than the size of the emission area in the corresponding sub-pixel area except for the circuit area occupied by the pixel circuit PC.

[0071] The wire substrate 20 may include a plurality of wiring lines connected to the pixel driving lines provided on the display substrate 10 in a one-to-one relationship, and may be bonded to the display substrate 10. That is, the wire substrate 20 may be bonded to the rear surface of the display substrate 10 using a substrate bonding member 15. The wire substrate 20 may transmit a signal to the pixel driving line and may increase the rigidity of the display substrate 10. Here, the substrate bonding member 15 may include an optically transparent adhesive (OCA) or an optically transparent resin (OCR).

[0072] The line substrate 20 according to the embodiment may include a second base substrate 200 and a plurality of data wiring lines 201 .

[0073] The second base substrate 200 may be formed of a glass material, a plastic material, and / or the like. For example, the second base substrate 200 may be formed of the same material as the first base substrate 100, or may be formed of tempered glass. Here, the tempered glass may include quartz glass and diamond glass or one of the laminated ones.

[0074] The second base substrate 200 according to the embodiment may have the same size as that of the display substrate 10. In this case, one side 200c of the second base substrate 200 may be disposed on the same vertical line VL as one side 100c of the display substrate 10 with respect to a vertical axis direction Z parallel to the thickness direction of the display substrate 10, but may extend slightly outward relative to the vertical line VL within an alignment process error, or may be disposed more inward than the vertical line VL. The front surface 200a of the second base substrate 200 may be bonded to the display substrate 100 (i.e., the entire rear surface 100b of the first base substrate 100) using a substrate bonding member 15.

[0075] The plurality of data wiring lines 201 may be disposed on the rear surface 200b of the second base substrate 200 in parallel with the plurality of data lines DL disposed on the display substrate 10. In this case, one edge of each of the plurality of data wiring lines 201 may overlap one edge of a corresponding data line among the plurality of data lines DL disposed on the display substrate 10 in a one-to-one relationship.

[0076] Each of the plurality of data wiring lines 201 according to the embodiment may have a relatively wider line width than the line width of each of the plurality of data lines DL, so that the line resistance is reduced. That is, unlike the display substrate 10, the pixel circuit including the TFT and / or the like is not disposed on the second bottom substrate 200, and the plurality of lines for supplying signals to the pixel driving lines may be disposed on the second bottom substrate 200, thereby providing a relatively large spare space in the region where the data wiring lines are disposed. Therefore, in the present embodiment, by utilizing the spare space of the second bottom substrate 200 to increase the line width of each of the plurality of data wiring lines, the voltage drop (IR drop) of the signal applied to each of the plurality of data wiring lines due to the line resistance is minimized.

[0077] The line substrate 20 according to the embodiment may further include at least one first pad portion PP1 and at least one second pad portion PP2 .

[0078] The at least one first pad portion PP1 may include a plurality of data pads that are disposed on the wiring substrate 20 and are respectively connected to the plurality of data wiring lines 201 in a one-to-one relationship. That is, the at least one first pad portion PP1 may be connected to a corresponding data wiring line among the plurality of data wiring lines 201, and may be disposed at an end of the corresponding data wiring line among the plurality of data wiring lines 201. Therefore, one end of each of the plurality of data wiring lines 201 may be connected to the other end of a corresponding first side wiring pattern among the plurality of first side wiring patterns 31 in a one-to-one relationship, and the other end of each of the plurality of data wiring lines 201 may be connected to a corresponding data pad among the plurality of data pads in a one-to-one relationship.

[0079] At least one second pad portion PP2 may include a plurality of gate pads that are disposed on the wiring substrate 20 and are respectively connected to the plurality of gate wiring lines 203 in a one-to-one relationship. That is, at least one second pad portion PP2 may be connected to a corresponding gate wiring line among the plurality of gate wiring lines 203, and may be disposed at an end of the corresponding gate wiring line among the plurality of gate wiring lines 203. Therefore, one end of each of the plurality of gate wiring lines 203 may be connected to the other end of a corresponding second side wiring pattern among the plurality of second side wiring patterns 41 in a one-to-one relationship, and the other end of each of the plurality of gate wiring lines 203 may be connected to a corresponding gate pad among the plurality of gate pads in a one-to-one relationship.

[0080] The side data connection member 30 may be disposed on one side 100 c of the display substrate 10 and one side 200 c of the line substrate 20 , and may connect the plurality of data lines DL to the plurality of data wiring lines 201 in a one-to-one relationship.

[0081] The side data connection member 30 according to the embodiment may include a plurality of first side wiring patterns 31. Each of the plurality of first side wiring patterns 31 may be directly disposed on one side 100c of the display substrate 10 and one side 200c of the line substrate 20, and may connect the plurality of data lines DL to the plurality of data wiring lines 201 in a one-to-one relationship. Each of the plurality of first side wiring patterns 31 may be disposed to surround the one side 100c of the display substrate 10 and one side 200c of the line substrate 20, and may be connected between the corresponding data line DL and the corresponding data wiring line 201. In this case, one side of each of the plurality of first side wiring patterns 31 may be electrically connected to an end of the corresponding data line DL, and the other side may be electrically connected to an end of the corresponding data wiring line 201. Each of the plurality of first side wiring patterns 31 may be disposed by a printing process using a conductive paste.

[0082] The side data connection member 30 according to the embodiment may include a data flexible film and a plurality of first side wiring patterns 31 .

[0083] The data flexible film may be disposed to surround one side 100 c of the display substrate 10 and one side 200 c of the wire substrate 20 .

[0084] A plurality of first side wiring patterns 31 may be disposed on the data flexible film in parallel with the plurality of data lines DL disposed on the display substrate 10. Portions other than two edges of each of the first side wiring patterns 31 may be covered by a passivation layer covering the data flexible film. Therefore, one side of each of the plurality of first side wiring patterns 31 exposed to one edge of the data flexible film may be electrically connected to an end of the corresponding data line DL, and the other side of each of the plurality of first side wiring patterns 31 exposed to the other edge of the data flexible film may be electrically connected to an end of the corresponding data wiring line 201. The side data connection member 30 using the data flexible film as a bottom may be a flexible printed circuit cable.

[0085] The corner between the front surface 100a and the side of the first bottom substrate 100 may be chamfered to have a certain angle or length, or may be rounded to have a certain curvature. That is, the corner between the front surface 100a and the side of the first bottom substrate 100 may be chamfered or rounded to prevent the side data connection member 30 provided in the corner between the front surface 100a and the side of the first bottom substrate 100 from being disconnected.

[0086] The display device according to the present embodiment may further include a plurality of gate wiring lines 203 disposed on the line substrate 20 .

[0087] The plurality of gate wiring lines 203 may be disposed on the rear surface 200b of the second base substrate 200 in parallel with the plurality of gate lines GL disposed on the display substrate 10. In this case, one edge of each of the plurality of gate wiring lines 203 may overlap one edge of a corresponding gate line among the plurality of gate lines GL disposed on the display substrate 10 in a one-to-one relationship.

[0088] Each of the plurality of gate wiring lines 203 according to the embodiment may have a relatively wider line width than the line width of each of the plurality of gate lines GL, so that the line resistance is reduced. That is, in the second base substrate 200, a relatively large spare space is provided in the region in which the gate wiring line is disposed. Therefore, in the present embodiment, by increasing the line width of each of the plurality of gate wiring lines by utilizing the spare space of the second base substrate 200, the voltage drop (IR drop) of the signal applied to each of the plurality of gate wiring lines due to the line resistance is minimized.

[0089] The display device according to the present embodiment may further include a side gate connection member 40 .

[0090] The side gate connection member 40 may be disposed on the other side 100 d of the display substrate 10 and the other side 200 d of the line substrate 20 , and may connect the plurality of gate lines GL to the plurality of data wiring lines 203 in a one-to-one relationship.

[0091] The side gate connection member 40 according to the embodiment may include a plurality of second side wiring patterns 41. Each of the plurality of second side wiring patterns 41 may be directly disposed on the other side 100d of the display substrate 10 and the other side 200c of the line substrate 20, and may connect the plurality of gate lines GL to the plurality of gate wiring lines 203 in a one-to-one relationship. Each of the plurality of second side wiring patterns 41 may be disposed to surround the other side 100d of the display substrate 10 and the other side 200d of the line substrate 20, and may be connected between the corresponding gate line GL and the corresponding gate wiring line 203. In this case, one side of each of the plurality of second side wiring patterns 41 may be electrically connected to an end of the corresponding gate line GL, and the other side may be electrically connected to an end of the corresponding gate wiring line 203. Each of the plurality of second side wiring patterns 41 may be disposed by performing a printing process using a conductive paste.

[0092] The side gate connection member 40 according to the embodiment may be manufactured as a flexible printed circuit based on a flexible film and may be disposed to surround the other side 100d of the display substrate 10 and the other side 200d of the wire substrate 20. For example, the side gate connection member 40 may include a gate flexible film and a plurality of second side wiring patterns 41.

[0093] The gate flexible film may be disposed to surround the other side 100 d of the display substrate 10 and the other side 200 d of the wire substrate 20 .

[0094] A plurality of second side wiring patterns 41 may be disposed on the gate flexible film in parallel with a plurality of gate lines GL disposed on the display substrate 10. Portions other than two edges of each of the second side wiring patterns 41 may be covered by a passivation layer covering the gate flexible film. Therefore, one side of each of the plurality of second side wiring patterns 41 exposed to one edge of the gate flexible film may be electrically connected to an end of the corresponding gate line GL, and the other side of each of the plurality of second side wiring patterns 41 exposed to the other edge of the gate flexible film may be electrically connected to an end of the corresponding gate wiring line 203.

[0095] The corner between the rear surface 200b and the side of the second bottom substrate 200 may be chamfered to have a certain angle or length, or may be rounded to have a certain curvature. That is, the corner between the rear surface 200b and the side of the second bottom substrate 200 may be chamfered or rounded to prevent the side gating connection member 40 provided in the corner between the rear surface 200b and the side of the second bottom substrate 200 from being disconnected.

[0096] The display device according to the present embodiment may further include a side sealing member 50 .

[0097] The side sealing member 50 may be provided to cover the outer surface of each of the display substrate 10 and the line substrate 20 bonded to each other. The side sealing member 50 may cover the side data connection member 30 disposed on one side 100c of the display substrate 10 and one side 200c of the line substrate 20 and the side gate connection member 40 disposed on the other side 100d of the display substrate 10 and the other side 200d of the line substrate 20, thereby electrically insulating the side data connection member 30 from the side gate connection member 40 and protecting the side data connection member 30 from the side gate connection member 40 from external impact.

[0098] The display device according to the present embodiment may include a data driving circuit 60 , a gate driving circuit 70 , a control board 80 , and a timing controller 90 .

[0099] The data driving circuit 60 may supply a corresponding data voltage to each of a plurality of data lines DL disposed on the display substrate 10. The data driving circuit 60 according to an embodiment may include a plurality of data flexible circuit films 61 and a plurality of data driving integrated circuits (ICs) 63.

[0100] The plurality of data flexible circuit films 61 may be respectively attached to the plurality of first pad parts PP1 provided on the second base substrate 200 of the line substrate 20 in a one-to-one relationship through a film attaching process.

[0101] Each of the plurality of data driver ICs 63 may be independently mounted on a corresponding data flexible circuit film among the plurality of data flexible circuit films 61. The data driver IC 63 may receive sub-pixel data and a data control signal supplied from the timing controller 90, convert the sub-pixel data into an analog data voltage on a sub-pixel basis according to the data control signal, and supply the analog data voltage to the data lines DL, respectively.

[0102] Alternatively, the plurality of data driver ICs 63 may be directly mounted on the line substrate 20 (i.e., the rear surface 200d of the second base substrate 200) and respectively connected to the plurality of first pad portions PP1 in a one-to-one relationship without being mounted on the data flexible circuit film 61. Here, the plurality of data driver ICs 63 may be mounted on the second base substrate 200 through a chip mounting process based on a chip on glass (COG) type. In this case, the data flexible circuit film 61 may be removed, and thus, the configuration of the data driver IC 60 is simplified.

[0103] The gate driving circuit 70 may supply a corresponding scan pulse to each of a plurality of gate lines GL disposed on the display substrate 10. The gate driving circuit 70 according to an embodiment may include a plurality of gate flexible circuit films 71 and a plurality of gate driving ICs 73.

[0104] The plurality of gate flexible circuit films 71 may be respectively attached to the plurality of second pad parts PP2 provided on the second base substrate 200 of the line substrate 20 in a one-to-one relationship through a film attaching process.

[0105] Each of the plurality of gate driving ICs 73 may be independently mounted on a corresponding gate flexible circuit film among the plurality of gate flexible circuit films 71. Each of the gate driving ICs 73 may generate a scan pulse based on a gate control signal supplied from the timing controller 90, and may supply the generated scan pulse to a corresponding gate line GL corresponding to a predetermined order.

[0106] Alternatively, the plurality of gate driver ICs 73 may be directly mounted on the line substrate 20 (i.e., the rear surface 200d of the second bottom substrate 200) and respectively connected to the plurality of second pad portions PP2 in a one-to-one relationship without being mounted on the gate flexible circuit film 71. Here, the plurality of gate driver ICs 73 may be mounted on the second bottom substrate 200 through a chip mounting process based on a COG type. In this case, the gate flexible circuit film 71 may be removed, and thus, the configuration of the gate driver circuit 70 is simplified.

[0107] like Figure 5As shown in , the gate driving circuit 70 according to the embodiment may be manufactured as an IC type, respectively, directly disposed on the rear surface 200d of the second base substrate 200 by a TFT manufacturing process without being mounted on the second base substrate 200, and connected to a plurality of gate wiring lines 203 in a one-to-one relationship. In this case, the gate driving circuit 70 may be configured with a shift register including a plurality of stages that output scan pulses to the gate wiring lines 203 in a predetermined order using a gate control signal (i.e., a gate start signal and a plurality of gate shift clocks) supplied from a timing controller.

[0108] Refer to Figures 1 to 4 , the control board 80 may be connected to the plurality of data flexible circuit films 61 and the plurality of gate flexible circuit films 71. For example, the control board 80 may be electrically connected to the plurality of data flexible circuit films 61 through a plurality of first signal transmission cables STC1, and may be electrically connected to the plurality of gate flexible circuit films 71 through a plurality of second signal transmission cables STC2. The control board 80 may support the timing controller 90 and may transmit signals and power between elements of the display driving circuit.

[0109] The timing controller 90 may be mounted on the control board 80 and may receive a timing synchronization signal and image data supplied from the display driving system through a user connector provided on the control board 80. The timing controller 90 may arrange the image data according to the sub-pixel arrangement structure of the display area AA based on the timing synchronization signal to generate sub-pixel data, and may supply the generated sub-pixel data to the corresponding data driver IC 63. In addition, the timing controller 90 may generate a data control signal and a gate control signal based on the timing synchronization signal, and may control the driving timing of each of the data driver IC 63 and the gate driver IC 73.

[0110] Alternatively, a plurality of data driver ICs 63, a plurality of gate driver ICs 73, and a timing controller 90 may be integrated into one integrated driver IC. In this case, one integrated driver IC may be mounted on the line substrate 20 (e.g., the rear surface 200d of the second bottom substrate 200), and each of the plurality of data wiring lines 201 and the plurality of gate wiring lines 203 may be additionally wired on the rear surface 200d of the second bottom substrate 200 and may be electrically connected to a corresponding channel provided in the integrated driver IC. In this case, the plurality of first pad portions PP1, the plurality of second pad portions PP2, the plurality of data flexible circuit films 61, and the plurality of gate flexible circuit films 71 may be omitted, thereby simplifying the configuration of the display driver circuit.

[0111] In addition, in the present embodiment, the corners of the first bottom substrate 100 of the display substrate 10 and the corners of the second bottom substrate 200 of the line substrate 20 may be chamfered to have a certain angle or length, or may be rounded to have a certain curvature. Therefore, in the present embodiment, a plurality of first side wiring patterns 31 and a plurality of second side wiring patterns 41 may be easily formed in the corners of the first bottom substrate 100 of the display substrate 10 and the corners of the second bottom substrate 200 of the line substrate 20 without being disconnected.

[0112] As described above, in the display device according to the present embodiment, the signal for pixel driving can be supplied to the pixel driving line provided on the display substrate 10 through the line substrate 20 and the side connecting members 30 and 40. Therefore, the display device minimizes or does not have a border area due to removing the pad portion provided in the border area of ​​the display substrate 10, and has a border width suitable for minimizing the boundary portion between display devices connected to each other in a multi-screen display device.

[0113] Figure 6 is a diagram for describing a display device according to an embodiment of the present disclosure and illustrates a display device in which Figure 1 An example of a configuration of a wire substrate in a display device illustrated in FIG. Therefore, only the wire substrate and elements related thereto will be described hereinafter.

[0114] Reference Figure 6 Together with Figure 1 The line substrate 20 according to the present embodiment may include a data line substrate 21 bonded to a portion of the rear surface of the display substrate 10 and a gate line substrate 23 bonded to a portion of the rear surface of the display substrate 10 .

[0115] The data line substrate 21 may be bonded to one rear surface of the display substrate 10. That is, the data line substrate 20 may be bonded to one rear surface 100b of the display substrate 10 using a substrate bonding member so as to overlap one edge of each of the plurality of data lines DL. The data line substrate 21 may include a plurality of data wiring lines 201 and one side disposed on the same line as one side of the display substrate 10 with respect to a thickness direction Z of the display substrate 10, and may be connected to the data driving circuit 60.

[0116] In the data line substrate 21 according to the embodiment, one side 21a may have the same length as one side of the display substrate 10, the other side 21b opposite to the one side 21a may have a length shorter than the length of the one side 21a, one short side 21c connecting one side of the one side 21a to one side of the other side 21b may be tilted, and another short side 21d connecting the other side of the one side 21a to the other side of the other side 21b may be set in a straight line shape. That is, one side 21a of the data line substrate 21 may have the same length as one side of the display substrate 10 for connecting the plurality of data wiring lines 201 to the plurality of first side wiring patterns 31 in a one-to-one relationship, and one short side 21c of the data line substrate 21 may be tilted to prevent the data line substrate 21 and the gate line substrate 23 from overlapping or interfering.

[0117] The data driving circuit 60 may be configured as an IC type and may be directly mounted on the rear surface of the data line substrate 21 to be connected to each of the plurality of data wiring lines 201 through a chip mounting process based on a chip on glass type. To this end, the data line substrate 21 may include a data chip mounting area with the data driving circuit 60 having a chip mounted thereon and a data pad portion connected to the data chip mounting area. The data driving circuit 60 may be connected to the control board 80 (see FIG. 1 ) through a plurality of first signal transmission cables STC1. Figure 3 ).

[0118] The gate line substrate 23 may be bonded to the other rear surface of the display substrate 10. That is, the gate line substrate 20 may be bonded to the other rear surface 100b of the display substrate 10 using a substrate bonding member so as to overlap one edge of each of the plurality of gate lines GL. The gate line substrate 23 may include a plurality of gate wiring lines 203 and the other side disposed on the same line as the other side of the display substrate 10 with respect to the thickness direction Z of the display substrate 10, and may be connected to the gate driving circuit 70.

[0119] The gate drive circuit 70 may be configured as an IC type and may be directly mounted on the rear surface of the gate line substrate 23 to be connected to each of the plurality of gate wiring lines 203 by a chip mounting process based on a chip on glass type. To this end, the gate line substrate 23 may include a gate chip mounting area with the gate drive circuit 70 having a chip mounted thereon and a gate pad portion connected to the gate chip mounting area, the gate drive circuit 70 having a chip mounted thereon. The gate pad portion may be connected to the control board 80 (see FIG. 1 ) through a plurality of second signal transmission cables STC2. Figure 3 ).

[0120] Alternatively, if Figure 5As shown in , the gate driving circuit 70 can be manufactured as an IC type respectively, directly set on the rear surface of the gate line substrate 23 without being mounted on the gate line substrate 23 through a TFT manufacturing process, and connected to multiple gate wiring lines 203 in a one-to-one relationship.

[0121] In the gate line substrate 23 according to the embodiment, the other side 23a may have the same length as the other side of the display substrate 10, the side 23b opposite to the other side 23a may have a length shorter than the length of the other side 23a, one short side 23c connecting one side of the one side 23b to one side of the other side 23a may be tilted, and another short side 23d connecting the other side of the one side 23b to the other side of the other side 23a may be set in a straight line shape. That is, the other side 23a of the gate line substrate 23 may have the same length as the other side of the display substrate 10 for connecting the plurality of gate wiring lines 203 to the plurality of second side wiring patterns 41 in a one-to-one relationship, and one short side 23c of the gate line substrate 23 may be tilted to prevent the data line substrate 21 and the gate line substrate 23 from overlapping or interfering.

[0122] The display device according to this embodiment provides Figures 1 to 5 In addition, the display device according to the present embodiment may include a spare space provided on the rear surface of the display substrate 10 not bonded to the wire substrate 20, and the spare space may be used as a storage space for a display driving system such as a control board. Therefore, the thickness of the display device according to the present embodiment is thin.

[0123] Figure 7 Is used to describe Figure 1 and Figure 6 Schematic diagram of a side data connection member of a display device illustrated in FIG.

[0124] Reference Figure 7 , the bonding substrate 1 including the display substrate 10 and the wire substrate 20 bonded to each other may include a plurality of grooves 1 a provided in the first non-display area IA1 .

[0125] The first non-display area IA1 of the bonding substrate 1 may be defined as a lower non-display area of ​​the bonding substrate 1 overlapping an edge of each of the plurality of data lines DL.

[0126] The plurality of first grooves 1a may be arranged at intervals along the first horizontal axis direction X, and may be recessedly disposed in a direction from one side of the bonding substrate 1 to the display area AA. The plurality of first grooves 1a according to the embodiment may be formed by a substrate cutting process. The substrate cutting process according to the embodiment may use a laser scribing process to cut a portion of the edge of the bonding substrate 1 corresponding to the interval between the plurality of data lines DL to form the plurality of first grooves 1a. Therefore, one side of the bonding substrate 1 may include a plurality of recessedly disposed grooves 1a and a plurality of protrusions 1b disposed between the plurality of first grooves 1a and overlapped with the ends of the plurality of data lines DL, respectively.

[0127] In the display device according to the present embodiment, the side data connection member 30 may be provided in each of the plurality of protrusions 1b provided on one side of the bonding substrate 1, and may connect the ends of the plurality of data lines DL in a one-to-one relationship to the plurality of data wiring lines 201. The side data connection member 30 according to the embodiment may include a plurality of first side wiring patterns 31 respectively surrounding the plurality of first protrusions 1b.

[0128] Each of the plurality of first side wiring patterns 31 may be arranged to surround half or less of the corresponding first protrusions of the plurality of first protrusions 1b. That is, each of the plurality of first side wiring patterns 31 may be arranged to completely surround approximately half of the corresponding first protrusions of the plurality of first protrusions 1b, and may be arranged by an immersion process using a conductive solution or a silver paste. Therefore, each of the plurality of first side wiring patterns 31 may be electrically connected to an end of a corresponding data line of a plurality of data lines DL in the front surface of the corresponding first protrusion of the plurality of first protrusions 1b, and may be electrically connected to an end of a corresponding data wiring line of a plurality of data wiring lines 201 in the rear surface of the corresponding first protrusion of the plurality of first protrusions 1b, thereby electrically connecting the corresponding data line DL to the corresponding data wiring line 201.

[0129] In addition, in the display device according to the present embodiment, the bonding substrate 1 may further include a plurality of second grooves and a plurality of second protrusions, the plurality of second grooves being arranged in the second non-display area and respectively overlapping with the ends of the plurality of gate lines, and the plurality of second protrusions being arranged between two adjacent second grooves in the plurality of second grooves. In addition, in the same manner and structure as the plurality of data wiring lines described above, a plurality of gate wiring lines are respectively formed in the plurality of second protrusions arranged on the other side of the bonding substrate 1. Here, the second non-display area of ​​the bonding substrate 1 may be defined as a right non-display area of ​​the bonding substrate 1 overlapping with the edge of each of the plurality of gate lines GL.

[0130] FIG. 8A to FIG. 8C It is used to describe manufacturing Figure 7 Schematic diagram of the method of the side data connection component illustrated in FIG.

[0131] Will refer to FIG. 8A to FIG. 8C A method for manufacturing a side data connection member according to the present embodiment will be described.

[0132] First, a display substrate 10 including a plurality of sub-pixels respectively disposed in a plurality of pixel areas defined by a plurality of data lines and a plurality of gate lines, and a line substrate 20 including a plurality of data wiring lines 201 and a plurality of gate wiring lines may be provided.

[0133] Then, if Fig. 8A As shown in , the bonding substrate 1 may be provided by bonding the display substrate 10 to the wire substrate 20 with a substrate bonding member. In this case, one side 100c of the display substrate 10 and one side 200c of the wire substrate 20 may be provided on the same vertical line.

[0134] Then, if Figure 8B As shown in , a plurality of first grooves 1a may be formed on one side 100c and one side 200c of the bonding substrate 1 by a substrate cutting process so that the ends of the plurality of data lines are extended. The substrate cutting process according to the embodiment may form a plurality of first grooves 1a by cutting a portion of each of the one side 100c and one side 200c of the bonding substrate 1 corresponding to the intervals between the plurality of data lines DL using a laser scribing process, thereby providing a plurality of first protrusions 1b respectively overlapping the ends of the plurality of data lines DL and the ends of the plurality of data wiring lines 201.

[0135] Then, if Figure 8C As shown in , a side data connection member 30 (i.e., a plurality of first side wiring patterns 31) may be formed, which respectively surround a plurality of first protrusions 1b disposed on one side 100c and one side 200c of the bonding substrate 1 in a one-to-one relationship. For example, the plurality of first side wiring patterns 31 may be formed by a dipping process in which approximately half of each of the first protrusions 1b is dipped in a conductive solution and the conductive solution is applied to the front surface, the side surface, and the rear surface of each of the plurality of first protrusions 1b. By performing the dipping process, each of the plurality of first side wiring patterns 31 that respectively cover the ends of the plurality of data lines DL and the ends of the plurality of data wiring lines 201 may be independently disposed, and the plurality of first side wiring patterns 31 may be electrically separated from each other from the plurality of first grooves 1a disposed on the one side 100c and one side 200c of the bonding substrate 1. Here, the conductive solution may contain a conductive paste, for example, a silver paste.

[0136] In addition, in the display device according to the present embodiment, in addition to the side gating connection member being arranged on the other side of the bonding substrate 1, the side gating connection member according to the present embodiment can be arranged with the same structure and manufacturing method as the structure and manufacturing method of the above-mentioned side data connection member, and therefore, a detailed description thereof is omitted.

[0137] Subsequently, when the side data connection member is disposed on one side of the bonding substrate 1 and the side gating connection member is disposed on the other side of the bonding substrate 1, a side sealing member may be formed on each side of the bonding substrate 1, thereby protecting each side of the bonding substrate 1 and electrically insulating the side data connection member 30 from the side gating connection member.

[0138] By using the side data connection member, the side gate connection member and the manufacturing method thereof according to the present embodiment, the process of forming the side wiring pattern on the side of the bonding substrate is simplified, the electrical short circuit between adjacent side wiring lines is prevented, and the chamfering process or rounding process for the edge of each of the display substrate 10 and the line substrate 20 or the edge of the bonding substrate 1 can be omitted. The side data connection member, the side gate connection member and the manufacturing method thereof according to the present embodiment can be equally applied to the following display device according to the embodiment of the present disclosure.

[0139] Fig. 9 is a diagram for describing a display substrate of a display device according to an embodiment of the present disclosure.

[0140] Reference Fig. 9 The display substrate 10 (ie, the first base substrate 100 ) of the display device according to the present embodiment may include a first display area AA1 , a second display area AA2 , a frame area BA, a plurality of first unit pixels UP1 , and a plurality of second unit pixels UP2 .

[0141] The first display area AA1 may be defined as a central area excluding the edge of the first bottom substrate 100. The second display area AA2 may be defined to surround the first display area AA1 and may overlap the edge of the first bottom substrate 100.

[0142] The non-display area IA may be disposed between the sides of the display substrate 100 and the second display area AA2 , may have a relatively very narrow width, and may be defined as a bezel area BA.

[0143] A plurality of first unit pixels UP1 may be provided in the first display area AA1. In this case, in the first display area AA1, the plurality of first unit pixels UP1 may be arranged at a predetermined first reference pixel pitch along the first horizontal axis direction X and at a predetermined second reference pixel pitch along the second horizontal axis direction Y. The first reference pixel pitch P may be defined as a distance between center portions of two first unit pixels UP1 adjacent to each other along the first horizontal axis direction X, and the second reference pixel pitch may be defined as a distance between center portions of two first unit pixels UP1 adjacent to each other along the second horizontal axis direction Y.

[0144] A plurality of second unit pixels UP2 may be disposed in the second display area AA2. In this case, the sizes of the second unit pixels UP2 may each be smaller than the size of each of the first unit pixels UP1. That is, the distance between the middle portion of each of the second unit pixels UP2 and the outer surface of the first base substrate 100 may be set to half or less of each of the reference pixel pitches.

[0145] Adjacent first unit pixels UP1 and second unit pixels UP2 may be arranged to have a reference pixel pitch P. Therefore, in the display device according to the present embodiment, a plurality of first unit pixels UP1 provided on the first base substrate 100 of the display substrate 10 may have the same size and may be arranged at the same reference pixel pitch, and in this case, the size of each of the plurality of second unit pixels UP2 adjacent to the outer surface of the first base substrate 100 is reduced, whereby the display device has a frame width suitable for minimizing a boundary portion between display devices joined to each other in a multi-screen display device.

[0146] The plurality of first unit pixels UP1 and the plurality of second unit pixels UP2 may each include at least three adjacent sub-pixels SP1 to SP3. The sub-pixels SP1 to SP3 are as described above, and thus, a detailed description thereof is omitted.

[0147] In the display substrate 10 according to the present embodiment, the size of the second unit pixel UP2 set in the second display area AA2 overlapping with the edge of the first base substrate 100 can be set to be smaller than the size of the first unit pixel UP1 set in the first display area AA1 of the first base substrate 100, and therefore, the display device has a border width suitable for minimizing the boundary portion between display devices joined to each other in a multi-screen display device.

[0148] Fig.10 Is used to describe Fig. 9 A cross-sectional view of the structure of a sub-pixel illustrated in FIG. Fig.11 Is used to describe Fig.10 A cross-sectional view of the structure of the light-emitting device illustrated in FIG.

[0149] Reference Fig.10 and Fig.11 Together with Fig. 9 , the plurality of sub-pixels SP1 to SP3 of the display substrate 10 according to the present embodiment may each include a pixel circuit PC, a passivation layer 110 , a recess 130 , a light emitting device 150 , a planarization layer 160 , a pixel electrode PE, and a common electrode CE.

[0150] First, in Fig.10 , the thickness of the first base substrate 100 is illustrated to be relatively thin, but the first base substrate 100 may generally have a thickness relatively much thicker than the total thickness of the stacked structure disposed on the first base substrate 100 .

[0151] The pixel circuit PC may include a switching TFT T1, a driving TFT T2, and a capacitor Cst. The pixel circuit PC is as described above, and therefore, a detailed description thereof is not provided. Hereinafter, for example, the structure of the driving TFT T2 will be described.

[0152] The driving TFT T2 may include a gate electrode GE, a semiconductor layer SCL, an ohmic contact layer OCL, a source electrode SE, and a drain electrode DE.

[0153] The gate GE may be formed on the first base substrate 100 together with the gate line GL. The gate GE may be covered by a gate insulating layer 103. The gate insulating layer 103 may be formed of a single layer or multiple layers including an inorganic material, and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), and / or the like.

[0154] The semiconductor layer SCL may be disposed in a predetermined pattern (or island) type on the gate insulating layer 103 to cover the gate electrode GE. The semiconductor layer SCL may be formed of a semiconductor material including one of amorphous silicon, polysilicon, oxide, and organic material, but is not limited thereto.

[0155] The ohmic contact layer OCL may be disposed in a predetermined pattern (or island) type on the semiconductor layer SCL. Here, the ohmic contact layer OCL serves as an ohmic contact between the semiconductor layer SCL and the source and drain electrodes SE and DE and may be omitted.

[0156] The source electrode SE may be formed on one side of the ohmic contact layer OCL to overlap one side of the semiconductor layer SCL. The source electrode SE may be formed together with the data line DL and the driving power line DPL.

[0157] The drain electrode DE may be formed on the other side of the ohmic contact layer OCL, overlap the other side of the semiconductor layer SCL, and may be separated from the source electrode SE. The drain electrode DE may be formed together with the source electrode SE and may branch or extend from the adjacent driving power line DPL.

[0158] In addition, the switching TFT T1 constituting the pixel circuit PC may be formed in the same structure as that of the driving TFT T2. In this case, the gate electrode of the switching TFT T1 may be branched or extended from the gate line GL, the first electrode of the switching TFT T1 may be branched or extended from the data line, and the second electrode of the switching TFT T1 may be connected to the gate electrode GE of the driving TFT T2 through a through hole provided in the gate insulating layer 103.

[0159] The pixel circuit PC may be covered by an interlayer insulating layer 105. The interlayer insulating layer 105 may be disposed on the entire first base substrate 100, covering the pixel circuit PC including the driving TFT T2. The interlayer insulating layer 105 according to an embodiment may be made of a material such as SiO x or SiN x The interlayer insulating layer 105 may not be provided.

[0160] The passivation layer 110 may be disposed on the entire first base substrate 100, covering the sub-pixel SP (i.e., the pixel circuit PC), or may be disposed on the entire first base substrate 100, covering the interlayer insulating layer 105. The passivation layer 110 may protect the pixel circuit PC including the driving TFT T2 and may provide a flat surface on the interlayer insulating layer 105. The passivation layer 110 according to an embodiment may be formed of an organic material such as styrene or photoacrylic, and in particular, may be formed of photoacrylic for the convenience of implementing a process.

[0161] The recess 130 may be provided in the emission region of the sub-pixel region defined in the sub-pixel SP and may accommodate the light emitting device 150. The recess 130 according to the embodiment may be provided recessed from the passivation layer 110 to have a certain depth D1. In this case, the recess 130 may include an accommodation space recessed from the top 110a of the passivation layer 110 to have a depth D1 corresponding to the thickness (or total height) of the light emitting device 150. Here, the bottom surface of the recess 130 may be formed by removing a portion of the passivation layer 110, the entire portion of the passivation layer 110, the entire portion of the passivation layer 110 and a portion of the interlayer insulating layer 105, or the entire portion of each of the passivation layer 110, the interlayer insulating layer 105, and the gate insulating layer 103 to have a depth D1 set based on the thickness of the light emitting device 150. For example, the recess 130 may be provided to a depth of 2 μm from the top 110a of the passivation layer 100. The concave portion 130 may have a groove or cup shape having a size wider than the rear surface (or bottom) of the light emitting device 150 .

[0162] The recess 130 according to the embodiment may include an inclined surface disposed between the bottom surface and the top 110 a of the passivation layer 110 , and the inclined surface may allow light emitted from the light emitting device 150 to proceed toward the front of the recess 130 .

[0163] The light emitting device 150 may be mounted on the recess 130 and may be electrically connected to the pixel circuit PC and the common power line CPL, and thus may emit light with current flowing from the pixel circuit PC (i.e., the driving TFT T2) to the common power line CPL. The light emitting device 150 according to an embodiment may include a light emitting layer EL, a first electrode (or anode terminal) E1, and a second electrode (or cathode terminal) E2.

[0164] The light emitting layer EL may emit light according to recombination of electrons and holes based on current flowing between the first electrode E1 and the second electrode E2 The light emitting layer EL according to an embodiment may include a first semiconductor layer 151 , an active layer 153 , and a second semiconductor layer 155 .

[0165] The first semiconductor layer 151 may supply electrons to the active layer 153. The first semiconductor layer 151 according to an embodiment may be formed of an n-GaN-based semiconductor material, and examples of the n-GaN-based semiconductor material may include GaN, AlGaN, InGaN, AlInGaN, etc. Here, as an impurity for doping the first semiconductor layer 151, silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), or carbon (C) may be used.

[0166] The active layer 153 may be disposed on one side of the first semiconductor layer 151. The active layer 153 may have a multi-quantum well (MQW) structure including a well layer and a barrier layer having a band gap higher than the well layer. The active layer 153 according to an embodiment may have an MQW structure of InGaN / GaN or the like.

[0167] The second semiconductor layer 155 may be disposed on the active layer 153 and may supply holes to the active layer 153. The second semiconductor layer 155 according to an embodiment may be formed of a p-GaN-based semiconductor material, and examples of the p-GaN-based semiconductor material may include GaN, AlGaN, InGaN, AlInGaN, etc. Here, magnesium (Mg), zinc (Zn), or beryllium (Be) may be used as an impurity for doping the second semiconductor layer 155.

[0168] The first electrode E1 may be disposed on the second semiconductor layer 155. The first electrode E1 may be connected to the source electrode SE of the driving TFT T2.

[0169] The second electrode E2 may be disposed on the other side of the first semiconductor layer 151, and may be electrically disconnected from the active layer 153 and the second semiconductor layer 155. The second electrode E2 may be connected to the common power line CPL.

[0170] Each of the first electrode E1 and the second electrode E2 according to the embodiment may be formed of a material including one or more materials of metal materials such as gold (Au), tungsten (W), platinum (Pt), silicon (Si), iridium (Ir), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti) or chromium (Cr) and alloys thereof. In other embodiments, each of the first electrode E1 and the second electrode E2 may be formed of a transparent conductive material, and examples of the transparent conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), etc. However, the present embodiment is not limited thereto.

[0171] In addition, the first semiconductor layer 151, the active layer 153, and the second semiconductor layer 155 may be provided in a structure sequentially stacked on a semiconductor substrate. Here, the semiconductor substrate may include a semiconductor material included in a sapphire substrate or a silicon substrate. The semiconductor substrate may be used as a growth semiconductor substrate for growing each of the first semiconductor layer 151, the active layer 153, and the second semiconductor layer 155, and then the semiconductor substrate may be separated from the first semiconductor layer 151 by a substrate separation process. Here, the substrate separation process may be a laser lift-off process or a chemical lift-off process. Therefore, since the growth semiconductor substrate is removed from the light emitting device 150, the thickness of the light emitting device 150 is thin, and therefore, it can be accommodated in the recess 130 provided in each sub-pixel SP.

[0172] The light emitting device 150 may emit light according to the recombination of electrons and holes based on the current flowing between the first electrode E1 and the second electrode E2. In this case, the light emitted from the light emitting device 150 may pass through the first electrode E1 and the second electrode E2 and may be output to the outside. In other words, the light emitted from the light emitting device 150 may pass through the first electrode E1 and the second electrode E2, and may be output toward the bottom surface of the recess 130 in a second direction opposite to the first direction, thereby displaying an image.

[0173] The light emitting device 150 may include a first portion (or front portion) FP and a second portion (or rear portion) RP opposite to the first portion FP, the first portion FP including a first electrode E1 and a second electrode E2 connected to the pixel circuit PC. In this case, the first portion FP may be relatively disposed farther from the bottom surface of the recess 130 than the second portion RP. Here, the size of the first portion FP may be smaller than that of the second portion RP, and in this case, the cross-sectional surface of the light emitting device 150 may have a trapezoidal shape including a top portion corresponding to the first portion EP and a bottom portion corresponding to the second portion RP.

[0174] The planarization layer 160 may be disposed on the passivation layer 110, covering the light emitting device 150. That is, the planarization layer 160 may be disposed on the passivation layer 110, having a thickness that enables the planarization layer 160 to cover the top of the planarization layer 110 and the front surface of the other receiving space of the concave portion 130 in which the light emitting device 150 is received.

[0175] The planarization layer 160 may provide a planar surface on the passivation layer 110. In addition, the planarization layer 160 may be buried in other receiving spaces of the recess 130 in which the light emitting device 150 is received, thereby fixing the position of the light emitting device 150.

[0176] The pixel electrode PE may electrically connect the first electrode E1 of the light emitting device 150 to the source electrode SE of the driving TFT T2 and may be defined as an anode electrode. The pixel electrode PE according to the embodiment may be disposed on the top 160a of the planarization layer 160, overlapping the driving TFT T2 and the first electrode E1 of the light emitting device 150. The pixel electrode PE may be electrically connected to the source electrode SE of the driving TFT T2 through the first circuit contact hole CCH1, which is disposed to pass through the interlayer insulating layer 105, the passivation layer 110, and the planarization layer 160, and the pixel electrode PE may be electrically connected to the first electrode E1 of the light emitting device 150 through the first electrode contact hole ECH1 disposed in the planarization layer 160. Therefore, the first electrode E1 of the light emitting device 150 may be electrically connected to the source electrode SE of the driving TFT T2 through the pixel electrode PE. If the display device has a top emission structure, the pixel electrode PE may be formed of a transparent conductive material, and if the display device has a bottom emission structure, the pixel electrode PE may be formed of a light reflective conductive material. Here, the transparent conductive material may be indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not limited thereto. The light reflective conductive material may be Al, Ag, Au, Pt, Cu, etc., but is not limited thereto. The pixel electrode PE including the light reflective conductive material may be formed of a single layer including the light reflective conductive material or a multilayer including a plurality of stacked single layers.

[0177] The common electrode CE may be electrically connected to the second electrode E2 of the light emitting device 150 and the common power line CPL and may be defined as a cathode electrode. The common electrode CE may be disposed on the top 160a of the planarization layer 160, overlapping the second electrode E2 of the light emitting device 150 and the common power line CPL. Here, the common electrode CE may be formed of the same material as that of the pixel electrode PE.

[0178] One side of the common electrode CE according to the embodiment may be electrically connected to the common power line CPL through the second circuit contact hole CCH2 provided to pass through the gate insulating layer 103, the interlayer insulating layer 105, the passivation layer 110, and the planarization layer 160. The other side of the common electrode CE may be electrically connected to the second electrode E2 of the light emitting device 150 through the second electrode contact hole ECH2 provided in the planarization layer 160, overlapping the second electrode E2 of the light emitting device 150. Therefore, the second electrode E2 of the light emitting device 150 may be electrically connected to the common power line CPL through the common electrode CE.

[0179] The pixel electrode PE and the common electrode CE according to the embodiment may be simultaneously provided by an electrode patterning process using a photolithography process, an etching process, and a deposition process for depositing an electrode material on the planarization layer 160 including the first and second circuit contact holes CCH1 and CCH2 and the first and second electrode contact holes ECH1 and ECH2. Therefore, in the present embodiment, since the pixel electrode PE and the common electrode CE connecting the light emitting device 150 and the pixel circuit PC are simultaneously formed, the electrode connection process is simplified, and the process time spent in the process of connecting the light emitting device 150 and the pixel circuit PC is greatly shortened, thereby increasing the yield of the light emitting diode display device.

[0180] The display device according to the present embodiment may further include a transparent buffer layer 170 .

[0181] The transparent buffer layer 170 may be disposed on the first base substrate 100, covering the entire portion of the planarization layer 160 in which the pixel electrode PE and the common electrode CE are disposed, and thus a flat surface may be provided on the planarization layer 160, thereby protecting the light emitting device 150 and the pixel circuit PC from external impact. Therefore, the pixel electrode PE and the common electrode CE may be disposed between the planarization layer 160 and the transparent buffer layer 170. The transparent buffer layer 170 may be an optically transparent adhesive (OCA) or an optically transparent resin (OCR), but is not limited thereto.

[0182] The display device according to the present embodiment may further include a reflective layer 101 disposed under the emission region of each sub-pixel SP.

[0183] The reflective layer 101 may be disposed between the bottom surface of the recess 130 and the first base substrate 100, overlapping the emission region including the light emitting device 150. The reflective layer 101 according to the embodiment may be formed of the same material as the gate electrode GE of the driving TFT T2, and may be disposed on the same layer as the gate electrode GE. The reflective layer 101 may reflect light incident from the light emitting device 150 toward the first portion EP of the light emitting device 150. Therefore, the display device according to the present embodiment may include the reflective layer 101, and thus, may have a top emission structure. However, if the display device according to the present embodiment has a bottom emission structure, the reflective layer 101 may be omitted.

[0184] Alternatively, the reflective layer 101 may be formed of the same material as that of the source / drain electrodes SE / DE of the driving TFT T2 , and may be disposed on the same layer as the source / drain electrodes SE / DE.

[0185] In the display device according to the present embodiment, the light emitting device 150 mounted in each sub-pixel SP may be adhered to the bottom surface of the recess 130 with the adhesive member 120 .

[0186] The adhesive member 120 may be disposed between the recess 130 of each sub-pixel SP and the light emitting device 150 , and may attach the light emitting device 150 to the bottom surface of the recess 130 , thereby mainly fixing the light emitting display device 150 .

[0187] The adhesive member 120 according to an embodiment may be attached (coated) to the second portion RP (i.e., the rear surface of the first semiconductor layer 151) of the light emitting device 150, and thus, in the installation process of installing the light emitting device 150 on the recess 130, the adhesive member 120 may be adhered to the recess 130 of each sub-pixel SP.

[0188] In other embodiments, the adhesive member 120 may be spread over the concave portion 130 of each sub-pixel SP, and may spread under the pressure applied thereto in the mounting process performed for the light emitting device 150, and thus, may be adhered to the second portion RP of the light emitting device 150. Therefore, the light emitting device 150 mounted on the concave portion 130 may be mainly fixed in position by the adhesive member 120. Therefore, according to the present embodiment, the mounting process for the light emitting device 150 may be performed only in the method of attaching the light emitting device 150 on the bottom surface of the concave portion 130, and thus, the mounting process time taken to perform the mounting process for the light emitting device 150 is shortened.

[0189] In other embodiments, the adhesive member 120 may be applied to the top 110a of the passivation layer 110 and the bottom surface and the inclined surface of the recess 130. That is, the adhesive member 120 may be provided to completely cover a portion of the front surface of the passivation layer 110 except for the contact hole. In other words, the adhesive member 120 may be provided between the passivation layer 110 and the planarization layer 160 and may be provided between the passivation layer 110 and the light emitting device 150. In other embodiments, the adhesive member 120 may be applied to a certain thickness on the entire top 110a of the passivation layer 110 in which the recess 130 is provided. When the contact hole is formed, a portion of the adhesive member 120 applied on the top 110a of the passivation layer 110 in which the contact hole is to be provided may be removed. Therefore, in the present embodiment, just before the mounting process for the light emitting device 150, the adhesive member 120 may be applied to the entire top 110a of the passivation layer 110 with a certain thickness, and therefore, according to the present embodiment, the process time taken to form the adhesive member 120 is shortened.

[0190] In the present embodiment, the adhesive member 120 may be disposed on the entire top portion 110 a of the passivation layer 110 , and thus the passivation layer 160 according to the present embodiment is disposed to cover the adhesive member 120 .

[0191] According to the embodiment, the installation process for the light-emitting device may include a process of installing a red light-emitting device on each of the red sub-pixels SP1, a process of installing a green light-emitting device on each of the green sub-pixels SP2, and a process of installing a blue light-emitting device on each of the blue sub-pixels SP3. In addition, it may also include a process of installing a white light-emitting device on each of the white sub-pixels.

[0192] The mounting process for the light emitting device according to the embodiment may include only a process of mounting the white light emitting device on each of the sub-pixels. In this case, the first base substrate 100 may include a color filter layer overlapping each sub-pixel. The color filter layer may transmit only light having a wavelength of a color corresponding to the corresponding sub-pixel in the white light.

[0193] The installation process for the light emitting device according to the embodiment may include only the process of installing the first color light emitting device on each sub-pixel. In this case, the first base substrate 100 may include a wavelength conversion layer and a color filter layer overlapping each sub-pixel. The wavelength conversion layer may emit light of a second color based on some of the light of the first color incident from the first color light emitting device. The color filter layer may transmit only light of a wavelength of a color corresponding to the corresponding sub-pixel in white light based on a combination of the light of the first color and the light of the second color. Here, the first color may be blue, and the second color may be yellow. The wavelength conversion layer may include a phosphor or quantum dot that emits light of a second color based on some of the light of the first color.

[0194] The display device according to the present embodiment provides the same effect as that of the above-mentioned display device, and since the light-emitting device 150 is accommodated in the recess 130 provided in each of the sub-pixels SP1 to SP3, the alignment accuracy is enhanced in the installation (or transfer) process for the light-emitting device 150, thereby increasing the yield.

[0195] Fig.12 is a plan view for describing a concave portion provided in a unit pixel according to an embodiment of the present disclosure, and Fig.13 It is along Fig.12 A cross-sectional view taken along line II' illustrated in FIG.

[0196] Reference Fig.12 and Fig.13 In the present embodiment, the first to third sub-pixels SP1 to SP3 constituting each of the plurality of first unit pixels UP1 may each include a concave portion 130 disposed recessed from the top of the passivation layer 110 .

[0197] First, in each of the first unit pixels UP1 , the second subpixel SP2 may be disposed in the middle of the unit pixel area, the first subpixel SP1 may be disposed on one side of the second subpixel SP2 , and the third subpixel SP3 may be disposed on the other side of the second subpixel SP2 .

[0198] The concave portion 130 disposed in the second sub-pixel SP2 may have a parallelogram shape, and a center line CLg2 of the concave portion 130 relative to the first horizontal axis direction X may match a second center line CL2 of the second sub-pixel SP2. For example, the concave portion 130 in the second sub-pixel SP2 may be disposed in a central portion of the first unit pixel UP1. Therefore, a distance L between a central portion of the concave portion 130 disposed in the second sub-pixel SP2 and an outer surface of the first base substrate 100 may be set to be half "P / 2" of the reference pixel pitch P or less.

[0199] The concave portion 130 disposed in the first subpixel SP1 may have a parallelogram shape and may be disposed close to the concave portion 130 disposed in the second subpixel SP2. That is, a center line CLg1 of the concave portion 130 disposed in the first subpixel SP1 with respect to the first horizontal axis direction X may be disposed at a position spaced apart from the center line CL1 of the first subpixel SP1 by a first distance d1 in a direction toward the second subpixel SP2.

[0200] The concave portion 130 disposed in the third subpixel SP3 may have a parallelogram shape and may be disposed close to the concave portion 130 disposed in the second subpixel SP2. That is, a center line CLg3 of the concave portion 130 disposed in the third subpixel SP3 relative to the first horizontal axis direction X may be disposed at a position spaced apart from the center line CLg3 of the third subpixel SP3 by a second distance d2 in a direction toward the second subpixel SP2.

[0201] The first to third sub-pixels SP1 to SP3 of each of the first unit pixels UP1 may have the same width Wa with respect to the first horizontal axis direction X.

[0202] In each of the first unit pixels UP1, the recesses 130 respectively provided in the first to third sub-pixels SP1 to PS3 may be provided to be concentrated on the central portion of the first unit pixel UP. Each first unit pixel UP1 may have a first width W1 corresponding to a predetermined resolution, and a plurality of first unit pixels UP1 may be arranged at a reference pixel pitch P. Here, the reference pixel pitch P may be defined as a distance between central portions of two first unit pixels UP1 adjacent to each other with respect to the first horizontal axis direction X and the second horizontal axis direction Y. In other words, the reference pixel pitch P may be defined as a distance between the same sub-pixels provided in two first unit pixels UP1 adjacent to each other with respect to the first horizontal axis direction X. That is, the reference pixel pitch P may be defined as a distance between the light-emitting devices 150 respectively provided in the second sub-pixels SP2 of two adjacent first unit pixels UP1. For example, the first unit pixel UP1 may be composed of a red sub-pixel SP1, a green sub-pixel SP2 and a blue sub-pixel SP3, and in this case, the reference pixel pitch P may be a distance between the recesses 130 (or light-emitting devices 150) respectively arranged in adjacent red sub-pixels SP1, a distance between the recesses 130 (or light-emitting devices 150) respectively arranged in adjacent green sub-pixels SP2, or a distance between the recesses 130 (or light-emitting devices 150) respectively arranged in adjacent blue sub-pixels SP3 relative to the first horizontal axis direction X.

[0203] In each of the second unit pixels UP2, the second sub-pixel SP2 may be disposed in the middle of the unit pixel area, the first sub-pixel SP1 may be disposed on one side of the second sub-pixel SP2, and the third sub-pixel SP3 may be disposed on the other side of the second sub-pixel SP2, and may be disposed adjacent to the outer surface of the first bottom substrate 100. Here, the outer surface of the first bottom substrate 100 may be defined as a side wall perpendicular to the end of the front surface 100a of the first bottom substrate 100, or may be defined as the outermost surface of the first bottom substrate 100 exposed to the outside. That is, the side wall of the first bottom substrate 100 may be directly exposed to the outside, or may be covered by a structure such as a wiring line, a passivation layer, etc., and thus may not be directly exposed to the outside. Therefore, the outer surface of the first bottom substrate 100 may be defined as the outermost surface of the first bottom substrate 100 exposed to the outside.

[0204] The concave portions 130 respectively provided in the first to third sub-pixels SP1 to SP3 in each second unit pixel UP2 are the same as those of the first unit pixel UP1 , and thus, a repeated description thereof is not provided.

[0205] In each of the second unit pixels UP2, since each of the first subpixel SP1 and the second subpixel SP2 is adjacent to the corresponding first unit pixel UP1, each of the first subpixel SP1 and the second subpixel SP2 may be configured to have the same width Wa as that of each subpixel of the corresponding first unit pixel UP1.

[0206] On the other hand, the third sub-pixel SP3 of each second unit pixel UP2 may be set to have a width Wb narrower than the width Wa of each of the first sub-pixel SP1 and the second sub-pixel SP2. In detail, in each second unit pixel UP2, the concave portion 130 may be set to be concentrated on the central portion of the unit pixel, so that even when a portion of the area of ​​the third sub-pixel SP3 adjacent to the non-display area IA of the first bottom substrate 100 is removed, the quality of the image displayed on the corresponding unit pixel UP2 is not affected. Therefore, the width Wb of the third sub-pixel SP3 relative to the first horizontal axis direction X may be reduced by a second distance d2 at which the light emitting device 150 mounted on the third sub-pixel SP3 is arranged close to the second sub-pixel SP2 relative to the center line CL3 of the third sub-pixel SP3. In this case, the maximum distance L between the second unit pixel UP2 and the outer surface of the first bottom substrate 100 may be set to half "P / 2" or less of the reference pixel pitch P followed by the arrangement of the plurality of first unit pixels UP1, that is, may be set to be equal to or less than half of the reference pixel pitch. Therefore, since the size of each of the third subpixels SP3 is reduced in the second unit pixel UP2 adjacent to the border area of ​​the first bottom substrate 100, the display device according to this embodiment has a border width suitable for the boundary portion between display devices connected to each other in a multi-screen display device.

[0207] In addition, the display device according to the embodiment of the present disclosure may further include a side sealing member 107 .

[0208] The side sealing member 107 may be provided to cover the outer surface of the substrate 100 and the side surface of the transparent buffer layer 170. The side sealing member 107 according to the embodiment may be formed of a silicon-based or UV-curing-based sealant (or resin), but in consideration of the process viscosity time, the side sealing member 107 may be formed of a UV-curing-based sealant. Moreover, the side sealing member 107 may have a color (e.g., blue, red, green, or black), or may be formed of a colored resin or a light-shielding resin for preventing side light leakage, without being limited thereto. The side sealing member 107 prevents side light leakage when the light emitted from the light-emitting device 150 of each sub-pixel SP travels in a direction from the inside of the transparent buffer layer 170 to the outermost surface, and buffers external influences to prevent the side surface of each of the substrate 100 and the transparent buffer layer 170 from being damaged by external influences.

[0209] Fig.14 : is a diagram for describing a modified embodiment of a recessed portion according to an embodiment of the present disclosure.

[0210] Reference Fig.14According to the modified embodiment, the plurality of recesses 130 respectively disposed in the plurality of sub-pixels SP1, SP2, and SP3 of each of the plurality of unit pixels UP1 and UP2 may have the same shape and may be recessed from the passivation layer 110 to have different depths D1, D2, and D3 in the corresponding sub-pixels.

[0211] The recess 130 according to an embodiment may be provided to have depths D1 to D3 different from those of the passivation layer 110 based on the height of the light emitting device 150 to be provided in the corresponding sub-pixel, thereby removing or minimizing height deviations (or step heights) between micro light emitting devices by color.

[0212] In order to realize a color image, the display device according to the present embodiment may include a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3, and the light-emitting device 150 may be arranged according to the color and may be arranged in the concave portion 130 arranged in the sub-pixel having the corresponding color. In this case, the color-based light-emitting device 150 may have different heights (or thicknesses) due to a process error of the manufacturing process. For example, the thickness of the color-based light-emitting device 150 may be thickened in the order of red, green, and blue. In this case, the depths D1 to D3 of the concave portion 130 may be carefully arranged in the order of the red sub-pixel SP1, the green sub-pixel SP2, and the blue sub-pixel SP3 based on the height of the corresponding light-emitting device 150.

[0213] Therefore, in the present embodiment, the depth of the recess 130 provided in each sub-pixel can be differently set based on the height (or thickness) of the light-emitting device 150 to be provided in the corresponding sub-pixel, and therefore, the highest surface (for example, the top of the first electrode E1) of the color-based light-emitting device 150 provided in each sub-pixel can be provided on the same horizontal line HL, thereby preventing the occurrence of an opening defect in which the first electrode (or the second electrode) of the color-based light-emitting device 150 is not exposed due to the thickness deviation between the color-based light-emitting device 150 in the patterning process of the first electrode contact hole and the second electrode contact hole. Moreover, in the present embodiment, in the top emission structure, the optical distance between the reflective layer 101 and the color-based micro light-emitting device of each sub-pixel is optimized by using the recess 130 provided to have different depths D1 to D3 in each sub-pixel, and therefore, the reflection efficiency of the reflective layer 101 is improved, thereby maximizing the light efficiency of each micro light-emitting device.

[0214] Fig.15 is a diagram for describing a modified embodiment of a recess according to an embodiment of the present disclosure.

[0215] Reference Fig.15In the present embodiment, the plurality of recesses 130 respectively disposed in the plurality of sub-pixels SP1 to SP3 of each of the plurality of unit pixels UP1 and UP2 may be connected to each other without a boundary portion and may include one accommodation space. That is, each of the plurality of first unit pixels UP1 and each of the plurality of second unit pixels UP2 may include only one recess 130 disposed above the entirety of the first to third sub-pixels SP1 to SP3.

[0216] The concave portion 130 may have a quadrilateral shape extending toward the first subpixel SP1 and the third subpixel SP3 relative to the central portion of each of the unit pixels UP1 and UP2 or the central line CL2 of the second subpixel SP2. That is, the central line CLg of the concave portion 130 may match the central line CL2 of the second subpixel SP2 relative to the first horizontal axis direction X.

[0217] As described above, in the present embodiment, since one recess 130 is provided in the unit pixels UP1 and UP2 , deviation of the light emitting device 150 in the manufacturing process corresponding to each of the sub-pixels SP1 to SP3 is prevented, and alignment accuracy of the light emitting device 150 is improved.

[0218] Fig.16 It is along Fig.12 Another cross-sectional view taken along line II' illustrated in FIG. 1 and illustrating an example in which a color filter is added to the display device according to an embodiment of the present disclosure. Hereinafter, therefore, only elements added to the display device according to an embodiment of the present disclosure will be described.

[0219] Reference Fig.16 Together with Fig.12 , the display device according to the present embodiment may further include a black matrix BM and a color filter layer CFL.

[0220] First, the light emitting device 150 disposed in each of the plurality of sub-pixels SP1 to SP3 may emit white light. That is, all the light emitting devices 150 disposed on the first base substrate 100 may be white light emitting devices emitting white light.

[0221] The black matrix BM may define an opening area of ​​each of the sub-pixels SP1 to SP3, and may be directly disposed on the top 170a of the transparent buffer layer 170, overlapping the light emitting device 150 of each of the sub-pixels SP1 to SP3 in a one-to-one relationship, thereby preventing color mixing between adjacent sub-pixels SP1 to SP3. The black matrix BM may include a light absorbing material.

[0222] Alternatively, the black matrix BM may be provided to cover the side surface of the transparent buffer layer 170 and the outer surface of the first base substrate 100. In this case, the black matrix BM prevents side light leakage when light emitted from the light emitting device 150 of each of the sub-pixels SP1 to SP3 travels in a direction from the inside of the transparent buffer layer 170 toward the outermost surface.

[0223] The color filter layer CFL may be formed directly on the top 170a of the transparent buffer layer 70, overlapping the opening area defined by the black matrix BM, and may include a red color filter CF1, a green color filter CF2, and a blue color filter CF3 corresponding to the respective colors defined in the plurality of sub-pixels SP1 to SP3. The color filter layer CL may transmit only light having a wavelength of a color corresponding to the corresponding sub-pixel SP among the white light emitted from each of the sub-pixels SP1 to SP3.

[0224] In addition, the display device according to the present embodiment may further include a cover layer 190 .

[0225] The cover layer 190 may be disposed on the first base substrate 100, covering the black matrix BM and the color filter layer CFL. The cover layer 190 according to the embodiment may be formed of a material having a low refractive index. For example, the cover layer 190 may be formed of LiF, MgF2, CaF2, ScF3 and / or the like and may have a multilayer structure with different refractive indices. The cover layer 190 may be disposed on the first base substrate 100, covering the black matrix BM and the color filter layer CFL, thereby protecting each of the sub-pixels SP1 to SP3 and effectively outputting the light emitted from the light emitting device 150 of each of the sub-pixels SP1 to SP3 to the outside.

[0226] Optionally, the display device according to the present embodiment may further include a side coating layer 109 .

[0227] The side coating layer 109 may be provided to cover the outer surface of the cover layer 109. The side coating layer 109 according to the embodiment may be provided to cover the outer surface of the cover layer 190 by a coating process using black ink including a black-based light absorbing material. In addition, the side coating layer 109 may be additionally provided on the outer surface of the first base substrate 100, the side surface of the black matrix BM, and the outer surface of the second base substrate 200. The side coating layer 109 prevents side light leakage when light emitted from the light emitting device 150 of each of the sub-pixels SP1 to SP3 travels in a direction from the inside of the cover layer 190 to the outermost surface.

[0228] The cover layer 190 may be replaced by a transparent substrate including a glass material or a transparent plastic material, and in this case, the transparent substrate may be adhered to the black matrix BM and the color filter layer CFL using a transparent adhesive member. In addition, the black matrix BM and the color filter layer CFL may be provided on the transparent substrate without being directly formed on the top 170a of the transparent buffer layer 170, and in this case, the transparent substrate including the black matrix BM and the color filter layer CFL may be adhered to the top 170a of the transparent buffer layer 170 using a transparent adhesive member.

[0229] As described above, in the present embodiment, since the light-emitting devices 150 having the same color are respectively mounted on the sub-pixels SP1 to SP3, the installation process for the light-emitting devices 150 can be performed without distinguishing the light-emitting devices by color, thereby shortening the installation process time spent on the installation process for the light-emitting devices.

[0230] Fig.17 It is along Fig.12 Another cross-sectional view taken along line II' illustrated in FIG. Fig.16 An example of adding a wavelength conversion layer to the display device illustrated in FIG. Therefore, the wavelength conversion layer and elements related thereto will be described hereinafter.

[0231] Reference Fig.17 In the display device according to the present embodiment, if the light emitting device 150 emitting light of the first color (except white) is equally disposed in each of the plurality of sub-pixels SP1 to SP3, a wavelength conversion layer 180 may be disposed on top of the transparent buffer layer 170 for realizing color through the plurality of unit sub-pixels UP1 and UP2. That is, the wavelength conversion layer 180 may be disposed between the color filter layer CFL and the color filter layer 170.

[0232] The wavelength conversion layer 180 may emit light of a second color based on the light of the first color incident from the light emitting device 150 of each of the sub-pixels SP1 to SP3. That is, the wavelength conversion layer 180 may absorb the light of the first color and may emit light of the second color by re-emission. Here, the light of the first color may be blue light, and the light of the second color may be yellow light.

[0233] For example, the wavelength conversion layer 180 may be directly coated on the top 170a of the transparent buffer layer 170 in a liquid state, and then the wavelength conversion layer 180 may be cured by a curing process using heat and / or light. As another example, the wavelength conversion layer 180 may be manufactured in a sheet form and may be directly adhered to the top 170a of the transparent buffer layer 170.

[0234] The wavelength conversion layer 180 according to an embodiment may include phosphors or quantum dots.

[0235] The phosphor according to the embodiment may be a yellow phosphor which is excited by blue light to emit yellow light, and may be, for example, a yttrium aluminum garnet (YAG)-based material.

[0236] The quantum dots according to the embodiments may be excited by blue light, emit yellow light, and may have a size for emitting light having a yellow wavelength, and may, for example, include CdS, CdSe, CdTe, ZnS, ZnSe, GaAs, GaP, GaAs-P, Ga-Sb, InAs, InP, InSb, AlAs, AlP, AlSb, and / or the like.

[0237] The light of the second color re-emitted from the wavelength conversion layer 180 according to the present embodiment and irradiated onto the cover layer 190 may be combined with the light of the first color irradiated onto the cover layer 190 without being re-emitted from the wavelength conversion layer 180, and thus may be converted into white light. The white light may be filtered by the color filter overlapping each of the sub-pixels SP1 to SP3, and thus may be emitted as color light corresponding to each of the sub-pixels SP1 to SP3.

[0238] In addition to the black matrix BM and the color filter layer CFL being disposed on the top portion 170a of the wavelength conversion layer 180, the black matrix BM and the color filter layer CFL are Fig.16 The same, therefore, the detailed description thereof will not be repeated.

[0239] As described above, in the present embodiment, since the light-emitting devices 150 having the same color are respectively mounted on the sub-pixels SP1 to SP3, the installation process for the light-emitting devices 150 can be performed without distinguishing the light-emitting devices by color, thereby shortening the installation process time spent on the installation process for the light-emitting devices.

[0240] The cover layer 190 may be replaced with a transparent substrate including a glass material or a transparent plastic material, and in this case, the transparent substrate may be adhered to the wavelength conversion layer 180 using a transparent adhesive member. In addition, the wavelength conversion layer 180 may be provided on the transparent substrate without being directly formed on the top 170a of the transparent buffer layer 170, and in this case, the transparent substrate may be adhered to the top 170a of the transparent buffer layer 170 using a transparent adhesive member.

[0241] In the display device according to the embodiment of the present disclosure, a micro light emitting diode display device having sub-pixels including a light emitting device has been described above as an example, but in addition to the micro light emitting diode display device, the technical features of the wire substrate according to the embodiment of the present disclosure can also be equally applied to all flat panel display devices such as LCD devices, organic light emitting display devices and quantum dot display devices.

[0242] Fig.18 is a diagram for describing a multi-screen display device according to an embodiment of the present disclosure, and Fig.19 It is along Fig.18 A cross-sectional view taken along line II-II' illustrated in FIG.

[0243] Reference Fig.18 and Fig.19 Together with Fig.13 , the multi-screen display device according to the present embodiment may include a plurality of screen modules 500 - 1 to 500 - 4 and a housing 600 .

[0244] These screen modules 500-1 to 500-4 may be arranged in an N×M form (where N is a positive integer equal to or greater than 2, and M is a positive integer equal to or greater than 2) to display individual images respectively or to display one image in a divided manner. These screen modules 500-1 to 500-4 may each include Figures 1 to 17 The light emitting diode display device according to the embodiment of the present disclosure is illustrated in the accompanying drawings, and a repeated description of the display device is not provided.

[0245] The side surfaces of the plurality of screen modules 500-1 to 500-4 according to the embodiment may be coupled to each other by a module coupling member 700 provided on the outer surface of the first base substrate 100. The module coupling member 700 may couple the side surfaces of two adjacent screen modules among the plurality of screen modules 500-1 to 500-4 arranged in a lattice form, thereby realizing a multi-screen display device. The module coupling member 700 according to the embodiment may be formed of an adhesive or a double-sided tape capable of making the thickness relatively thin so as to minimize the interval between two adjacent screen modules among the plurality of screen modules 500-1 to 500-4.

[0246] In each of the plurality of screen modules 500-1 to 500-4, the maximum distance L between the second unit pixel UP2 and the outer surface of the display substrate 10 may be half "P / 2" or less of the reference pixel pitch P followed by the arrangement of the plurality of first unit pixels UP1. Therefore, the maximum distance between the second unit pixels UP2 of two adjacent screen modules whose side surfaces are bonded to each other with the module coupling member 70 therebetween may be equal to or less than the reference pixel pitch P. In other words, the pixel pitch between the second unit pixels UP2 of the two adjacent screen modules may be equal to or less than the reference pixel pitch P followed by the arrangement of the first unit pixels UP1 respectively arranged in the plurality of screen modules 500-1 to 500-4. Therefore, in the present embodiment, the area of ​​the dark portion caused by the boundary portion between two adjacent screen modules in the screen modules 500-1 to 500-4 is minimized or eliminated, and thus, an image that minimizes the sense of discontinuity of the entire screen may be displayed.

[0247] The housing 600 may support the rear edge of each of the plurality of screen modules 500-1 to 500-4 and may cover the rear surfaces of the plurality of screen modules 500-1 to 500-4. The housing 600 according to the embodiment may include a housing plate 610 and a housing side wall 630, the housing plate 610 covering the rear surface of each of the plurality of screen modules 500-1 to 500-4, and the housing side wall 630 being disposed perpendicular to the housing plate 610 and supporting the rear edge of each of the plurality of screen modules 500-1 to 500-4.

[0248] The outer casing plate 610 according to the embodiment may be configured as a single body covering the entire rear surface of each of the plurality of screen modules 500 - 1 to 500 - 4 .

[0249] The outer casing plate 610 according to the embodiment may be configured to have a plurality of partition plates overlapping each of the plurality of screen modules 500 - 1 to 500 - 4 .

[0250] The housing side wall 630 may be installed perpendicular to the top of the housing plate 610, overlap the rear edge of each of the plurality of screen modules 500-1 to 500-4, and may independently support the rear edge of each of the plurality of screen modules 500-1 to 500-4. In this case, the housing side wall 630 may support the rear edge of each of the plurality of screen modules 500-1 to 500-4 through the module support member 650. Here, the module support member 650 may be an elastic member, a foam pad, a double-sided tape, etc.

[0251] In addition, the housing 600 may include a plurality of module housings having a housing plate 610 and a housing side wall 630. Each of the plurality of housing modules may independently support the rear edge of the plurality of screen modules 500-1 to 500-4 and may cover the rear surfaces of the plurality of screen modules 500-1 to 500-4. In this case, the housing 600 may include a housing joint member 800 disposed between the plurality of module housings. The housing joint member 800 may be inserted into the interval between the adjacent module housings and may be fixed to the housing plate 610 of each of the adjacent module housings by a fastening member such as a bolt, a screw and / or the like.

[0252] In addition, the multi-screen display device according to the present embodiment may further include an integrated control board 900 and an image signal generator 910 mounted on the integrated control board 900 .

[0253] The integrated control board 900 may be disposed in a receiving space disposed on a rear surface of each of the plurality of screen modules 500-1 to 500-4 through the housing 600. The integrated control board 900 may be connected to the control board 250 of each of the plurality of screen modules 500-1 to 500-4 through at least one signal cable 930.

[0254] The image signal generator 910 may be mounted on the integrated control board 900. The image signal generator 910 may receive a raw image signal supplied from an external host driving system, and may generate a module-based input image signal corresponding to each of the images to be displayed by the display devices of the plurality of screen modules 500-1 to 500-4, respectively, based on the received raw image signal. That is, the image signal generator 910 may receive all resolution information (including the first display area AA1 and the second display area AA2) about each of the plurality of screen modules 500-1 to 500-4, divide the raw image signal according to the resolution information about each module to generate a module-based input image signal, and supply the module-based input image signal to the corresponding plane module of the plurality of screen modules 500-1 to 500-4. Therefore, each of the plurality of screen modules 500-1 to 500-4 may display a module-based image corresponding to the module-based panel image data based on the input image signal supplied from the image signal generator 910.

[0255] As described above, the multi-screen display device according to the present embodiment includes screen modules 500-1 to 500-4 configured with the light-emitting diode display device according to the embodiment of the present disclosure, so that the area in which the dark portion caused by the boundary portion between two adjacent screen modules among the screen modules 500-1 to 500-4 appears is minimized or eliminated, and thus, an image that minimizes the sense of discontinuity of the entire screen can be displayed.

[0256] Fig. 20A and Fig. 20B 1 is a diagram illustrating respective images displayed by a related art multi-screen display device and a multi-screen display device according to an embodiment of the present disclosure.

[0257] First, refer to Fig. 20A In the multi-screen display device in the related art, since only images are displayed on the display area AA of each of the multiple display devices, it can be found that due to the border area BA based on the front shell of each of the multiple display devices, a dark portion appears in the boundary portion between the display devices connected to each other, and a disconnected image caused by the dark portion of the boundary portion is displayed in the entire screen.

[0258] On the other hand, refer to Fig. 20B In the multi-screen display device according to an embodiment of the present disclosure, since the pixel pitch between the second unit pixels of two adjacent screen modules whose side surfaces are bonded to each other is equal to or smaller than the reference pixel pitch of the first unit pixel, it can be found that the area in which the dark portion caused by the boundary portion between the plurality of screen modules appears is minimized or eliminated, and thus, an image with the least sense of discontinuity of the entire screen is displayed.

[0259] As a result, even when the side surfaces of multiple screen modules are connected to each other in a grid form, the multi-screen display device of an embodiment of the present disclosure can display an image that minimizes the sense of discontinuity of the entire screen, thereby enhancing the user's immersion when viewing the image displayed on the large-size screen.

[0260] As described above, according to the embodiments of the present disclosure, the display device minimizes or eliminates the border area by removing the pad portion provided in the border area of ​​the display substrate, and has a border width suitable for minimizing the boundary portion between the display devices connected to each other in the multi-screen display device. In addition, according to the embodiments of the present disclosure, even when the side surfaces of a plurality of screen modules are connected to each other in a grid form, an image that minimizes the discontinuity of the entire screen is displayed, thereby enhancing the user's immersion when viewing an image displayed on a large-size screen.

[0261] It should be clear to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover the modified and modified forms of the present disclosure, provided that they fall within the scope of the attached claims and their equivalents.

[0262] CROSS-REFERENCE TO RELATED APPLICATIONS

[0263] This application claims the benefit of Korean Patent Application No. 10-2016-0184460, filed on Dec. 30, 2016, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A display device, comprising: a substrate configured to include a first region and a second region outside the first region; a plurality of first unit pixels, wherein the plurality of first unit pixels are arranged in the first region of the substrate; a plurality of second unit pixels, wherein the plurality of second unit pixels are arranged in the second region of the substrate, wherein each of the plurality of second unit pixels and the plurality of first unit pixels is configured to include a plurality of light emitting devices; a reflective layer, the reflective layer being disposed below each of the plurality of light emitting devices, Wherein, the reflective layer and the gate are arranged on the same layer; and a planarization layer, the planarization layer surrounding at least one light emitting device among the plurality of light emitting devices on at least four sides, Each of the plurality of second unit pixels is configured to have a size different from a size of each of the plurality of first unit pixels.

2. The display device according to claim 1, wherein: Each of the plurality of second unit pixels is configured to have a size smaller than that of each of the plurality of first unit pixels.

3. The display device according to claim 1, wherein: The plurality of first unit pixels are arranged at a reference pixel pitch, The distance between adjacent first unit pixels and second unit pixels has the reference pixel pitch, The reference pixel pitch is a distance between center portions of two first unit pixels adjacent to each other.

4. The display device according to claim 3, wherein: The plurality of first unit pixels are configured to have the same size.

5. The display device according to claim 1, wherein: The plurality of first unit pixels are arranged at a reference pixel pitch, and A distance between a central portion of each of the plurality of second unit pixels and an outer surface of the substrate is half or less of the reference pixel pitch.

6. The display device according to claim 1, wherein: A distance between the plurality of light emitting devices arranged in the first unit pixel is equal to a distance between the plurality of light emitting devices arranged in the second unit pixel.

7. The display device according to claim 1, wherein: Each of the plurality of light emitting devices comprises: a first portion configured to include a first electrode and a second electrode; and The second part is opposite to the first part.

8. The display device according to claim 1, wherein: Each of the plurality of first unit pixels and the plurality of second unit pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and In each of the plurality of second unit pixels, the third sub-pixel is disposed closer to an outer surface of the substrate and is configured to have a size different from that of each of the first sub-pixel and the second sub-pixel.

9. The display device according to claim 8, wherein: In each of the plurality of second unit pixels, the third sub-pixel is configured to have a size smaller than a size of each of the first sub-pixel and the second sub-pixel.

10. The display device according to claim 8, wherein: The light emitting device included in the second sub-pixel is disposed at a central portion of the corresponding unit pixel, The light emitting device included in the first sub-pixel is disposed closer to the second sub-pixel with respect to a central portion of the first sub-pixel, and The light emitting device included in the third sub-pixel is disposed closer to the second sub-pixel with respect to a central portion of the third sub-pixel.

11. The display device according to claim 1, further comprising a wire substrate bonded to the substrate by using a substrate bonding member, in: The substrate is a display substrate, and One side of the wire substrate is disposed on the same line as one side of the display substrate with respect to a thickness direction of the display substrate.

12. The display device according to claim 11, further comprising a side data connection member located on the one side of the display substrate and the one side of the line substrate, in: The display substrate is further configured to include a plurality of pixel driving lines for driving each of the plurality of light emitting devices, The wiring substrate is configured to include a plurality of wiring lines, and The side data connection member is configured to connect the plurality of pixel driving lines to the plurality of wiring lines.

13. The display device according to claim 1, wherein: The reflective layer is formed of the same material as that of the gate electrode.

14. The display device according to claim 1 further comprises a side data connection member, which is located on one side of the substrate and on one side of a line substrate, the line substrate being joined to the substrate by using a substrate joining member, and the side data connection member connects a plurality of data lines of the substrate to a plurality of data wiring lines in a one-to-one relationship.

15. A multi-screen display device, comprising a plurality of screen modules, in, Each of the plurality of screen modules includes the display device according to any one of claims 1 to 14.

16. The multi-screen display device according to claim 15, wherein: The maximum distance between the second unit pixels of two adjacent screen modules is equal to or smaller than the distance between the center portions of the two adjacent unit pixels, or In each of the plurality of screen modules, a distance between a central portion of the second unit pixel and an outer surface of the substrate is half or less of a distance between central portions of two adjacent unit pixels.

17. The multi-screen display device according to claim 15, wherein: The plurality of screen modules include a first screen module and a second screen module adjacent to each other, and A distance between a central portion of a second unit pixel disposed in the first screen module and a central portion of a second unit pixel disposed in the second screen module is equal to or smaller than a distance between central portions of two adjacent unit pixels.

Images