Gate drive circuit and light emitting display device including the gate drive circuit

Abstract

The present invention relates to a gate drive circuit and a light-emitting display device including the gate drive circuit, wherein the charging characteristics of the control node are improved. The gate drive circuit includes first to m-th stage circuits, wherein each of the first to m-th stage circuits includes: first to third control nodes; a node control circuit that controls the voltage of each of the first to third control nodes; and an output buffer circuit that outputs each of a scan signal, a sensing signal, and a carry signal according to each of the first to third control nodes, and the node control circuit includes a node setting circuit that charges a first gate high potential voltage to the first control node in response to a first carry signal provided from a previous stage circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure claims the benefit of and priority to Korean Patent Application No. 10-2019-0180144, filed on December 31, 2019, which is hereby incorporated by reference in its entirety as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a gate driving circuit and a light-emitting display device including the gate driving circuit. Background Art

[0004] Since the light-emitting display device displays images by using self-light-emitting diodes, the light-emitting display device has a fast response speed, low power consumption, and a good viewing angle, and thus has attracted widespread attention as a next-generation display device.

[0005] The light-emitting display device may include a pixel having a light-emitting diode and a pixel circuit driving the light-emitting diode. For example, the pixel circuit includes: a driving thin film transistor that controls a driving current flowing to the light-emitting diode; and at least one switching thin film transistor that controls (or programs) a gate-source voltage of the driving thin film transistor according to a scan signal. The switching thin film transistor of the pixel circuit can be switched by an output signal of a gate driving circuit directly formed in a substrate of the display panel. For example, the gate driving circuit can output a signal for switching the switching thin film transistor of the pixel circuit according to the voltage of the control node.

[0006] Recently, a technology for inserting a black image in a light-emitting display device to shorten the motion picture response time has been proposed. The black image insertion technology can shorten the motion picture response time by displaying a black image between adjacent frames to eliminate the influence of the previous frame image on the next frame image.

[0007] External compensation technology has been used to enhance the quality of images displayed in light-emitting display devices. The external compensation technology can compensate for driving characteristic deviations between pixels by sensing pixel voltage or current based on the driving characteristics (or electrical characteristics) of the pixels and modulating the data of the input image based on the sensing results.

[0008] However, in the gate driving circuit of the light-emitting display device of the prior art, the charging characteristics of the control node deteriorate due to the change in the threshold voltage of the thin film transistor, so that the gate driving circuit may output an abnormal signal, or may operate erroneously due to the voltage drop (IR Drop) of the gate driving voltage based on the leakage current of the thin film transistor connected to the control node.

[0009] The light-emitting display device to which the black image insertion technology and / or the external compensation technology are applied sequentially displays a black image based on horizontal lines (or horizontal pixel lines). Due to the degradation of the charging characteristics of the control node generated in the gate driving circuit, the leakage current of the thin film transistor connected to the control node, or the insufficient time for sensing the driving characteristics of the pixel, a black image is displayed within one frame, thereby generating a defect in picture quality, and reliability may be degraded due to such a defect in picture quality.

[0010] The disclosure of the above background technology is owned by the inventor of the present disclosure for the purpose of designing this specification, or is technical information obtained through the process of designing this specification, but cannot be regarded as known technology disclosed to the public before this specification is disclosed. Summary of the invention

[0011] The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a gate driving circuit and a light emitting display device including the gate driving circuit, in which charging characteristics of a control node are improved.

[0012] Another object of the present disclosure is to provide a gate driving circuit and a light emitting display device including the same, in which a voltage drop of a gate driving voltage is minimized by a leakage current of a thin film transistor connected to a control node.

[0013] In addition to the objects of the present disclosure as described above, those skilled in the art will clearly understand other objects and features of the present disclosure from the following description of the present disclosure.

[0014] A gate drive circuit according to one embodiment of the present disclosure includes first to m-th stage circuits, wherein each of the first to m-th stage circuits includes: first to third control nodes; a node control circuit that controls the voltage of each of the first to third control nodes; and an output buffer circuit that outputs each of a scan signal, a sense signal, and a carry signal according to each of the first to third control nodes, the node control circuit including a node setting circuit that charges a first gate high potential voltage to the first control node in response to a first carry signal provided from a previous stage circuit.

[0015] A light-emitting display device according to one embodiment of the present disclosure includes: a light-emitting display panel including a plurality of pixels; a plurality of gate line groups having a first gate line and a second gate line connected to the plurality of pixels, and a plurality of data lines and reference lines connected to the plurality of pixels and crossing the plurality of gate line groups; a gate driving circuit portion connected to the plurality of gate line groups; a data driving circuit portion connected to the plurality of data lines and the plurality of reference lines; and a timing controller controlling the driving timing of each of the gate driving circuit portion and the data driving circuit portion, wherein the gate driving circuit includes first to m-th stage circuits, each of the first to m-th stage circuits includes: first to third control nodes; a node control circuit controlling a voltage of each of the first to third control nodes; and an output buffer circuit outputting each of a scan signal, a sensing signal and a carry signal according to each of the first to third control nodes, and the node control circuit includes a node setting circuit charging a first gate high potential voltage to the first control node in response to a first carry signal provided from a previous stage circuit.

[0016] In addition to the above objects, details of various embodiments according to the present disclosure are included in the detailed description and drawings.

[0017] According to one embodiment of the present disclosure, a gate driving circuit and a light emitting display device including the gate driving circuit may be provided, wherein charging characteristics of a control node are improved.

[0018] According to one embodiment of the present disclosure, a gate driving circuit and a light emitting display device including the same may be provided, in which a voltage drop of a gate driving voltage is minimized by a leakage current of a thin film transistor connected to a control node.

[0019] In addition to the effects of the present disclosure as described above, other advantages and features of the present disclosure will be clearly understood by those skilled in the art from the above description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0021] Figure 1 is a view showing a light emitting display device according to one embodiment of the present disclosure;

[0022] Figure 2 It is shown Figure 1 The equivalent circuit diagram of the pixel shown;

[0023] Figure 3is a waveform showing an output signal of a gate driving circuit according to one embodiment of the present disclosure;

[0024] Figure 4 is a timing diagram showing data voltages, scan signals, and sensing signals for driving pixels arranged on one horizontal line;

[0025] Figure 5 is a timing diagram showing a scan signal, a sensing signal, and a data voltage for driving pixels disposed on an n-th horizontal line;

[0026] Figure 6 It is shown Figure 1 The waveform of the gate driving circuit according to one embodiment of the present disclosure is shown;

[0027] Figure 7 is shown applied to Figure 6 The signal of the gate control signal line shown and the voltage of the control node and the output signal waveform of each of the first-stage circuit and the second-stage circuit;

[0028] Figure 8 It is shown Figure 6 The block diagram of the nth stage circuit and the (n+1)th stage circuit shown;

[0029] Fig. 9 It is shown Figure 8 A circuit diagram of an n-th stage circuit and an (n+1)-th stage circuit according to an embodiment of the present disclosure is shown;

[0030] Fig.10 It is shown Fig. 9 A view of input waveforms and output waveforms of each of the n-th stage circuit and the (n+1)-th stage circuit shown;

[0031] FIG. 11A to FIG. 11I is a view showing an operation process of each of an n-th stage circuit and an (n+1)-th stage circuit;

[0032] Fig. 12A and Fig. 12B is a view showing a charging path of a first control node implemented in each stage circuit of a gate driving circuit according to an embodiment of the present disclosure and a comparative example;

[0033] Fig.13A and Fig. 13B are waveforms showing output characteristics of a gate driving circuit according to one embodiment of the present disclosure and a comparative example; and

[0034] Fig.14A and Fig. 14Bis a view showing a charging voltage waveform of a first control node of each of the gate driving circuits according to one embodiment of the present disclosure and a comparative example. DETAILED DESCRIPTION

[0035] The following embodiments described with reference to the accompanying drawings will illustrate the advantages and features of the present disclosure and their implementation methods. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure comprehensive and complete, and to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0036] The shapes, sizes, ratios, angles, and values ​​disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. The same reference numerals represent the same elements throughout. In the following description, when the detailed description of the related known functions or configurations is determined to be unnecessary to obscure the focus of the present disclosure, the detailed description will be omitted.

[0037] In the case where “including,” “having,” and “comprising” described in the present disclosure are used, additional parts may be added unless “only” is used. Terms in the singular form may include plural forms unless otherwise specified.

[0038] When interpreting an element, although there is no explicit description, the element is interpreted as including the error range.

[0039] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "over", "under", and "immediately next to", unless "just" or "directly" is used, one or more other parts may be provided between the two parts.

[0040] When describing a time relationship, for example, when a time sequence is described as “after,” “subsequently,” “next,” and “before,” discontinuous cases may be included unless “just” or “directly” is used.

[0041] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0042] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0043] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be combined or combined with each other in part or in whole, and can interoperate with each other in a variety of ways and be driven technically. The embodiments of the present disclosure can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0044] In the present disclosure, the pixel circuit and gate drive circuit formed on the substrate of the light-emitting display panel can be implemented as an n-type MOSFET type thin film transistor, but not limited to this. The pixel circuit and gate drive circuit can be implemented as a p-type MOSFET type thin film transistor. The thin film transistor may include a gate, a source and a drain. In a thin film transistor, the carrier moves from the source to the drain. In an n-type thin film transistor, since the carrier is an electron, the source voltage is lower than the drain voltage, so that the electron can move from the source to the drain. In an n-type thin film transistor, since the electron moves from the source to the drain, the current moves from the drain to the source. In a p-type thin film transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that the hole moves from the source to the drain. In a p-type thin film transistor, since the hole moves from the source to the drain, the current moves from the source to the drain. In a MOSFET type thin film transistor, the source and drain are not fixed, but can be changed depending on the voltage applied thereto. Therefore, in the description of the embodiment according to the present disclosure, the description will be made based on referring to any one of the source and the drain as a first source / drain electrode and referring to the other of the source and the drain as a second source / drain electrode.

[0045] Hereinafter, a gate drive circuit according to the present disclosure and a light-emitting display device including the gate drive circuit will be described in detail with reference to the accompanying drawings. As much as possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar components. Since the proportions of each element shown in the accompanying drawings are different from the actual proportions, for ease of description, the present disclosure is not limited to the proportions shown.

[0046] Figure 1 is a view showing a light emitting display device according to one embodiment of the present disclosure, Figure 2 It is shown Figure 1 The equivalent circuit diagram of the pixel shown is Figure 3 is a waveform showing an output signal of a gate driving circuit according to one embodiment of the present disclosure.

[0047] Reference Figures 1 to 3 , a light emitting display device according to one embodiment of the present disclosure may include a light emitting display panel 100 , a timing controller 300 , a gate driving circuit part 500 , and a data driving circuit part 700 .

[0048] The light-emitting display panel 100 may include a display area AA (or an active area) defined on a substrate, and a non-display area IA (or a non-active area) surrounding the display area AA.

[0049] The display area AA may include a plurality of gate line groups GLG, a plurality of data lines DL, a plurality of reference lines RL, and a plurality of pixels P.

[0050] Each of the plurality of gate line groups GLG may extend transversely along a first direction X, and may be disposed on the substrate to be spaced apart from another gate line group along a second direction Y crossing the first direction X. Each of the gate line groups GLG may include a first gate line (scanning signal line) GLa and a second gate line (sensing signal line) GLb.

[0051] Each of the plurality of data lines DL may extend longitudinally along the second direction Y, and may be disposed on the substrate to be spaced apart from another data line along the first direction X. As shown in FIG.

[0052] Each of the plurality of reference lines RL may be disposed on the substrate to be parallel to each of the plurality of data lines DL. For example, the reference line RL may be denoted as a sensing line.

[0053] Each of the plurality of pixels P may be disposed in a pixel region defined by the plurality of gate line groups GLG and the plurality of data lines DL.

[0054] Each of the plurality of pixels P according to one embodiment may be a red pixel, a green pixel, or a blue pixel. In this case, the red pixel, the green pixel, and the blue pixel may implement one unit pixel.

[0055] According to another embodiment, each of the plurality of pixels P may be a red pixel, a green pixel, a blue pixel or a white pixel. In this case, the red pixel, the green pixel, the blue pixel and the white pixel adjacent to each other may implement a unit pixel for displaying a color image.

[0056] The display area AA may further include a plurality of horizontal lines or a plurality of horizontal pixel lines along a length direction of each of the plurality of gate line groups GLG. The pixels P disposed in each horizontal line or horizontal pixel line may be commonly connected to the same gate line group GLG.

[0057] Each of the plurality of pixels P may include a light emitting diode ELD and a pixel circuit PC for controlling light emission of the light emitting diode ELD.

[0058] The pixel circuit PC may be switched according to a signal provided through a gate line group GLG adjacent thereto to output a data current based on a differential voltage Vdata-Vref of a data voltage Vdata provided through a data line DL adjacent thereto and a reference voltage Vref provided through a reference line RL adjacent thereto.

[0059] The pixel circuit PC according to one embodiment may include a first switching thin film transistor Tsw1, a second switching thin film transistor Tsw2, a driving thin film transistor Tdr, and a storage capacitor Cst. In the following description, a thin film transistor will be referred to as a "TFT".

[0060] At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be an amorphous silicon TFT, a polycrystalline silicon TFT, an oxide TFT, or an organic TFT. For example, in the pixel circuit PC, some of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be TFTs having excellent response characteristics including a semiconductor layer (or an active layer) made of low temperature polycrystalline silicon (LTPS), and another one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be a TFT having excellent off-current characteristics including a semiconductor layer (or an active layer) made of oxide.

[0061] The first switch TFT Tsw1 includes a gate electrode connected to the first gate line GLa of the gate line group GLG, a first source / drain electrode connected to the data line DL adjacent thereto, and a second source / drain electrode connected to the gate node Ng of the driving TFT Tdr. The first switch TFT Tsw1 supplies a data voltage Vdata supplied through the data line DL adjacent thereto to the gate node Ng of the driving TFT Tdr according to the scan signals SC[1] to SC[n] supplied through the first gate line GLa.

[0062] The second switch TFT Tsw2 includes a gate electrode connected to the second gate line GLb of the gate line group GLG, a first source / drain electrode connected to the source node Ns of the driving TFT Tdr, and a second source / drain electrode connected to the reference line RL adjacent thereto. The second switch TFT Tsw2 supplies a reference voltage Vref supplied through the reference line RL adjacent thereto to the source node Ns of the driving TFT Tdr according to the sensing signals SE[1] to SE[m] supplied through the second gate line GLb.

[0063] The storage capacitor Cst may be formed between the gate node Ng and the source node Ns of the driving TFT Tdr. The storage capacitor Cst according to one embodiment may include: a first capacitor electrode connected to the gate node Ng of the driving TFT Tdr; a second capacitor electrode connected to the source node Ns of the driving TFT Tdr; and a dielectric layer formed in an overlap region between the first capacitor electrode and the second capacitor electrode. Such a storage capacitor Cst charges a differential voltage between the gate node Ng and the source node Ns of the driving TFT Tdr, and then switches the driving TFT Tdr according to the charged voltage.

[0064] The driving TFT Tdr may include: a gate electrode (or gate node Ng) commonly connected to the second source / drain electrode of the first switch TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst; a first source / drain electrode (or source node Ns) commonly connected to the first source / drain electrode of the second switch TFT Tsw2 and the second capacitor electrode of the storage capacitor Cst and the light emitting diode ELD; and a second source / drain electrode (or drain node) connected to the pixel driving power source EVDD. The driving TFT Tdr may be turned on by the voltage of the storage capacitor Cst to control the amount of current flowing from the pixel driving power source EVDD to the light emitting diode ELD.

[0065] The light emitting diode ELD emits light according to the data current supplied from the pixel circuit PC to emit light with brightness corresponding to the data current.

[0066] The light emitting diode ELD according to one embodiment may include: a pixel electrode (or anode electrode) PE electrically connected to a pixel circuit PC; a self-luminous diode; and a common electrode (or cathode electrode) CE disposed on the self-luminous diode and connected to a pixel common power supply EVSS.

[0067] The pixel electrode PE may be disposed in a light emitting region (or opening region) defined in the pixel P, and electrically connected to a source node Ns of the pixel circuit PC through a contact hole disposed in an insulating layer (or planarization layer) covering the pixel circuit PC. Depending on the top emission structure or the bottom emission structure of the light emitting diode ELD, the pixel electrode PE may be made of a transparent conductive metal material or a reflective metal material.

[0068] The self-light emitting diode ELD is formed on the pixel electrode PE and directly contacts the pixel electrode PE. The light emitting diode ELD emits light according to the data current supplied from the pixel circuit PC to emit light with brightness corresponding to the data current.

[0069] The self-light emitting diode according to one embodiment may be a common layer commonly formed in each of the plurality of pixels P so as not to be identified by the pixel P. The self-light emitting diode may emit white light in response to a current flowing between the pixel electrode PE and the common electrode CE. The self-light emitting diode according to one embodiment may include an organic light emitting diode or an inorganic light emitting diode, or may include a deposition structure or a hybrid structure of an organic light emitting diode (or an inorganic light emitting diode) and a quantum dot light emitting diode.

[0070] An organic light emitting diode according to one embodiment includes two or more light emitting material layers (or light emitting portions) for emitting white light. For example, the organic light emitting diode may include a first light emitting material layer and a second light emitting material layer for emitting white light by mixing the first light and the second light. In this case, the first light emitting material layer may include at least one of a blue light emitting material, a green light emitting material, a red light emitting material, a yellow light emitting material, and a yellow-green light emitting material. The second light emitting material layer may include at least one of a blue light emitting material, a green light emitting material, a red light emitting material, a yellow light emitting material, and a yellow-green light emitting material to emit a second light, and the second light may be mixed with the first light emitted from the first light emitting material layer to produce white light.

[0071] The organic light emitting diode according to one embodiment may further include at least one functional layer for improving light emitting efficiency and / or lifespan. For example, the functional layer may be disposed in each of the upper and / or lower portions of the light emitting material layer.

[0072] The inorganic light emitting diode according to one embodiment may include a semiconductor light emitting diode, a micro light emitting diode, or a quantum dot light emitting diode. For example, when the light emitting diode ELD is an inorganic light emitting diode, the light emitting diode ELD may have a size of, but not limited to, 1 micrometer to 100 micrometers.

[0073] The common electrode CE may be disposed on the display area AA and may be in direct contact with the self-luminous diode or may be in direct electrical contact with the self-luminous diode. Depending on the top emission structure or bottom emission structure of the light emitting diode ELD, the common electrode CE may be made of a transparent conductive metal material or a reflective metal material.

[0074] The number of gate lines GLa and GLb connected to each of the plurality of pixels P may vary depending on the structure or driving method of the pixel P. For example, when the first switching TFT Tsw1 and the second switching TFT Tsw2 have a dual scanning structure in which the TFT Tsw1 and the TFT Tsw2 are driven differently from each other, each pixel P is connected to two gate lines GLa and GLb. When the first switching TFT Tsw1 and the second switching TFT Tsw2 have a single scanning structure in which the TFT Tsw1 and the TFT Tsw2 are driven equally to each other, each pixel P is connected to one gate line group GLG. In the present disclosure, for the convenience of description, a description will be given based on the dual scanning structure, but the technical spirit of the present disclosure is not limited to the dual scanning structure.

[0075] The timing controller 300 may be implemented to control the light-emitting display panel 100 in a display mode and a sensing mode based on a vertical synchronization signal Vsync and a horizontal synchronization signal of a timing synchronization signal TSS provided from a display driving system (or a host controller).

[0076] The display mode of the light-emitting display panel 100 can be driven to sequentially display an input image and a black image with a certain time difference in a plurality of horizontal lines. The display mode according to one embodiment may include: an image display period (or light-emitting display period) IDP for displaying an input image; and a black display period (or pulsed non-light-emitting period) for displaying a black image.

[0077] The sensing mode (or real-time sensing mode) of the light-emitting display panel 100 may be a real-time sensing drive for sensing the driving characteristics of the pixels P disposed in one of the plurality of horizontal lines after the image display period (IDP) in one frame, and updating the compensation value of each pixel based on the sensing value to compensate for the driving characteristic variation of the corresponding pixel P. The sensing mode according to one embodiment may sense the driving characteristics of the pixels P disposed in any one of the plurality of horizontal lines according to an irregular order in the vertical blank period VBP of each frame. Since the pixels P that emit light according to the display mode do not emit light in the sensing mode, when the horizontal lines are sequentially sensed in the sensing mode, line dimming may occur due to the non-luminescence of the sensed horizontal lines. On the other hand, when the horizontal lines are sensed in the sensing mode in an irregular order or a random order, line dimming may be minimized or avoided due to the visual distraction effect.

[0078] According to one embodiment, the timing controller 300 may set each frame Fn, Fn+1 for displaying an image on the light-emitting display panel 100 as an image display period IDP, a black display period BDP, and a real-time sensing period RSP. For example, the timing controller 300 may set the vertical effective period VAP of one frame period Fn, Fn+1 as a display period IDP, BDP for a display mode, and may set the vertical blank period VBP as a sensing period (or real-time sensing period) RSP for a sensing mode.

[0079] The timing controller 300 can change the duty cycle (or luminous duty cycle) of the image display period IDP by controlling the start timing of the black display period BDP in one frame Fn, Fn+1. The timing controller 300 according to one embodiment can extract the motion vector of the input image by comparing and analyzing the input image based on the frame Fn, Fn+1, and can change the start timing of the black display period BDP according to the motion vector of the image. For example, if the motion vector of the image is greater than the reference value, the timing controller 300 can reduce the duty cycle of the image display period IDP by advancing the start timing of the black display period BDP in one frame Fn, Fn+1, thereby increasing the maximum instantaneous brightness of the pixel P. Therefore, the motion picture response time can be reduced, and the motion blur can be minimized at the same time. On the contrary, if the motion vector of the image is less than the reference value, the timing controller 300 can increase the duty cycle of the image display period IDP by delaying the start timing of the black display period BDP in one frame Fn, Fn+1, thereby increasing the brightness of the pixel P. Therefore, the motion picture response time can be reduced, and the motion blur can be minimized at the same time.

[0080] The timing controller 300 may generate and output a gate control signal GCS and a data control signal DCS for driving the light-emitting display panel 100 in the image display period IDP, the black display period BDP, and the sensing period RSP based on a timing synchronization signal TSS provided from a display driving system (or a host controller).

[0081] The data control signal DCS may include a source start pulse, a source sampling clock, and a source output that can control the driving timing of the data driving circuit part 700 .

[0082] The gate control signal GCS may include a gate start signal, a first reset signal, a second reset signal, a gate driving clock, and a line sensing ready signal to control the driving timing of the gate driving circuit part 500 .

[0083] The timing controller 300 may generate a corresponding gate driving clock in each of the image display period IDP, the black display period BDP, and the sensing period RSP. For example, the timing controller 300 may generate an image display gate driving clock in the image display period IDP, a black display gate driving clock in the black display period BDP, and a sensing gate driving clock in the sensing period RSP. The image display gate driving clock, the black display gate driving clock, and the sensing gate driving clock may be different from each other.

[0084] The timing controller 300 can align the input data Idata provided from the display driving system (or host controller) in each image display period IDP of the display mode to be suitable for driving the light-emitting display panel 100 as pixel image data PID, and then provide the aligned pixel image data to the data driving circuit unit 700.

[0085] The timing controller 300 may generate pixel black data PBD in each black display period BDP of the display mode, and provide the generated pixel black data PBD to the data driving circuit part 700. For example, the timing controller 300 may generate a preset non-light emitting gray value or a black gray value of the light emitting diode ELD as the pixel black data PBD.

[0086] The timing controller 300 may generate pixel sensing data PSD in each sensing period RSP of the sensing mode, and provide the generated pixel sensing data PSD to the data driving circuit section 700. For example, the timing controller 300 may generate a gray value as the pixel sensing data PSD that may turn on the driving TFT Tdr of the pixel disposed in the horizontal line to be sensed in the sensing period RSP. At this time, the pixel sensing data PSD corresponding to the pixels constituting the unit pixel may have the same gray value or a corresponding gray value different for each pixel.

[0087] The gate driving circuit part 500 may be disposed in the non-display area IA of the light-emitting display panel 100 and electrically connected to the plurality of gate line groups GLG. The gate driving circuit part 500 may sequentially drive the plurality of gate line groups GLG based on the gate control signal GCS provided from the timing controller 300.

[0088] The gate driving circuit section 500 may generate scanning signals SC and sensing signals SE corresponding to the image display period IDP, the black display period BDP, and the sensing period RSP, respectively, based on the gate control signal GCS provided from the timing controller 300, and may provide the generated scanning signals SC and sensing signals SE to the corresponding gate line groups GLG. For example, the gate driving circuit section 500 sequentially provides scanning signals SC[1] to SC[m] and sensing signals SE[1] to SE[m] to the plurality of gate line groups GLG in the vertical active period VAP of each frame period, and may output scanning signals SC[i], SC[n] and sensing signals SE[i], SE[n] to any one of the gate line groups GLG in the vertical blank period VBP of each frame period.

[0089] According to one embodiment, the gate driving circuit unit 500 sequentially provides scan signals SC[1] to SC[m] having a first scan pulse SCP1 corresponding to an image display period IDP and a second scan pulse SCP2 corresponding to a black display period BDP to a first gate line GLa of each of a plurality of gate line groups GLG in a display mode, and may sequentially provide sensing signals SE[1] to SE[m] having a first sensing pulse SEP1 synchronized with the first scan pulse SCP1 to a second gate line GLb of each of a plurality of gate line groups GLG.

[0090] Alternatively, the gate driving circuit portion 500 may divide the plurality of gate line groups GLG into a plurality of horizontal groups, and may simultaneously provide the second scanning pulse SCP2 of the scanning signal SC[i] based on the horizontal groups in the black display period BDP of the display mode. For example, when the display area AA is virtually divided into the first area and the second area, in the middle of sequentially providing the first scanning pulse SCP1 to the plurality of first gate lines GLa disposed in the first area, the gate driving circuit portion 500 may simultaneously provide the second scanning pulse SCP2 to the plurality of first gate lines GLa disposed in the second area in the display mode.

[0091] According to one embodiment, the gate driving circuit unit 500 can provide the scanning signals SC[i], SC[n] having the third scanning pulse SCP3 (or sensing scanning pulse) and the fourth scanning pulse SCP4 (or reset scanning pulse) to the first gate line GLa of the gate line group GLG arranged in any specific horizontal line to be sensed among the multiple gate line groups GLG in each sensing mode of each frame Fn, Fn+1, and can provide the sensing signals SE[i], SE[n] having the second sensing pulse SEP2 (or sensing sensing pulse) overlapping with all the third scanning pulse SCP3 and the fourth scanning pulse SCP4 to the second gate line GLb of the gate connection group GLG arranged in the specific horizontal line.

[0092] As an example, in the sensing mode of the Nth frame Fn, when the sensing drive is performed on the pixel P of the i-th gate line group connected to the multiple gate line groups GLG, the gate driving circuit unit 500 can provide the scanning signal SC[i] having the third scanning pulse SCP3 and the fourth scanning pulse SCP4 to the first gate line GLa of the i-th gate line group, and at the same time provide the sensing signal SE[i] having the second sensing pulse SEP2 overlapping with all of the third scanning pulse SCP3 and the fourth scanning pulse SCP4 to the second gate line GLb of the i-th gate line group.

[0093] As another example, in the sensing mode of the (N+1)th frame Fn+1, when a sensing drive (or a sensing period RSP) is performed on a pixel P of an nth gate line group connected to a plurality of gate line groups GLG, the gate driving circuit unit 500 may provide a scanning signal SC[n] having a third scanning pulse SCP3 and a fourth scanning pulse SCP4 to a first gate line GLa of the nth gate line group, and simultaneously provide a sensing signal SE[n] having a second sensing pulse SEP2 overlapping with all of the third scanning pulse SCP3 and the fourth scanning pulse SCP4 to a second gate line GLb of the nth gate line group.

[0094] The gate driving circuit part 500 may be directly formed or built in the non-display region of the display panel 100 according to a manufacturing process of a TFT, and thus is respectively connected to the plurality of gate line groups GLG.

[0095] As an example, the gate driving circuit part 500 may be implemented in the non-display area IA on the left side of the substrate and drive the plurality of gate line groups GLG in a proper order according to a single feeding method.

[0096] As another example, the gate driving circuit unit 500 may be implemented in the non-display area IA at each of the left and right sides of the substrate, and drive the plurality of gate line groups GLG in an appropriate order according to the dual feeding method or the single feeding method. For example, in the single feeding method, the gate driving circuit unit 500 implemented in the non-display area IA on the left side of the substrate may sequentially drive the odd-numbered gate line groups in the plurality of gate line groups GLG, and the gate driving circuit unit 500 implemented in the non-display area IA on the right side of the substrate may sequentially drive the even-numbered gate line groups in the plurality of gate line groups GLG. In the dual feeding method, each of the gate driving circuit unit 500 implemented in the non-display area IA on the left side of the substrate and the gate driving circuit unit 500 implemented in the non-display area IA on the right side of the substrate may simultaneously and sequentially drive the plurality of gate line groups GLG.

[0097] The data driving circuit part 700 may be connected to a plurality of data lines DL provided in the light-emitting display panel 100. The data driving circuit part 700 according to one embodiment may convert the data PID, PBD, and PSD into analog-type data voltages Vdata by using the data PID, PBD, PSD, and the data control signal DCS provided from the timing controller 300 and a plurality of reference gamma voltages provided from a power source, and may provide the converted data voltages to the corresponding data lines DL.

[0098] In the image display period IDP of the display mode, the data driving circuit section 700 may convert the pixel image data PID into the image data voltage Vdata based on the data control signal DCS provided from the timing controller 300, and provide the converted image data voltage Vdata to the corresponding data line DL, and may generate a reference voltage Vref at the same time, and provide the generated reference voltage Vref to the reference line RL. The image data voltage Vdata may be synchronized with the first scanning pulse SCP1 of the scanning signal SC[1] to SC[m] provided to the gate line group GLG corresponding to the image display period IDP of the display mode. The reference voltage Vref may be synchronized with the display sensing pulse SEP of the sensing signal SE[1] to SE[m] provided to the gate line group GLG corresponding to the image display period IDP of the display mode.

[0099] In the black display period BDP of the display mode, the data driving circuit part 700 may convert the pixel black data PBD into the black data voltage Vdata based on the data control signal DCS provided from the timing controller 300, and provide the converted black data voltage Vdata to the corresponding data line DL. The black data voltage Vdata may be synchronized with the second scan pulse SCP2 for displaying the scan signals SC[i] and SC[n] provided to the gate line group GLG corresponding to the black display period BDP of the display mode.

[0100] In the sensing period RSP of the sensing mode, the data driving circuit part 700 may convert the pixel sensing data PSD into the sensing data voltage Vdata based on the data control signal DCS provided from the timing controller 300, and provide the converted sensing data voltage Vdata to the corresponding data line DL, and may generate a reference voltage Vref, and provide the generated reference voltage Vref to the reference line RL. The sensing data voltage Vdata may be synchronized with the third scanning pulse SCP3 of the scanning signals SC[i] and SC[n] provided to the gate line group GLG corresponding to the sensing period RSP of the sensing mode. The reference voltage Vref may be synchronized with the second sensing pulse SEP2 of the sensing signals SE[i] and SE[n] provided to the gate line group GLG corresponding to the sensing period RSP of the sensing mode.

[0101] In the sensing period RSP of the sensing mode, the data driving circuit section 700 may sense the driving characteristics of the pixel P, for example, the characteristic value of the driving TFT, through the plurality of reference lines RL, and may generate sensing low data corresponding to the sensing value, and provide the generated sensing low data to the timing controller 300. The data driving circuit section 700 may generate a restoration data voltage Vdata synchronized with the fourth scanning pulse SCP4 of the scanning signals SC[i] and SC[n], the scanning signals SC[i] and SC[n] being provided to the gate line group GLG corresponding to the sensing period RSP of the sensing mode, and provide the generated restoration data voltage Vdata to the data line DL, thereby restoring (or restoring) the display state (or driving state) of the pixel P connected to the gate line group GLG corresponding to the sensing period RSP to a previous state equivalent to the sensing period RSP. For example, when the image display period IDP is performed before the sensing period RSP, the restoration data voltage Vdata may be the image data voltage Vdata. When the black display period BDP is performed before the sensing period RSP, the restoration data voltage Vdata may be the black data voltage Vdata.

[0102] Meanwhile, the timing controller 300 according to one embodiment stores the sensing low data of each pixel P provided from the data driving circuit section 700 in the storage circuit according to the sensing mode. In the display mode, the timing controller 300 may compensate the pixel image data PID to be provided to the sensing pixel P based on the sensing low data stored in the storage circuit, and provide the compensated pixel image data to the data driving circuit section 700. For example, the sensing low data may include sequential change information of each of the driving TFT and the light emitting diode ELD provided in the pixel P. Therefore, the timing controller 300 may sense the characteristic value (e.g., threshold voltage or mobility) of the driving TFT provided in each pixel in the sensing mode, and may compensate the pixel image data PDI to be provided to each pixel P based on the sensed characteristic value, thereby minimizing or avoiding the degradation of the picture quality based on the characteristic value deviation of the driving TFT in the plurality of pixels P. Since the sensing mode of the light emitting display device is a known art of the present disclosure to the applicant, its detailed description will be omitted. For example, the light-emitting display device according to the present disclosure may sense the driving characteristic value set in each pixel P through a sensing mode disclosed in Korean Laid-Open Patent No. 10-2016-009317, No. 10-2017-0054654, or No. 10-2018-0002099.

[0103] Figure 4 is a timing diagram showing data voltages, scan signals, and sensing signals for driving pixels arranged on one horizontal line.

[0104] Reference Figure 2 and Figure 4 , the pixel P according to one embodiment of the present disclosure may be driven (or operated) in the image display period IDP and the black display period BDP of one frame.

[0105] The image display period IDP of the pixel P may include an image data address period t1 and a light emitting period t2.

[0106] At the image data addressing period (or the first data addressing period) t1 of the pixel P, the first switch TFT Tsw1 provided in the pixel P is turned on by the first scan pulse SCP1 of the scan signal SC[1] provided by the first gate line GLa of the first gate line group GLG1, and the second switch TFT Tsw2 is turned on by the sense pulse SEP of the sense signal SE[1] provided by the second gate line GLb of the first gate line group GLG1. Therefore, the image data voltage Vdata of the pixel image data PID provided through the data line DL is applied to the gate node Ng of the driving TFT Tdr, and at the same time, the reference voltage Vref provided through the reference line RL is applied to the source node Ns of the driving TFT Tdr. Therefore, at the image data addressing period t1, the voltage difference Vdata-Vref between the gate node Ng and the source node Ns of the driving TFT Tdr may be set to a voltage higher than the threshold voltage of the driving TFT Tdr, and the storage capacitor Cst may store the differential voltage Vdata-Vref of the image data voltage Vdata and the reference voltage Vref. In this case, the image data voltage Vdata may have a voltage level at which the threshold voltage of the driving TFT Tdr sensed by the sensing mode is reflected or compensated in the actual data voltage.

[0107] At the light emission period t2 of the pixel P, each of the first switch TFT Tsw1 and the second switch TFT Tsw2 provided in the pixel P is turned off, so that the driving TFT Tdr provided in the pixel P is turned on by the voltage Vdata-Vref charged in the storage capacitor Cst. Therefore, the driving TFT Tdr supplies the data current determined by the differential voltage Vdata-Vref of the image data voltage Vdata and the reference voltage Vref to the light emitting diode ELD, so that the light emitting diode ELD emits light proportional to the data current flowing from the pixel driving power supply EVDD to the pixel common power supply EVSS. That is, at the light emission period t2, if the first switch TFT Tsw1 and the second switch TFT Tsw2 are turned off, the current flows to the driving TFT Tdr, and the light emitting diode ELD starts to emit light proportional to the current, whereby the voltage of the source node Ns of the driving TFT Tdr increases, and the voltage of the gate node Ng of the driving TFT Tdr increases as much as the voltage of the source node Ns of the driving TFT Tdr increases through the storage capacitor Cst. Therefore, the gate-source voltage Vgs of the driving TFT Tdr can be continuously maintained by the voltage of the storage capacitor Cst, and the light emission of the light emitting diode ELD can be continuously maintained until the start timing of the black display period BDP. The light emission period of the light emitting diode ELD may correspond to a light emission duty ratio.

[0108] The black display period BDP of the pixel P may include a black data address period t3 and a non-light emitting period t4.

[0109] At the black data addressing period (or the second data addressing period) t3 of the pixel P, the first switch TFT Tsw1 provided in the pixel P is turned on by the second scan pulse SCP2 of the scan signal SC[1] provided by the first gate line GLa of the first gate line group GLG1, and the second switch TFT Tsw2 is maintained in the off state by the sensing signal SE[1] of the TFT off voltage level provided by the second gate line GLb of the first gate line group GLG1. Therefore, the black data voltage Vdata of the pixel black data PBD provided by the data line DL is applied to the gate node Ng of the driving TFT Tdr. At this time, the source node Ns of the driving TFT Tdr may be maintained at the operating voltage level (or non-light emitting start voltage) of the light emitting diode ELD according to the off state of the second switch TFT Tsw2. The black data voltage Vdata may have a voltage level lower than the operating voltage level (or non-light emitting voltage level) of the light emitting diode ELD, or a voltage level lower than the threshold voltage of the driving TFT Tdr. Therefore, at the black data addressing period t3, when the voltage Vgs between the gate node Ng and the source node Ns changes to be lower than the threshold voltage of the driving TFT Tdr by the black data voltage Vdata, the driving TFT Tdr is turned off. Thus, when the data current supplied from the driving TFT Tdr to the light emitting diode ELD is cut off, the light emission of the light emitting diode ELD stops, so that the pixel P displays a black image due to the non-light emission of the light emitting diode ELD.

[0110] At the non-light emitting period t4 of the pixel P, the first switch TFT Tsw1 provided in the pixel P is turned off, and the second switch TFT Tsw2 is maintained in the off state, thereby maintaining the driving TFT Tdr in the off state. For this reason, the light emitting diode ELD can maintain a non-light emitting state, and the non-light emitting of the light emitting diode ELD can be maintained until the start timing of the image data addressing period t1 or the sensing period RSP of the next frame. The non-light emitting period of the light emitting diode ELD may correspond to a black duty ratio or a non-light emitting duty ratio.

[0111] At the same time, pixels P set on other horizontal lines among the multiple horizontal lines set in the display area except any specific horizontal line to be sensed can be driven substantially the same as pixels P set on the above-mentioned first horizontal line in the image display period IDP and the black display period BDP.

[0112] Figure 5 is a timing diagram showing data voltages, scan signals, and sensing signals for driving pixels disposed on an n-th horizontal line.

[0113] Reference Figure 2 and Figure 5, the pixel P according to one embodiment of the present disclosure may be driven (or operated) in the image display period IDP, the black display period BDP, and the sensing period RSP of one frame.

[0114] The image display period IDP of the pixel P may include an image data address period t1 and a light emitting period t2. Since the image data address period t1 and the light emitting period t2 are substantially equivalent to the reference period t1, the image display period IDP of the pixel P may include an image data address period t1 and a light emitting period t2. Figure 4 The contents described above are not described herein, and therefore their repeated description will be omitted.

[0115] The black display period IDP of the pixel P may include a black data address period t3 and a non-luminescent period t4. Since the black data address period t3 and the non-luminescent period t4 are substantially equivalent to the reference period Figure 4 The contents described above are not described herein, and therefore their repeated description will be omitted.

[0116] The sensing period RSP of the pixel P may include a sensing data address period t5 and a sampling period t6 .

[0117] At the sensing data addressing period (or the third data addressing period) t5 of the pixel P, the first switch TFT Tsw1 provided in the pixel P is turned on by the third scanning pulse SCP3 of the scanning signal SC[n] provided by the first gate line GLa of the nth gate line group GLGn, and the second switch TFT Tsw2 is turned on by the second sensing pulse SEP2 of the sensing signal SE[n] provided by the second gate line GLb of the nth gate line group GLGn. Therefore, the sensing data voltage Vdata of the pixel sensing data PSD provided by the data line DL is applied to the gate node Ng of the driving TFT Tdr, and at the same time, the reference voltage Vref provided by the reference line RL is applied to the source node Ns of the driving TFT Tdr. Therefore, at the sensing data addressing period t5, the voltage Vgs between the gate node Ng and the source node Ns of the driving TFT Tdr is set to correspond to the sensing data voltage. For example, the sensing data voltage Vdata may have a level set to a target voltage of a threshold voltage of the sensing driving TFT Tdr.

[0118] At the sampling period t6 (or real-time sensing period) of the pixel P, the first switch TFT Tsw1 provided in the pixel P is turned off by the scanning signal SC[n] of the TFT off voltage level provided by the first gate line GLa of the nth gate line group GLGn, and the second switch TFT Tsw2 is kept in the on state by the second sensing pulse SEP2 of the sensing signal SE[n] provided by the second gate line GLb of the nth gate line group GLGn. The reference line RL is electrically connected to the sensing unit embedded in the data driving circuit. Therefore, the sensing unit of the data driving circuit can sample the sensing pixel current or the sensing pixel voltage provided by the source node Ns of the second switch TFT Tsw2 and the driving TFT Tdr and the reference line RL, and can convert the sampled sampling signal by analog-to-digital conversion to generate sensing low data, and provide the generated sensing low data to the timing controller 300.

[0119] The sensing period RSP of the pixel P according to one embodiment of the present disclosure may further include a data recovery period t7 .

[0120] At the data recovery period t7 (or real-time sensing period) of the pixel P, the first switch TFT Tsw1 provided in the pixel P is turned off by the scanning signal SC[n] of the TFT off voltage level provided by the first gate line GLa of the nth gate line group GLGn, and the second switch TFT Tsw2 is kept in the on state by the second sensing pulse SEP2 of the sensing signal SE[n] provided by the second gate line GLb of the nth gate line group GLGn. The reference line RL is electrically separated from the sensing unit of the data driving circuit and is electrically connected to the reference power supply. Therefore, the recovery data voltage Vdata of the pixel black data PBD provided by the data line DL is applied to the gate node Ng of the driving TFT Tdr, and at the same time, the reference voltage Vref provided by the reference line RL is applied to the source node Ns of the driving TFT Tdr. Therefore, at the data recovery period t7, the voltage between the gate node Ng and the source node Ns of the driving TFT Tdr is restored to the previous state of the sensing period RSP, so that the pixel P can emit light again, and the re-emission of the light emitting diode ELD can continue to reach the image data addressing period t1 of the next frame Fn+1.

[0121] Figure 6 It is shown Figure 1 . The waveform of the gate driving circuit according to one embodiment of the present disclosure is shown in FIG.

[0122] Reference Figure 1 and Figure 6 , the gate driving circuit part 500 according to one embodiment of the present disclosure may include a gate driving circuit 510 .

[0123] The gate drive circuit 510 may include a gate control signal line GCSL, a gate drive voltage line GDVL, and a first-stage circuit ST[1] to an m-th-stage circuit ST[m]. The gate drive circuit 510 may also include a front dummy stage circuit portion DSTP1 disposed at a front end of the first-stage circuit ST[1] and a rear dummy stage circuit portion DSTP2 disposed at a rear end of the m-th-stage circuit ST[m].

[0124] The gate control signal line GCSL receives a gate control signal GCS provided from the timing controller 300. The gate control signal line GCSL according to one embodiment may include a gate start signal line, a first reset signal line, a second reset signal line, a plurality of gate driving clock lines, a display panel turn-on signal line, and a sensing ready signal line.

[0125] The gate start signal line may receive a gate start signal Vst provided from the timing controller 300. For example, the gate start signal line may be connected to the front dummy stage circuit part DSTP1.

[0126] The first reset signal line may receive a first reset signal RST1 provided from the timing controller 300. The second reset signal line may receive a second reset signal RST2 provided from the timing controller 300. For example, each of the first and second reset signal lines may be commonly connected to the front dummy stage circuit portion DSTP1, the first stage circuit ST[1] to the m-th stage circuit ST[m], and the rear dummy stage circuit portion DSTP2.

[0127] The plurality of gate drive clock lines may include a plurality of carry clock lines, a plurality of scan clock lines, and a plurality of sense clock lines that receive a plurality of carry shift clocks, a plurality of scan shift clocks, and a plurality of sense shift clocks, respectively. The clock lines included in the plurality of gate drive clock lines may be selectively connected to the front dummy stage circuit portion DSTP1, the first stage circuit ST[1] to the mth stage circuit ST[m], and the rear dummy stage circuit portion DSTP2.

[0128] The display panel turn-on signal line may receive a display panel turn-on signal POS provided from the timing controller 300. For example, the display panel turn-on signal line may be commonly connected to the front dummy stage circuit part DSTP1 and the first to mth stage circuits ST[1] to ST[m].

[0129] The sensing ready signal line may receive a line sensing ready signal LSPS provided from the timing controller 300. For example, the sensing ready signal line may be commonly connected to the first to m-th stage circuits ST[1] to ST[m]. Alternatively, the sensing ready signal line may be additionally connected to the front dummy stage circuit part DSTP1.

[0130] The gate drive voltage line GDVL may include: first to fourth gate high potential voltage lines, which respectively receive first to fourth gate high potential voltages having corresponding voltage levels different from each other from the power supply circuit; and first to third gate low potential voltage lines, which respectively receive first to third gate low potential voltages having corresponding voltage levels different from each other from the power supply circuit.

[0131] According to one embodiment, the first gate high potential voltage may have a voltage level higher than the voltage level of the second gate high potential voltage. The third and fourth gate high potential voltages may be swung opposite to each other, or inversely relative to each other, to alternate current drive between a high voltage (or TFT on voltage or first voltage) and a low voltage (or TFT off voltage or second voltage). For example, when the third gate high potential voltage (or gate odd high potential voltage) has a high voltage, the fourth gate high potential voltage (or gate even high potential voltage) may have a low voltage. When the third gate high potential voltage has a low voltage, the fourth gate high potential voltage may have a high voltage.

[0132] Each of the first and second gate high potential voltage lines may be commonly connected to the first to m-th stage circuits ST[1] to ST[m], the front dummy stage circuit portion DSTP1, and the rear dummy stage circuit portion DSTP2.

[0133] The third gate high potential voltage line can be commonly connected to the odd-numbered stage circuits of the first stage circuit ST[1] to the mth stage circuit ST[m], and can be commonly connected to the odd-numbered dummy stage circuits of each of the front dummy stage circuit portion DSTP1 and the rear dummy stage circuit portion DSTP2.

[0134] The fourth gate high potential voltage line can be commonly connected to the even-numbered stage circuits of the first stage circuit ST[1] to the mth stage circuit ST[m], and can be commonly connected to the even-numbered dummy stage circuits of each of the front dummy stage circuit portion DSTP1 and the rear dummy stage circuit portion DSTP2.

[0135] According to one embodiment, the first gate low potential voltage and the second gate low potential voltage may have substantially the same voltage level. The third gate low potential voltage may have a TFT off voltage level. The first gate low potential voltage may have a voltage level higher than the voltage level of the third gate low potential voltage. In one embodiment of the present disclosure, the first gate low potential voltage may be set to a voltage level higher than the voltage level of the third gate low potential voltage, whereby the off current of the TFT having a gate electrode connected to a control node of a stage circuit to be described later can be surely cut off to ensure the stability and reliability of the operation of the corresponding TFT.

[0136] The first to third gate low potential voltage lines may be commonly connected to the first-stage circuit ST[1] to the m-th-stage circuit ST[m].

[0137] The front dummy stage circuit part DSTP1 may sequentially generate a plurality of carry signals in response to the gate start signal Vst provided from the timing controller 300 , thereby providing the generated carry signal to any one of the subsequent stages as a carry signal or a gate start signal.

[0138] The post-dummy stage circuit part DSTP2 may sequentially generate a plurality of post-carry signals to provide the post-carry signal (or the stage reset signal) to any one of the previous stages.

[0139] The first stage circuit ST[1] to the m-th stage circuit ST[m] may be connected to each other to be mutually dependent on each other. The first stage circuit ST[1] to the m-th stage circuit ST[m] may generate the first scan signal SC[1] to the m-th scan signal SC[m] and the first sensing signal SE[1] to the m-th sensing signal SE[m], and output the generated signals to the corresponding gate line group GLG provided on the light-emitting display panel 100. The first stage circuit ST[1] to the m-th stage circuit ST[m] may generate the first carry signal CS[1] to the m-th carry signal CS[m], and provide the generated signals to any one of the subsequent stages as a carry signal (or a gate start signal), and at the same time provide the generated signals to any one of the previous stages as a post-carry signal (or a stage reset signal).

[0140] Two adjacent levels ST[n] and ST[n+1] of the first-level circuit ST[1] to the m-th-level circuit ST[m] can share the sensing control circuit and some of the control nodes Qbo, Qbe, and Qm with each other, thereby simplifying the circuit configuration of the gate drive circuit 500 and reducing the area occupied by the gate drive circuit unit 500 in the light-emitting display panel 100.

[0141] Figure 7 is shown applied to Figure 6 1 and 2 show waveforms of signals of the gate control signal line and voltages of control nodes and output signals of each of the first-stage circuit and the second-stage circuit.

[0142] Reference Figure 6 and Figure 7 According to an embodiment of the present disclosure, the gate control signal GCS applied to the gate control signal line may include a gate start signal Vst, a line sensing preparation signal LSPS, a first reset signal RST1, a second reset signal RST2, a display panel turn-on signal POS and a plurality of gate driving clocks GDC.

[0143] The gate start signal Vst is a signal for controlling the start timing of each of the image display period IDP and the black display period BDP of each frame, and can be generated just before each of the image display period IDP and the black display period BDP starts. For example, the gate start signal Vst can be generated twice per frame.

[0144] The gate start signal Vst according to one embodiment may include a first gate start pulse (or image display gate start pulse) Vst1 generated just before the image display period IDP starts within one frame and a second gate start pulse (or black display gate start pulse) Vst2 generated just before the black display period BDP starts.

[0145] The line sensing preparation signal LSPS may be irregularly or randomly generated within the image display period IDP of each frame. Each of the line sensing preparation signals LSPS generated per frame may be different from the start timing of one frame.

[0146] The line sensing preparation signal LSPS according to one embodiment may include a line sensing selection pulse LSP1 and a line sensing release pulse LSP2 .

[0147] The line sensing selection pulse LSP1 may be a signal for selecting any one horizontal line to be sensed among a plurality of horizontal lines. The line sensing selection pulse LSP1 may be synchronized with a carry signal or a gate start pulse provided to any one of the stage circuits ST[1] to ST[m] as a gate start signal. For example, the line sensing selection pulse LSP1 may be represented as a sensing line precharge control signal.

[0148] The line sensing release pulse LSP2 may be a signal for releasing the line sensing of the completely sensed horizontal line. The line sensing release pulse LSP2 may be generated between an end timing of the sensing period RSP and a start timing of the line sensing selection pulse LSP1.

[0149] The first reset signal RST1 may be generated when the sensing mode starts. The second reset signal RST2 may be generated when the sensing mode ends. Optionally, the second reset signal RST2 may be omitted or equal to the first reset signal RST1.

[0150] When the light-emitting display device is powered on, a display panel turn-on signal POS may be generated. The display panel turn-on signal POS may be generally provided to all stage circuits implemented in the gate driving circuit 510. Therefore, all stage circuits implemented in the gate driving circuit 510 may be initialized or reset by the high voltage display panel turn-on signal POS at the same time.

[0151] The plurality of gate driving clocks GDC may include a plurality of carry shift clocks CRCLK[1] to CRCLK[x] having respective phases different from each other or sequentially shifted phases, a plurality of scan shift clocks SCCLK[1] to SCCLK[x] having respective phases different from each other or sequentially shifted phases, and a plurality of sense shift clocks SECLK[1] to SECLK[x] having respective phases different from each other or sequentially shifted phases.

[0152] The carry shift clocks CRCLK[1] to CRCLK[x] may be clock signals for generating carry signals, the scan shift clocks SCCLK[1] to SCCLK[x] may be clock signals for generating scan signals having scan pulses, and the sense shift clocks SECLK[1] to SECLK[x] may be clock signals for generating sense signals having sense pulses.

[0153] Each of the scan shift clocks SCCLK[1] to SCCLK[x] and the sense shift clocks SECLK[1] to SECLK[x] may swing between a high voltage and a low voltage. The swing voltage width of the carry shift clock according to one embodiment may be greater than the switching voltage width of each of the scan shift clocks SCCLK[1] to SCCLK[x] and the sense shift clocks SECLK[1] to SECLK[x].

[0154] For the display mode, each of the scan shift clocks SCCLK[1] to SCCLK[x] and the sense shift clocks SECLK[1] to SECLK[x] may swing. For the sense mode, a specific one of the scan shift clocks SCCLK[1] to SCCLK[x] may swing to correspond to Figure 5 The third scan pulse SCP3 and the fourth scan pulse SCP4 shown in FIG. 1 may be swung to correspond to the third scan pulse SCP3 and the fourth scan pulse SCP4 shown in FIG. 1 , and the other scan shift clocks may be kept at a low voltage. For the sensing mode, a specific one of the sensing shift clocks SECLK[1] to SECLK[x] may swing to correspond to Figure 5 The second scan pulse SCP2 shown in FIG. 1 is used, and the other sensing shift clocks can be kept at a low voltage. These clocks can overlap with each other to ensure sufficient charging time during high-speed driving. The high voltage periods of adjacent clocks can overlap with each other as much as the set period.

[0155] Figure 8 It is shown Figure 6 : block diagram of the nth stage circuit and the (n+1)th stage circuit shown in .

[0156] Reference Figures 6 to 8, the n-th stage circuit ST[n] may be an odd-numbered stage circuit of the first stage circuit ST[1] to the m-th stage circuit ST[m].

[0157] The nth stage circuit ST[n] according to one embodiment may include first to fifth odd control nodes 1Qo, 1Qbo, 1Qbe, 1Qho and 1Qmo, a first sensing control circuit SCC1, a first node control circuit NCC1, a first inverter circuit IC1, a first node reset circuit NRC1 and a first output buffer circuit OBC1.

[0158] The first odd control node 1Qo may be electrically connected to each of the first sensing control circuit SCC1 , the first node control circuit NCC1 , the first inverter circuit IC1 , the first node reset circuit NRC1 , and the first output buffer circuit OBC1 .

[0159] Each of the second odd control node 1Qbo and the third odd control node 1Qbe may be electrically connected to each of the first node control circuit NCC1 , the first inverter circuit IC1 , the first node reset circuit NRC1 , and the first output buffer circuit OBC1 .

[0160] The second odd-numbered control node 1Qbo may be electrically connected to the (n+1)th stage circuit ST[n+1].

[0161] The third odd-numbered control node 1Qbe may be electrically connected to the (n+1)th stage circuit ST[n+1].

[0162] The fourth odd control node 1Qho may be electrically connected to each of the first sensing control circuit SCC1 , the first node control circuit NCC1 , and the first node reset circuit NRC1 .

[0163] The fifth odd control node 1Qmo may be electrically connected to each of the first sensing control circuit SCC1 and the first node reset circuit NRC1, and may be electrically connected to the (n+1)th stage circuit ST[n+1].

[0164] The first sensing control circuit SCC1 may be implemented to control the potential of the fifth odd control node 1Qmo through the first gate high potential voltage GVdd1 in response to the line sensing preparation signal LSPS and the (n-2)th carry signal CS[n-2] (second carry signal), and to control the potential of the first odd control node 1Qo through the first gate high potential voltage GVdd1 in response to the voltage of the fifth odd control node 1Qmo and the first reset signal RST1. The first sensing control circuit SCC1 may be implemented to release or reset the potential of the first odd control node 1Qo through the third gate low potential voltage GVss3 in response to the display panel turn-on signal POS provided when the light emitting display device is powered on.

[0165] The first node control circuit NCC1 may be implemented to control a voltage of each of the first to third odd-numbered control nodes 1Qo, 1Qbo, and 1Qbe.

[0166] The first node control circuit NCC1 may be implemented to control the potential of the first odd control node 1Qo through the first gate high potential voltage GVdd1 in response to the (n-3)th carry signal CS[n-3] (the first carry signal), and may be implemented to control the potential of each of the first odd control node 1Qo and the fourth odd control node 1Qho through the third gate low potential voltage GVss3 in response to the (n+4)th carry signal CS[n+4] (or the second back-carry signal). Alternatively, the first node control circuit NCC1 may be implemented to control the potential of each of the first odd control node 1Qo and the fourth odd control node 1Qho through the third gate low potential voltage GVss3 in response to the (n+3)th carry signal CS[n+3] (or the first back-carry signal).

[0167] The first node control circuit NCC1 may be implemented to control the potential of the fourth odd control node 1Qho by the first gate high potential voltage GVdd1 in response to the voltage of the first odd control node 1Qo. The first node control circuit NCC1 may be implemented to control the potential of each of the first odd control node 1Qo and the fourth odd control node 1Qho by the third gate low potential voltage GVss3 in response to the voltage of the second odd control node 1Qbo or the voltage of the third odd control node 1Qbe.

[0168] The first inverter circuit IC1 may be implemented to control the potential of the second odd control node 1Qbo through the third gate high potential voltage GVddo or the third gate low potential voltage GVss3 in response to the voltage of the first odd control node 1Qo. For example, when the potential of the first odd control node 1Qo is a high voltage or higher, the first inverter circuit IC1 may control the potential of the second odd control node 1Qbo through the third gate low potential voltage GVss3. In addition, the first inverter circuit IC1 may be implemented to control the potential of the second odd control node 1Qbo through the third gate high potential voltage GVddo or the third gate low potential voltage GVss3 in response to the voltage of the first even control node 2Qe of the (n+1)-th stage circuit ST[n+1]. For example, when the potential of the first even control node 2Qe of the (n+1)-th stage circuit ST[n+1] is a low voltage, the first inverter circuit IC1 may control the potential of the second odd control node 1Qbo through the third gate high potential voltage GVddo.

[0169] The first node reset circuit NRC1 may be implemented to control the potential of the second odd control node 1Qbo using the third gate low potential voltage GVss3 in response to the (n-3)th carry signal CS[n-3]. The first node reset circuit NRC1 may be implemented to control the potential of the second odd control node 1Qbo using the third gate low potential voltage GVss3 in response to the voltage of the fifth odd control node 1Qmo and the first reset signal RST1. The first node reset circuit NRC1 may be implemented to control the potential of the first odd control node 1Qo using the third gate low potential voltage GVss3 in response to the voltage of the fifth odd control node 1Qho, the voltage of the fifth odd control node 1Qmo and the second reset signal RST2.

[0170] The first output buffer circuit OBC1 may be implemented to output the nth scan shift clock SCCLK[n] as the nth scan signal SC[n] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo, and 1Qbe. The first output buffer circuit OBC1 may be implemented to output the nth sense shift clock SECLK[n] as the nth sense signal SE[n] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo, and 1Qbe. The first output buffer circuit OBC1 may be implemented to output the nth carry shift clock CRCLK[n] as the nth carry signal CS[n] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo, and 1Qbe.

[0171] According to one embodiment, when the potential of the first odd control node 1Qo is bootstrapped based on the coupling between the boosting capacitor and the clock implemented between the first odd control node 1Qo and the output node, the first output buffer circuit OBC1 can output each of the corresponding scan shift clock SCCLK[n], sense shift clock SECLK[n] and carry shift clock CRCLK[n] to the corresponding output node.

[0172] The (n+1)th stage circuit ST[n+1] according to one embodiment may be an even-numbered stage circuit of the first stage circuit ST[1] to the mth stage circuit ST[m].

[0173] According to one embodiment, the (n+1)th stage circuit ST[n+1] may include first to fifth even control nodes 2Qe, 2Qbo, 2Qbe, 2Qhe and 2Qme, a second sensing control circuit SCC2, a second node control circuit NCC2, a second inverter circuit IC2, a second node reset circuit NRC2 and a second output buffer circuit OBC2.

[0174] The first even control node 2Qe may be electrically connected to each of the second sensing control circuit SCC2 , the second node control circuit NCC2 , the second inverter circuit IC2 , the second node reset circuit NRC2 , and the second output buffer circuit OBC2 .

[0175] Each of the second even control node 2Qbo and the third even control node 2Qbe may be electrically connected to each of the second node control circuit NCC2 , the second inverter circuit IC2 , the second node reset circuit NRC2 , and the second output buffer circuit OBC2 .

[0176] The second even control node 2Qbo can be electrically connected to the third odd control node 1Qbe of the n-th stage circuit ST[n]. Therefore, the third odd control node 1Qbe of the n-th stage circuit ST[n] and the second even control node 2Qbo of the (n+1)-th stage circuit ST[n+1] can be connected or shared with each other.

[0177] The third even control node 2Qbe can be electrically connected to each of the second odd control nodes 1Qbo of the n-th stage circuit ST[n]. Therefore, the second odd control node 1Qbo of the n-th stage circuit ST[n] and the third even control node 2Qbe of the (n+1)-th stage circuit ST[n+1] can be connected or shared with each other.

[0178] The fourth even control node 2Qhe may be electrically connected to each of the second sensing control circuit SCC2 , the second node control circuit NCC2 , and the second node reset circuit NRC2 .

[0179] The fifth even control node 2Qme may be electrically connected to the second node reset circuit NRC2, and may be electrically connected to the fifth odd control node 1Qmo and the first node reset circuit NRC1 of the n-th stage circuit ST[n].

[0180] The second sense control circuit SCC2 may share the potential of the fifth odd control node 1Qmo of the first sense control circuit SCC1 implemented in the n-th stage circuit ST[n]. For example, the second sense control circuit SCC2 may share the following circuit, which is implemented to control the potential of the fifth odd control node 1Qmo using the first gate high potential voltage GVdd1 in response to the line sense preparation signal LSPS and the (n-2)th carry signal CS[n-2] in the first sense control circuit SCC1 implemented in the n-th stage circuit ST[n].

[0181] The second sensing control circuit SCC2 may be implemented to control the potential of the first even control node 2Qe using the first gate high potential voltage GVdd1 provided from the first sensing control circuit SCC1 of the n-th stage circuit ST[n] in response to the first reset signal RST1. The second sensing control circuit SCC2 may be implemented to release or reset the potential of the first even control node 2Qe through the third gate low potential voltage GVss3 in response to the display panel turn-on signal POS provided when the light emitting display device is powered on.

[0182] The second node control circuit NCC2 may be implemented to control a voltage of each of the first to third even-numbered control nodes 2Qe, 2Qbo, and 2Qbe.

[0183] The second node control circuit NCC2 can be implemented to control the potential of the first even control node 2Qe through the first gate high potential voltage GVdd1 in response to the (n-2)th carry signal CS[n-2], and can be implemented to control the potential of each of the first even control node 2Qe and the fourth even control node 2Qhe through the third gate low potential voltage GVss3 in response to the (n+4)th carry signal CS[n+4].

[0184] The second node control circuit NCC2 may be implemented to control the potential of the fourth even control node 2Qhe through the first gate high potential voltage GVdd1 in response to the voltage of the first even control node 2Qe. The second node control circuit NCC2 may be implemented to control the potential of each of the first even control node 2Qe and the fourth even control node 2Qhe through the third gate low potential voltage GVss3 in response to the voltage of the second even control node 2Qbo or the voltage of the third even control node 2Qbe.

[0185] The second inverter circuit IC2 may be implemented to control the potential of the second even control node 2Qbo by the fourth gate high potential voltage GVdde or the third gate low potential voltage GVss3 in response to the voltage of the first even control node 2Qe. For example, when the potential of the first even control node 2Qe is a high voltage or higher, the second inverter circuit IC2 may control the potential of the second even control node 2Qbo by the third gate low potential voltage GVss3. The second inverter circuit IC2 may be implemented to control the potential of the second even control node 2Qbo by the third gate high potential voltage GVddo or the third gate low potential voltage GVss3 in response to the voltage of the first odd control node 1Qo of the n-th stage circuit ST[n]. For example, when the potential of the first odd control node 1Qo of the n-th stage circuit ST[n] is a low voltage, the second inverter circuit IC2 may control the potential of the second even control node 2Qbo by the fourth gate high potential voltage GVdde.

[0186] The second node reset circuit NRC2 may be implemented to control the potential of the second even control node 2Qbo using the third gate low potential voltage GVss3 in response to the (n-3)th carry signal CS[n-3]. The second node reset circuit NRC2 may be implemented to control the potential of the second even control node 2Qbo using the third gate low potential voltage GVss3 in response to the voltage of the fifth even control node 2Qme and the first reset signal RST1. The second node reset circuit NRC2 may be implemented to control the potential of the first even control node 2Qe using the third gate low potential voltage GVss3 in response to the voltage of the fourth even control node 2Qhe, the voltage of the fifth even control node 2Qme and the second reset signal RST2.

[0187] The second output buffer circuit OBC2 may be implemented to output the (n+1)th scan shift clock SCCLK[n+1] as the (n+1)th scan signal SC[n+1] in response to the voltage of each of the first to third even control nodes 2Qe, 2Qbo, and 2Qbe. The second output buffer circuit OBC2 may be implemented to output the (n+1)th sense shift clock SECLK[n+1] as the (n+1)th sense signal SE[n+1] in response to the voltage of each of the first to third even control nodes 2Qe, 2Qbo, and 2Qbe. The second output buffer circuit OBC2 may be implemented to output the (n+1)th carry shift clock CRCLK[n+1] as the (n+1)th carry signal CS[n+1] in response to the voltage of each of the first to third even control nodes 2Qe, 2Qbo, and 2Qbe.

[0188] According to one embodiment, when the potential of the first even control node 2Qe is bootstrapped based on the coupling between the boosting capacitor and the clock implemented between the first even control node 2Qe and the output node, the second output buffer circuit OBC2 can output each of the corresponding scan shift clock SCCLK[n+1], sense shift clock SECLK[n+1] and carry shift clock CRCLK[n+1] to the corresponding output node.

[0189] In a gate drive circuit according to an embodiment of the present disclosure, some circuits including the fifth odd control node 1Qmo in the sensing control circuits SCC1 and SCC2 implemented in the n-th stage circuit ST[n] can be shared with the (n+1)-th stage circuit ST(n+1) adjacent thereto, thereby simplifying the circuit configuration for the sensing mode. In a gate drive circuit according to an embodiment of the present disclosure, the n-th stage circuit ST[n] and the (n+1)-th stage circuit ST[n+1] adjacent to each other can share the second and third control nodes 1Qbo, 1Qbe, 2Qbo and 2Qbe driven alternately with each other, thereby simplifying the configuration of the inverter circuits IC1 and IC2 of the stage circuits.

[0190] At the same time, for the convenience of description, Figure 8 The foregoing description is based on dividing the control nodes implemented in each of the n-th stage circuit ST[n] and the (n+1)-th stage circuit ST[n+1] into odd control nodes and even control nodes, but is not limited thereto. For example, it should be understood that each of the first stage circuit ST[1] to the m-th stage circuit ST[m] includes the first to fifth control nodes.

[0191] Fig. 9 It is shown Figure 8 : A circuit diagram of the nth stage circuit and the (n+1)th stage circuit shown in FIG.

[0192] Reference Figures 7 to 9 , the n-th stage circuit ST[n] according to one embodiment of the present disclosure may include a first sensing control circuit SCC1 selectively connected to first to fifth odd control nodes 1Qo, 1Qbo, 1Qbe, 1Qho and 1Qmo, a first node control circuit NCC1, a first inverter circuit IC1, a first node reset circuit NRC1 and a first output buffer circuit OBC1.

[0193] The first node control circuit NCC1 according to one embodiment may include first to tenth TFTs T1 to T10.

[0194] The first to fourth TFTs T1, T2, T3a, T3b, T4a, and T4b are used to control or set the potential of the first odd-numbered control node 1Qo, and thus may be represented as a first node setting circuit.

[0195] The first TFT T1 and the second TFT T2 may be electrically connected in series between a first gate high potential voltage line for transmitting the first gate high potential voltage GVdd1 and the first odd control node 1Qo, and may be implemented to charge the first gate high potential voltage GVdd1 in the first odd control node 1Qo in response to the (n-3)th carry signal CS[n-3].

[0196] In this case, the (n-3)th carry signal CS[n-3] may be the first carry signal.

[0197] The first TFT T1 may output the first gate high potential voltage GVdd1 to the first connection node Nc1 in response to the (n-3)th carry signal CS[n-3] provided through the carry input line. For example, the first TFT T1 may be turned on according to the high voltage (n-3)th carry signal CS[n-3] to output the first gate high potential voltage GVdd1 to the first connection node Nc1.

[0198] The second TFT T2 may electrically connect the first connection node Nc1 to the first odd control node 1Qo in response to the (n-3)th carry signal CS[n-3]. For example, the second TFT T2 may be turned on simultaneously with the first TFT T1 according to the (n-3)th carry signal CS[n-3] of a high voltage to provide the first gate high potential voltage GVdd1 provided through the first connection node Nc1 to the first odd control node 1Qo.

[0199] The third TFTs T3a and T3b may provide the second gate high potential voltage GVdd2 to the first connection node Nc1 in response to the second gate high potential voltage GVdd2. For example, the third TFTs T3a and T3b may be turned on according to the second gate high potential voltage GVdd2 to always provide the second gate high potential voltage GVdd2 to the first connection node Nc1 between the first TFT T1 and the second TFT T2, thereby preventing the turn-off current of the first TFT T1 and the current leakage of the first odd control node 1Qo from occurring. For example, the third TFTs T3a and T3b may completely turn off the first TFT T1 turned off by the (n-3)th carry signal CS[n-3] having a low voltage by increasing the voltage difference between the gate voltage of the first TFT T1 and the first connection node Nc1. Therefore, the voltage drop (or current leakage) of the first odd control node 1Qo due to the turn-off current of the turned-off first TFT T1 may be prevented, thereby stably maintaining the voltage of the first odd control node 1Qo. For example, when the threshold voltage of the first TFT T1 has a negative polarity (-), the gate-source voltage Vgs of the first TFT T1 can be fixed to a negative polarity (-) by the second gate high potential voltage GVdd2 provided to the drain electrode. For this reason, the turned-off first TFT T1 can be turned into a completely turned-off state, thereby preventing the occurrence of current leakage based on the turn-off current.

[0200] The second gate high potential voltage GVdd2 is set to a voltage level lower than the first gate high potential voltage GVdd1. The resistance of the second gate high potential voltage GVdd2 is set to be higher than the resistance of the first gate high potential voltage GVdd1 to reduce the voltage drop of the first gate high potential voltage GVdd1. The second gate high potential voltage line for providing the second gate high potential voltage GVdd2 can be used as a path through which the leakage current of the third TFTs T3a and T3b flows, thereby reducing the voltage drop of the first gate high potential voltage GVdd1. Therefore, in one embodiment of the present disclosure, the first gate high potential voltage line and the second gate high potential voltage line can be separated from each other to independently configure the voltage drop components of the first gate high potential voltage line and the second gate high potential voltage line, thereby minimizing the voltage drop of the first gate high potential voltage line. Therefore, the erroneous operation of the gate drive circuit caused by the voltage drop of the first gate high potential voltage line can be avoided.

[0201] The third TFTs T3a and T3b according to one embodiment may include a (3-1)th TFT T3a and a (3-2)th TFT T3b electrically connected in series to each other between the second gate high potential voltage line and the first connection node Nc1 to prevent leakage current from occurring due to an off current.

[0202] The (3-1)th TFT T3a may be turned on by the second gate high potential voltage GVdd2 to provide the second gate high potential voltage GVdd2 to the (3-2)th TFT T3b. For example, the (3-1)th TFT T3a may be connected to the second gate high potential voltage line in the form of a diode.

[0203] The (3-2)th TFT T3b may be turned on by the second gate high potential voltage GVdd2 simultaneously with the (3-1)th TFT T3a to supply the second gate high potential voltage GVdd2 supplied through the (3-1)th TFT T3a to the first connection node Nc1.

[0204] The fourth TFTs T4a and T4b may provide the first gate high potential voltage GVdd1 to the fourth odd control node 1Qho in response to the first odd control node 1Qo. For example, the fourth TFTs T4a and T4b may be turned on according to the high voltage of the first odd control node 1Qo to provide the first gate high potential voltage GVdd1 to the fourth odd control node 1Qho.

[0205] The fourth TFTs T4a and T4b according to one embodiment may include a (4-1)th TFT T4a and a (4-2)th TFT T4b electrically connected in series to each other between the first gate high potential voltage line and the fourth odd control node 1Qho to prevent leakage current from occurring due to an off current.

[0206] The (4-1)th TFT T4a may be turned on by the high voltage of the first odd-numbered control node 1Qo to supply the first gate high potential voltage GVdd1 to the (4-2)th TFT T4b.

[0207] The (4-2)th TFT T4b may be turned on by the high voltage of the first odd control node 1Qo simultaneously with the (4-1)th TFT T4a to supply the first gate high potential voltage GVdd1 supplied through the (4-1)th TFT T4a to the fourth odd control node 1Qho.

[0208] The fifth TFT T5 and the sixth TFT T6 may be implemented to control the potential of each of the first odd control node 1Qo and the fourth odd control node 1Qho by the third gate low potential voltage GVss3 in response to the (n+4)th carry signal CS[n+4]. The fifth TFT T5 and the sixth TFT T6 may be represented as a first odd discharge circuit.

[0209] The fifth TFT T5 may be implemented to control the potential of the fourth odd control node 1Qho through the third gate low potential voltage GVss3 in response to the (n+4)th carry signal CS[n+4]. For example, the fifth TFT T5 may be turned on according to the high voltage (n+4)th carry signal CS[n+4] to discharge or reset the potential of the fourth odd control node 1Qho to the third gate low potential voltage GVss3.

[0210] The sixth TFT T6 may electrically connect the first odd control node 1Qo with the fourth odd control node 1Qho in response to the (n+4)th carry signal CS[n+4]. For example, the sixth TFT T6 may be turned on simultaneously with the fifth TFT T5 according to the (n+4)th carry signal CS[n+4] of the high voltage to provide the third gate low potential voltage GVss3 provided through the fifth TFT T5 and the fourth odd control node 1Qho to the first odd control node 1Qo, thereby discharging or resetting the potential of the first odd control node 1Qo to the third gate low potential voltage GVss3.

[0211] The fourth odd control node 1Qho between the fifth TFT T5 and the sixth TFT T6 can be provided with the first gate high potential voltage GVdd1 through the fourth TFTs T4a and T4b. Therefore, the fourth TFTs T4a and T4b can completely turn off the sixth TFT T6 turned off by the (n+4)th carry signal CS[n+4] of the low voltage by increasing the voltage difference between the gate voltage of the sixth TFT T6 and the fourth odd control node 1Qho. Therefore, the voltage drop (or current leakage) of the first odd control node 1Qo through the turned-off sixth TFT T6 can be prevented from occurring, thereby stably maintaining the voltage of the first odd control node 1Qo.

[0212] The seventh and eighth TFTs T7 and T8 may be implemented to control the potential of each of the first and fourth odd control nodes 1Qo and 1Qho by the third gate low potential voltage GVss3 in response to the voltage of the second odd control node 1Qbo. The seventh and eighth TFTs T7 and T8 may be represented as a second odd discharge circuit.

[0213] The seventh TFT T7 may be implemented to control the potential of the fourth odd control node 1Qho through the third gate low potential voltage GVss3 in response to the voltage of the second odd control node 1Qbo. For example, the seventh TFT T7 may be turned on according to the high voltage of the second odd control node 1Qbo to discharge or reset the potential of the fourth odd control node 1Qho to the third gate low potential voltage GVss3.

[0214] The eighth TFT T8 may electrically connect the first odd control node 1Qo to the fourth odd control node 1Qho in response to the voltage of the second odd control node 1Qbo. For example, the eighth TFT T8 may be turned on by the high voltage of the second odd control node 1Qbo at the same time as the seventh TFT T7 to provide the third gate low potential voltage GVss3 provided through the seventh TFT T7 and the fourth odd control node 1Qho to the first odd control node 1Qo, thereby discharging or resetting the potential of the first odd control node 1Qo to the third gate low potential voltage GVss3.

[0215] The fourth odd control node 1Qho between the seventh TFT T7 and the eighth TFT T8 can be provided with the first gate high potential voltage GVdd1 through the fourth TFTs T4a and T4b. Therefore, the fourth TFTs T4a and T4b can completely turn off the eighth TFT T8 turned off by the (n+4)th carry signal CS[n+4] of the low voltage by increasing the voltage difference between the gate voltage of the eighth TFT T8 and the fourth odd control node 1Qho. Therefore, the voltage drop (or current leakage) of the first odd control node 1Qo through the turned-off eighth TFT T8 can be prevented from occurring, thereby stably maintaining the voltage of the first odd control node 1Qo.

[0216] The ninth TFT T9 and the tenth TFT T10 may be implemented to control the potential of each of the first odd control node 1Qo and the fourth odd control node 1Qho by the third gate low potential voltage GVss3 in response to the voltage of the third odd control node 1Qbe. The ninth TFT T9 and the tenth TFT T10 may be represented as a third odd discharge circuit.

[0217] The ninth TFT T9 may be implemented to control the potential of the fourth odd control node 1Qho by the third gate low potential voltage GVss3 in response to the voltage of the third odd control node 1Qbe. For example, the ninth TFT T9 may be turned on according to the high voltage of the third odd control node 1Qbe to discharge or reset the potential of the fourth odd control node 1Qho to the third gate low potential voltage GVss3.

[0218] The tenth TFT T10 may electrically connect the first odd control node 1Qo with the fourth odd control node 1Qho in response to the voltage of the third odd control node 1Qbe. For example, the tenth TFT T10 may be turned on by the high voltage of the third odd control node 1Qbe simultaneously with the ninth TFT T9 to provide the third gate low potential voltage GVss3 provided through the ninth TFT T9 and the fourth odd control node 1Qho to the first odd control node 1Qo, thereby discharging or resetting the potential of the first odd control node 1Qo to the third gate low potential voltage GVss3.

[0219] The fourth odd control node 1Qho between the ninth TFT T9 and the tenth TFT T10 can be provided with the first gate high potential voltage GVdd1 through the fourth TFTs T4a and T4b. Therefore, the fourth TFTs T4a and T4b can completely turn off the tenth TFT T10 turned off by the (n+4)th carry signal CS[n+4] of the low voltage by increasing the voltage difference between the gate voltage of the tenth TFT T10 and the fourth odd control node 1Qho. Therefore, the voltage drop (or current leakage) of the first odd control node 1Qo through the turned-off tenth TFT T10 can be prevented from occurring, thereby stably maintaining the voltage of the first odd control node 1Qo.

[0220] The first converter circuit IC1 according to one embodiment may include 11th to 15th TFTs T11a, T11b, T12, T13, T14, and T15.

[0221] The 11th TFTs T11a and T11b may provide the third gate high potential voltage GVddo to the second connection node Nc2 in response to the third gate high potential voltage GVddo. The 11th TFTs T11a and T11b according to one embodiment may include (11-1)th and (11-2)th TFTs T11a and T11b, which are electrically connected in series to each other between the third gate high potential voltage line and the second connection node Nc2 to prevent leakage current due to an off current from occurring.

[0222] The (11-1)th TFT T11a may be turned on by the third gate high potential voltage GVddo to provide the third gate high potential voltage GVddo to the (11-2)th TFT T11b. For example, the (11-1)th TFT T11a may be connected to the third gate high potential voltage line in the form of a diode.

[0223] The (11-2)th TFT T11b may be turned on by the third gate high potential voltage GVddo simultaneously with the (11-1)th TFT T11a to supply the third gate high potential voltage GVddo supplied through the (11-1)th TFT T11a to the second connection node Nc2.

[0224] The 12th TFT T12 may be turned on or off according to the voltage of the second connection node Nc2, and may provide the third gate high potential voltage GVddo to the second odd-numbered control node 1Qbo when it is turned on.

[0225] The 13th TFT T13 may be turned on or off according to the voltage of the first odd control node 1Qo, and may discharge or reset the potential of the second odd control node 1Qbo to the third gate low potential voltage GVss3 when it is turned on.

[0226] The 14th TFT T14 may be turned on or off according to the voltage of the first odd control node 1Qo, and may discharge or reset the potential of the second connection node Nc2 to the second gate low potential voltage GVss2 when it is turned on.

[0227] The 15th TFT T15 may be turned on or off according to the voltage of the first even control node 2Qe of the (n+1)th stage circuit ST[n+1], and may discharge or reset the potential of the second connection node Nc2 to the second gate low potential voltage GVss2 when it is turned on.

[0228] The first sensing control circuit SCC1 according to one embodiment may include 16th to 22nd TFTs T16 to T22 and a pre-charge capacitor Cpc.

[0229] The 16th to 18th TFTs T16 to T18 and the precharge capacitor Cpc may be implemented to control the fifth odd control node 1Qmo through the (n-2)th carry signal CS[n-2] in response to the line sensing preparation signal LSPS and the (n-2)th carry signal CS[n-2]. The 16th to 18th TFTs T16 to T18 and the precharge capacitor Cpc may be represented as a line sensing precharge circuit or a line sensing preparation circuit for precharging the voltage of the fifth odd control node 1Qmo in the display mode. For example, the fifth odd control node 1Qmo may be represented as a storage node or a precharge node for the sensing mode.

[0230] The 16th TFT T16 may output the (n-2)th carry signal CS[n-2] to the third connection node Nc3 in response to the line sensing preparation signal LSPS. For example, in the image display mode, the 16th TFT T16 may be turned on according to the line sensing selection pulse LSP1 transmitted through the sensing preparation signal line to output the (n-2)th carry signal CS[n-2] of a high voltage synchronized with the line sensing selection pulse LSP1 to the third connection node Nc3. In the image display mode, the 16th TFT T16 may be turned on according to the line sensing release pulse LSP2 transmitted through the sensing preparation signal line to output the (n-2)th carry signal CS[n-2] of a low voltage to the third connection node Nc3.

[0231] The 17th TFT T17 may electrically connect the third connection node Nc3 to the fifth odd control node 1Qmo in response to the line sensing preparation signal LSPS. For example, the 17th TFT T17 may be turned on simultaneously with the 16th TFT T16 according to the line sensing preparation signal LSP of a high voltage to provide the (n-2)th carry signal CS[n-2] provided through the 17th TFT T17 and the third connection node Nc3 to the fifth odd control node 1Qmo. The third connection node Nc3 may be a connection line between the 16th TFT T16 and the 17th TFT T17.

[0232] The 18th TFT T18 may provide the first gate high potential voltage GVdd1 to the third connection node Nc3 in response to the voltage of the fifth odd control node 1Qmo. For example, the 18th TFT T18 may be turned on according to the high voltage of the fifth odd control node 1Qmo to provide the first gate high potential voltage GVdd1 to the third connection node Nc3, thereby preventing the voltage leakage of the fifth odd control node 1Qmo from occurring. For example, the 18th TFT T18 may turn off the 16th TFT T16 turned off by the line sensing preparation signal LSPS of the low voltage by increasing the voltage difference between the gate voltage of the 16th TFT T16 and the third connection control node Nc3. Therefore, the voltage drop (or current leakage) of the fifth odd control node 1Qmo through the turned-off 16th TFT T16 may be prevented from occurring, thereby stably maintaining the voltage of the fifth odd control node 1Qmo.

[0233] A precharge capacitor Cpc may be formed between the fifth odd control node 1Qmo and the first gate high potential voltage line to store a differential voltage between the voltage of the fifth odd control node 1Qmo and the first gate high potential voltage GVdd1. For example, a first electrode of the precharge capacitor Cpc may be electrically connected to the fifth odd control node 1Qmo connected to the gate electrode of the 18th TFT T18, and a second electrode of the precharge capacitor Cpc may be electrically connected to the fifth gate high potential voltage line. The precharge capacitor Cpc stores a high voltage of the (n-2)th carry signal CS[n-2] according to the turning on of the 16th, 17th, and 18th TFTs T16, T17, and T18, and maintains the voltage of the fifth odd control node 1Qmo for a certain period of time by the voltage stored when the 16th, 17th, and 18th TFTs T16, T17, and T18 are turned off. For example, the voltage of the fifth odd-numbered control node 1Qmo may be maintained until the 16th and 17th TFTs T16 and T17 are turned on again by the line sensing release pulse LSP2 of the line sensing preparation signal LSPS.

[0234] The 19th and 20th TFTs T19 and T20 may be implemented to control the potential of the first odd control node 1Qo by the first gate high potential voltage GVdd1 in response to the voltage of the fifth odd control node 1Qmo and the first reset signal RST1. The 19th and 20th TFTs T19 and T20 may be expressed as a sensing line selection circuit.

[0235] The 19th TFT T19 may output the first gate high potential voltage GVdd1 to the shared node Ns in response to the voltage of the fifth odd control node 1Qmo. For example, the 19th TFT T19 may be turned on according to the high voltage of the fifth odd control node 1Qmo precharged with the first gate high potential voltage GVdd1 to provide the first gate high potential voltage GVdd1 to the shared node Ns.

[0236] The 20th TFT T20 may electrically connect the 19th TFT T19 to the first odd control node 1Qo in response to the first reset signal RST1. For example, the 20th TFT T20 may be turned on according to the first reset signal RST1 of a high voltage to supply the first gate high potential voltage GVdd1 supplied through the 19th TFT T19 and the shared node Ns to the first odd control node 1Qo, thereby charging the first gate high potential voltage GVdd1 in the first odd control node 1Qo to activate the first odd control node 1Qo.

[0237] The 21st and 22nd TFTs T21 and T22 may be implemented to discharge or reset the potential of the first odd control node 1Q0 to the third gate low potential voltage GVss3 in response to the display panel turn-on signal POS provided when the light emitting display device is powered on. The 21st and 22nd TFTs T21 and T22 may be represented as a first stage initialization circuit.

[0238] The 21st TFT T21 may provide the third gate low potential voltage GVss3 provided through the third gate low potential voltage line to the fourth odd control node 1Qho in response to the display panel turn-on signal POS. For example, the 21st TFT T21 may be turned on according to the high voltage display panel turn-on signal POS to discharge or reset the potential of the fourth odd control node 1Qo to the third gate low potential voltage GVss3.

[0239] The 22nd TFT T22 may electrically connect the first odd control node 1Qo with the fourth odd control node 1Qho in response to the display panel turn-on signal POS. For example, the 22nd TFT T22 may be turned on simultaneously with the 21st TFT T21 according to the high voltage display panel turn-on signal POS to provide the third gate low potential voltage GVss3 provided through the 21st TFT T21 and the fourth odd control node 1Qho to the first odd control node 1Qo, thereby charging or resetting the potential of the first odd control node 1Qo to the third gate low potential voltage GVss3.

[0240] The first gate high potential voltage GVdd1 may be provided to the fourth odd control node 1Qho between the 21st TFT T21 and the 22nd TFT T22 through the fourth TFT T4a and T4b of the first control circuit NCC1. Therefore, the fourth TFT T4a and T4b may completely turn off the 22nd TFT T22 turned off by the display panel turn-on signal POS of the low voltage by increasing the voltage difference between the gate voltage of the 22nd TFT TFT22 and the fourth odd control node 1Qho. Therefore, the voltage drop (or current leakage) of the first odd control node 1Q0 through the turned-off 22nd TFT T22 may be prevented from occurring, thereby stably maintaining the voltage of the first odd control node 1Q0.

[0241] Optionally, the first sensing control circuit SCC1 may be omitted. That is, since the first sensing control circuit SCC1 is a circuit for sensing the driving characteristics of the pixel according to the sensing mode, if the pixel is not driven in the sensing mode, the first sensing control circuit SCC1 is an unnecessary element and thus may be omitted.

[0242] The first node reset circuit NRC1 according to one embodiment may include 23rd to 28th TFTs T21 to T28.

[0243] The 23rd TFT T23 may be implemented to control the potential of the second odd control node 1Qbo by the third gate low potential voltage GVss3 in response to the (n-3)th carry signal CS[n-3]. The 23rd TFT T23 may be denoted as a (1-1)th reset circuit.

[0244] In the display mode, the 23rd TFT T23 may be turned on according to the (n-3)th carry signal CS[n-3] of a high voltage to discharge or reset the potential of the second odd control node 1Qbo to the third gate low potential voltage GVss3.

[0245] The 24th and 25th TFTs T24 and T25 may be implemented to control the potential of the second odd control node 1Qbo through the third gate low potential voltage GVss3 in response to the voltage of the fifth odd control node 1Qmo and the first reset signal RST1. The 24th and 25th TFTs T24 and T25 may be denoted as a (1-2)th reset circuit.

[0246] The 24th TFT T24 may provide the third gate low potential voltage GVss3 to the fourth connection node Nc4 in response to the fifth odd control node 1Qmo. For example, the 24th TFT T24 may be turned on according to the high voltage of the fifth odd control node 1Qmo to provide the third gate low potential voltage GVss3 to the fourth connection node Nc4.

[0247] The 25th TFT T25 may electrically connect the second odd control node 1Qbo to the fourth connection node Nc4 in response to the first reset signal RST1. For example, the 25th TFT T25 may be turned on according to the first reset signal RST1 of a high voltage to provide the third gate low potential voltage GVss3 provided through the 24th TFT T24 and the fourth connection node Nc4 to the second odd control node 1Qbo. The fourth connection node Nc4 may be a connection line between the 24th TFT T24 and the 25th TFT T25.

[0248] The 26th to 28th TFTs T26, T27, and T28 may be implemented as: in the sensing mode, in response to the voltage of the fourth odd control node 1Qho, the voltage of the fifth odd control node 1Qmo, and the second reset signal RST2, the potential of the first odd control node 1Qo is controlled using the third gate low potential voltage GVss3. The 26th to 28th TFTs T26, T27, and T28 may be represented as a fourth odd discharge circuit.

[0249] In response to the voltage of the fourth odd control node 1Qho, the voltage of the fifth odd control node 1Qmo and the second reset signal RST2, the 26th to 28th TFTs T26, T27 and T28 can be electrically connected in series between the first odd control node 1Qo and the fourth connection node Nc4, and electrically connect the first odd control node 1Qo with the fourth connection node Nc4.

[0250] The 26th TFT T26 may electrically connect the first odd control node 1Qo with the fifth connection node Nc5 in response to the second reset signal RST2. For example, the 26th TFT T26 may be turned on according to the high voltage second reset signal RST2 to electrically connect the first odd control node 1Qo with the fifth connection node Nc5.

[0251] The 27th TFT T27 may electrically connect the fifth connection node Nc5 with the fourth odd control node 1Qho in response to the voltage of the fifth odd control node 1Qmo. For example, the 27th TFT T27 may be turned on according to the high voltage of the fifth odd control node 1Qmo to electrically connect the fifth connection node Nc5 with the fourth odd control node 1Qho.

[0252] The 28th TFT T28 may electrically connect the fourth odd control node 1Qho with the fourth connection node Nc4 in response to the second reset signal RST2. For example, the 28th TFT T28 may be turned on according to the high voltage second reset signal RST2 to electrically connect the fourth odd control node 1Qho with the fourth connection node Nc4.

[0253] Meanwhile, when the first sensing control circuit SCC1 is omitted, the 24th to 28th TFTs T24, T25, T26, T27, and T28 may be omitted.

[0254] The first output buffer circuit OBC1 according to one embodiment may include 29th to 37th TFTs T29 to T37 and first to third coupling capacitors Cc1, Cc2, and Cc3.

[0255] The 29th to 31st TFTs T29, T30, and T31 and the first coupling capacitor Ccl may output the nth scan shift clock SCCLK[n] as the nth scan signal SC[n] in response to the voltages of the first to third odd-numbered control nodes 1Qo, 1Qbo, and 1Qbe. The 29th to 31st TFTs T29, T30, and T31 and the first coupling capacitor Ccl may be represented as a scan output circuit.

[0256] The 29th TFT T29 (or the first odd pull-up TFT) may output the nth scan signal SC[n] having a scan pulse of a high voltage corresponding to the nth scan shift clock SCCLK[n] to the first output node No1 according to the voltage of the first odd control node 1Qo, so as to provide the scan pulse of the nth scan signal SC[n] to the first gate line of the nth gate line group. For example, the 29th TFT T29 may include a gate electrode connected to the first odd control node 1Qo, a first source / drain electrode connected to the first output node No1 (or the scan output terminal), and a second source / drain electrode connected to the nth scan clock line.

[0257] According to one embodiment, Figure 3As shown in, based on the nth scan shift clock SCCLK[n], the 29th TFT T29 can provide the first scan pulse SCP1 to the first gate line of the nth gate line group in the image display period of the display mode, and can provide the second scan pulse SCP2 to the first gate line of the nth gate line group in the black display period of the display mode. In the sensing mode, when the driving characteristics of the pixels implemented in the nth horizontal line are sensed, the 29th TFT T29 can additionally provide the third scan pulse SCP3 and the fourth scan pulse SCP4 to the first gate line of the nth gate line group in the sensing period RSP based on the nth scan shift clock SCCLK[n].

[0258] The 30th TFT T30 (or the (1-1)th odd pull-down TFT) may output the nth scan signal SC[n] of a low voltage corresponding to the first gate low potential voltage GVss1 to the first output node No1 according to the voltage of the second odd control node 1Qbo, so as to provide the nth scan signal SC[n] of the low voltage to the first gate line of the nth gate line group. For example, the 30th TFT T30 may include a gate electrode connected to the second odd control node 1Qbo, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to the first gate low potential voltage line.

[0259] The 31st TFT T34 (or the (1-2)th odd pull-down TFT) may output the nth scan signal SC[n] of the low voltage corresponding to the first gate low potential voltage GVss1 to the first output node No1 according to the voltage of the third odd control node 1Qbe, so as to provide the nth scan signal SC[n] of the low voltage to the first gate line of the nth gate line group. For example, the 31st TFT T31 may include a gate electrode connected to the third odd control node 1Qbe, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to the first gate low potential voltage line.

[0260] Since the time that the 30th TFT T30 and the 31st TFT T31 are maintained in the on state is relatively longer than the time that the 29th TFT T29 is maintained in the on state, the degradation speed may be relatively faster than the degradation speed of the 29th TFT T29. Therefore, the 30th TFT T30 and the 31st TFT T31 according to the present disclosure may be alternately driven on a specific time period basis according to the opposite voltage of each of the second odd control node 1Qbo and the third odd control node 1Qbe, so that the degradation speed may be delayed. For example, when the 30th TFT T30 is maintained in the on state, the 31st TFT T31 may be maintained in the off state. Conversely, when the 30th TFT T30 is maintained in the off state, the 31st TFT T31 may be maintained in the on state.

[0261] The first coupling capacitor Ccl may be implemented between the first odd control node 1Qo and the first output node No1. Alternatively, the first coupling capacitor Cc1 may be implemented by a parasitic capacitance between the gate electrode of the 29th TFT T29 and the first output node No1. The first coupling capacitor Cc1 generates a bootstrap in the first odd control node 1Qo according to the phase shift (or change) of the nth scan shift clock SCCLK[n], whereby the 29th TFT T29 may be fully turned on. Therefore, the nth scan shift clock SCCLK[n] of a high voltage may be output to the first output node No1 through the 29th TFT T29 that is fully turned on without loss.

[0262] The 32nd to 34th TFTs T32, T33, and T34 and the second coupling capacitor Cc2 may be implemented to output the nth sensing shift clock SECLK[n] as the nth sensing signal SE[n] in response to the first to third odd-numbered control nodes 1Qo, 1Qbo, and 1Qbe. The 32nd to 34th TFTs T32, T33, and T34 and the second coupling capacitor Cc2 may be represented as a sensing output circuit.

[0263] The 32nd TFT T32 (or the second odd pull-up TFT) may output the nth sensing signal SE[n] having a sensing pulse of a high voltage corresponding to the nth sensing shift clock SECLK[n] to the second output node No2 according to the voltage of the first odd control node 1Qo, so as to provide the sensing pulse of the nth sensing signal SE[n] to the second gate line of the nth gate line group. For example, the 32nd TFT T32 may include a gate electrode connected to the first odd control node 1Qo, a first source / drain electrode connected to the second output node No2 (or the sensing output terminal), and a second source / drain electrode connected to the nth sensing clock line.

[0264] According to one embodiment, Figure 3 As shown in , based on the nth sensing shift clock SECLK[n], the 32nd TFT T32 can provide the first sensing pulse SEP1 to the second gate line of the nth gate line group in the image display period of the display mode. In the sensing mode, when the driving characteristics of the pixels implemented in the nth horizontal line are sensed, the 32nd TFT T32 can additionally provide the second sensing pulse SEP2 to the second gate line of the nth gate line group in the sensing period RSP based on the nth sensing shift clock SECLK[n].

[0265] The 33rd TFT T33 (or the (2-1)th odd pull-down TFT) may output the nth sensing shift clock SECLK[n] of a low voltage corresponding to the first gate low potential voltage GVss1 to the second output node No2 according to the voltage of the second odd control node 1Qbo, so as to provide the nth sensing shift clock SECLK[n] of a low voltage to the second gate line of the nth gate line group. For example, the 33rd TFT T33 may include a gate electrode connected to the second odd control node 1Qbo, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the first gate low potential voltage line.

[0266] The 34th TFT T34 (or the (2-2)th odd pull-down TFT) may output the nth sensing shift clock SECLK[n] of a low voltage corresponding to the first gate low potential voltage GVss1 to the second output node No2 according to the voltage of the third odd control node 1Qbe, so as to provide the nth sensing shift clock SECLK[n] of a low voltage to the second gate line of the nth gate line group. For example, the 34th TFT T34 may include a gate electrode connected to the third odd control node 1Qbe, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the first gate low potential voltage line.

[0267] The 33rd TFT T33 and the 34th TFT T34 according to the present disclosure may be alternately driven on a specific period basis according to the opposite voltage of each of the second odd control node 1Qbo and the third odd control node 1Qbe, whereby the degradation speed may be delayed.

[0268] The second coupling capacitor Cc2 may be implemented between the first odd control node 1Qo and the second output node No2. Alternatively, the second coupling capacitor Cc2 may be implemented by a parasitic capacitance between the gate electrode of the 32nd TFT T32 and the second output node No2. The second coupling capacitor Cc2 generates a bootstrap in the first odd control node 1Qo according to the phase shift (or change) of the nth sensing shift clock SECLK[n], whereby the 32nd TFT T32 may be fully turned on. Therefore, the nth sensing shift clock SECLK[n] of a high voltage may be output to the second output node No2 through the 32nd TFT T32 that is fully turned on without loss.

[0269] The 35th to 37th TFTs T35, T36, and T37 and the third coupling capacitor Cc3 may be implemented to output the nth carry shift clock CRCLK[n] as the nth carry signal CS[n] in response to the voltages of the first to third odd-numbered control nodes 1Qo, 1Qbo, and 1Qbe. The 35th to 37th TFTs T35, T36, and T37 and the third coupling capacitor Cc3 may be represented as a carry output circuit.

[0270] The 35th TFT T35 (or the third odd pull-up TFT) can output the nth carry signal CS[n] having a carry pulse of a high voltage corresponding to the nth carry shift clock CRCLK[n] to the third output node No3 according to the voltage of the first odd control node 1Qo, so as to provide the nth carry signal CS[n] of the high voltage to the previous stage circuit or the next stage circuit. According to one embodiment, based on the nth carry shift clock CRCLK[n], the 35th TFT T35 can output the nth carry signal CS[n] to the previous stage circuit or the next stage circuit based on the nth carry shift clock CRCLK[n] in the display mode. For example, the 35th TFT T35 may include a gate electrode connected to the first odd control node 1Qo, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the nth carry clock line.

[0271] The 36th TFT T36 (or the (3-1)th odd pull-down TFT) may output the low voltage n-carry signal CS[n] corresponding to the first gate low potential voltage GVss1 to the third output node No3 according to the voltage of the second odd control node 1Qbo, so as to provide the low voltage n-carry signal CS[n] to the previous stage circuit or the next stage circuit. For example, the 36th TFT T36 may include a gate electrode connected to the second odd control node 1Qbo, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate low potential voltage line.

[0272] The 37th TFT T37 (or the (3-2)th odd pull-down TFT) may output the low voltage n-carry signal CS[n] corresponding to the first gate low potential voltage GVss1 to the third output node No3 according to the voltage of the third odd control node 1Qbe, so as to provide the low voltage n-carry signal CS[n] to the previous stage circuit or the next stage circuit. For example, the 37th TFT T37 may include a gate electrode connected to the third odd control node 1Qbe, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate low potential voltage line.

[0273] The 36th TFT T36 and the 37th TFT T37 according to the present disclosure may be alternately driven on a specific period basis according to the opposite voltage of each of the second odd control node 1Qbo and the third odd control node 1Qbe, whereby the degradation speed may be delayed.

[0274] The third coupling capacitor Cc3 may be implemented between the first odd control node 1Qo and the third output node No3. Alternatively, the third coupling capacitor Cc3 may be implemented by a parasitic capacitance between the gate electrode of the 35th TFT T35 and the third output node No3. The third coupling capacitor Cc3 generates a bootstrap in the first odd control node 1Qo according to the phase shift (or change) of the n-th shift clock CRCLK[n], whereby the 35th TFT T35 may be fully turned on. Therefore, the high voltage n-th shift clock CRCLK[n] may be output to the third output node No3 through the 35th TFT T35 that is fully turned on without loss.

[0275] The first and second coupling capacitors Ccl and Cc2 of the first to third coupling capacitors Ccl, Cc2, and Cc3 may generate coupling between the scan output circuit and the sense output circuit, or may be used as a holding capacitor. In this case, the potential of the first odd-numbered control node 1Qo may be reduced, whereby the driving characteristics and reliability of the gate drive circuit may be degraded. Therefore, in order to prevent coupling between the scan output circuit and the sense output circuit, any one of the first coupling capacitor Cc1 and the second coupling capacitor Cc2 may be omitted. For example, the first coupling capacitor Cc1 of the first coupling capacitor Cc1 and the second coupling capacitor Cc2 may be omitted.

[0276] The (n+1)th stage circuit ST[n+1] according to one embodiment of the present disclosure may include a second sense control circuit SCC2, a second node control circuit NCC2, a second converter circuit IC2, a second node reset circuit NRC2, and a second output buffer circuit OBC2, which are selectively connected to the first to fifth even control nodes 2Qe, 2Qbo, 2Qbe, 2Qhe, and 2Qme. Except for the second sense control circuit SCC2, the (n+1)th stage circuit ST[n+1] may be implemented to be substantially the same as the nth stage circuit ST[n].

[0277] Except that the (n+1)th stage circuit ST[n+1] shares the line sensing preparation circuit, the second odd control node 1Qbo, the third odd control node 1Qbe and the fourth odd control node 1Qmo and controls the potential of the first even control node 2Qe by the first gate high potential voltage GVdd1 in response to the (n-2)th carry signal CS[n-2] and the fourth gate high potential voltage GVdde, the (n+1)th stage circuit ST[n+1] according to one embodiment is substantially the same as the nth stage circuit ST[n]. Therefore, the elements of the (n+1)th stage circuit ST[n+1] that are the same as the elements of the nth stage circuit ST[n] will be given the same reference numerals, and repeated descriptions of the same elements will be omitted or simplified.

[0278] The second node control circuit NCC2 according to one embodiment may include first to tenth TFTs T1 to T10.

[0279] The first to fourth TFTs T1 to T4 are used to control or set the potential of the second even-numbered control node 2Qbo, and thus may be represented as a second node setting circuit.

[0280] The first TFT T1 and the second TFT T2 may be implemented to be electrically connected in series between a first gate high potential voltage line for transmitting a first gate high potential voltage GVdd1 and the first odd control node 1Qo, and to charge the first gate high potential voltage GVdd1 in the first even control node 2Qe in response to the (n-2)th carry signal CS[n-2].

[0281] The first TFT T1 may be turned on according to the (n−2)th carry signal CS[n−2] of a high voltage to output the first gate high potential voltage GVdd1 to the first connection node Nc1 .

[0282] The second TFT T2 may be turned on according to the (n-2)th carry signal CS[n-2] of a high voltage simultaneously with the first TFT T1 to provide the first gate high potential voltage GVdd1 provided through the first TFT T1 and the first connection node Nc1 to the first even control node 2Qe.

[0283] The third TFTs T3a and T3b may be turned on according to the second gate high potential voltage GVdd2 to always provide the second gate high potential voltage GVdd2 to the first connection node Nc1 between the first TFT T1 and the second TFT T2, thereby preventing the occurrence of an off current of the first TFT T1 and a current leakage of the first even control node 2Qe.

[0284] The third TFTs T3a and T3b according to one embodiment may include (3-1)th and (3-2)th TFTs T3a and T3b, which are electrically connected in series to each other between the second gate high potential voltage line and the first connection node Nc1 to prevent the occurrence of leakage current due to the off current.

[0285] The (3-1)th TFT T3a may be connected to the second gate high potential voltage line in the form of a diode. The (3-2)th TFT T3b may be turned on by the second gate high potential voltage GVdd2 simultaneously with the (3-1)th TFT T3a to supply the second gate high potential voltage GVdd2 supplied by the (3-1)th TFT T3a to the first connection node Nc1.

[0286] The fourth TFTs T4 a and T4 b may be turned on according to the high voltage of the first even control node 2Qe to supply the first gate high potential voltage GVdd1 to the fourth even control node 2Qhe.

[0287] The fourth TFTs T4a and T4b according to one embodiment may include (4-1)th and (4-2)th TFTs T4a and T4b, which are electrically connected to each other in series between the first gate high potential voltage line and the fourth even control node 2Qhe to prevent the occurrence of leakage current due to the off current.

[0288] The (4-1)th TFT T4a may be turned on by the high voltage of the first even control node 2Qe to supply the first gate high potential voltage GVdd1 to the (4-2)th TFT T4b.

[0289] The (4-2)th TFT T4b may be turned on by the high voltage of the first even control node 2Qe simultaneously with the (4-1)th TFT T4a to supply the first gate high potential voltage GVdd1 supplied through the (4-1)th TFT T4a to the fourth even control node 2Qhe.

[0290] The fifth TFT T5 and the sixth TFT T6 may be implemented to control the potential of each of the second even control node 2Qbo and the fourth even control node 2Qhe by the third gate low potential voltage GVss3 in response to the (n+4)th carry signal CS[n+4]. The fifth TFT T5 and the sixth TFT T6 may be represented as a first even discharge circuit.

[0291] The fifth TFT T5 may be turned on according to the (n+4)th carry signal CS[n+4] of a high voltage to discharge or reset the potential of the fourth even control node 2Qhe to the third gate low potential voltage GVss3.

[0292] The sixth TFT T6 can be turned on simultaneously with the fifth TFT T5 according to the high voltage (n+4)th carry signal CS[n+4] to provide the third gate low potential voltage GVss3 provided through the fifth TFT T5 and the fourth even control node 2Qhe to the first even control node 2Qe, thereby discharging or resetting the potential of the first even control node 2Qe to the third gate low potential voltage GVss3.

[0293] The seventh and eighth TFTs T7 and T8 may be implemented to control the potential of each of the first and fourth even control nodes 2Qe and 2Qhe in response to the second even control node 2Qbo by the third gate low potential voltage GVss3. The seventh and eighth TFTs T7 and T8 may be represented as a second even discharge circuit.

[0294] The seventh TFT T7 may be turned on according to the high voltage of the second even control node 2Qbo to discharge or reset the potential of the fourth even control node 2Qhe to the third gate low potential voltage GVss3 .

[0295] The eighth TFT T8 can be turned on by the high voltage of the second even control node 2Qbo at the same time as the seventh TFT T7 to provide the third gate low potential voltage GVss3 provided through the seventh TFT T7 and the fourth even control node 2Qhe to the first even control node 2Qe, thereby discharging or resetting the potential of the first even control node 2Qe to the third gate low potential voltage GVss3.

[0296] The ninth and tenth TFTs T9 and T10 may be implemented to control the potential of each of the first and fourth even control nodes 2Qe and 2Qhe by the third gate low potential voltage GVss3 in response to the third even control node 2Qbe. The ninth and tenth TFTs T9 and T10 may be represented as a third even discharge circuit.

[0297] The ninth TFT T9 may be turned on according to the high voltage of the third even control node 2Qbe to discharge or reset the potential of the fourth even control node 2Qhe to the third gate low potential voltage GVss3 .

[0298] The tenth TFT T10 can be turned on by the high voltage of the third even control node 2Qbe at the same time as the ninth TFT T9 to provide the third gate low potential voltage GVss3 provided through the ninth TFT T9 and the fourth even control node 2Qhe to the first even control node 2Qe, thereby discharging or resetting the potential of the first even control node 2Qe to the third gate low potential voltage GVss3.

[0299] The second converter circuit IC2 according to one embodiment may include 11th to 15th TFTs T11a, T11b, T12, T13, T14, and T15.

[0300] The 11th TFTs T11a and T11b may provide the fourth gate high potential voltage GVdde to the second connection node Nc2 in response to the fourth gate high potential voltage GVdde. The 11th TFTs T11a and T11b according to one embodiment may include (11-1)th and (11-2)th TFTs T11a and T11b, which are electrically connected in series to each other between the fourth gate high potential voltage line and the second connection node Nc2 to prevent the occurrence of leakage current due to the off current.

[0301] The (11-1)th TFT T11a may be connected to the fourth gate high potential voltage line in the form of a diode. The (11-2)th TFT T11b may be turned on by the fourth gate high potential voltage GVdde simultaneously with the (11-1)th TFT T11a to supply the fourth gate high potential voltage GVdde supplied through the (11-1)th TFT T11a to the second connection node Nc2.

[0302] The 12th TFT T12 may be turned on or off according to the voltage of the second connection node Nc2, and may provide the fourth gate high potential voltage GVdde to the second even control node 2Qbo when it is turned on.

[0303] The 13th TFT T13 may be turned on or off according to the voltage of the first even control node 2Qe, and may discharge or reset the potential of the second even control node 2Qbo to the third gate low potential voltage GVss3 when it is turned on.

[0304] The 14th TFT T14 may be turned on or off according to the voltage of the first even control node 1Qo, and may discharge or reset the potential of the second connection node Nc2 to the second gate low potential voltage GVss2 when it is turned on.

[0305] The 15th TFT T15 may be turned on or off according to the voltage of the first even control node 2Qe of the (n+1)th stage circuit ST[n+1], and may discharge or reset the potential of the second connection node Nc2 to the second gate low potential voltage GVss2 when it is turned on.

[0306] The second sensing control circuit SCC2 according to one embodiment may include 20th to 22nd TFTs T20 , T21 , and T22 .

[0307] The 20th TFT T20 may be implemented to control the potential of the first even control node 2Qe by the first gate high potential voltage GVdd1 provided from the first sensing control circuit SCC1 of the nth stage circuit ST[n] in response to the first reset signal RST1.

[0308] The 20th TFT T20 can be turned on according to the high voltage first reset signal RST1 to provide the first gate high potential voltage GVdd1 provided through the shared node Ns of the nth stage circuit ST[n] to the first even control node 2Qe, thereby charging the first gate high potential voltage GVdd1 in the first even control node 2Qe to activate the first even control node 2Qe.

[0309] The 21st and 22nd TFTs T21 and T22 may be implemented to discharge or reset the potential of the first even control node 2Qe to the third gate low potential voltage GVss3 in response to a display panel turn-on signal POS provided when the light emitting display device is powered on. The 21st and 22nd TFTs T21 and T22 may be represented as a second stage initialization circuit.

[0310] The 21st TFT T21 may be turned on according to the display panel turn-on signal POS of a high voltage to discharge or reset the potential of the fourth even control node 2Qhe to the third gate low potential voltage GVss3 .

[0311] The 22nd TFT T22 can be turned on simultaneously with the 21st TFT T21 according to the high voltage display panel turn-on signal POS to provide the third gate low potential voltage GVss3 provided through the 21st TFT T21 and the fourth even control node 2Qhe to the first even control node 2Qe, thereby charging or resetting the potential of the first even control node 2Qe to the third gate low potential voltage GVss3.

[0312] Optionally, when the n-th stage circuit ST[n] is omitted, the second sensing control circuit SCC2 may be omitted.

[0313] The second node reset circuit NRC2 according to one embodiment may include 23rd to 28th TFTs T21 to T28.

[0314] The 23rd TFT T23 may be implemented to control the potential of the second even control node 2Qbo by the third gate low potential voltage GVss3 in response to the (n-3)th carry signal CS[n-3]. The 23rd TFT T23 may be represented as a (2-1)th reset circuit.

[0315] In the display mode, the 23rd TFT T23 may be turned on according to the (n-3)th carry signal CS[n-3] of a high voltage to discharge or reset the potential of the second even control node 2Qbo to the third gate low potential voltage GVss3.

[0316] The 24th and 25th TFTs T24 and T25 may be implemented to control the potential of the second even control node 2Qbo by the third gate low potential voltage GVss3 in response to the voltage of the fifth even control node 2Qme and the first reset signal RST1. The 24th and 25th TFTs T24 and T25 may be represented as a (2-2)th reset circuit.

[0317] The 24th TFT T24 may be turned on according to the high voltage of the fifth even control node 2Qme to supply the third gate low potential voltage GVss3 to the fourth connection node Nc4 .

[0318] The 25th TFT T25 may be turned on according to the high voltage first reset signal RST1 to provide the third gate low potential voltage GVss3 provided through the 24th TFT T24 and the fourth connection node Nc4 to the second even control node 2Qbo. The fourth connection node Nc4 may be a connection line between the 24th TFT T24 and the 25th TFT T25.

[0319] The 26th to 28th TFTs T26, T27, and T28 may be implemented to control the potential of the first even control node 2Qe using the third gate low potential voltage GVss3 in response to the voltage of the fourth even control node 2Qhe, the voltage of the fifth even control node 2Qme, and the second reset signal RST2 in the sensing mode. The 26th to 28th TFTs T26, T27, and T28 may be represented as a fourth even discharge circuit.

[0320] In response to the voltage of the fourth odd control node 2Qhe, the voltage of the fifth even control node 2Qme and the second reset signal RST2, the 26th to 28th TFTs T26, T27 and T28 can be electrically connected in series between the first even control node 2Qe and the fourth connection node Nc4, and electrically connect the first even control node 2Qe with the fourth connection node Nc4.

[0321] The 26th TFT T26 may be turned on according to the second reset signal RST2 of a high voltage to electrically connect the first even control node 2Qe and the fifth connection node Nc5 .

[0322] The 27th TFT T27 may be turned on according to the high voltage of the fifth even control node 2Qme to electrically connect the fifth connection node Nc5 with the fourth even control node 2Qhe.

[0323] The 28th TFT T28 may be turned on according to the second reset signal RST2 of a high voltage to electrically connect the fourth even control node 2Qhe with the fourth connection node Nc4.

[0324] Alternatively, when the second sensing control circuit SCC2 is omitted, the 24th to 28th TFTs T24, T25, T26, T27, and T28 may be omitted.

[0325] The second output buffer circuit OBC2 according to one embodiment may include 29th to 37th TFTs T29 to T37 and first to third coupling capacitors Cc1, Cc2, and Cc3.

[0326] The 29th to 31st TFTs T29, T30, and T31 and the first coupling capacitor Ccl may be implemented to output the (n+1)th scan shift clock SCCLK[n+1] as the (n+1)th scan signal SC[n+1] in response to the voltages of the first to third even-numbered control nodes 2Qe, 2Qbo, and 2Qbe. The 29th to 31st TFTs T29, T30, and T31 and the first coupling capacitor Ccl may be represented as a scan output circuit.

[0327] The 29th TFT T29 (or the first even pull-up TFT) can output the (n+1)th scan signal SC[n+1] having a scan pulse of a high voltage corresponding to the (n+1)th scan shift clock SCCLK[n+1] to the first output node No1 according to the voltage of the first even control node 2Qe, so as to provide the scan pulse of the (n+1)th scan signal SC[n+1] to the first gate line of the nth gate line group.

[0328] According to one embodiment, Figure 7As shown in, based on the (n+1)th scan shift clock SCCLK[n+1], the 29th TFT T29 can provide the first scan pulse SCP1 to the first gate line of the nth gate line group in the image display period of the display mode, and can provide the second scan pulse SCP2 to the first gate line of the (n+1)th gate line group in the black display period of the display mode. In the sensing mode, when the driving characteristics of the pixels implemented in the (n+1)th horizontal line are sensed, the 29th TFT T29 can additionally provide the third scan pulse SCP3 and the fourth scan pulse SCP4 to the first gate line of the (n+1)th gate line group in the sensing period RSP based on the (n+1)th scan shift clock SCCLK[n+1].

[0329] The 30th TFT T30 (or the (1-1)th even pull-down TFT) can output the (n+1)th scan signal SC[n+1] of a low voltage corresponding to the first gate low potential voltage GVss1 to the first output node No1 according to the voltage of the second even control node 2Qbo, so as to provide the (n+1)th scan signal SC[n+1] of a low voltage to the first gate line of the (n+1)th gate line group.

[0330] The 31st TFT T31 (or the (1-2)th even pull-down TFT) can output the (n+1)th scan signal SC[n+1] of a low voltage corresponding to the first gate low potential voltage GVss1 to the first output node No1 according to the voltage of the third even control node 2Qbe, so as to provide the (n+1)th scan signal SC[n+1] of a low voltage to the first gate line of the (n+1)th gate line group.

[0331] The 30th TFT T30 and the 31st TFT T31 according to the present disclosure may be alternately driven on a specific period basis according to the opposite voltage of each of the second even control node 2Qbo and the third even control node 2Qbe, whereby the degradation speed may be delayed.

[0332] The first coupling capacitor Ccl may be implemented between the first even control node 2Qe and the first output node No1. Alternatively, the first coupling capacitor Cc1 may be implemented by a parasitic capacitance between the gate electrode of the 29th TFT T29 and the first output node No1.

[0333] The 32nd to 34th TFTs T32, T33, and T34 and the second coupling capacitor Cc2 may be implemented to output the (n+1)th sensing shift clock SECLK[n+1] as the (n+1)th sensing signal SE[n+1] in response to the voltages of the first to third even-numbered control nodes 2Qe, 2Qbo, and 2Qbe. The 32nd to 34th TFTs T32, T33, and T34 and the second coupling capacitor Cc2 may be represented as a sensing output circuit.

[0334] The 32nd TFT T32 (or the second even pull-up TFT) can output the (n+1)th sensing signal SE[n+1] having a sensing pulse of a high voltage corresponding to the (n+1)th sensing shift clock SECLK[n+1] to the second output node No2 according to the voltage of the first even control node 2Qe, so as to provide the sensing pulse of the (n+1)th sensing signal SE[n+1] to the second gate line of the (n+1)th gate line group.

[0335] According to one embodiment, Figure 7 As shown in, based on the (n+1)th sensing shift clock SECLK[n+1], the 32nd TFT T32 can provide the first sensing pulse SEP1 to the second gate line in the (n+1)th gate line group in the image display period of the display mode. In the sensing mode, when the driving characteristics of the pixels implemented in the (n+1)th horizontal line are sensed, the 32nd TFT T32 can additionally provide the second sensing pulse SEP2 to the second gate line of the (n+1)th gate line group in the sensing period RSP based on the (n+1)th sensing shift clock SECLK[n+1].

[0336] The 33rd TFT T33 (or the (2-1)th even pull-down TFT) can output the (n+1)th sensing shift clock SECLK[n+1] of a low voltage corresponding to the first gate low potential voltage GVss1 to the second output node No2 according to the voltage of the second even control node 2Qbo, so as to provide the (n+1)th sensing shift clock SECLK[n+1] of a low voltage to the second gate line of the (n+1)th gate line group.

[0337] The 34th TFT T34 (or the (2-2)th even pull-down TFT) can output the (n+1)th sensing shift clock SECLK[n+1] of a low voltage corresponding to the first gate low potential voltage GVss1 to the second output node No2 according to the voltage of the third even control node 2Qbe, so as to provide the (n+1)th sensing shift clock SECLK[n+1] of a low voltage to the second gate line of the (n+1)th gate line group.

[0338] The 33rd TFT T33 and the 34th TFT T34 according to the present disclosure may be alternately driven on a specific period basis according to the opposite voltage of each of the second even control node 2Qbo and the third even control node 2Qbe, whereby the degradation speed may be delayed.

[0339] The second coupling capacitor Cc2 may be implemented between the first even control node 2Qe and the second output node No2. Alternatively, the second coupling capacitor Cc2 may be implemented by a parasitic capacitance between the gate electrode of the 32nd TFT T32 and the second output node No2.

[0340] The 35th to 37th TFTs T35, T36, and T37 and the third coupling capacitor Cc3 may be implemented to output the (n+1)th carry shift clock CRCLK[n+1] as the nth carry signal SE[n] in response to the voltages of the first to third even-numbered control nodes 2Qe, 2Qbo, and 2Qbe. The 35th to 37th TFTs T35, T36, and T37 and the third coupling capacitor Cc3 may be represented as a carry output circuit.

[0341] The 35th TFT T35 (or the third even-numbered pull-up TFT) can output the (n+1)th carry signal CS[n+1] having a high voltage carry pulse corresponding to the (n+1)th carry shift clock CRCLK[n+1] to the third output node No3 according to the voltage of the first even-numbered control node 2Qe, so as to provide the high voltage (n+1)th carry signal CS[n+1] to the previous stage circuit or the subsequent stage circuit. According to one embodiment, as Figure 7 As shown in, based on the (n+1)th carry shift clock CRCLK[n+1], the 35th TFT T35 can output the (n+1)th carry signal CS[n+1] to the previous circuit or the next circuit in the display mode based on the (n+1)th carry shift clock CRCLK[n+1].

[0342] The 36th TFT T36 (or the (3-1) even-numbered pull-down TFT) can output the (n+1)th carry signal CS[n+1] of a low voltage corresponding to the first gate low potential voltage GVss1 to the third output node No3 according to the voltage of the second even-numbered control node 2Qbo, so as to provide the (n+1)th carry signal CS[n+1] of the low voltage to the previous circuit or the next circuit.

[0343] The 37th TFT T37 (or the (3-2) even-numbered pull-down TFT) can output the (n+1)th carry signal CS[n+1] of a low voltage corresponding to the first gate low potential voltage GVss1 to the third output node No3 according to the voltage of the third even-numbered control node 2Qbe, so as to provide the (n+1)th carry signal CS[n+1] of the low voltage to the previous circuit or the next circuit.

[0344] The 36th TFT T36 and the 37th TFT T37 according to the present disclosure may be alternately driven on a specific period basis according to the opposite voltage of each of the second even control node 2Qbo and the third even control node 2Qbe, whereby the degradation speed may be delayed.

[0345] The third coupling capacitor Cc3 may be implemented between the first even control node 2Qe and the third output node No3. Alternatively, the third coupling capacitor Cc3 may be implemented by a parasitic capacitance between the gate electrode of the 35th TFT T35 and the third output node No3.

[0346] Any one of the first coupling capacitor Cc1 and the second coupling capacitor Cc2 among the first to third coupling capacitors Cc1, Cc2, and Cc3 may be omitted. For example, the first coupling capacitor Cc1 among the first coupling capacitor Cc1 and the second coupling capacitor Cc2 may be omitted.

[0347] Fig.10 It shows Fig. 9 A view of an input waveform and an output waveform of each of the n-th stage circuit and the (n+1)-th stage circuit shown in FIG. FIG. 11A to FIG. 11I It shows Fig. 9 A view of the operation process of each of the n-th stage circuit and the (n+1)-th stage circuit shown in FIG. FIG. 11A to FIG. 11I In FIG. 1 , a thick solid line indicates a node having a high voltage or higher potential and a TFT that is turned on, and a thin solid line indicates a node having a low voltage potential and a TFT that is turned off. Fig.10 as well as FIG. 11A to FIG. 11I In the description of FIG. 1 , the operation description of the TFT implemented in the nth level circuit and the (n+1)th level circuit is the same as that of FIG. Fig. 9 The descriptions in are basically the same and their repeated descriptions will be omitted.

[0348] Reference Fig.10 and Fig.11A, in the first display period td1 of the image display period IDP of the display mode according to one embodiment of the present disclosure, according to the operation of the first node control circuit NCC1 in response to the (n-3)th carry signal CS[n-3] of the high voltage, the first odd control node 1Qo of the n-th stage circuit ST[n] is charged with the first gate high potential voltage GVdd1. According to the operation of the first inverter circuit IC1 in response to the charging voltage of the first odd control node 1Qo, the second odd control node 1Qbo of the n-th stage circuit ST[n] is discharged with the third gate low potential voltage GVss3. According to the operation of the second inverter circuit IC2 in response to the charging voltage of the first odd control node 1Qo of the n-th stage circuit ST[n], the first even control node 2Qe of the (n+1)-th stage circuit ST[n+1] is discharged with the third gate low potential voltage GVss3. According to the operation of the second node reset circuit NRC2 in response to the (n-3)th carry signal CS[n-3] of the high voltage, the second even control node 2Qbo of the (n+1)th stage circuit ST[n+1] is discharged using the third gate low potential voltage GVss3. The third odd control node 1Qbe of the nth stage circuit ST[n] is connected to the second even control node 2Qbo of the (n+1)th stage circuit ST[n+1] and is thus discharged using the third gate low potential voltage GVss3. The third even control node 2Qbe of the (n+1)th stage circuit ST[n+1] is connected to the second odd control node 1Qbo of the nth stage circuit ST[n] and is thus discharged using the third gate low potential voltage GVss3.

[0349] In the first display period td1 of the image display period IDP, the first gate high potential voltage GVdd1 charged at the first odd control node 1Qo of the n-th stage circuit ST[n] is provided from the first gate high potential voltage line through the two TFTs T1 and T2, thereby enhancing the voltage charging characteristics of the first odd control node 1Qo.

[0350] At the first display period td1 of the image display period IDP, since each of the nth scan shift clock SCCLK[n], the nth sense shift clock SECLK[n] and the nth carry shift clock CRCLK[n] is maintained at a low voltage, no bootstrapping is generated at the first odd control node 1Qo, and thus each of the odd pull-up TFTs T29, T32 and T35 of the first output buffer circuit OBC1 is maintained in an off state and is not turned on.

[0351] Reference Fig.10 and Fig. 11B, in the second display period td2 of the image display period IDP of the display mode according to one embodiment of the present disclosure, according to the operation of the first sensing control circuit SCC1 having the line sensing selection pulse LSP1 having a high voltage in response to the (n-2)th carry signal CS[n-2] and the line sensing preparation signal LSPS having a high voltage, the fifth odd control node 1Qmo of the n-th stage circuit ST[n] is charged with the first gate high potential voltage GVdd1. The first odd control node 1Qo of the n-th stage circuit ST[n] is kept charged at the first gate high potential voltage GVdd1 in the first display period td1. According to the operation of the second node control circuit NCC2 in response to the (n-2)th carry signal CS[n-2] having a high voltage, the first even control node 2Qe of the (n+1)-th stage circuit ST[n+1] is charged with the first gate high potential voltage GVdd1. The first gate high potential voltage GVdd1 charged at the first even control node 2Qe is provided from the first gate high potential voltage line through the two TFTs T1 and T2, thereby enhancing the voltage charging characteristics of the first even control node 2Qe. According to the operation of the first inverter circuit IC1 in response to the charging voltage of the first odd control node 1Qo, the second odd control node 1Qbo of the n-th stage circuit ST[n] is maintained at the third gate low potential voltage GVss3. The third even control node 2Qbe of the (n+1)-th stage circuit ST[n+1] is connected to the second odd control node 1Qbo of the n-th stage circuit ST[n] and is therefore maintained at the third gate low potential voltage GVss3. According to the operation of the second inverter circuit IC2 in response to the charging voltage of the first even control node 2Qe, the second even control node 2Qbo of the (n+1)-th stage circuit ST[n+1] is maintained at the third gate low potential voltage GVss3. The third odd control node 1Qbe of the n-th stage circuit ST[n] is connected to the second even control node 2Qbo of the (n+1)-th stage circuit ST[n+1] and is thus maintained at the third gate low potential voltage GVss3.

[0352] At the second display period td2 of the image display period IDP, since each of the n-th scanning shift clock SCCLK[n], the n-th sensing shift clock SECLK[n] and the n-th carry shift clock CRCLK[n] is maintained at a low voltage, no bootstrap is generated at the first odd control node 1Qo, thereby each of the odd pull-up TFTs T29, T32 and T35 of the first output buffer circuit OBC1 is maintained in an off state and is not turned on. Moreover, when each of the (n+1)-th scanning shift clock SCCLK[n+1], the (n+1)-th sensing shift clock SECLK[n+1] and the (n+1)-th carry shift clock CRCLK[n+1] is maintained at a low voltage, no bootstrap is generated at the first even control node 2Qe, thereby each of the even pull-up TFTs T29, T32 and T35 of the second output buffer circuit OBC2 is maintained in an off state and is not turned on.

[0353] Reference Fig.10 and Fig. 11C , within the third display period td3 of the image display period IDP of the display mode according to one embodiment of the present disclosure, each of the second odd control node to the fifth odd control node 1Qbo, 1Qbe, 1Qho and 1Qmo of the n-th stage circuit ST[n] and each of the first even control node to the fifth even control node 2Qe, 2Qbo, 2Qbe, 2Qhe and 2Qme of the (n+1)-th stage circuit ST[n+1] maintains the voltage state of the second display period td2 unchanged.

[0354] In the third display period td3 of the image display period IDP, since each of the nth scan shift clock SCCLK[n], the nth sense shift clock SECLK[n] and the nth carry shift clock CRCLK[n] is input as a high voltage, a bootstrap is generated at the first odd control node 1Qo, whereby each of the odd pull-up TFTs T29, T32 and T35 of the first output buffer circuit OBC1 is fully turned on. Therefore, the nth stage circuit ST[n] outputs the nth scan signal SC[n] of the first scan pulse SCP1 having a high voltage through the first output node No1, outputs the nth sense signal SE[n] of the first sense pulse SEP1 having a high voltage through the second output node No2, and outputs the nth carry signal CS[n] having a high voltage through the third output node No3. Therefore, the image data addressing period of the pixels set on the nth horizontal line can be performed.

[0355] At the third display period td3 of the image display period IDP, since each of the (n+1)th scan shift clock SCCLK[n+1], the (n+1)th sense shift clock SECLK[n+1], and the (n+1)th carry shift clock CRCLK[n+1] is maintained at a low voltage and then input as a high voltage in the clock non-overlapping period, a bootstrap is generated at the first even control node 2Qe, whereby each of the even pull-up TFTs T29, T32, and T35 of the second output buffer circuit OBC2 is fully turned on. Therefore, the (n+1)th stage circuit ST[n+1] outputs the (n+1)th scan signal SC[n+1] of the first scan pulse SCP1 having a high voltage through the first output node No1, outputs the (n+1)th sense signal SE[n+1] of the first sense pulse SEP1 having a high voltage through the second output node No2, and outputs the (n+1)th carry signal CS[n+1] having a high voltage through the third output node No3. Therefore, the image data addressing period of the pixels arranged on the (n+1)th horizontal line can be performed.

[0356] Reference Fig.10 and Fig.11D , after the third display period td3 of the image display period IDP of the display mode according to one embodiment of the present disclosure, the fifth odd-numbered control node 1Qmo of the n-th stage circuit ST[n] maintains the charging state unchanged.

[0357] After the third display period td3 of the image display period IDP, the first odd control node 1Qo of the n-stage circuit ST[n] is discharged by the third gate low potential voltage GVss3 according to the operation of the first node control circuit NCC1 in response to the (n+4)th carry signal CS[n+4] (or the (n+3)th carry signal CS[n+3]) of the high voltage. The second odd control node 1Qbo of the n-stage circuit ST[n] is charged by the third gate high potential voltage GVddo according to the operation of the first inverter circuit IC1 in response to the discharge of the first odd control node 1Qo. Therefore, since each of the odd pull-down TFTs T30, T33, and T36 is turned on by the charging voltage of the second odd control node 1Qbo, the first output buffer circuit OBC1 outputs the n-th scan signal SC[n] of the low voltage through the first output node No1, outputs the n-th sense signal SE[n] of the low voltage through the second output node No2, and outputs the n-th carry signal CS[n] of the low voltage through the third output node No3. Therefore, the pixels disposed on the n-th horizontal line may emit light according to the data current corresponding to the addressed image data voltage.

[0358] After the third display period td3 of the image display period IDP, according to the operation of the second node control circuit NCC2 in response to the (n+4)th carry signal CS[n+4] of the high voltage, the first even control node 2Qe of the (n+1)th stage circuit ST[n+1] is discharged using the third gate low potential voltage GVss3. The third even control node 2Qbe of the (n+1)th stage circuit ST[n+1] is connected to the second odd control node 1Qbo of the nth stage circuit ST[n] and is thus charged using the third gate high potential voltage GVddo. Therefore, since each of the even-numbered pull-down TFTs T31, T34, and T37 is turned on by the charge voltage of the third even-numbered control node 2Qbe, the second output buffer circuit OBC2 outputs the (n+1)th scan signal SC[n+1] of a low voltage through the first output node No1, outputs the (n+1)th sensing signal SE[n+1] of a low voltage through the second output node No2, and outputs the (n+1)th carry signal CS[n+1] of a low voltage through the third output node No3. Therefore, the pixels disposed on the (n+1)th horizontal line can emit light according to the data current corresponding to the addressed image data voltage.

[0359] Reference Fig.10 and Fig.11E , during the black display period BDP of the display mode according to one embodiment of the present disclosure, the fifth odd-numbered control node 1Qmo of the n-th stage circuit ST[n] maintains the charging state unchanged.

[0360] In the first black period tb1 of the black display period BDP, the first odd control node 1Qo of the n-th stage circuit ST[n] is charged with the first gate high potential voltage GVdd1 according to the operation of the first node control circuit NCC1 in response to the (n-3)th carry signal CS[n-3] of the high voltage. The second odd control node 1Qbo of the n-th stage circuit ST[n] is discharged with the third gate low potential voltage GVss3 according to the operation of the first inverter circuit IC1 in response to the charging voltage of the first odd control node 1Qo.

[0361] During the first black period tb1 of the black display period BDP, a first gate high potential voltage GVdd1 charged at the first odd control node 1Qo of the n-th stage circuit ST[n] is provided from the first gate high potential voltage line through two TFTs T1 and T2, thereby enhancing the voltage charging characteristics of the first odd control node 1Qo.

[0362] During the first black period tb1 of the black display period BDP, according to the operation of the second inverter circuit IC2 in response to the charging voltage of the first odd control node 1Qo, the first even control node 2Qe of the (n+1)-th stage circuit ST[n+1] is discharged using the third gate low potential voltage GVss3. The second even control node 2Qbo of the (n+1)-th stage circuit ST[n+1] is connected to the third odd control node 1Qbe of the n-th stage circuit ST[n], and is therefore maintained at the third gate low potential voltage GVss3. The third even control node 2Qbe of the n+1-th stage circuit ST[n+1] is connected to the second odd control node 1Qbo of the n-th stage circuit ST[n], and is therefore maintained at the third gate low potential voltage GVss3.

[0363] In the second black period tb2 and the third black period tb3 after the first black period tb1 of the black display period BDP, the fifth odd control node 1Qmo of the n-th stage circuit ST[n] remains in a charged state. Since the first black period tb1 and the second black period tb2 are connected to the n-th stage circuit ST[n] except that only the n-th scan shift clock SCCLK[n] is input as a high voltage, the first black period tb1 and the second black period tb2 are connected to the n-th stage circuit ST[n] Fig.11D The second display period td2 and the third display period td3 shown in FIG. 1 are substantially the same, and thus a repeated description thereof will be omitted. Therefore, in the second black period tb2 and the third black period tb3 of the black display period BDP, the pixels disposed on the nth horizontal line may display a black image because the black data voltage is addressed by the nth scan signal SC[n] having the second scan pulse SCP2 of a high voltage.

[0364] Reference Fig.10 and Fig.11F , at the first sensing period ts1 of the sensing period RSP of the sensing mode according to one embodiment of the present disclosure, the first odd control node 1Qo of the n-th stage circuit ST[n] is charged with the first gate high potential voltage GVdd1 according to the operation of the first sensing control circuit SCC1 in response to the first reset signal RST1 of the high voltage. The second odd control node 1Qbo of the n-th stage circuit ST[n] is discharged with the third gate low potential voltage GVss3 according to the operation of the first inverter circuit IC1 in response to the charging voltage of the first odd control node 1Qo.

[0365] In the first sensing period ts1 of the sensing period RSP, the first even control node 2Qe of the (n+1)-stage circuit ST[n+1] is discharged by the first gate high potential voltage GVdd1 provided through the shared node Ns of the n-stage circuit ST[n] according to the operation of the second sensing control circuit SCC2 in response to the first reset signal RST1 of the high voltage. The second even control node 2Qbo of the (n+1)-stage circuit ST[n+1] is discharged by the third gate low potential voltage GVss3 according to the operation of the second inverter circuit IC2 in response to the charging voltage of the first even control node 2Qe.

[0366] At the first sensing period ts1 of the sensing period RSP, since each of the n-th scanning shift clock SCCLK[n], the n-th sensing shift clock SECLK[n], and the n-th carry shift clock CRCLK[n] is maintained at a low voltage, no bootstrap is generated at the first odd control node 1Qo, and thus each of the odd pull-up TFTs T29, T32, and T35 of the first output buffer circuit OBC1 is maintained in an off state and is not turned on. Similarly, at the first sensing period ts1 of the sensing period RSP, since each of the (n+1)-th scanning shift clock SCCLK[n+1], the (n+1)-th sensing shift clock SECLK[n+1], and the (n+1)-th carry shift clock CRCLK[n+1] is maintained at a low voltage, no bootstrap is generated at the first even control node 2Qe, and thus each of the even pull-up TFTs T29, T32, and T35 of the second output buffer circuit OBC2 is maintained in an off state and is not turned on.

[0367] Reference Fig.10 and Fig.11G In the second sensing period ts2 of the sensing period RSP of the sensing mode according to one embodiment of the present disclosure, each of the n-th scanning shift clock SCCLK[n] and the n-th sensing shift clock SECLK[n] is input as a high voltage, and the n-th carry shift clock CRCLK[n] is input as a low voltage, and a bootstrap is generated at the first odd control node 1Qo, whereby each of the odd pull-up TFTs T29, T32, and T35 of the first output buffer circuit OBC1 is fully turned on. Therefore, the n-th stage circuit ST[n] outputs the n-th scanning signal SC[n] of the third scanning pulse SCP3 having a high voltage through the first output node No1, outputs the n-th sensing signal SE[n] of the second sensing pulse SEP2 having a high voltage through the second output node No2, and outputs the n-th carry signal CS[n] having a low voltage through the third output node No3. Therefore, the sensing data addressing period of the pixels arranged on the n-th horizontal line can be performed in the second sensing period ts2 of the sensing period RSP.

[0368] At the second sensing period ts2 of the sensing period RSP, since each of the (n+1)th scan shift clock SCCLK[n+1], the (n+1)th sensing shift clock SECLK[n+1] and the (n+1)th carry shift clock CRCLK[n+1] is maintained at a low voltage, no bootstrapping is generated at the first even control node 2Qe, and thus each of the even pull-up TFTs T29, T32 and T35 of the second output buffer circuit OBC2 is maintained in an off state and not turned on.

[0369] In the fourth sensing period ts4 after the third sensing period ts3 of the sensing period RSP, each of the n-th scanning shift clock SCCLK[n] and the n-th carry shift clock CRCLK[n] is input as a low voltage, and the n-th sensing shift clock SECLK[n] is input as a high voltage, whereby each of the odd-numbered pull-up TFTs T29, T32, and T35 of the first output buffer circuit OBC1 is maintained in a turned-on state. Therefore, the n-th stage circuit ST[n] outputs the n-th scanning signal SC[n] of a low voltage through the first output node No1, outputs the n-th sensing signal SE[n] of the second sensing pulse SEP2 of a high voltage as it is through the second output node No2, and outputs the n-th carry signal CS[n] of a low voltage as it is through the third output node No3. Therefore, a sampling period for sensing the driving characteristics of the pixels disposed on the n-th horizontal line can be performed in the fourth sensing period ts4 of the sensing period RSP.

[0370] In the fifth sensing period ts5 after the fourth sensing period ts4 of the sensing period RSP, the nth scanning shift clock SCCLK[n] is input as a high voltage, the nth sensing shift clock SECLK[n] is maintained as a high voltage, and the nth carry shift clock CRCLK[n] is maintained at a low voltage, whereby each of the odd-numbered pull-up TFTs T29, T32, and T35 of the first output buffer circuit OBC1 is maintained in a turned-on state. Therefore, the nth stage circuit ST[n] outputs the nth scanning signal SC[n] of the fourth scanning pulse SCP4 having a high voltage through the first output node No1, outputs the nth sensing signal SE[n] of the second sensing pulse SEP2 having a high voltage as it is through the second output node No2, and outputs the nth carry signal CS[n] having a low voltage as it is through the third output node No3. Therefore, a data recovery period for restoring the light emitting state of the pixels disposed on the nth horizontal line to the previous state of the sensing period RSP can be performed in the fourth sensing period ts4 of the sensing period RSP.

[0371] Reference Fig.10 and Fig.11HIn the fifth sensing period ts5 of the sensing period RSP of the sensing mode according to one embodiment of the present disclosure, the first odd control node 1Qo of the n-th stage circuit ST[n] is discharged by the third gate low potential voltage GVss3 according to the operation of the first node reset circuit NRC1 in response to the second reset signal RST2 of the high voltage and the charging voltage of the fifth odd control node 1Qmo. Therefore, the sensing mode of the pixels set on the n-th horizontal line can be released.

[0372] At the fifth sensing period ts5 of the sensing period RSP, the second odd control node 1Qbo of the n-th stage circuit ST[n] is charged with the third gate high potential voltage GVddo according to the operation of the first inverter circuit IC1 in response to the discharge voltage of the first odd control node 1Qo. Therefore, since each of the odd pull-down TFTs T30, T33, and T36 is turned on by the charge voltage of the second odd control node 1Qbo, the first output buffer circuit OBC1 outputs the n-th scan signal SC[n] of a low voltage through the first output node No1, outputs the n-th sensing signal SE[n] of a low voltage through the second output node No2, and outputs the n-th carry signal CS[n] of a low voltage through the third output node No3.

[0373] In the fifth sensing period ts5 of the sensing period RSP, according to the operation of the second node reset circuit NRC2 in response to the second reset signal RST2 of the high voltage and the charging voltage of the fifth odd control node 1Qmo, the first even control node 2Qe of the (n+1)th stage circuit ST[n+1] is discharged using the third gate low potential voltage GVss3. The third even control node 2Qbe of the (n+1)th stage circuit ST[n+1] is connected to the second odd control node 1Qbo of the nth stage circuit ST[n] and is therefore charged using the third gate high potential voltage GVddo. Therefore, since each of the even-numbered pull-down TFTs T31, T34 and T37 is turned on by the charging voltage of the third even-numbered control node 2Qbe, the second output buffer circuit OBC2 outputs the (n+1)th scan signal SC[n+1] of a low voltage through the first output node No1, outputs the (n+1)th sensing signal SE[n+1] of a low voltage through the second output node No2, and outputs the (n+1)th carry signal CS[n+1] of a low voltage through the third output node No3.

[0374] Reference Fig.10 and Fig.11IAt the start time of the display mode after the sensing mode according to one embodiment of the present disclosure, according to the operation of the first sensing control circuit SCC1 with the line sensing release pulse LSP2 with a high voltage in response to the line sensing preparation signal LSPS, the fifth odd control node 1Qmo of the n-stage circuit ST[n] is charged or discharged with the (n-2)th carry signal CS[n-2] with a low voltage. The second odd control node 1Qbo of the n-stage circuit ST[n] maintains a charged state with the third gate high potential voltage GVddo. Therefore, since each of the odd pull-down TFTs T30, T33, and T36 is maintained in a turned-on state by the charging voltage of the second odd control node 1Qbo, the first output buffer circuit OBC1 outputs the n-th scan signal SC[n] with a low voltage through the first output node No1, outputs the n-th sensing signal SE[n] with a low voltage through the second output node No2, and outputs the n-th carry signal CS[n] with a low voltage through the third output node No3.

[0375] At the start time of the display mode after the sensing mode, the third even control node 2Qbe of the (n+1)th stage circuit ST[n+1] is connected to the second odd control node 1Qbo of the nth stage circuit ST[n], and thus maintains a charged state with the third gate high potential voltage GVddo. Therefore, since each of the even pull-down TFTs T31, T34, and T37 is turned on by the charging voltage of the third even control node 2Qbe, the second output buffer circuit OBC2 outputs the (n+1)th scan signal SC[n+1] of a low voltage through the first output node No1, outputs the (n+1)th sensing signal SE[n+1] of a low voltage through the second output node No2, and outputs the (n+1)th carry signal CS[n+1] of a low voltage through the third output node No3.

[0376] Fig. 12A and Fig. 12B is a view showing a charging path of a first control node implemented in each stage circuit of a gate driving circuit according to an embodiment of the present disclosure and a comparative example, Fig.13A and Fig. 13B are waveforms showing output characteristics of a gate driving circuit according to one embodiment of the present disclosure and a comparative example.

[0377] Reference Fig. 12AAccording to the comparative example, the high voltage of the (n-3)th carry signal CS[n-3] of high voltage can be used to charge the first control nodes Qo and Qe in each stage circuit ST[n], and the high voltage of the (n-3)th carry signal CS[n-3] is provided by the first TFT T1 and the second TFT T2 turned on by the (n-3)th carry signal CS[n-3] of high voltage output from the previous stage circuit ST[n-3]. At this time, the high voltage of the (n-3)th carry signal CS[n-3] can be charged at the first control nodes Qo and Qe by passing through the first TFT T1 and the second TFT T2 from the carry clock line and the pull-up TFT T35 of the previous stage circuit ST[n-3]. Therefore, in the comparative example, the voltage charging rate of the first control nodes Qo and Qe may be degraded by the voltage drop of the (n-3)th carry signal CS[n-3], which is generated by the resistance components of the three TFTs set on the charging path of the first control nodes Qo and Qe. In particular, in the comparative example, when the on-current or mobility characteristics of the TFT are degraded by the degradation of the TFT or the threshold voltage shift, the voltage charging rate of the first control nodes Qo and Qe may be further degraded. Therefore, since the voltage charging rate of the first control nodes Qo and Qe is degraded by the on-current degradation of the TFT, the gate driving circuit according to the comparative example may output as follows. Fig.13A The abnormal signal shown in .

[0378] Reference Fig. 12B According to one embodiment of the present disclosure, the first control nodes Qo and Qe implemented in each stage circuit ST[n] can be charged with the first gate high potential voltage GVdd1, and the first gate high potential voltage line provides the first gate high potential voltage GVdd1 through the first TFT T1 and the second TFT T2 turned on by the (n-3)th carry signal CS[n-3] of the high voltage output from the previous stage circuit ST[n-3]. At this time, the first gate high potential voltage GVdd1 can be charged at the first control nodes Qo and Qe by passing through the first TFT T1 and the second TFT T2 from the first gate high potential voltage line. Therefore, in one embodiment of the present disclosure, the voltage charging rate of the first control nodes Qo and Qe can be improved by reducing the resistance component based on reducing the number of TFTs set on the charging path of the first control nodes Qo and Qe, compared with the comparative example. In addition, in one embodiment of the present disclosure, the first gate high potential voltage GVdd1 of the DC voltage (rather than the carry clock according to the comparative example) can be discharged at the first control nodes Qo and Qe, thereby improving the voltage charging capability of the first control nodes Qo and Qe. Therefore, in one embodiment of the present disclosure, the voltage charging capability of the first control nodes Qo and Qe can be significantly improved, thereby improving the output characteristics of the output signal, such as Fig.13A Therefore, in one embodiment of the present disclosure, erroneous operation of the gate driving circuit caused by degradation of the voltage charging rate of the first control nodes Qo and Qe due to degradation of the on-current or mobility of the TFT caused by degradation of the TFT or threshold voltage drift can be avoided.

[0379] Fig.14A and Fig. 14B is a view showing a charging voltage waveform of a first control node of each of the gate driving circuits according to one embodiment of the present disclosure and a comparative example. Fig.14A The comparative example shown in FIG. 1 shows the charging voltage waveform of the first control node when the on-current characteristic of the first TFT deteriorates to 30% (a), 40% (b), and 50% (c). Fig. 14B One embodiment of the present disclosure shown in shows a charging voltage waveform of the first control node when the on-current characteristic of the first TFT deteriorates to 40% (a), 50% (b), 60% (c), 70% (d), and 80% (e).

[0380] As from Fig.14A As will be appreciated, it is noted that when the on-current characteristic of the first TFT deteriorates to 30% (a) and 40% (b), the voltage charging of the first control node according to the comparative example is performed normally, but when the on-current characteristic of the first TFT deteriorates to 50% (c), the voltage charging of the first control node according to the comparative example cannot be performed normally. Therefore, when the on-current characteristic of the first TFT deteriorates to 50% (c) or more, the gate driving circuit according to the comparative example may erroneously operate due to the degradation of the voltage charging rate of the first control node.

[0381] As from Fig. 14B As will be appreciated, note that when the on-current characteristics of the first TFT deteriorate to 40% (a), 50% (b), 60% (c) and 70% (d), the voltage charging of the first control node according to one embodiment of the present disclosure is performed normally, but when the on-current characteristics of the first TFT deteriorate to 80% (e), the voltage charging of the first control node according to one embodiment of the present disclosure cannot be performed normally. Therefore, due to the improvement of the voltage charging rate of the first control node, when the on-current characteristics of the first TFT deteriorate to a level less than 80% (e), the gate drive circuit according to one embodiment of the present disclosure can operate normally. Therefore, in one embodiment of the present disclosure, the reliability of the gate drive circuit can be improved to reduce the degradation of the on-current characteristics of the first TFT.

[0382] A gate driving circuit and a light emitting display device including the gate driving circuit according to an embodiment of the present disclosure will be described below.

[0383] A gate driving circuit according to one embodiment of the present disclosure includes a first-stage circuit to an m-th-stage circuit, each of which includes: a first control node to a third control node; a node control circuit that controls the voltage of each of the first control node to the third control node; and an output buffer circuit that outputs each of a scan signal, a sense signal, and a carry signal according to each of the first control node to the third control node, and the node control circuit includes a node setting circuit that charges a first gate high potential voltage to the first control node in response to a first carry signal provided from a previous-stage circuit.

[0384] According to one embodiment of the present disclosure, the first gate high potential voltage may be provided to the first control node by passing through two thin film transistors from a first gate high potential voltage line.

[0385] According to one embodiment of the present disclosure, a node setting circuit may include a first thin film transistor and a second thin film transistor, which are electrically connected in series between a first gate high potential voltage line transmitting a first gate high potential voltage and a first control node, and are together turned on by a first carry signal of the first voltage.

[0386] According to one embodiment of the present disclosure, the node setting circuit may further include a third thin film transistor that always provides a second gate high potential voltage to the first connection node between the first thin film transistor and the second thin film transistor.

[0387] According to one embodiment of the present disclosure, the second gate high potential voltage may be lower than the first gate high potential voltage.

[0388] According to one embodiment of the present disclosure, the third thin film transistor may include a (3-1)th thin film transistor and a (3-2)th thin film transistor, wherein the (3-1)th thin film transistor and the (3-2)th thin film transistor are electrically connected in series between a second gate high potential voltage line transmitting a second gate high potential voltage and a first control node, and are turned on together by the second gate high potential voltage.

[0389] According to one embodiment of the present disclosure, the second control node implemented in the n-th level circuit of the first level circuit to the m-th level circuit can be electrically connected to the third control node implemented in the (n+1)-th level circuit, and the third control node implemented in the n-th level circuit can be electrically connected to the second control node implemented in the (n+1)-th level circuit.

[0390] According to one embodiment of the present disclosure, each of the first-stage circuit to the m-th-stage circuit may further include: an inverter circuit that controls the voltage of the second control node according to the voltage of the first control node; and a node reset circuit that resets the voltage of the second control node to a gate low potential voltage in response to a first carry signal.

[0391] According to one embodiment of the present disclosure, the inverter circuit of the nth stage circuit can additionally control the voltage of the second control node of the nth stage circuit according to the voltage of the first control node of the (n+1)th stage circuit, and the inverter circuit of the (n+1)th stage circuit can additionally control the voltage of the second control node of the (n+1)th stage circuit according to the voltage of the first control node of the nth stage circuit.

[0392] According to one embodiment of the present disclosure, each of the first-level circuits to the m-th-level circuits may include: a storage node; and a sensing control circuit that controls each of the voltage of the storage node and the voltage of the first control node, and the sensing control circuit of the n-th-level circuit may also include the following sensing control circuit, which controls the voltage of the storage node in response to a second carry signal and a line sensing ready signal provided from the previous-level circuit, outputs a first gate high potential voltage to a shared node according to the voltage of the storage node, and provides the first gate high potential voltage to the first control node in response to a first reset signal and the voltage of the storage node.

[0393] According to one embodiment of the present disclosure, the sensing control circuit of each of the first to m-th stage circuits may reset the voltage of the first control node to a gate low potential voltage in response to a display panel turn-on signal.

[0394] According to one embodiment of the present disclosure, the node reset circuit of the n-th level circuit can discharge the voltage of the first control node of the n-th level circuit using a gate low potential voltage in response to a first reset signal and the voltage of the storage node, and discharge the voltage of the first control node of the n-th level circuit using a gate low potential voltage in response to a second reset signal and the voltage of the storage node.

[0395] According to one embodiment of the present disclosure, the sensing control circuit of the (n+1)th level circuit can be electrically connected to the storage node of the nth level circuit, and in response to a first reset signal, the first gate high potential voltage provided through the shared node of the nth level circuit is supplied to the first control node of the (n+1)th level circuit.

[0396] According to one embodiment of the present disclosure, the node reset circuit of the (n+1)th stage circuit can discharge the voltage of the first control node using a gate low potential voltage in response to a first reset signal and the voltage of the storage node, and discharge the voltage of the first control node of the (n+1)th stage circuit using a gate low potential voltage in response to a second reset signal and the voltage of the storage node.

[0397] According to one embodiment of the present disclosure, each of the first to m-th level circuits can sequentially output a scan signal, a sensing signal, and a carry signal during a vertical valid period of each frame cycle, and any one of the first to m-th level circuits can output a scan signal and a sensing signal during a vertical blank period of each frame cycle.

[0398] A light-emitting display device according to one embodiment of the present disclosure includes: a light-emitting display panel including a plurality of pixels, a plurality of gate line groups having a first gate line and a second gate line connected to the plurality of pixels, and a plurality of data lines and reference lines connected to the plurality of pixels and crossing the plurality of gate line groups; a gate driving circuit portion connected to the plurality of gate line groups; a data driving circuit portion connected to the plurality of data lines and the plurality of reference lines; and a timing controller controlling the driving timing of each of the gate driving circuit portion and the data driving circuit portion, and the gate driving circuit includes a first stage circuit to an m-th stage circuit, and each of the first stage circuit to the m-th stage circuit includes: a first control node to a third control node; a node control circuit controlling a voltage of each of the first control node to the third control node; and an output buffer circuit outputting each of a scan signal, a sensing signal and a carry signal according to each of the first control node to the third control node, and the node control circuit includes a node setting circuit charging a first gate high potential voltage to the first control node in response to a first carry signal provided from a previous stage circuit.

[0399] According to one embodiment of the present disclosure, a timing controller may control a light-emitting display panel in a display mode and a sensing mode, a gate driving circuit unit may provide a scanning signal and a sensing signal to any one of a plurality of gate line groups in a sensing mode, and a data driving circuit unit may supply a sensing data voltage synchronized with the scanning signal to a plurality of data lines in a sensing mode, and sense driving characteristics of pixels through a plurality of reference lines.

[0400] According to one embodiment of the present disclosure, a timing controller can control a display mode in an image display period and a black display period, a gate driving circuit unit can provide a scan signal only to a first gate line corresponding to at least one of a plurality of gate line groups during the black display period, and a data driving circuit unit can provide a black data voltage synchronized with the scan signal to a plurality of data lines during the black display period.

[0401] According to one embodiment of the present disclosure, each of the plurality of pixels may display an image in an image display period and display a black image in a black display period.

[0402] According to one embodiment of the present disclosure, the gate driving circuit unit can sequentially provide scanning signals and sensing signals to multiple gate line groups during the vertical effective period of each frame cycle, and output the scanning signals and sensing signals to any one of the multiple gate line groups during the vertical blank period of each frame cycle.

[0403] The gate drive circuit according to the embodiment of the present disclosure and the light-emitting display device including the gate drive circuit can be applied to all electronic devices including a light-emitting display panel and / or a gate drive circuit built into the light-emitting display panel. For example, the gate drive circuit according to the embodiment of the present disclosure and the light-emitting display device including the gate drive circuit can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, portable multimedia players (PMPs), personal digital assistants (PDAs), electronic notepads, desktop personal computers (PCs), laptops, network computers, workstations, navigation devices, car navigation devices, car display devices, televisions (TVs), wallpaper display devices, signage devices, game consoles, notebook computers, monitors, cameras, camcorders, household appliances, etc.

[0404] It will be apparent to those skilled in the art that the above disclosure is not limited by the above embodiments and drawings, and that various substitutions, modifications and variations may be made in the disclosure without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope and equivalents of the claims are intended to fall within the scope of the disclosure.

[0405] The various embodiments described above can be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If it is necessary to adopt the concepts of various patents, applications, and publications to provide other embodiments, various aspects of the embodiments can be modified.

[0406] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A gate drive circuit, comprising a first stage circuit to an m-th stage circuit, wherein each of the first stage circuit to the m-th stage circuit include: A first control node to a third control node; a node control circuit that controls a voltage of each of the first to third control nodes; as well as an output buffer circuit that outputs each of a scan signal, a sense signal, and a carry signal according to each of the first to third control nodes; The node control circuit includes a node setting circuit, and the node setting circuit charges a first gate high potential voltage to the first control node in response to a first carry signal provided from a previous stage circuit. The node setting circuit includes a first thin film transistor and a second thin film transistor, the first thin film transistor and the second thin film transistor are electrically connected in series between a first gate high potential voltage line transmitting the first gate high potential voltage and the first control node, and the first thin film transistor and the second thin film transistor are turned on together by a first carry signal of a first voltage, and The node setting circuit further includes a third thin film transistor, and the third thin film transistor always provides a second gate high potential voltage to a first connection node between the first thin film transistor and the second thin film transistor.

2. The gate drive circuit according to claim 1, in, The second gate high potential voltage is lower than the first gate high potential voltage.

3. The gate driving circuit according to claim 1, in, The third thin film transistor includes a (3-1)th thin film transistor and a (3-2)th thin film transistor, the (3-1)th thin film transistor and the (3-2)th thin film transistor are electrically connected in series between a second gate high potential voltage line transmitting the second gate high potential voltage and the first control node, and the (3-1)th thin film transistor and the (3-2)th thin film transistor are turned on together by the second gate high potential voltage.

4. The gate driving circuit according to claim 1, in, The second control node implemented in the n-th level circuit of the first-level circuit to the m-th level circuit is electrically connected to the third control node implemented in the (n+1)-th level circuit, and the third control node implemented in the n-th level circuit is electrically connected to the second control node implemented in the (n+1)-th level circuit.

5. The gate driving circuit according to claim 4, in, Each of the first to m-th level circuits further includes: an inverter circuit that controls a voltage of the second control node according to a voltage of the first control node; and A node reset circuit is configured to reset the voltage of the second control node to a gate low potential voltage in response to the first carry signal.

6. The gate driving circuit according to claim 5, in, The inverter circuit of the nth stage circuit further controls the voltage of the second control node of the nth stage circuit according to the voltage of the first control node of the (n+1)th stage circuit, and the inverter circuit of the (n+1)th stage circuit further controls the voltage of the second control node of the (n+1)th stage circuit according to the voltage of the first control node of the nth stage circuit.

7. The gate driving circuit according to claim 5, in, Each of the first to m-th level circuits comprises: Storage nodes; and a sensing control circuit that controls each of a voltage of the storage node and a voltage of the first control node, Among them, the sensing control circuit of the nth stage circuit also includes the following sensing control circuit, which controls the voltage of the storage node in response to the second carry signal and the line sensing ready signal provided from the previous stage circuit, outputs the first gate high potential voltage to the shared node according to the voltage of the storage node, and provides the first gate high potential voltage to the first control node in response to the first reset signal and the voltage of the storage node.

8. The gate driving circuit according to claim 7, in, The sensing control circuit of each of the first to m-th stage circuits resets the voltage of the first control node to the gate low potential voltage in response to a display panel turn-on signal.

9. The gate driving circuit according to claim 7, in, The node reset circuit of the n-th level circuit discharges the voltage of the first control node of the n-th level circuit using the gate low potential voltage in response to the first reset signal and the voltage of the storage node, and discharges the voltage of the first control node of the n-th level circuit using the gate low potential voltage in response to the second reset signal and the voltage of the storage node.

10. The gate driving circuit according to claim 7, in, The sensing control circuit of the (n+1)th level circuit is electrically connected to the storage node of the nth level circuit, and in response to the first reset signal, provides the first gate high potential voltage provided through the shared node of the nth level circuit to the first control node of the (n+1)th level circuit.

11. The gate driving circuit according to claim 9, in, The node reset circuit of the (n+1)th stage circuit discharges the voltage of the first control node using the gate low potential voltage in response to the first reset signal and the voltage of the storage node, and discharges the voltage of the first control node of the (n+1)th stage circuit using the gate low potential voltage in response to the second reset signal and the voltage of the storage node.

12. The gate drive circuit according to any one of claims 1 to 11, in, Each of the first-level circuits to the m-th-level circuits sequentially outputs the scan signal, the sensing signal and the carry signal during a vertical valid period of each frame cycle, and any one of the first-level circuits to the m-th-level circuits outputs the scan signal and the sensing signal during a vertical blank period of each frame cycle.

13. A light-emitting display device, include: A light emitting display panel, comprising: a plurality of pixels; a plurality of gate line groups, the plurality of gate line groups having first gate lines and second gate lines connected to the plurality of pixels; and a plurality of data lines and reference lines, the plurality of data lines and reference lines being connected to the plurality of pixels and crossing the plurality of gate line groups; a gate driving circuit unit connected to the plurality of gate line groups; a data driving circuit section connected to the plurality of data lines and the plurality of reference lines; and a timing controller that controls a driving timing of each of the gate driving circuit section and the data driving circuit section, Wherein, the gate driving circuit unit includes the gate driving circuit according to any one of claims 1 to 11.

14. The light-emitting display device according to claim 13, in, The timing controller controls the light-emitting display panel in a display mode and a sensing mode, the gate driving circuit unit provides a scanning signal and a sensing signal to any one of the plurality of gate line groups in the sensing mode, and the data driving circuit unit provides a sensing data voltage synchronized with the scanning signal to a plurality of data lines through the plurality of reference lines in the sensing mode and senses the driving characteristics of the pixels.

15. The light emitting display device according to claim 14, in, The timing controller controls the display mode in an image display period and a black display period, the gate driving circuit unit provides the scanning signal only to a first gate line corresponding to at least one of the plurality of gate line groups during the black display period, and the data driving circuit unit provides a black data voltage synchronized with the scanning signal to the plurality of data lines during the black display period.

16. The light emitting display device according to claim 15, in, Each of the plurality of pixels displays an image during the image display period, and displays a black image during the black display period.

17. The light emitting display device according to claim 13, in, The gate driving circuit section sequentially provides the scanning signal and the sensing signal to the plurality of gate line groups in a vertical effective period of each frame period, and outputs the scanning signal and the sensing signal to any one of the plurality of gate line groups in a vertical blank period of each frame period.

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