Method for manufacturing a display device

Abstract

A method for manufacturing a display device is disclosed, the method comprising: forming a pixel electrode on a substrate; forming a pixel defining layer, the pixel defining layer at least covering an edge of the pixel electrode and comprising an opening exposing a portion of the pixel electrode; 2 ) is added to the surface of the pixel electrode exposed by the opening in the pixel defining layer to perform a first dry cleaning, wherein oxygen (O 2 ) is added at a flow rate in a range of about 1200 sccm to about 3600 sccm. 2 ); performing a second dry cleaning after the first dry cleaning; forming an intermediate layer on the pixel electrode after the second dry cleaning; and forming a counter electrode on the intermediate layer and the pixel defining layer.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2020-0001565 filed on January 6, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more exemplary embodiments of the present invention relate to a method of manufacturing a display apparatus, and more particularly, to a method of manufacturing a display apparatus including performing dry cleaning on components of the display apparatus. Background Art

[0003] A display device is a device for displaying data. The display device may be used as a display for a small product such as a mobile phone, or may be used as a display for a large product such as a television.

[0004] Generally, a display device includes a plurality of pixels that receive an electrical signal and emit light based on the received electrical signal to display an image to the outside. Each pixel includes a light emitting device. For example, an organic light emitting display device includes an organic light emitting diode as a light emitting device. Generally, an organic light emitting display device includes a thin film transistor and an organic light emitting diode, and the organic light emitting diode itself emits light.

[0005] As applications of display devices have diversified, various designs have been attempted to improve the quality of display devices. For example, a light emitting device included in a display device having an increased lifespan has been developed. Summary of the invention

[0006] According to an exemplary embodiment of the present invention, a method for manufacturing a display device includes: forming a pixel electrode on a substrate; forming a pixel defining layer, the pixel defining layer at least covering an edge of the pixel electrode and including an opening exposing a portion of the pixel electrode; 2 ) is added to the surface of the pixel electrode exposed by the opening in the pixel defining layer to perform a first dry cleaning, wherein oxygen (O 2 ) is added at a flow rate in a range of about 1200 sccm to about 3600 sccm. 2 ); performing a second dry cleaning after the first dry cleaning; forming an intermediate layer on the pixel electrode after the second dry cleaning; and forming a counter electrode on the intermediate layer and the pixel defining layer.

[0007] In an exemplary embodiment of the present invention, the first dry cleaning includes removing organic residues from the surface of the pixel electrode.

[0008] In an exemplary embodiment of the present invention, the organic residue includes the same material as that of the pixel defining layer.

[0009] In an exemplary embodiment of the present invention, the method further includes: forming a planarization layer on the substrate; forming a contact hole passing through the planarization layer; and performing a third dry cleaning on the planarization layer and the contact hole.

[0010] In an exemplary embodiment of the present invention, the first dry cleaning is performed substantially the same as the third dry cleaning.

[0011] In an exemplary embodiment of the present invention, the method further includes performing a cleaning process between the first dry cleaning and the second dry cleaning.

[0012] In an exemplary embodiment of the present invention, the method further includes performing an oven process.

[0013] In an exemplary embodiment of the present invention, oxygen (O 2 ) during the first dry cleaning process has a flow rate greater than that of oxygen (O 2 )The flow rate during the second dry cleaning is large.

[0014] In an exemplary embodiment of the present invention, oxygen (O 2 ) to perform a second dry cleaning.

[0015] In an exemplary embodiment of the present invention, nitrogen (N) is added at a flow rate in a range of about 200 sccm to about 600 sccm. 2 ) to perform a second dry cleaning.

[0016] In an exemplary embodiment of the present invention, source power is applied during the first dry cleaning and the second dry cleaning.

[0017] In an exemplary embodiment of the present invention, the source power applied during the first dry cleaning is in the range of about 500 W to about 1500 W, and the source power applied during the second dry cleaning is in the range of about 300 W to about 800 W.

[0018] In an exemplary embodiment of the present invention, bias power is applied during the first dry cleaning.

[0019] In an exemplary embodiment of the present invention, the bias power applied during the first dry cleaning is in the range of about 750W to about 2250W.

[0020] In an exemplary embodiment of the present invention, pressure is applied during the first dry cleaning and the second dry cleaning.

[0021] In an exemplary embodiment of the present invention, the pressure applied during the first dry cleaning is in the range of about 5 mTorr to about 35 mTorr, and the pressure applied during the second dry cleaning is about 5 mTorr or less.

[0022] In an exemplary embodiment of the present invention, a process time of the first dry cleaning is in a range of about 15 seconds to about 45 seconds.

[0023] In an exemplary embodiment of the present invention, the process time of the second dry cleaning is in the range of about 50 seconds to about 80 seconds.

[0024] In an exemplary embodiment of the present invention, a portion of the pixel defining layer is removed during the first dry cleaning to increase the width of the opening exposing the portion of the pixel electrode.

[0025] In an exemplary embodiment of the present invention, the thickness of the pixel defining layer is reduced by about 1 μm or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 is a schematic plan view of a display device according to an exemplary embodiment of the present invention;

[0028] Figure 2 is a schematic plan view of a display panel according to an exemplary embodiment of the present invention;

[0029] Figure 3 is a circuit diagram of a pixel in a display device according to an exemplary embodiment of the present invention;

[0030] Figure 4 is a flowchart of a method of manufacturing a display device according to an exemplary embodiment of the present invention;

[0031] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Fig. 5F are cross-sectional views sequentially illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention;

[0032] Figure 6 is a diagram according to an exemplary embodiment of the present invention;

[0033] Figure 7 is a diagram according to an exemplary embodiment of the present invention;

[0034] Fig. 8A is a diagram according to an exemplary embodiment of the present invention; and

[0035] Figure 8B is a diagram according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0036] Exemplary embodiments of the present invention will now be more fully described with reference to the accompanying drawings. It will be understood that the present invention can be implemented in different forms and therefore should not be construed as being limited to the exemplary embodiments set forth herein. It will be understood that throughout the specification, the same reference numerals may refer to the same elements and therefore redundant descriptions may be omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0037] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the spirit and scope of the present invention, the first component discussed below may be referred to as the second component.

[0038] In addition, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0039] For the sake of clarity, the size of the components in the drawings may be exaggerated. In other words, because the size and thickness of the elements in the drawings may be exaggerated for the sake of clarity, the present invention is not limited thereto.

[0040] When the exemplary embodiments of the present invention can be implemented differently, the order of processes can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0041] In the following embodiments, it will be understood that when a film, layer, region, element or component is referred to as being "connected to" or "bonded to" another film, layer, region, element or component, the film, layer, region, element or component may be directly connected or bonded to the other film, layer, region, element or component or intervening elements may be present.

[0042] It will be understood that the x-axis, y-axis and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0043] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a schematic plan view of a display device 1 according to an exemplary embodiment of the present invention;

[0045] Reference Figure 1, the display apparatus 1 may include a display area DA in which an image is displayed and a peripheral area PA arranged around the display area DA. The display apparatus 1 may provide an image to the outside by using light emitted from the display area DA.

[0046] The substrate 100 may include various materials, such as glass, metal or plastic. According to an exemplary embodiment of the present invention, the substrate 100 may include a flexible material. A flexible material refers to a substrate that can be bent, folded or rolled. The substrate 100 including a flexible material may include, for example, ultra-thin glass, metal or plastic.

[0047] The pixel PX may be arranged in the display area DA of the substrate 100. The pixel PX may include a display element such as an organic light emitting diode. The pixel PX may include a plurality of pixels. The pixel PX may be arranged in various forms (e.g., a stripe form, a pentile form, or a mosaic form) and realize an image.

[0048] In a plan view, the display area DA may be configured in a rectangular shape, such as Figure 1 In an exemplary embodiment of the present invention, the display area DA may be provided in a polygonal shape (eg, a triangular shape, a pentagonal shape, a hexagonal shape, etc.), a circular shape, an elliptical shape, or a combination thereof.

[0049] The peripheral area PA of the substrate 100 is an area arranged around the display area DA and may be an area in which no image is displayed. Various lines configured to transmit electrical signals to the display area DA, pads (or "pads") to which a printed circuit board (PCB) or a driver integrated circuit (IC) chip is attached, etc. may be located in the peripheral area PA.

[0050] Figure 2 is a schematic plan view of a display panel 10 according to an exemplary embodiment of the present invention.

[0051] Reference Figure 2 , the display panel 10 may include a display area DA and a peripheral area PA and may include a plurality of pixels PX arranged in the display area DA. The pixels PX may each include a display element such as an organic light emitting diode. The pixels PX may each emit, for example, red light, green light, blue light, or white light from an organic light emitting diode. Hereinafter, in this specification, a pixel PX refers to a sub-pixel that emits light of different colors, and the pixels PX may each be, for example, one of a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. The display area DA may be covered with an encapsulation member to be protected from external air or moisture.

[0052] The pixels PX may each be electrically connected to an external circuit disposed in the peripheral area PA. A first scan driving circuit 130, a second scan driving circuit 131, an emission control driving circuit 133, a terminal 140, a data driving circuit 150, a first power line 160, and a second power line 170 may be disposed in the peripheral area PA.

[0053] The first scan driving circuit 130 and the second scan driving circuit 131 may provide scan signals to the pixels PX through the scan lines SL. The second scan driving circuit 131 may be arranged in parallel with the first scan driving circuit 130 with the display area DA therebetween. Some pixels PX arranged in the display area DA may be electrically connected to the first scan driving circuit 130, and other pixels PX may be electrically connected to the second scan driving circuit 131. In an exemplary embodiment of the present invention, the second scan driving circuit 131 may be omitted.

[0054] The emission control driving circuit 133 may provide an emission control signal to the pixel PX through the emission control line EL.

[0055] The terminal 140 may be arranged on one side of the substrate 100. The terminal 140 may be exposed without being covered by the insulating layer and thus may be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB may transmit a signal or power of the controller to the display panel 10.

[0056] The control signal generated by the controller can be transmitted to the first scan driving circuit 130 and the second scan driving circuit 131 through the printed circuit board PCB. The controller can respectively connect the first power supply voltage and the second power supply voltage ( Figure 3 The first power supply voltage (driving voltage) ELVDD can be provided to the pixel PX through the driving voltage line PL connected to the first power supply line 160, and the second power supply voltage ELVSS can be provided to the counter electrode ( Fig. 5F 230).

[0057] The data driving circuit 150 may be electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to the pixel PX through the connection line 151 and the data line DL. The connection line 151 is connected to the terminal 140 , and the data line DL is connected to the connection line 151 . Figure 2The data driving circuit 150 is shown to be disposed on the printed circuit board PCB. However, in an exemplary embodiment of the present invention, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

[0058] The first power line 160 may include a first sub-line 162 and a second sub-line 163 extending in parallel to each other and in the second direction DR2, and the display area DA is between the first sub-line 162 and the second sub-line 163. For example, the first sub-line 162 and the second sub-line 163 are respectively disposed at opposite sides of the display area DA. The second power line 170 may partially surround the display area DA. For example, the second power line 170 may have a square or rectangular shape with one side open.

[0059] Figure 3 is a circuit diagram of a pixel PX in a display device according to an exemplary embodiment of the present invention.

[0060] Reference Figure 3 , the pixel PX includes a pixel circuit PC connected to the scan line SL and the data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

[0061] The pixel circuit PC may include a driving thin film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 may be electrically connected to the scan line SL and the data line DL, and may be configured to transmit a data signal Dm to the driving TFT T1 through the data line DL according to a scan signal Sn input through the scan line SL.

[0062] The storage capacitor Cst may be electrically connected to the switching TFT T2 and the driving voltage line PL and may be configured to store a voltage corresponding to a difference between a voltage received from the switching TFT T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0063] The driving TFT T1 may be electrically connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light with a certain brightness according to the driving current.

[0064] Already referred to Figure 3 The case where the pixel circuit PC includes two TFTs and one storage capacitor is described, but the present invention is not limited thereto. For example, the pixel circuit PC may include three or more TFTs and / or two or more storage capacitors.

[0065] Figure 4 is a flowchart of a method of manufacturing a display device according to an exemplary embodiment of the present invention. FIG. 5A to FIG. 5F are cross-sectional views sequentially illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

[0066] Reference Figure 4 , manufacturing a display device according to an exemplary embodiment of the present invention ( Figure 1 The method of 1) may include: forming an insulating layer, etc. on a mother substrate 100' (S10); performing a first dry cleaning PT1 on the insulating layer, etc. (S20); forming a pixel electrode 210 and a pixel defining layer 119 (S30); performing a second dry cleaning PT2 on the pixel electrode 210 and the pixel defining layer 119 (S40); dividing the mother substrate 100' into a plurality of substrates 100 (S50); performing a third dry cleaning PT3 on the pixel electrode 210 and the pixel defining layer 119 (S80); and forming an intermediate layer 220 and a counter electrode 230 (S90).

[0067] In addition, in an exemplary embodiment of the present invention, after dividing the mother substrate 100 ′ into a plurality of substrates 100 , the method may further include performing a cleaning process ( S60 ) and an oven process ( S70 ).

[0068] The insulating layer and the like are formed on the mother substrate 100' (S10) and the gate insulating layer is sequentially formed on the mother substrate 100' (S20). Figure 5A 111 and 113) and interlayer insulation layer ( Figure 5A 115) corresponds to.

[0069] In an exemplary embodiment of the present invention, the first dry cleaning PT1 (S20) may be performed in the same manner as the second dry cleaning PT2 (S40), and the second dry cleaning PT2 may remove organic residues on the surface of the pixel electrode 210 ( Figure 5C In this case, the organic residue OR on the surface of the pixel electrode 210 may include the same material as that of the pixel defining layer 119. For example, the first dry cleaning PT1 may clean the planarization layer ( Figure 5B 117) on the upper surface.

[0070] In the following, reference will be made to FIG. 5A to FIG. 5F A method of manufacturing a display device according to an exemplary embodiment of the present invention is described in detail according to a stacking order.

[0071] Reference Figure 5AA buffer layer 110, semiconductor layers A1 and A2, a first gate insulating layer 111, gate electrodes G1 and G2, a second gate insulating layer 113, an upper electrode CE2, an interlayer insulating layer 115, and a planarization layer 117 are sequentially formed on a mother substrate 100'. The first gate electrode G1 of the gate electrodes G1 and G2 may also be a lower electrode CE1, and the lower electrode CE1 and the upper electrode CE2 may form a storage capacitor Cst.

[0072] The mother substrate 100' may include, for example, a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the mother substrate 100' is flexible or bendable, the mother substrate 100' may include, for example, a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0073] The mother substrate 100' may have a single layer or multilayer structure including the above-mentioned materials. In the case of a multilayer structure, the mother substrate 100' may further include an inorganic layer. In an exemplary embodiment of the present invention, the mother substrate 100' may have a structure including a first organic layer, an inorganic layer disposed on the first organic layer, and a second organic layer disposed on the inorganic layer.

[0074] The buffer layer 110 may include, for example, silicon oxide (SiO 2 ) or silicon nitride (SiN x ), and can be formed by a deposition process such as chemical vapor deposition (CVD) or sputtering.

[0075] A barrier layer may be further included between the mother substrate 100' and the buffer layer 110. The barrier layer may prevent or minimize impurities from penetrating from the mother substrate 100', etc. into the semiconductor layers A1 and A2. The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite, and may have a single-layer structure or a multi-layer structure including an inorganic material and an organic material.

[0076] Semiconductor layers A1 and A2 may be arranged on the buffer layer 110. The semiconductor layers A1 and A2 may be formed by patterning an initial semiconductor layer. The initial semiconductor layer may include, for example, amorphous silicon or an oxide semiconductor, and may be deposited by CVD. In addition, for example, when the initial semiconductor layer includes an amorphous silicon layer, after film formation, the initial semiconductor layer may be crystallized into a polycrystalline silicon layer by various methods such as rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), or sequential lateral solidification (SLS).

[0077] In an exemplary embodiment of the present invention, the semiconductor layers A1 and A2 may each include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and zinc (Zn).

[0078] The semiconductor layers A1 and A2 may each include a channel region and a source region and a drain region disposed on both sides of the channel region. The semiconductor layers A1 and A2 may each be a single layer or a multilayer.

[0079] The first gate insulating layer 111 and the second gate insulating layer 113 may be stacked and arranged on the mother substrate 100' to cover the semiconductor layers A1 and A2. The first gate insulating layer 111 and the second gate insulating layer 113 may each include, for example, silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO 2 ), and each may be formed by a deposition process such as CVD or sputtering. However, the present invention is not limited thereto.

[0080] The gate electrodes G1 and G2 may be arranged on the first gate insulating layer 111 to at least partially overlap with the semiconductor layers A1 and A2. For example, the gate electrodes G1 and G2 may overlap with the channel regions of the semiconductor layers A1 and A2, respectively. The gate electrodes G1 and G2 may each include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or multiple layers. For example, the gate electrodes G1 and G2 may each be a single Mo layer.

[0081] The gate electrodes G1 and G2 are shown to be disposed on the first gate insulating layer 111, but in an exemplary embodiment of the present invention, the gate electrodes G1 and G2 may be disposed on the second gate insulating layer 113. In addition, the gate electrodes G1 and G2 of the TFTs TFT1 and TFT2 may be disposed on the same layer or may be disposed on layers different from each other.

[0082] The lower electrode CE1 of the storage capacitor Cst may be arranged on the first gate insulating layer 111, and the lower electrode CE1 of the storage capacitor Cst may include the same material as the gate electrodes G1 and G2. The upper electrode CE2 of the storage capacitor Cst may overlap the lower electrode CE1 (with the second gate insulating layer 113 therebetween) and may generate capacitance. In this case, the second gate insulating layer 113 may serve as a dielectric layer of the storage capacitor Cst.

[0083] like Figure 5A As shown in , the lower electrode CE1 of the storage capacitor Cst may overlap the first TFT TFT1. For example, the gate electrode G1 of the first TFT TFT1 may serve as the lower electrode CE1 of the storage capacitor Cst.

[0084] In order to form the gate electrodes G1 and G2 and the lower electrode CE1 of the storage capacitor Cst, a metal layer may be formed on the surface of the mother substrate 100' and then patterned. For example, a metal layer may be provided on the entire surface of the mother substrate 100' before patterning the metal layer. The metal layer may be formed by a deposition process such as CVD, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD), but the present invention is not limited thereto. The method of forming the upper electrode CE2 of the storage capacitor Cst may be substantially the same as the method of forming the gate electrodes G1 and G2 and the lower electrode CE1 of the storage capacitor Cst.

[0085] The interlayer insulating layer 115 may be formed to cover the upper electrode CE2 of the storage capacitor Cst on the surface of the mother substrate 100'. For example, the interlayer insulating layer 115 may be disposed on the entire surface of the mother substrate 100'. The interlayer insulating layer 115 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO 2 ), and may be formed by a deposition process such as CVD or sputtering. However, the present invention is not limited thereto.

[0086] The first contact hole CNT1 may be formed to pass through the first and second gate insulating layers 111 and 113 and the interlayer insulating layer 115 , and may expose the source region and / or the drain region of the semiconductor layers A1 and A2 .

[0087] The source electrodes S1 and S2 and the drain electrodes D1 and D2 may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may each be a single layer or a multilayer including the above materials. For example, the source electrodes S1 and S2 and the drain electrodes D1 and D2 may each have a multilayer structure of Ti / Al / Ti. The source electrodes S1 and S2 and the drain electrodes D1 and D2 may be connected to the source region or the drain region of the semiconductor layers A1 and A2 through the first contact hole CNT1. For example, the source electrodes S1 and S2 may be connected to the source region of the semiconductor layers A1 and A2, and the drain electrodes D1 and D2 may be connected to the drain region of the semiconductor layers A1 and A2.

[0088] The source electrodes S1 and S2 and the drain electrodes D1 and D2 may be covered with an inorganic protective layer. The inorganic protective layer may be silicon nitride (SiN X ) and silicon oxide (SiO X An inorganic protective layer may be provided to cover and protect some lines arranged on the interlayer insulating layer 115.

[0089] A planarization layer 117 may be disposed on the interlayer insulating layer 115 to cover the source electrodes S1 and S2 and the drain electrodes D1 and D2. The planarization layer 117 may be a single layer or multiple layers including an organic material or an inorganic material. The planarization layer 117 may include a general polymer (e.g., benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS)), a polymer derivative having a phenolic group, an acryl polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and any blends thereof. The planarization layer 117 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO 2 After the planarization layer 117 is formed, chemical mechanical polishing may be performed on the planarization layer 117 to provide a flat upper surface.

[0090] Reference Figure 5B , a second contact hole CNT2 that passes through the planarization layer 117 and exposes the drain electrodes D1 and D2 may be formed by a mask process.

[0091] After forming the second contact hole CNT2, the first dry cleaning PT1 may be performed on the planarization layer 117. In an exemplary embodiment of the present invention, the first dry cleaning PT1 may be a plasma treatment. The plasma treatment corresponds to a step of introducing oxygen (O 2 ) or argon (Ar) gas to apply radio frequency to generate plasma and irradiate the surface of the planarization layer 117 to clean the surface of the planarization layer 117 through a chemical reaction.

[0092] In an exemplary embodiment of the present invention, oxygen (O 2 ) to perform the first dry cleaning PT1. Because oxygen (O 2 ) has a higher partial pressure than the partial pressures of other gases, so the residue of the planarization layer 117 generated when the second contact hole CNT2 is formed can be effectively removed.

[0093] In an exemplary embodiment of the present invention, oxygen (O 2 ) can be in the range of about 1200 sccm to about 3600 sccm. When oxygen (O 2 ) to perform the first dry cleaning PT1, foreign matter or particles can be removed from the surface of the planarization layer 117 at a rate of about 900 angstroms / minute.

[0094] In an exemplary embodiment of the present invention, pressure may be applied during the first dry cleaning PT1, and source power may be applied to generate plasma. For example, oxygen (O 2 ) is used to make an ionized gas. In an exemplary embodiment of the present invention, the pressure may be in the range of about 5 mTorr to about 35 mTorr, and the source power may be in the range of about 500 W to about 1500 W.

[0095] In an exemplary embodiment of the present invention, a bias power may also be applied during the first dry cleaning PT1. When the bias power is applied, the gas ionized by the source power is attracted to a voltage with an opposite polarity by the bias power. Therefore, the kinetic energy may be increased, thereby more effectively removing residues and the like from the planarization layer 117. In addition, when the bias power is applied, residues and the like may be uniformly removed from the planarization layer 117. In an exemplary embodiment of the present invention, the bias power may be applied in a range of about 750W to about 2250W.

[0096] Reference Figure 5C , the pixel electrode 210 may be formed on the planarization layer 117. The pixel electrode 210 may be formed by, for example, depositing a conductive layer on the entire upper surface of the planarization layer 117 and performing a mask process and an etching process on the planarization layer 117.

[0097] The pixel electrode 210 may include a (semi) transmissive electrode or a reflective electrode. In an exemplary embodiment of the present invention, the pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer arranged above the reflective layer. The reflective layer may include, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or any mixture thereof. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an exemplary embodiment of the present invention, the pixel electrode 210 may include ITO / Ag / ITO.

[0098] Because the second contact hole ( Figure 5B The pixel electrode 210 may be electrically connected to the drain electrodes D1 and D2 through the second contact hole CNT2. For example, the pixel electrode 210 may be connected to the first drain electrode D1 through the second contact hole CNT2.

[0099] A pixel defining layer 119 may be formed on the planarization layer 117. For example, the pixel defining layer 119 may be formed on the entire upper surface of the planarization layer 117. The pixel defining layer 119 may cover at least an edge of the pixel electrode 210 and include an opening OP exposing a central portion of the pixel electrode 210. The pixel defining layer 119 may include at least one organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin, and may be formed by spin coating or the like.

[0100] The pixel defining layer 119 can increase the distance between the edge of the pixel electrode 210 and the counter electrode ( Fig. 5F 230), thereby preventing arcing, etc. from occurring at the edge of the pixel electrode 210.

[0101] After forming the pixel defining layer 119, a second dry cleaning PT2 may be performed on the pixel defining layer 119. In an exemplary embodiment of the present invention, the second dry cleaning PT2 may be performed with Figure 5B The first dry cleaning PT1 performed in the embodiment is substantially the same as that performed in the embodiment of the present invention. For example, the second dry cleaning PT2 may be a plasma treatment and may be performed by adding oxygen (O 2) in a range of about 1200 sccm to about 3600 sccm. 2 ) to execute.

[0102] When, as in the present embodiment, oxygen (O 2 ) to perform the second dry cleaning PT2, oxygen (O 2) is higher than the partial pressure of other gases. Therefore, the organic residue OR (e.g., the residue of the pixel defining layer 119) generated on the surface of the pixel electrode 210 while forming the opening OP of the pixel defining layer 119 can be effectively removed. For example, when oxygen (O 2 ) to perform the second dry cleaning PT2, the organic residue OR can be removed from the pixel electrode 210 at a rate of about 900 angstroms / minute.

[0103] In an exemplary embodiment of the present invention, pressure may be applied during the second dry cleaning PT2, and source power and bias power may also be applied. In an exemplary embodiment of the present invention, during the second dry cleaning PT2, pressure may be applied in the range of about 5 mTorr to about 35 mTorr, source power may be applied in the range of about 500 W to about 1500 W, and bias power may be applied in the range of about 750 W to about 2250 W.

[0104] In the comparative example, when dry cleaning is not performed after forming the pixel defining layer, organic residues corresponding to a portion of the pixel defining layer may exist on the surface of the pixel electrode. This may change the characteristics of the organic light emitting diode OLED on which the pixel electrode is arranged. Therefore, the life of the organic light emitting diode OLED may be shortened.

[0105] Therefore, in the present embodiment, the second dry cleaning PT2 may be performed after forming the pixel defining layer 119. When the pixel defining layer 119 including the opening OP is formed and the second dry cleaning PT2 is performed after forming the pixel defining layer 119. 2 ) and applying pressure, source power, bias power, etc. to perform a second dry cleaning PT2, the organic residue OR can be evenly removed from the surface of the pixel electrode 210, thereby improving the surface properties of the pixel electrode 210 and increasing the life of the light-emitting device including the intermediate layer 220 as an emission layer arranged on the pixel electrode 210.

[0106] In an exemplary embodiment of the present invention, the process time of the second dry cleaning PT2 may be in the range of about 15 seconds to about 45 seconds. In this case, the life of the light emitting device may be further increased. Figure 6 Describe this.

[0107] In an exemplary embodiment of the present invention, a portion of the pixel defining layer 119 may be removed during the second dry cleaning PT2 to increase the width of the opening OP of the pixel defining layer 119. When the width of the opening OP increases, the aperture ratio may increase. When the same driving current as that applied before the aperture ratio is increased is supplied, a higher brightness may be obtained due to the increased aperture ratio. In addition, when the aperture ratio increases, the life of the light emitting device may be further increased.

[0108] In an exemplary embodiment of the present invention, when the process time of the second dry cleaning PT2 is about 30 seconds, the Figure 1 The size of the pixel PX in the display area DA shown in FIG. 1 may be increased to about 1 μm or less, for example, about 0.2 μm to about 0.3 μm. The increase in the size of the pixel PX may be caused by a decrease in the thickness of the pixel defining layer 119 by about 1 μm or less when the second dry cleaning PT2 is performed for about 30 seconds.

[0109] In this embodiment, when the thickness of the pixel defining layer 119 is reduced by about 1 μm or less and the size of the pixel PX is increased by about 1 μm or less (e.g., about 0.2 μm to about 0.3 μm) due to the second dry cleaning PT2, the lifespan of a light-emitting device such as an organic light-emitting diode OLED can be increased by about 20 hours.

[0110] Reference Figure 5D After the second dry cleaning PT2, the mother substrate 100' may be divided into a plurality of substrates 100 and subsequent processes may be performed on the plurality of substrates 100. In an exemplary embodiment of the present invention, the mother substrate 100' may be divided into a plurality of substrates 100 by, for example, laser cutting.

[0111] Reference Figure 5E In an exemplary embodiment of the present invention, a cleaning process may be sequentially performed on the surfaces of the pixel electrode 210 and the pixel defining layer 119 disposed on the substrate 100. Figure 4 S60), oven process ( Figure 4 S70) and the third dry cleaning PT3 ( Figure 4 In addition, for the sake of convenience, Figure 5E One substrate among the plurality of substrates 100 is shown as an example. In addition, the aforementioned process steps (S60, S70, S80) may be applied to the plurality of substrates 100.

[0112] In an exemplary embodiment of the present invention, the cleaning process S60 may be performed by using water (H 2 The oven process S70 may be used to remove residual particles and the like existing on the surfaces of the pixel electrode 210 and the pixel defining layer 119 by washing the residual particles and the like. The oven process S70 may be used to evaporate the water (H2O) used during the washing process (S60) by heat.2 O) and other process correspondence.

[0113] In an exemplary embodiment of the present invention, the third dry cleaning PT3 may be a plasma treatment. 2 ) and oxygen (O 2 ) is added to the surface of the pixel electrode 210 and the pixel defining layer 119 to perform the third dry cleaning PT3. For example, nitrogen (N 2 ) may have a flow rate in the range of about 200 sccm to about 600 sccm, and oxygen (O 2 ) can be in the range of about 20 sccm or less. For example, the oxygen gas (O 2 ) may be greater than the flow rate of oxygen (O 2 ) has a high flow rate.

[0114] In addition, in an exemplary embodiment of the present invention, pressure may be applied during the third dry cleaning PT3, and source power may be applied to generate plasma. For example, oxygen (O 2 In an exemplary embodiment of the present invention, the pressure during the third dry cleaning PT3 may be about 5 mTorr or less, and the source power may be in the range of about 300 W to about 800 W.

[0115] In this embodiment, when the source power applied during the third dry cleaning PT3 is in the range of about 300W to about 800W, the life of the light emitting device can be further increased. In addition, because the source power is low, defects caused by static electricity can be reduced. Figure 7 Describe this.

[0116] In the comparative example, the dry cleaning after the oven process is omitted. In this case, the work function of the pixel electrode is reduced. Since the work function of the pixel electrode involves the hole injection into the emission layer, this interferes with the hole injection in the pixel electrode.

[0117] However, when nitrogen (N) is added after the oven process S70 according to the present embodiment, 2 ) and oxygen (O 2 ) and applying pressure, source power, etc. to perform the third dry cleaning PT3, the work function of the pixel electrode 210 will increase. The increase in the work function can promote hole injection into the intermediate layer 220 to increase the efficiency of the light-emitting device such as the organic light-emitting diode OLED. In addition, the organic residue OR that may partially remain on the surface of the pixel electrode 210 can be removed by the third dry cleaning PT3.

[0118] In an exemplary embodiment of the present invention, the process time of the third dry cleaning PT3 may be adjusted. For example, the process time of the third dry cleaning PT3 may be in the range of about 50 seconds to about 80 seconds, for example, about 65 seconds.

[0119] Reference Fig. 5F For example, the pixel defining layer 119 may be provided with a plurality of holes formed therein. FIG. 5C to FIG. 5E An intermediate layer 220 is formed on the pixel electrode 210 on which the surface treatment is performed. The intermediate layer 220 may include a low molecular weight material or a high molecular weight material. The intermediate layer 220 may be formed by, for example, vacuum deposition, screen printing, inkjet printing, or laser induced thermal imaging (LITI).

[0120] The intermediate layer 220 of the organic light emitting diode OLED may include an organic emission layer. The organic emission layer may include an organic material, and the organic material includes a fluorescent or phosphorescent material that emits red light, green light, blue light or white light. The organic emission layer may be a low molecular weight organic material or a high molecular weight organic material. For example, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL) may be arranged above and below the organic emission layer. The intermediate layer 220 may be arranged to correspond to each of the pixel electrodes 210. However, the present invention is not limited thereto. For example, various modifications may be made to the intermediate layer 220. For example, the intermediate layer 220 may include an integral layer above the pixel electrode 210.

[0121] The counter electrode 230 may be formed to correspond to the organic light emitting diode OLED. For example, the counter electrode 230 may be disposed on the intermediate layer 220 and may overlap the pixel electrode 210. The counter electrode 230 may be formed to cover the display area ( Figure 1 The counter electrode 230 may be formed by, for example, a deposition process such as CVD, PECVD, LPCVD, PVD, sputtering, or ALD.

[0122] The counter electrode 230 may include a transmissive electrode or a reflective electrode. In an exemplary embodiment of the present invention, the counter electrode 230 may include a transparent or semi-transparent electrode and may include a metal thin film having a low work function and containing, for example, Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or any mixture thereof. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In may be disposed on the metal thin film. 2 O 3 .

[0123] Figure 6 , Figure 7 , Fig. 8A and Figure 8Bis a diagram according to an exemplary embodiment of the present invention.

[0124] Figure 6 : is a graph showing the white (W) luminance life according to the process time of the second dry cleaning PT2.

[0125] Figure 6 The white (W) luminance life when the second dry cleaning PT2 is omitted and the third dry cleaning PT3 is performed for about 65 seconds at a source power of about 1000 W (reference 1) is shown. In addition, Figure 6 The white (W) brightness lifetime when both the second dry cleaning PT2 and the third dry cleaning PT3 are omitted (reference 2) and the white (W) brightness lifetime when the second dry cleaning PT2 is performed for about 15 seconds to about 100 seconds and the third dry cleaning PT3 is performed for about 65 seconds with a source power of about 800W are shown.

[0126] Figure 6 The brightness life time (hours) shown in refers to the amount of time it takes for the brightness to decay from 100% to 93%. For example, Figure 6 The time (hours) of the luminance life shown in FIG. 1 is the time measured until the luminance decreases by 7%.

[0127] When the second dry cleaning PT2 is omitted and the third dry cleaning PT3 is performed for about 65 seconds with a source power of about 1000W (reference 1), the white (W) brightness life is about 330 hours, and when both the second dry cleaning PT2 and the third dry cleaning PT3 are omitted (reference 2), the white (W) brightness life is about 312 hours.

[0128] When the second dry cleaning PT2 is performed for approximately 15 seconds to approximately 100 seconds and the third dry cleaning PT3 is performed for approximately 65 seconds with a source power of approximately 800 W, the white (W) brightness life is approximately 468 hours to approximately 574 hours, which is further increased compared to when the second dry cleaning PT2 is omitted (reference 1) and when both the second dry cleaning PT2 and the third dry cleaning PT3 are omitted (reference 2).

[0129] For example, since the white (W) luminance lifetime is shortest when both the second dry cleaning PT2 and the third dry cleaning PT3 are omitted (reference 2), it can be seen that the second dry cleaning PT2 and the third dry cleaning PT3 are associated with the luminance lifetime.

[0130] In an exemplary embodiment of the present invention, the process time of the second dry cleaning PT2 may be in the range of about 15 seconds to about 45 seconds, and the process time of the third dry cleaning PT3 may be in the range of about 50 seconds to about 80 seconds, for example, about 65 seconds. In addition, a source power of about 800 W may be applied during the third dry cleaning PT3. In this case, referring to Figure 6 , it can be seen that the brightness life of white (W) increases the most.

[0131] For example, according to an exemplary embodiment of the present invention, the Figure 5C All organic residues on the surface of 210) Figure 5C The surface characteristics of the pixel electrode 210 can be improved. As a result, an intermediate layer ( Fig. 5F 220) of the life of the light-emitting device.

[0132] Figure 7 is a graph showing white (W) luminance lifetime according to source power applied during the third dry cleaning PT3.

[0133] For example, Figure 7 1 shows the white (W) luminance lifetime by changing the conditions of the third dry cleaning PT3 after performing the second dry cleaning PT2 for about 15 seconds. The luminance lifetime can be compared with the above reference Figure 6 The time described corresponds to the time taken until the brightness drops by 7%.

[0134] In an exemplary embodiment of the present invention, the process time of the third dry cleaning PT3 may be adjusted. For example, the third dry cleaning PT3 may be performed for about 50 seconds to about 80 seconds, for example, about 65 seconds.

[0135] Reference Figure 7 , when the third dry cleaning PT3 is performed with a source power of about 800W, the white (W) brightness life is about 555 hours. When the third dry cleaning PT3 is performed with a source power of about 1000W, the white (W) brightness life is about 374 hours. In addition, when the third dry cleaning PT3 is performed with a source power of about 2000W, the white (W) brightness life is about 419 hours. In this way, it can be seen that when the source power applied during the third dry cleaning PT3 is about 800W, the white (W) brightness life increases the most.

[0136] In an exemplary embodiment of the present invention, the source power applied during the third dry cleaning PT3 may be in the range of 300 W to 800 W. In this case, the brightness life can be increased. In addition, because the source power is low, defects caused by static electricity generated on the surface of the pixel electrode 210 can be reduced.

[0137] Fig. 8A is a graph showing the green (G) luminance life according to the process time of the second dry cleaning PT2 and the conditions of the third dry cleaning PT3, Figure 8B is a graph showing the blue (B) luminance life according to the process time of the second dry cleaning PT2 and the conditions of the third dry cleaning PT3.

[0138] Fig. 8A and Figure 8B The improvement rates (%) of the brightness lifetimes of green (G) and blue (B) based on the brightness lifetime when the second dry cleaning PT2 is omitted (reference 1) are shown in the following cases: when the third dry cleaning PT3 is performed with a source power of about 800 W and the process time of the second dry cleaning PT2 is changed (corresponding to the white dots); when the third dry cleaning PT3 is performed with a source power of about 1000 W and the process time of the second dry cleaning PT2 is changed (corresponding to the shaded dots); and when the third dry cleaning PT3 is performed with a source power of about 2000 W and the process time of the second dry cleaning PT2 is changed (corresponding to the black dots).

[0139] It can be seen that the luminance lifespans of green (G) and blue (B) increase more when the second dry cleaning PT2 is performed than when the second dry cleaning PT2 is omitted (reference 1).

[0140] For example, refer to Fig. 8A In region I, when the third dry cleaning PT3 is performed with a source power of about 800 W and the process time of the second dry cleaning PT2 is in the range of about 15 seconds to about 30 seconds, the green (G) brightness lifetime can be increased by about 70%, compared to when the second dry cleaning PT2 is omitted (reference 1).

[0141] Similarly, refer to Figure 8B In region II, when the third dry cleaning PT3 is performed with a source power of about 800 W and the process time of the second dry cleaning PT2 is in the range of about 15 seconds to about 30 seconds, the blue (B) brightness lifetime can be increased by about 250%, compared to when the second dry cleaning PT2 is omitted (reference 1).

[0142] In addition, comparing the conditions of the third dry cleaning PT3 when the second dry cleaning PT2 is performed for about 15 seconds to about 30 seconds, it can be seen that when the source power is about 800W, the brightness life of green (G) and blue (B) increases the most.

[0143] In an exemplary embodiment of the present invention, the second dry cleaning PT2 and the third dry cleaning PT3 may be performed before the intermediate layer 220 as the emission layer is deposited on the pixel electrode 210. In this way, the organic residue OR may be removed from the pixel electrode 210, thereby increasing the life of the light emitting device including the intermediate layer 220. In addition, since the work function of the pixel electrode 210 may be increased, hole injection in the pixel electrode 210 may be promoted.

[0144] As described above, according to the exemplary embodiments of the present invention, a method of manufacturing a display device in which the life of a light emitting device is increased can be provided. The scope of the present invention is not limited by these effects.

[0145] Although the present invention has been described with reference to exemplary embodiments thereof, workers skilled in the art will recognize that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a display device, the method comprising: forming a pixel electrode on a substrate; forming a pixel defining layer, wherein the pixel defining layer at least covers an edge of the pixel electrode and comprises an opening for exposing a portion of the pixel electrode; performing a first dry cleaning by adding oxygen to a surface of the pixel electrode exposed by the opening in the pixel defining layer, wherein the oxygen is added at a flow rate in a range of 1200 sccm to 3600 sccm; performing a cleaning process and an oven process after the first dry cleaning; performing a second dry cleaning by adding nitrogen and oxygen to surfaces of the pixel electrode and the pixel defining layer after the oven process; forming an intermediate layer on the pixel electrode after the second dry cleaning; and A counter electrode is formed on the intermediate layer and the pixel defining layer.

2. The method according to claim 1, wherein: The first dry cleaning includes removing organic residues from the surface of the pixel electrode.

3. The method according to claim 2, wherein: The organic residue includes the same material as that of the pixel defining layer.

4. The method according to claim 1, further comprising: forming a planarization layer on the substrate; forming a contact hole through the planarization layer; as well as A third dry cleaning is performed on the planarization layer and the contact hole.

5. The method according to claim 4, wherein: The execution of the first dry cleaning is the same as the execution of the third dry cleaning.

6. The method according to claim 1, wherein: A flow rate of the oxygen gas during the first dry cleaning is greater than a flow rate of the oxygen gas during the second dry cleaning.

7. The method according to claim 6, wherein: The second dry cleaning is performed by adding the oxygen gas at a flow rate of 20 sccm or less.

8. The method according to claim 7, wherein: The second dry cleaning is performed by adding nitrogen gas at a flow rate in a range of 200 sccm to 600 sccm.

9. The method according to claim 1, wherein: applying source power during the first dry cleaning and the second dry cleaning, and wherein the source power applied during the first dry cleaning is in the range of 500W to 1500W, and The source power applied during the second dry cleaning is in the range of 300W to 800W.

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