Display device and method of driving the same

Abstract

The present invention discloses a display device and a method for driving the display device. The display device includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and a second scan line; a first scan driver connected to a first scan start line and a first scan line; and a second scan driver connected to a second scan start line and a second scan line. In a first frame period, after a first scan start signal with a conduction level is supplied to the first scan start line, a second scan start signal with a conduction level is supplied to the second scan start line after a first period. In a second frame period, the difference between the time when the first scan start signal with a conduction level is supplied and the time when the second scan start signal with a conduction level is supplied corresponds to a second period. The second period is shorter than the first period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0173279 filed in the Korean Intellectual Property Office on December 23, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display device and a driving method thereof. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information increases. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly being utilized.

[0005] Each pixel of the display device may emit light having brightness corresponding to a data voltage supplied through a data line, and the display device may display an image frame by using a combination of the light emitted from the pixels.

[0006] A plurality of pixels may be connected to each data line. Therefore, a scan driver is required to provide a scan signal for selecting a pixel to be supplied with a data voltage among the plurality of pixels. The scan driver is configured in the form of a shift register to sequentially provide a scan signal having a conduction level in units of scan lines.

[0007] A clock signal may be provided to control the scan driver. As the frequency of the clock signal becomes higher and higher, more and more power consumption is required. Summary of the invention

[0008] Aspects of the embodiments relate to a display device in which the frequency of a clock signal is controlled according to a type of a frame so that power consumption can be reduced, and a driving method of the display device.

[0009] According to an embodiment of the present disclosure, a display device is provided, which includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and the second scan line; a first scan driver connected to the first scan start line and the first scan line; and a second scan driver connected to the second scan start line and the second scan line, wherein, in a first frame period, after a first period of time has passed after a first scan start signal with a conduction level is supplied to the first scan start line, the second scan start line is supplied with a second scan start signal with a conduction level, wherein in a second frame period, a difference between a time when the first scan start signal with the conduction level is supplied and a time when the second scan start signal with the conduction level is supplied corresponds to a second period of time, wherein the second period of time is shorter than the first period of time.

[0010] In the first frame period, the first scan clock signal supplied to the first scan driver may have a first cycle. In the second frame period, the first scan clock signal may have a second cycle longer than the first cycle.

[0011] In the first frame period, the second scan clock signal supplied to the second scan driver may have a first cycle. In the second frame period, the second scan clock signal may have a second cycle.

[0012] The display device may further include: a first emission driver connected to the first emission stop line and the first emission line; and a second emission driver connected to the second emission stop line and the second emission line. The first pixel may be connected to the first emission line, and the second pixel may be connected to the second emission line. In the first frame period, after the first emission stop signal with a cut-off level is supplied to the first emission stop line, after a third period, the second emission stop line may be supplied with a second emission stop signal with a cut-off level. In the second frame period, the difference between the time when the first emission stop signal with a cut-off level is supplied and the time when the second emission stop signal with a cut-off level is supplied may correspond to a fourth period. The fourth period may be shorter than the third period.

[0013] In the first frame period, the first emission clock signal supplied to the first emission driver may have a third cycle. In the second frame period, the first emission clock signal may have a fourth cycle longer than the third cycle.

[0014] In the first frame period, the second emission clock signal supplied to the second emission driver may have a third cycle. In the second frame period, the second emission clock signal may have a fourth cycle.

[0015] The display device may further include a third pixel connected to the first data line and a third scan line as a next scan line of the first scan line. The third scan line may be connected to the first scan driver. In the first frame period, the difference between the time when the first scan signal with the on level is applied to the first scan line and the time when the third scan signal with the on level is applied to the third scan line may correspond to the third period. In the second frame period, the difference between the time when the first scan signal with the on level is applied and the time when the third scan signal with the on level is applied may correspond to the fourth period. The fourth period may be longer than the third period.

[0016] The display device may further include a fourth pixel connected to the first data line and a fourth scan line as a next scan line of the second scan line. The fourth scan line may be connected to the second scan driver. In the first frame period, the difference between the time when the second scan signal with the on level is applied to the second scan line and the time when the fourth scan signal with the on level is applied to the fourth scan line may correspond to the third period. In the second frame period, the difference between the time when the second scan signal with the on level is applied and the time when the fourth scan signal with the on level is applied may correspond to the fourth period.

[0017] The display device may further include a fifth pixel connected to the first data line and a fifth scan line which is a previous scan line of the second scan line. The fifth scan line may be connected to the first scan driver. In the first frame period, the time when the fifth scan signal with the conduction level is applied to the fifth scan line may be earlier than the time when the second scan signal with the conduction level is applied. In the second frame period, the time when the fifth scan signal with the conduction level is applied may be later than the time when the second scan signal with the conduction level is applied.

[0018] A minimum value of the second period may be 0 seconds, and a maximum value of the second period may correspond to a vertical blanking period.

[0019] When the number of pixels connected to the first data line between the first pixel and the second pixel is X and the horizontal period is Y, the first period may correspond to (X+1)×Y.

[0020] According to another embodiment of the present disclosure, a method for driving a display device is provided, the method comprising: in a first frame period, supplying a first scan start signal with an on-level to a first scan start line connected to a first scan driver; in the first frame period, after a first period has passed after the first scan start signal with an on-level is supplied, supplying a second scan start signal with an on-level to a second scan start line connected to a second scan driver; and in a second frame period which is a next frame period of the first frame period, supplying the first scan start signal with an on-level and the second scan start signal with an on-level with a time difference of a second period, wherein the second period is shorter than the first period.

[0021] In the first frame period, the first scan clock signal supplied to the first scan driver may have a first cycle. In the second frame period, the first scan clock signal may have a second cycle longer than the first cycle.

[0022] In the first frame period, the second scan clock signal supplied to the second scan driver may have a first cycle. In the second frame period, the second scan clock signal may have a second cycle.

[0023] The method may further include: supplying a first emission stop signal having a cutoff level to a first emission stop line connected to a first emission driver in a first frame period; supplying a second emission stop signal having a cutoff level to a second emission stop line connected to a second emission driver after a third period has passed after the first emission stop signal having a cutoff level is supplied in the first frame period; and supplying the first emission stop signal having a cutoff level and the second emission stop signal having a cutoff level with a time difference of a fourth period in a second frame period. The fourth period may be shorter than the third period.

[0024] In the first frame period, the first emission clock signal supplied to the first emission driver may have a third cycle. In the second frame period, the first emission clock signal may have a fourth cycle longer than the third cycle.

[0025] In the first frame period, the second emission clock signal supplied to the second emission driver may have a third cycle. In the second frame period, the second emission clock signal may have a fourth cycle.

[0026] The method may further include: supplying a first scan signal having an on-level to a first scan line by a first scan driver in a first frame period; supplying a second scan signal having an on-level to a second scan line, which is a next scan line of the first scan line, by the first scan driver after a third period has passed after the first scan signal having an on-level is supplied in the first frame period; and supplying the first scan signal having an on-level and the second scan signal having an on-level with a time difference of a fourth period by the first scan driver in a second frame period. The fourth period may be longer than the third period.

[0027] The method may further include: in a first frame period, supplying a third scan signal with an on-level to a third scan line by a second scan driver; in the first frame period, after a third period has passed after the third scan signal with an on-level is supplied, supplying a fourth scan signal with an on-level to a fourth scan line which is the next scan line of the third scan line by the second scan driver; and in a second frame period, supplying the third scan signal with an on-level and the fourth scan signal with an on-level with a time difference of the fourth period by the second scan driver.

[0028] The method may further include: in the first frame period, supplying, by the first scan driver, a fifth scan signal having an on level to a fifth scan line which is a previous scan line of the third scan line. In the first frame period, the fifth scan signal having an on level may be supplied earlier than the third scan signal having an on level. In the second frame period, the fifth scan signal having an on level may be supplied later than the third scan signal having an on level. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Example embodiments will now be described more fully below with reference to the accompanying drawings. However, the subject matter of the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these example embodiments are provided to make this disclosure thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0030] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0031] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0032] Figure 2 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0033] Figure 3 is a diagram illustrating a high frequency driving method according to an embodiment of the present disclosure.

[0034] Figure 4 is a diagram illustrating a data writing period according to an embodiment of the present disclosure.

[0035] Figure 5 is a diagram illustrating a data writing period according to another embodiment of the present disclosure.

[0036] Figure 6 is a diagram illustrating a low frequency driving method according to an embodiment of the present disclosure.

[0037] Figure 7 is a diagram illustrating a bias refresh period according to an embodiment of the present disclosure.

[0038] Figure 8 is a diagram illustrating a bias refresh period according to another embodiment of the present disclosure.

[0039] Fig. 9 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0040] Fig.10 is a diagram illustrating a third scan driver according to an embodiment of the present disclosure.

[0041] Fig.11 It is shown Fig.10 A diagram of a scanning stage of a third scanning driver is shown in FIG.

[0042] Fig.12 It is shown Fig.11 FIG. 4 is a diagram showing a driving method of a scanning stage.

[0043] Fig.13 is a diagram illustrating a first scan driver according to an embodiment of the present disclosure.

[0044] Fig.14 It is shown Fig.13 A diagram of a scanning stage of a first scanning driver is shown in FIG.

[0045] Fig.15 It is shown Fig.14 FIG. 4 is a diagram showing a driving method of a scanning stage.

[0046] Fig.16 is a diagram illustrating a second scan driver according to an embodiment of the present disclosure.

[0047] Fig.17 is a diagram illustrating a transmit driver according to an embodiment of the present disclosure.

[0048] Fig.18 is a diagram illustrating a first emission driver according to an embodiment of the present disclosure.

[0049] Fig.19 It is shown Fig.18 A diagram of the emitter stage of a first emitter driver is shown in FIG.

[0050] Fig. 20 It is shown Fig.19 FIG. 4 is a diagram showing a driving method of an emitter stage.

[0051] Fig.21 is a diagram illustrating a second emission driver according to an embodiment of the present disclosure.

[0052] Fig. 22 and Fig.23 This is a diagram showing a case where data writing frames are continuous.

[0053] Figure 24 to Figure 26 This is a diagram showing a case where a data writing frame and a bias refresh frame are consecutive. DETAILED DESCRIPTION

[0054] Hereinafter, example embodiments are described in more detail with reference to the accompanying drawings so that those skilled in the art can practice the present disclosure. The present disclosure can be implemented in various suitable and different forms, without being limited to the example embodiments described in this specification. As used herein, when describing embodiments of the present disclosure, the use of the term "may" refers to "one or more embodiments of the present disclosure".

[0055] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations of measurements or calculations that one of ordinary skill in the art will recognize. It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or there can be one or more intervening elements or layers.

[0056] Portions not relevant to the description (e.g., elements and / or processes that may be involved in practicing the present disclosure but are not relevant to the present disclosure) may be omitted to clearly describe the present disclosure, and throughout the specification, identical or similar constituent elements will be represented by identical reference numerals. Thus, identical or similar elements may be identified in different drawings using identical reference numerals. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0057] In addition, for better understanding and ease of description, the size and thickness of each component shown in the drawings may be exaggerated, and the present disclosure is not limited thereto. For clear expression or description, the thickness of certain parts and regions may be exaggerated.

[0058] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0059] refer to Figure 1 , the display device 9 may include a timing controller 10 , a data driver 20 , a scan driver 30 , an emission driver 40 and a pixel unit 50 .

[0060] The timing controller 10 may receive an external input signal from an external processor, and the external input signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and an RGB data signal (eg, red, green, and blue data signals), and the like.

[0061] The vertical synchronization signal may include multiple pulses. As used herein, a pulse may, for example, refer to a voltage pulse or a current pulse. When each pulse of the vertical synchronization signal is generated, this may indicate that the previous frame period ends and the current frame period begins relative to the time when the pulse is generated. The interval between adjacent pulses of the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include multiple pulses. When each pulse of the horizontal synchronization signal is generated, this may indicate that the previous horizontal period ends and the new horizontal period begins relative to the time when the pulse is generated. The interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may have an enable level in one or more horizontal periods (e.g., a specific horizontal period) and a disable level in other periods. When the data enable signal has an enable level, this may indicate that an RGB data signal is supplied in the corresponding horizontal period. The RGB data signal may be supplied in units of pixel rows in each of the corresponding horizontal periods. The timing controller 10 may generate gray values ​​based on the RGB data signal to correspond to the specifications of the display device 9. The timing controller 10 may generate control signals to be supplied to the data driver 20 , the scan driver 30 , the emission driver 40 , and the like to correspond to the specifications of the display device 9 .

[0062] The data driver 20 may generate data voltages to be supplied to the data lines DL1, DL2, ..., and DLm by using the grayscale values ​​and control signals received from the timing controller 10. For example, the data driver 20 may sample the grayscale values ​​by using the clock signal, and supply data voltages corresponding to the grayscale values ​​to the data lines DL1, DL2, ..., and DLm in units of pixel rows (e.g., pixels connected to the same scan line). Here, m may be an integer greater than 0.

[0063] The scan driver 30 may generate scan signals to be supplied to the scan lines GIL1, GWNL1, GWPL1, GBL1, . . . , GILn, GWNLn, GWPLn, and GBLn by receiving a clock signal and a scan start signal, etc. from the timing controller 10. Here, n may be an integer greater than 0.

[0064] The scan driver 30 may include a plurality of sub-scan drivers. In an example, a first sub-scan driver may provide scan signals for scan lines GIL1, ..., and GILn, a second sub-scan driver may provide scan signals for scan lines GWNL1, ..., and GWNLn, a third sub-scan driver may provide scan signals for scan lines GWPL1, ..., and GWPLn, and a fourth sub-scan driver may provide scan signals for scan lines GBL1, ..., and GBLn. Each of the sub-scan drivers may include a plurality of scan stages connected in the form of a shift register. For example, the scan driver 30 may generate a scan signal in a manner that sequentially transmits a scan start signal of a pulse having a conduction level (e.g., a conduction amplitude) supplied to a scan start line to a next scan stage.

[0065] In another example, the first sub-scan driver and the second sub-scan driver may be integrated to provide scan signals of the scan lines GIL1, GWNL1, ..., GILn, and GWNLn, and the third sub-scan driver and the fourth sub-scan driver may be integrated to provide scan signals of the scan lines GWPL1, GBL1, ..., GWPLn, and GBLn. For example, the previous scan line of the nth scan line GWNLn (e.g., the (n-1)th scan line) may be connected to the same electrical node as the nth scan line GILn. In addition, for example, the next scan line of the nth scan line GWPLn (e.g., the (n+1)th scan line) may be connected to the same electrical node as the nth scan line GBLn.

[0066] The first sub-scan driver and the second sub-scan driver may supply a scan signal having a pulse of a first polarity to the scan lines GIL1, GWNL1, ..., GILn, and GWNLn. In addition, the third sub-scan driver and the fourth sub-scan driver may supply a scan signal having a pulse of a second polarity to the scan lines GWPL1, GBL1, ..., GWPLn, and GBLn. The first polarity and the second polarity may be opposite polarities to each other.

[0067] In the following, polarity may represent the logic level of a pulse. For example, when a pulse has a first polarity, the pulse may have a high level. A pulse with a high level may be referred to as a rising pulse. When a rising pulse is supplied to the gate electrode of an N-type (e.g., N-type) transistor, the N-type transistor may be turned on. For example, a rising pulse may be a turn-on level relative to an N-type transistor. Assume that a voltage having a level sufficiently lower than the level of the gate electrode of the N-type transistor (e.g., than the voltage applied to the gate electrode) is applied to the source electrode of the N-type transistor. For example, the N-type transistor may be an NMOS transistor.

[0068] In addition, when the pulse has a second polarity, the pulse may have a low level. A pulse with a low level may be referred to as a falling pulse. When a falling pulse is supplied to the gate electrode of a P-type (e.g., P-type) transistor, the P-type transistor may be turned on. For example, the falling pulse may be a turn-on level relative to the P-type transistor. Assume that a voltage having a level sufficiently higher than the level of the gate electrode of the P-type transistor (e.g., than the voltage applied to the gate electrode) is applied to the source electrode of the P-type transistor. For example, the P-type transistor may be a PMOS transistor.

[0069] The emission driver 40 may generate an emission signal to be provided to the emission lines EL1, EL2, ..., and ELn by receiving a clock signal and an emission stop signal, etc. from the timing controller 10. For example, the emission driver 40 may sequentially provide an emission signal of a pulse having a cut-off level (e.g., a cut-off amplitude) to the emission lines EL1, EL2, ..., and ELn. For example, the emission driver 40 may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal of a pulse having a cut-off level to a next emission stage under the control of a clock signal.

[0070] The pixel unit 50 includes pixels. For example, the pixels PXnm may be connected to corresponding data lines DLm, corresponding scan lines GILn, GWNLn, GWPLn, and GBLn, and corresponding emission lines ELn.

[0071] Figure 2 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0072] refer to Figure 2 , the pixel PXnm according to an embodiment of the present disclosure may include transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light emitting diode LD.

[0073] A first electrode of transistor T1 may be connected to a first electrode of transistor T2, a second electrode of transistor T1 may be connected to a first electrode of transistor T3, and a gate electrode of transistor T1 may be connected to a second electrode of transistor T3. Transistor T1 may be referred to as a driving transistor.

[0074] A first electrode of the transistor T2 may be connected to the first electrode of the transistor T1, a second electrode of the transistor T2 may be connected to the data line DLm, and a gate electrode of the transistor T2 may be connected to the scan line GWPLn. The transistor T2 may be referred to as a scan transistor.

[0075] A first electrode of the transistor T3 may be connected to a second electrode of the transistor T1, a second electrode of the transistor T3 may be connected to a gate electrode of the transistor T1, and a gate electrode of the transistor T3 may be connected to the scan line GWNLn. The transistor T3 may be referred to as a diode-connected transistor.

[0076] A first electrode of the transistor T4 may be connected to the second electrode of the storage capacitor Cst, a second electrode of the transistor T4 may be connected to the initialization line VINTL, and a gate electrode of the transistor T4 may be connected to the scan line GILn. The transistor T4 may be referred to as a gate initialization transistor.

[0077] A first electrode of the transistor T5 may be connected to the power line ELVDDL, a second electrode of the transistor T5 may be connected to the first electrode of the transistor T1, and a gate electrode of the transistor T5 may be connected to the emission line ELn. The transistor T5 may be referred to as a first emission transistor.

[0078] A first electrode of transistor T6 may be connected to the second electrode of transistor T1, a second electrode of transistor T6 may be connected to the anode of light emitting diode LD, and a gate electrode of transistor T6 may be connected to emission line ELn. Transistor T6 may be referred to as a second emission transistor.

[0079] A first electrode of the transistor T7 may be connected to the anode of the light emitting diode LD, a second electrode of the transistor T7 may be connected to the initialization line VINTL, and a gate electrode of the transistor T7 may be connected to the scan line GBLn. The transistor T7 may be referred to as an anode initialization transistor.

[0080] A first electrode of the storage capacitor Cst may be connected to the power line ELVDDL, and a second electrode of the storage capacitor Cst may be connected to the gate electrode of the transistor T1 .

[0081] The anode of the light emitting diode LD can be connected to the second electrode of the transistor T6, and the cathode of the light emitting diode LD can be connected to the power line ELVSSL. The voltage applied to the power line ELVSSL can be set to be lower than the voltage applied to the power line ELVDDL. The light emitting diode LD can be an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, etc.

[0082] Transistors T1, T2, T5, T6, and T7 may be implemented with P-type (e.g., P-class) transistors (e.g., may be P-type (e.g., P-class) transistors). Channels of transistors T1, T2, T5, T6, and T7 may be configured with polysilicon (e.g., may include or may be polysilicon). The polysilicon transistor may be a low temperature polysilicon (LTPS) transistor. The polysilicon transistor has high electron mobility and has fast driving characteristics according to the high electron mobility.

[0083] Transistors T3 and T4 may be implemented with N-type (e.g., N-type) transistors (e.g., may be N-type (e.g., N-type) transistors). The channels of transistors T3 and T4 may be configured with oxide semiconductors (e.g., may include or may be oxide semiconductors). Oxide semiconductor transistors may be formed by a low temperature process and have a charge mobility lower than that of polysilicon transistors. Thus, the oxide semiconductor transistor has a current leakage amount generated in the off state, which is less than the current leakage amount of the polysilicon transistor.

[0084] In some embodiments, the transistor T7 may be configured with an N-type (eg, N-type) oxide semiconductor transistor instead of a polysilicon transistor. Instead of the scan line GBLn, one of the scan lines GWNLn and GILn may be connected to the gate electrode of the transistor T7.

[0085] Figure 3 is a diagram illustrating a high frequency driving method according to an embodiment of the present disclosure.

[0086] When the pixel unit 50 displays frames at the first driving frequency, the display device 9 can be said to be in the first display mode. In addition, when the pixel unit 50 displays frames at a second driving frequency lower than the first driving frequency, the display device 9 can be said to be in the second display mode.

[0087] In the first display mode, the display device 9 may display image frames at a frequency of 20 Hz or higher (eg, 60 Hz).

[0088] The second display mode may be a low power display mode. In the second display mode, the display device 9 may display image frames at a frequency less than 20 Hz (e.g., 1 Hz). For example, during normal use mode, a situation where only the time and date are displayed in the "always on mode" may correspond to the second display mode.

[0089] The period 1TP may include multiple frame periods 1FP. The period 1TP is a period arbitrarily defined for comparing the first display mode and the second display mode. The period 1TP may represent the same time interval in the first display mode and the second display mode. For ease of description, it is assumed that the frame period 1FP has the same time interval in the first display mode and the second display mode. Therefore, the period 1TP in the first display mode and the second display mode may include the same number of frame periods 1FP.

[0090] In the first display mode, each frame period 1FP may include a data writing period WP and an emission period EP. Figure 3, based on the first pixel row, the data write period WP is located at the initial stage of the frame period 1FP and the emission period EP is located after the data write period WP. However, in the case of a pixel row other than the first pixel row, the data write period WP may be located in the middle or later stage of the frame period 1FP.

[0091] Therefore, the pixel PXnm may display a plurality of image frames corresponding to a plurality of frame periods 1FP based on the data voltage received in the data writing period WP during the period 1TP.

[0092] Figure 4 is a diagram illustrating a data writing period according to an embodiment of the present disclosure. Figure 5 is a diagram illustrating a data writing period according to another embodiment of the present disclosure.

[0093] First, during the data writing period WP, ​​the emission signal En having the off level (high level) may be supplied to the emission line ELn. Therefore, during the data writing period WP, ​​the transistors T5 and T6 may be in the off state.

[0094] Next, a first pulse of a conduction level (high level) (e.g., a first pulse of a scan signal GIn) is supplied to the scan line GILn. In some embodiments, after the emission signal En begins to be supplied to the emission line ELn, the first pulse of the scan signal GIn may begin to be supplied to the scan line GILn. Therefore, the transistor T4 is turned on, and the gate electrode of the transistor T1 and the initialization line VINTL are connected to each other. Therefore, the voltage of the gate electrode of the transistor T1 is initialized to the initialization voltage of the initialization line VINTL and is maintained by the storage capacitor Cst. For example, the initialization voltage of the initialization line VINTL may be a voltage sufficiently lower than the voltage of the power line ELVDDL. For example, the initialization voltage may be a voltage having a level equal to or similar to the level of the voltage of the power line ELVSSL. Therefore, the transistor T1 may be turned on.

[0095] Next, a first pulse (e.g., a first pulse of each of the scan signals GWPn and GWNn) of a turn-on level (e.g., a low level of a first pulse of a scan signal GWPn and a high level of a first pulse of a scan signal GWNn) is supplied to the scan lines GWPLn and GWNLn, and the corresponding transistors T2 and T3 are turned on. Therefore, the data voltage Dm applied to the data line DLm is written (e.g., applied to or stored in) the storage capacitor Cst through the transistors T2, T1, and T3. However, the data voltage Dm corresponds to the grayscale value G(n-4) of the pixel four horizontal periods (e.g., four horizontal periods earlier) before. The data voltage Dm is not used for the emission of the pixel PXnm, but is used to apply a turn-on bias voltage to the transistor T1. When the turn-on bias voltage is applied before the set data voltage Dm is written to the transistor T1, the hysteresis phenomenon can be minimized or reduced.

[0096] Next, a first pulse having a turn-on level (low level) (eg, a first pulse of the scan signal GBn) is supplied to the scan line GBLn, and the transistor T7 is turned on. Thus, the anode voltage of the light emitting diode LD is initialized.

[0097] A second pulse (eg, a second pulse of the scanning signal GIn) having a conduction level (high level) is supplied to the scanning line GILn, and the above-mentioned driving process is performed again. For example, the conduction bias voltage is applied to the transistor T1 again, and the anode voltage of the light emitting diode LD is initialized.

[0098] By repeating the above process, when the third pulse having the on level is supplied to the scan lines GWPLn and GWNLn, the data voltage Dm corresponding to the gray value Gn of the pixel PXnm is written to the storage capacitor Cst. The data voltage Dm written to the storage capacitor Cst is a voltage obtained by reflecting the decrease (e.g., reduction) of the threshold voltage of the transistor T1.

[0099] Finally, when the emission signal En becomes a conduction level (low level), transistors T5 and T6 are in (e.g., return to) a conduction state. Therefore, a drive current path connecting the power line ELVDDL, transistors T5, T1 and T6, the light emitting diode LD and the power line ELVSSL is formed, and the drive current flows through the drive current path. The amount of the drive current corresponds to the data voltage Dm stored in the storage capacitor Cst. Because the drive current flows through the transistor T1, the decrease in the threshold voltage of the transistor T1 is reflected. Therefore, the decrease in the threshold voltage reflected to the data voltage Dm stored in the storage capacitor Cst and the decrease in the threshold voltage reflected to the drive current offset each other, and thus, the drive current corresponding to the data voltage Dm can flow regardless of the threshold voltage of the transistor T1.

[0100] The light emitting diode LD emits light with set brightness according to the amount of driving current.

[0101] In the present embodiment, the case where each scanning signal (e.g., GIn, GWPn, GWNn, and GBn) includes three pulses is described. However, in another embodiment, each scanning signal may include two or more than four pulses. In yet another embodiment, each scanning signal may include one pulse, and therefore, the process of applying the on-bias voltage to the transistor T1 is omitted (see Figure 5 ). In the following, for the convenience of description, Figure 5 Let's describe the data writing period WP.

[0102] In addition, the interval between adjacent pulses of the horizontal synchronization signal Hsync may correspond to one horizontal period. For example, one horizontal period may correspond to the time difference between the start of one pulse of the horizontal synchronization signal Hsync and the start of an adjacent pulse of the horizontal synchronization signal Hsync. Figure 4 2 shows the case where the pulse of the horizontal synchronization signal Hsync has a low level, but in another embodiment, the pulse of the horizontal synchronization signal Hsync may have a high level.

[0103] Figure 6 is a diagram illustrating a low frequency driving method according to an embodiment of the present disclosure.

[0104] In the second display mode, a first frame period 1FP during the period 1TP may include a data write period WP and an emission period EP, and each of the other frame periods 1FP during the period 1TP may include a bias refresh period BP and an emission period EP.

[0105] The transistors T3 and T4 of the pixel PXnm maintain an off state in other frame periods 1FP during the period 1TP (for example, the frame period 1FP after the first frame period 1FP during the period 1TP), and therefore, the storage capacitor Cst maintains the same data voltage during a plurality of image frames. For example, the transistors T3 and T4 are configured as oxide semiconductor transistors, and thus, current leakage can be minimized or reduced.

[0106] Thus, the pixel PXnm may display the same single image frame during the period 1TP based on the data voltage supplied during the data writing period WP.

[0107] Figure 7 is a diagram illustrating a bias refresh period according to an embodiment of the present disclosure. Figure 8 is a diagram illustrating a bias refresh period according to another embodiment of the present disclosure.

[0108] refer to Figure 7 , in the bias refresh period BP, the scan signals GIn and GWNn having the cut-off level (low level) are supplied. Therefore, as described above, in the bias refresh period BP, the data voltage written into the storage capacitor Cst does not change. The reference data voltage Vref may be applied to the data line DLm.

[0109] However, in the bias refresh period BP, the emission signal En and the scanning signals GWPn and GBn having the same waveform as that in the data write period WP can be supplied. Thus, in multiple frame periods 1FP of the period 1TP, the light emitted from the light emitting diode LD has a similar waveform, so that under low-frequency driving, the user sees little or no flicker.

[0110] refer to Figures 1 to 7 The described pixel PXnm is an embodiment suitable for high-frequency drive and low-frequency drive. The embodiment to be described later can also be applied to a pixel having another circuit to which high-frequency drive and low-frequency drive can be performed. For example, the transistors T1 to T7 of the pixel PXnm can all be configured as only P-type (e.g., P-class) transistors. Thus, the scan driver 30 only includes a sub-scan driver of a P-type transistor, and therefore, the configuration of the scan driver 30 can be simplified. For example, the transistors of the pixel PXnm may not include emission transistors T5 and T6. Therefore, the emission driver 40 may be unnecessary.

[0111] In the present embodiment, the case where each of the scanning signals GWPn and GBn includes three pulses is described. However, in another embodiment, each of the scanning signals GWPn and GBn may include two or more than four pulses. In still another embodiment, each of the scanning signals GWPn and GBn may include one pulse, and thus, the process of applying the on-bias voltage to the transistor T1 is omitted (see Figure 8 ). In the following, for the convenience of description, Figure 8 Let's describe the bias refresh period BP.

[0112] Fig. 9 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0113] refer to Fig. 9 , the scan driver 30 according to an embodiment of the present disclosure may include a first scan driver 30P1 , a second scan driver 30P2 , and a third scan driver 30N.

[0114] As reference Figure 1As described, in some embodiments, the scan signals of the scan lines GIL1 to GILn may be provided by the third scan driver 30N. In another embodiment, the scan signals of the scan lines GIL1 to GILn may be provided from a separate scan driver. In addition, in some embodiments, the scan signals of the scan lines GBL1 to GBLn may be provided by the first scan driver 30P1 and the second scan driver 30P2. In another embodiment, the scan signals of the scan lines GBL1 to GBLn may be provided from a separate scan driver.

[0115] The first scan driver 30P1 may be connected to the first scan start line FLML1, the scan clock line PCKLS, and the scan lines GWPL1, GWPL2, GWPL3, ..., and GWPLp. Here, p may be an integer greater than 0. At least one of the scan clock signals supplied to the first scan driver 30P1 through the scan clock line PCKLS may be defined as a first scan clock signal.

[0116] The second scan driver 30P2 may be connected to the second scan start line FLML2, the scan clock line PCKLS, and the scan lines GWPL(p+1), GWPL(p+2), ... and GWPLq. Here, q may be an integer greater than p. At least one of the scan clock signals supplied to the second scan driver 30P2 through the scan clock line PCKLS may be defined as a second scan clock signal. The second scan driver 30P2 may be connected to the same scan clock line PCKLS as the first scan driver 30P1. For example, the first scan clock signal and the second scan clock signal may be the same. However, the embodiment is not limited thereto, and for example, the second scan driver 30P2 may be connected to a different scan clock line from the first scan driver 30P1, and the first scan clock signal and the second scan clock signal may be different. In some embodiments, the second scan driver 30P2 may be connected to a second scan start line FLML2 independent of the first scan start line FLML1 of the first scan driver 30P1. The first scan line GWPL(p+1) of the second scan driver 30P2 may correspond to the next scan line of the last scan line GWPLp of the first scan driver 30P1.

[0117] The third scan driver 30N may be connected to the third scan start line FLML3 , the scan clock line NCKLS, and the scan lines GWNL1 , GWNL2 , GWNL3 , . . . , GWNLp, GWNL(p+1), GWNL(p+2), . . . , and GWNLq.

[0118] Fig.10 is a diagram illustrating a third scan driver according to an embodiment of the present disclosure.

[0119] Fig.10 The third scan driver 30N shown in FIG. Figure 1 Those skilled in the art can replace the first sub-scanning driver with the scanning lines GIL1 to GILn. Fig.10 The scanning lines GWNL1, GWNL2, GWNL3, GWNL4, ... and GWNLn shown in the reference Figure 1 For example, in some embodiments, except that the scan lines GWNL1 to GWNLn are replaced with the scan lines GIL1 to GILn, the scan lines GWNL1 to GWNLn are replaced with the scan lines GIL1 to GILn. Figure 1 The first sub-scan driver described can be used with reference to Fig.10 The third scan driver 30N is described to have the same structure or configuration.

[0120] refer to Fig.10 , the third scan driver 30N may include scan stages NST1, NST2, NST3, NST4, . . . , NSTn. Each of the scan stages NST1 to NSTn may be connected to a previous scan line (or carry line) through a first input terminal 201. However, since the first scan stage NST1 does not have a previous scan line connected to the first scan stage NST1, the first scan stage NST1 may be connected to the third scan start line FLML3 through the first input terminal 201.

[0121] Each of the odd scanning stages NST1, NST3, ... may include a second input terminal 202 connected to the clock line NCKL1 and a third input terminal 203 connected to the clock line NCKL2. Each of the even scanning stages NST2, NST4, ..., NSTn may include a second input terminal 202 connected to the clock line NCKL2 and a third input terminal 203 that may be connected to the clock line NCKL1.

[0122] In some embodiments, each of the odd scanning stages NST1, NST3, ... may include a second input terminal 202 connected to the clock line NCKL2 and a third input terminal 203 connected to the clock line NCKL1. Each of the even scanning stages NST2, NST4, ..., NSTn may include a second input terminal 202 connected to the clock line NCKL1 and a third input terminal 203 connected to the clock line NCLK2.

[0123] The scanning stages NST1 to NSTn may be connected to corresponding scanning lines GWNL1 to GWNLn through output terminals 204 , respectively.

[0124] The scanning stages NST1 to NSTn may be connected to each other in the form of a shift register. For example, each of the scanning stages NST1 to NSTn may generate a scanning signal in such a manner that a third scanning start signal having a pulse of an on level supplied to the third scanning start line FLML3 is sequentially transmitted to the next scanning stage.

[0125] Fig.11 It is shown Fig.10 A diagram of a scanning stage of a third scanning driver is shown in FIG.

[0126] refer to Fig.11 ,Will Fig.10 The first scanning stage NST1 of the scan driver N30 shown in FIG. 1 is shown as an example embodiment. Fig.10 The other scanning stages NST2, NST3, NST4, . . . , and NSTn shown in FIG. 4 have substantially the same configuration as the scanning stage NST1, and therefore, overlapping descriptions may not be repeated.

[0127] The scanning stage NST1 may include transistors P1 to P12 and capacitors CN1 to CN3. The transistors P1 to P12 may be P-type (eg, P-class) transistors.

[0128] A first electrode of the transistor P2 may be connected to the second electrode of the transistor P1 , a second electrode of the transistor P2 may be connected to the third scan start line FLML3 , and a gate electrode of the transistor P2 may be connected to the clock line NCKL1 .

[0129] A first electrode of the transistor P3 may be connected to the node NN3 , a second electrode of the transistor P3 may be connected to the clock line NCKL1 , and a gate electrode of the transistor P3 may be connected to the first electrode of the transistor P2 .

[0130] In some embodiments, transistor P3 may include a first sub-transistor and a second sub-transistor connected in series. The first electrode of the first sub-transistor may be connected to node NN3, the second electrode of the first sub-transistor may be connected to the first electrode of the second sub-transistor, and the gate electrode of the first sub-transistor may be connected to the first electrode of transistor P2. The first electrode of the second sub-transistor may be connected to the second electrode of the first sub-transistor, the second electrode of the second sub-transistor may be connected to the clock line NCKL1, and the gate electrode of the second sub-transistor may be connected to the first electrode of transistor P2. According to this embodiment, current leakage can be reduced, and excessive source-drain voltage can be divided. Therefore, the stress applied to transistor P3 can be reduced.

[0131] A first electrode of the transistor P4 may be connected to the node NN3 , a second electrode of the transistor P4 may be connected to the power line VLNL, and a gate electrode of the transistor P4 may be connected to the clock line NCKL1 .

[0132] A first electrode of the transistor P5 may be connected to the node NN4 , a second electrode of the transistor P5 may be connected to the clock line NCKL2 , and a gate electrode of the transistor P5 may be connected to the node NN2 .

[0133] A first electrode of the transistor P6 may be connected to the power line VHNL, a second electrode of the transistor P6 may be connected to the node NN4 , and a gate electrode of the transistor P6 may be connected to the node NN3 .

[0134] A first electrode of the transistor P7 may be connected to a first electrode of the capacitor CN3 , a second electrode of the transistor P7 may be connected to the clock line NCKL2 , and a gate electrode of the transistor P7 may be connected to a second electrode of the capacitor CN3 .

[0135] A first electrode of the transistor P8 may be connected to the node NN1 , a second electrode of the transistor P8 may be connected to a first electrode of the capacitor CN3 , and a gate electrode of the transistor P8 may be connected to the clock line NCKL2 .

[0136] A first electrode of transistor P9 may be connected to the power supply line VHNL, a second electrode of transistor P9 may be connected to node NN1 , and a gate electrode of transistor P9 may be connected to node NN2 (eg, through transistor P1 ).

[0137] A first electrode of the transistor P10 may be connected to the power line VHNL, a second electrode of the transistor P10 may be connected to the scan line GWNL1 , and a gate electrode of the transistor P10 may be connected to the node NN1 .

[0138] A first electrode of the transistor P11 may be connected to the scan line GWNL1 , a second electrode of the transistor P11 may be connected to the power line VLNL, and a gate electrode of the transistor P11 may be connected to the node NN2 .

[0139] A first electrode of the transistor P12 may be connected to the second electrode of the capacitor CN3 , a second electrode of the transistor P12 may be connected to the node NN3 , and a gate electrode of the transistor P12 may be connected to the power line VLNL.

[0140] A first electrode of the transistor P1 may be connected to the node NN2 , a second electrode of the transistor P1 may be connected to the first electrode of the transistor P2 , and a gate electrode of the transistor P1 may be connected to the power line VLNL.

[0141] A first electrode of the capacitor CN1 may be connected to the power line VHNL, and a second electrode of the capacitor CN1 may be connected to the node NN1.

[0142] A first electrode of the capacitor CN2 may be connected to the node NN4 , and a second electrode of the capacitor CN2 may be connected to the node NN2 .

[0143] A first electrode of the capacitor CN3 may be connected to a first electrode of the transistor P7 , and a second electrode of the capacitor CN3 may be connected to a gate electrode of the transistor P7 .

[0144] Fig.12 It is shown Fig.11 FIG. 4 is a diagram showing a driving method of a scanning stage.

[0145] refer to Fig.12 , a timing diagram of a third scan start signal FLM3 applied to a third scan start line FLML3, a clock signal NCK2 applied to a clock line NCKL2, a clock signal NCK1 applied to a clock line NCKL1, a node voltage VNN2 of a node NN2, a node voltage VNN3 of a node NN3, a node voltage VNN1 of a node NN1, and a scan signal GWN1 applied to a scan line GWNL1 is shown. The horizontal synchronization signal Hsync is shown as a reference signal for the timing. The interval between pulses of the horizontal synchronization signal Hsync may be referred to as a horizontal period.

[0146] A voltage having a high level may be applied to the power line VHNL, and a voltage having a low level may be applied to the power line VLNL. For example, the voltage applied to the power line VHNL may be higher than the voltage applied to the power line VLNL. In the description of the driving method, the transistors P12 and P1 each have a gate electrode connected to the power line VLNL and are in an on state during most periods (e.g., during most of the time), and therefore, a description of the transistors P12 and P1 may not be provided.

[0147] First, at time t1a, the third scanning start signal FLM3 having a cut-off level (high level) is supplied, and the clock signal NCK1 having a low level is supplied. Therefore, the transistors P2 and P4 are turned on.

[0148] When the transistor P2 is turned on, the third scan start signal FLM3 having a high level is transmitted to the node NN2, and the node voltage VNN2 has a high level. The transistors P3, P5, P9, and P11 are turned off by the node voltage VNN2 having a high level.

[0149] When the transistor P4 is turned on, the node NN3 and the power supply line VLNL are connected to each other, and therefore, the node voltage VNN3 has a low level. The transistors P6 and P7 are turned on by the node voltage VNN3 having a low level.

[0150] When the transistor P6 is turned on, the node NN4 and the power line VHNL are connected to each other. Therefore, the power line VHNL supports one end of the capacitor CN2 (eg, the first electrode of the capacitor CN2), and thus the node voltage VNN2 of the node NN2 can be stably maintained.

[0151] When transistor P7 is turned on, the first electrode of capacitor CN3 and clock line NCKL2 are connected to each other. Since clock signal NCK2 having a high level is applied to the gate electrode of transistor P8, transistor P8 is in a cut-off state, and therefore, node voltage VNN1 does not change (eg, node voltage VNN1 has a high level).

[0152] At time t2a, the clock signal NCK2 having a low level is supplied.

[0153] The clock signal NCK2 having a low level is supplied to the first electrode of the capacitor CN3 through the transistor P7. Due to the coupling of the capacitor CN3, a voltage having a level lower than the low level is applied to the gate electrode of the transistor P7. Thus, the transistor P7 can stably maintain a conducting state and has improved driving characteristics.

[0154] According to the present embodiment, due to the transistor P12, the node voltage VNN3 is not affected by the coupling of the capacitor CN3. When a voltage having a level lower than the low level is applied to the first electrode of the transistor P12 due to the coupling of the capacitor CN3, the first electrode of the transistor P12 is used as a drain electrode. Therefore, the node NN3 corresponding to the second electrode of the transistor P12 is used as a source electrode (e.g., the source electrode of the transistor P12). In addition, because a voltage having a low level is applied to the gate electrode of the transistor P12 through the power line VLNL, a voltage having a level higher than the low level is applied to the source electrode of the transistor P12, so that the transistor P12 is turned on. At the current time, the node voltage VNN3 of the node NN3 has a low level, and therefore, the transistor P12 is in a cut-off state.

[0155] Therefore, according to the present embodiment, the node voltage VNN3 is maintained by the transistor P12, and thus an excessive bias voltage is prevented or blocked from being applied to the transistors P3 and P4, so that the lifespan of the transistors P3 and P4 can be extended.

[0156] In addition, the transistor P8 is turned on by the clock signal NCK2 having a low level. Therefore, the node NN1 and the clock line NCKL2 are connected to each other through the transistors P7 and P8. Therefore, the transistor P10 is turned on by the node voltage VNN1 having a low level. The transistor P9 maintains a cut-off state due to the node voltage VNN2 having a high level.

[0157] The power supply line VHNL and the scanning line GWNL1 are connected to each other through the transistor P10 in the on state. Therefore, a voltage having a high level is supplied to the scanning line GWNL1 as the scanning signal GWN1 having a high level.

[0158] At time t3a, the clock signal NCK1 with a low level is supplied. Therefore, the transistor P4 is turned on, and the node NN3 is connected to the power line VLNL. Therefore, the node voltage VNN3 maintains a low level. In addition, the transistor P2 is turned on, and the third scan start signal FLM3 with a low level is supplied to the node NN2. Therefore, the transistors P3, P5, P9 and P11 are turned on. Therefore, the transistor P10 is diode-connected, and therefore, the voltage with a high level applied to the power line VHNL is not transmitted to the scan line GWNL1. The voltage with a low level applied to the power line VLNL is transmitted to the scan line GWNL1 through the transistor P11 in the on state.

[0159] At time t4a, the clock signal NCK1 having a high level is supplied. Since the transistor P3 is in an on state, the node voltage VNN3 increases. Therefore, the transistors P6 and P7 are turned off.

[0160] At time t5a, a clock signal NCK2 having a low level is provided. Since transistor P5 is in the on state, node voltage VNN2 decreases to a level lower than the low level due to coupling of capacitor CN2. Thus, transistor P11 can stably maintain the on state and have improved driving characteristics.

[0161] According to the present embodiment, due to the transistor P1, the node corresponding to the second electrode of the transistor P1 is not affected by the coupling of the capacitor CN2. When a voltage having a level lower than the low level is applied to the node NN2 as the first electrode of the transistor P1 due to the coupling of the capacitor CN2, the first electrode of the transistor P1 is used as a drain electrode. Therefore, the node corresponding to the second electrode of the transistor P1 is used as a source electrode. In addition, because a voltage having a low level is applied to the gate electrode of the transistor P1 through the power line VLNL, a voltage having a level higher than the low level is applied to the source electrode of the transistor P1, so that the transistor P1 is turned on. At the present time, a voltage having a low level is applied to the source electrode of the transistor P1, and therefore, the transistor P1 is in a cut-off state.

[0162] Therefore, according to the present embodiment, transistor P1 maintains the voltage of the node corresponding to the second electrode of transistor P1, so that excessive bias voltage is prevented or blocked from being applied to transistors P2 and P3. Therefore, the life of transistors P2 and P3 can be extended.

[0163] Fig.13 is a diagram illustrating a first scan driver according to an embodiment of the present disclosure.

[0164] refer to Fig.13 , the first scan driver 30P1 may include scan stages PST11 to PST14. The scan stages PST11 to PST14 may be connected to the corresponding scan lines GWPL1 to GWPL4 and the scan clock line PCKLS. The scan stages PST11 to PST14 may be implemented with the same circuit.

[0165] Each of the scanning stages PST11 to PST14 may include a first input terminal 1001 , a second input terminal 1002 , a third input terminal 1003 , and an output terminal 1004 .

[0166] The first input terminal 1001 of the first scanning stage PST11 may be connected to the first scanning start line FLML1. The first input terminal 1001 of each of the other scanning stages PST12 to PST14 may be connected to the scanning line (or carry line) of the previous scanning stage. In the example, the first scanning start signal is supplied to the first input terminal 1001 of the first scanning stage PST11, and the output signal (e.g., scanning signal or carry signal) of the previous scanning stage is supplied to the first input terminal 1001 of each of the other scanning stages PST12 to PST14.

[0167] The second input terminal 1002 of the j-th (j is an odd or even number) scanning stage can be connected to the clock line PCKL1, and the third input terminal 1003 of the j-th scanning stage can be connected to the clock line PCKL2. The second input terminal 1002 of the (j+1)-th scanning stage can be connected to the clock line PCKL2, and the third input terminal 1003 of the (j+1)-th scanning stage can be connected to the clock line PCKL1.

[0168] The pulses of the clock signals PCK1 and PCK2 applied to the clock lines PCKL1 and PCKL2 have the same period (eg, two horizontal periods), but have different phases. Therefore, the pulses of the clock signals PCK1 and PCK2 may not overlap with each other (see Fig.15 ).

[0169] Moreover, each of the scanning stages PST11 to PST14 can be connected to a power line VHPL and a power line VLPL. The voltage of the power line VHPL can be set to a cut-off level (gate cut-off voltage or a voltage with a high level). In addition, the voltage of the power line VLPL can be set to a conduction level (gate on voltage or a voltage with a low level).

[0170] Fig.14 It is shown Fig.13 FIG. 4 is a diagram of a scanning stage of a first scanning driver shown in FIG.

[0171] For ease of description, Fig.14 The first scanning stage PST11 and the second scanning stage PST12 are shown in FIG. Fig.14 , the first scanning stage PST11 may include a first driver 1210 , a second driver 1220 , and an output unit (buffer) 1230 .

[0172] The output unit 1230 controls a voltage supplied to the output terminal 1004 corresponding to (eg, according to) voltages of the node NP1 and the second node NP2. To this end, the output unit 1230 includes a transistor M5 and a transistor M6.

[0173] The transistor M5 is located between the power supply line VHPL and the output terminal 1004, and a gate electrode of the transistor M5 is connected to the node NP1. The transistor M5 controls the connection between the power supply line VHPL and the output terminal 1004 corresponding to (eg, according to) a voltage applied to the node NP1.

[0174] The transistor M6 is located between the output terminal 1004 and the third input terminal 1003, and the gate electrode of the transistor M6 is connected to the node NP2. The transistor M6 controls the connection between the output terminal 1004 and the third input terminal 1003 corresponding to (e.g., according to) the voltage applied to the node NP2. The output unit 1230 is driven as a buffer. In addition, the output unit 1230 can be configured by connecting a plurality of transistors in parallel. For example, in some embodiments, each of the transistors M5 and M6 can be implemented as a plurality of transistors in parallel.

[0175] The first driver 1210 controls the voltage of the node NP3 corresponding to (eg, according to) signals supplied to the first to third input terminals 1001 to 1003. To this end, the first driver 1210 includes transistors M2 to M4 (eg, transistors M2, M3, and M4).

[0176] The transistor M2 is located between the first input terminal 1001 and the node NP3, and a gate electrode of the transistor M2 is connected to the second input terminal 1002. The transistor M2 controls the connection between the first input terminal 1001 and the node NP3 corresponding to (eg, according to) a signal supplied to the second input terminal 1002.

[0177] The transistor M3 and the transistor M4 are connected in series between the node NP3 and the power supply line VHPL. The transistor M3 is located between the transistor M4 and the node NP3, and the gate electrode of the transistor M3 is connected to the third input terminal 1003. The transistor M3 controls the connection between the transistor M4 and the node NP3 in response to (e.g., according to) a signal supplied to the third input terminal 1003.

[0178] The transistor M4 is located between the transistor M3 and the power supply line VHPL, and a gate electrode of the transistor M4 is connected to the node NP1. The transistor M4 controls the connection between the transistor M3 and the power supply line VHPL corresponding to (eg, according to) the voltage of the node NP1.

[0179] The second driver 1220 controls the voltage of the node NP1 corresponding to (eg, according to) the voltages of the second input terminal 1002 and the node NP3. To this end, the second driver 1220 includes a transistor M1, a transistor M7, a transistor M8, a capacitor CP1, and a capacitor CP2.

[0180] The capacitor CP1 is connected between the node NP2 and the output terminal 1004. The capacitor CP1 charges a voltage corresponding to (eg, according to) the turning on (eg, on state) and the turning off (eg, off state) of the transistor M6.

[0181] The second capacitor CP2 is connected between the node NP1 and the power supply line VHPL. The capacitor CP2 charges the voltage applied to the node NP1.

[0182] The transistor M7 is located between the node NP1 and the second input terminal 1002, and a gate electrode of the transistor M7 is connected to the node NP3. The transistor M7 controls the connection between the node NP1 and the second input terminal 1002 corresponding to (eg, according to) the voltage of the node NP3.

[0183] The transistor M8 is located between the node NP1 and the power line VLPL, and a gate electrode of the transistor M8 is connected to the second input terminal 1002. The transistor M8 controls the connection between the node NP1 and the power line VLPL corresponding to (eg, according to) the voltage of the second input terminal 1002.

[0184] The transistor M1 is located between the node NP3 and the node NP2, and the gate electrode of the transistor M1 is connected to the power line VLPL. While maintaining (e.g., having) the on-state of the transistor M1, the transistor M1 maintains (e.g., provides) the electrical connection between the node NP3 and the node NP2. In addition, the transistor M1 limits the voltage drop width of the node NP3 corresponding to the voltage of the node NP2. For example, although the voltage of the node NP2 drops to a voltage lower than the voltage of the power line VLPL, the voltage of the node NP3 is not lower than the voltage obtained by subtracting the threshold voltage of the transistor M1 from the voltage of the power line VLPL.

[0185] Meanwhile, the second scanning stage PST12 may have substantially the same configuration as that of the first scanning stage PST11 except for signals supplied to the first, second, and third input terminals 101, 102, and 103. Therefore, an overlapping description of the second scanning stage PST12 may not be repeated.

[0186] Fig.15 It is shown Fig.14 FIG. 4 is a diagram showing a driving method of a scanning stage.

[0187] For ease of description, we will Fig.15 The operation process using the first scanning stage PST11 is described in FIG.

[0188] refer to Fig.15 , the clock signal PCK1 and the clock signal PCK2 have a cycle of two horizontal periods 2H, and are supplied in different horizontal periods. For example, the clock signal PCK2 is set to a signal shifted by half a cycle (i.e., one horizontal period 1H) relative to the clock signal PCK1. In addition, the first scan start signal FLM1 supplied to the first input terminal 1001 can be synchronized with the clock signal PCK1 supplied to the second input terminal 1002.

[0189] Supply of a signal may mean that the signal has an on-level (here, a low level). Suspension of supply of a signal may mean that the signal has an off-level (here, a high level).

[0190] In addition, when the first scan start signal FLM1 is supplied, the first input terminal 1001 may be set to a voltage having a low level, and when the first scan start signal FLM1 is not supplied, the first input terminal 1001 may be set to a voltage having a high level. In addition, when a clock signal is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 may be set to a voltage having a low level, and when the clock signal is not supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 may be set to a voltage having a high level.

[0191] The operation process will be described in more detail. First, the first scanning start signal FLM1 is supplied to be synchronized with the clock signal PCK1.

[0192] When the clock signal PCK1 is supplied, the transistor M2 and the transistor M8 are turned on. When the transistor M2 is turned on, the first input terminal 1001 and the node NP3 are electrically connected to each other. Because the transistor M1 is set to the on state in most periods (e.g., during most of the time), the node NP2 is electrically connected to the node NP3.

[0193] When the first input terminal 1001 and the node NP3 are electrically connected to each other, the voltage VNP2 of the node NP2 and the voltage VNP3 of the node NP3 are set to a low level by the first scan start signal FLM1 supplied to the first input terminal 1001. When the voltage VNP2 of the node NP2 and the voltage VNP3 of the node NP3 are set to a low level, the transistor M6 and the transistor M7 are turned on.

[0194] When the transistor M6 is turned on, the third input terminal 1003 and the output terminal 1004 are electrically connected to each other. The third input terminal 1003 is set to a voltage with a high level (for example, the clock signal PCK2 is not supplied), and therefore, a voltage with a high level is also output to the output terminal 1004. When the transistor M7 is turned on, the second input terminal 1002 and the node NP1 are electrically connected to each other. According to the clock signal PCK1 supplied to the second input terminal 1002, the voltage VNP1 of the node NP1 is set to a low level.

[0195] In addition, when the clock signal PCK1 is supplied, the transistor M8 is turned on. When the transistor M8 is turned on, the voltage of the power line VLPL is supplied to the node NP1. The voltage of the power line VLPL is set to a voltage equal to (or approximate to) a low level of the clock signal PCK1, and therefore, the node NP1 stably maintains a voltage having a low level.

[0196] When the node NP1 is set to a voltage having a low level, the transistor M4 and the transistor M5 are turned on. When the transistor M4 is turned on, the power line VHPL and the transistor M3 are electrically connected to each other. Because the transistor M3 is set to a cut-off state, the node NP3 stably maintains a voltage having a low level even when the transistor M4 is turned on. When the transistor M5 is turned on, the voltage of the power line VHPL is supplied to the output terminal 1004. The voltage of the power line VHPL is set to be equal to (or approximate to) a voltage having a high level supplied to the third input terminal 1003, and therefore, the output terminal 1004 stably maintains a voltage having a high level.

[0197] Subsequently, the supply of the first scan start signal FLM1 and the clock signal PCK1 is suspended. When the supply of the clock signal PCK1 is suspended, the transistor M2 and the transistor M8 are turned off. The transistor M6 and the transistor M7 corresponding to the voltage stored in the capacitor CP1 remain in a conducting state. For example, the voltage stored in the capacitor CP1 is applied to the gate electrode of the transistor M6 and the gate electrode of the transistor M7. For example, due to the voltage stored in the capacitor CP1, the node NP2 and the node NP3 maintain a voltage with a low level.

[0198] When the transistor M6 is kept in the on state, the electrical connection between the output terminal 1004 and the third input terminal 1003 is maintained. When the transistor M7 is kept in the on state, the node NP1 is kept electrically connected to the second input terminal 1002. Corresponding to the time when the supply of the clock signal PCK1 is suspended, the voltage of the second input terminal 1002 is set to a voltage with a high level, and therefore, the node NP1 is also set to a voltage with a high level. When the voltage with a high level is supplied to the node NP1, the transistor M4 and the transistor M5 are turned off.

[0199] Then, the clock signal PCK2 is supplied to the third input terminal 1003. Since the transistor M6 is set to the on state, the clock signal PCK2 supplied to the third input terminal 1003 is supplied to the output terminal 1004. The output terminal 1004 outputs the clock signal PCK2 as the scanning signal GWP1 having the on level to the first scanning line GWPL1.

[0200] Meanwhile, when the clock signal PCK2 is supplied to the output terminal 1004 , the voltage VNP2 of the node NP2 drops to a voltage lower than the voltage of the power line VLPL due to coupling of the capacitor CP1 , and therefore, the transistor M6 stably maintains an on state.

[0201] Meanwhile, although the voltage VNP2 of the node NP2 drops, the node NP3 may approximately maintain the voltage of the power line VLPL (eg, a voltage obtained by subtracting the threshold voltage of the transistor M1 from the voltage of the power line VLPL).

[0202] After the scanning signal GWP1 having the on level is output to the first scanning line GWPL1, the supply of the clock signal PCK2 is suspended. When the supply of the clock signal PCK2 is suspended, the output terminal 1004 outputs a voltage having a high level. In addition, corresponding to the voltage having a high level, the voltage VNP2 of the node NP2 increases to a voltage close to the voltage of the power line VLPL.

[0203] Subsequently, the clock signal PCK1 is supplied. When the clock signal PCK1 is supplied, the transistor M2 and the transistor M8 are turned on. When the transistor M2 is turned on, the first input terminal 1001 and the node NP3 are electrically connected to each other. The first scan start signal FLM1 is not supplied to the first input terminal 1001, and therefore, is set to a voltage having a high level. Thus, when the transistor M1 is turned on, a voltage having a high level is supplied to the node NP3 and the node NP2, and therefore, the transistor M6 and the transistor M7 are turned off.

[0204] When the transistor M8 is turned on, the voltage of the power line VLPL is supplied to the node NP1, and thus, the transistors M4 and M5 are turned on. When the transistor M5 is turned on, the voltage of the power line VHPL is supplied to the output terminal 1004. Subsequently, the transistors M4 and M5 maintain a turned-on state corresponding to the voltage charged in the capacitor CP2, and thus, the voltage of the power line VHPL is stably supplied to the output terminal 1004.

[0205] In addition, when the clock signal PCK2 is supplied, the transistor M3 is turned on. Since the transistor M4 is set to the on state, the voltage of the power supply line VHPL is supplied to the node NP3 and the node NP2. The transistor M6 and the transistor M7 are stably kept in the off state.

[0206] The output signal (e.g., scanning signal) of the first scanning stage PST11 is supplied to the second scanning stage PST12 to be synchronized with the clock signal PCK2. The second scanning stage PST12 outputs the scanning signal GWP2 having an on level to the second scanning line GWPL2 to be synchronized with the clock signal PCK1. By repeating the above process, the scanning stages PST11 to PST14 sequentially output the scanning signals having an on level to the scanning lines GWPL1 to GWPL4.

[0207] Fig.16 is a diagram illustrating a second scan driver according to an embodiment of the present disclosure.

[0208] refer to Fig.16 , the second scan driver 30P2 may include scan stages PST21 to PST24. The scan stages PST21 to PST24 may be connected to the corresponding scan lines GWPL(p+1) to GWPL(p+4) and the scan clock line PCKLS. The scan stages PST21 to PST24 may be implemented with the same circuit.

[0209] Each of the scanning stages PST21 to PST24 may include a first input terminal 1001 , a second input terminal 1002 , a third input terminal 1003 , and an output terminal 1004 .

[0210] The first input terminal 1001 of the first scanning stage PST21 may be connected to the second scanning start line FLML2. The first input terminal 1001 of each of the other scanning stages PST22 to PST24 may be connected to the scanning line (or carry line) of the previous scanning stage. In the example, the first scanning start signal is supplied to the first input terminal 1001 of the first scanning stage PST21, and the output signal (e.g., scanning signal or carry signal) of the previous scanning stage is supplied to the first input terminal 1001 of each of the other scanning stages PST22 to PST24.

[0211] The second input terminal 1002 of the k-th (k is an odd or even number) scanning stage can be connected to the clock line PCKL1, and the third input terminal 1003 of the k-th scanning stage can be connected to the clock line PCKL2. Fig.16 As shown in , the number k is an odd number. The second input terminal 1002 of the (k+1)th scanning stage may be connected to the clock line PCKL2, and the third input terminal 1003 of the (k+1)th scanning stage may be connected to the clock line PCKL1.

[0212] The pulses of the clock signals PCK1 and PCK2 applied to the clock lines PCKL1 and PCKL2 have the same cycle (eg, two horizontal periods 2H), but have different phases. Therefore, the pulses of the clock signals PCK1 and PCK2 may not overlap each other.

[0213] Also, each of the scanning stages PST21 to PST24 may be connected to a power line VHPL and a power line VLPL. A voltage of the power line VHPL may be set to an off level. Also, a voltage of the power line VLPL may be set to an on level.

[0214] The circuit configuration of the scanning stages PST21 to PST24 may be the same as that of the above-described scanning stages PST11 to PST14 , and therefore, overlapping descriptions may not be repeated.

[0215] Fig.17is a diagram illustrating a transmit driver according to an embodiment of the present disclosure.

[0216] refer to Fig.17 , the transmission driver 40 according to an embodiment of the present disclosure may include a first transmission driver 41 and a second transmission driver 42 .

[0217] The first emission driver 41 may be connected to the first emission stop line ELML1, the emission clock line ECKLS, and the emission lines EL1, EL2, EL3, ..., and ELp. At least one of the emission clock signals supplied to the first emission driver 41 through the emission clock line ECLKS may be referred to as a first emission clock signal.

[0218] The second emission driver 42 may be connected to a second emission stop line ELML2, an emission clock line ECKLS, and emission lines EL(p+1), EL(p+2), ..., ELq. At least one of the emission clock signals supplied to the second emission driver 42 through the emission clock line ECKLS may be referred to as a second emission clock signal. The second emission driver 42 may be connected to the same emission clock line ECKLS as the first emission driver 41. In some embodiments, the second emission driver 42 may be connected to a second emission stop line ELML2 independent of the first emission stop line ELML1 of the first emission driver 41. For example, the second emission driver 42 may be connected to a different emission stop line than the first emission driver 41, and the first emission stop signal and the second emission stop signal may be different. The first emission line EL(p+1) of the second emission driver 42 may correspond to the next emission line of the last emission line ELp of the first emission driver 41.

[0219] Fig.18 is a diagram illustrating a first emission driver according to an embodiment of the present disclosure.

[0220] refer to Fig.18 , the first emission driver 41 may include a plurality of emission stages EST11 to EST14. Fig.18 , four transmitting stages EST11 to EST14 are shown. The transmitting stages EST11 to EST14 may be connected to corresponding transmitting lines EL1 to EL4, respectively, and may be commonly connected to a transmitting clock line ECKLS. The transmitting stages EST11 to EST14 may have substantially the same circuit structure.

[0221] Each of the transmitting stages EST11 to EST14 may include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 .

[0222] The first input terminal 101 may receive an output signal (e.g., a launch signal or a carry signal) of a previous launch stage or a first launch stop signal. In an example, the first input terminal 101 of the first launch stage EST11 may be connected to the first launch stop line ELML1, and the first input terminal 101 of each of the other launch stages EST12 to EST14 may be connected to the launch line of the previous launch stage.

[0223] The second input terminal 102 of the lth (l is an odd or even number) emitting stage may be connected to the clock line ECKL1, and the third input terminal 103 of the lth emitting stage may be connected to the clock line ECKL2. Fig.18 As shown in , l may be an odd number. In addition, the second input terminal 102 of the (l+1)th transmitting stage may be connected to the clock line ECKL2, and the third input terminal 103 of the (l+1)th transmitting stage may be connected to the clock line ECKL1. For example, the clock line ECKL1 and the clock line ECKL2 may be alternately connected to the second input terminal 102 and the third input terminal 103 of each transmitting stage.

[0224] The pulses of the clock signal ECK1 applied to the clock line ECKL1 and the pulses of the clock signal ECK2 applied to the clock line ECKL2 do not overlap each other in time (see Fig. 20 ). Each pulse may have a conduction level.

[0225] The transmitting stages EST11 to EST14 may be connected to a power line VDDL and a power line VSSL. The voltage of the power line VDDL may be set to a cut-off level, and the voltage of the power line VSSL may be set to a turn-on level. The voltage level of the transmitting signal may be set based on the voltage of one of the power lines VDDL and VSSL.

[0226] Fig.19 It is shown Fig.18 0047] Figure 2 is a diagram of the emitter stage of the first emitter driver shown in FIG.

[0227] refer to Fig.19 , the transmitting stage EST11 may include an input unit 210 , an output unit 220 , a first signal processor 230 , a second signal processor 240 , a third signal processor 250 , and a first stabilizer 260 .

[0228] The output unit 220 may supply the voltage of the power line VDDL or the power line VSSL to the output terminal 104 corresponding to (eg, according to) the voltages of the nodes NE1 and NE2. To this end, the output unit 220 may include transistors Q10 and Q11.

[0229] The transistor Q10 may be connected between the power supply line VDDL and the output terminal 104. In addition, the gate electrode of the transistor Q10 may be connected to the node NE1. The transistor Q10 may be turned on or off corresponding to (e.g., according to) the voltage of the node NE1. The voltage of the power supply line VDDL supplied to the output terminal 104 when the transistor Q10 is turned on may be output as an emission signal having an off level through the emission line EL1.

[0230] The transistor Q11 may be connected between the output terminal 104 and the power supply line VSSL. In addition, the gate electrode of the transistor Q11 may be connected to the node NE2. The transistor Q11 may be turned on or off corresponding to the voltage of the node NE2. When the transistor Q11 is turned on, the voltage of the power supply line VSSL supplied to the output terminal 104 may be output as an emission signal having an on level through the emission line EL1.

[0231] The input unit 210 may control voltages of the nodes NE3 and NE4 corresponding to (eg, according to) signals supplied to the first and second input terminals 101 and 102. To this end, the input unit 210 may include transistors Q7, Q8, and Q9.

[0232] The transistor Q7 may be connected between the first input terminal 101 and the node NE4. In addition, the gate electrode of the transistor Q7 may be connected to the second input terminal 102. When a clock signal having an on level is supplied to the second input terminal 102, the transistor Q7 may be turned on to electrically connect the first input terminal 101 and the node NE4.

[0233] The transistor Q8 may be connected between the node NE3 and the second input terminal 102. In addition, a gate electrode of the transistor Q8 may be connected to the node NE4. The transistor Q8 may be turned on or off corresponding to (eg, according to) a voltage of the node NE4.

[0234] The transistor Q9 may be connected between the node NE3 and the power supply line VSSL. In addition, the gate electrode of the transistor Q9 may be connected to the second input terminal 102. When a clock signal having an on level is supplied to the second input terminal 102, the transistor Q9 may be turned on to supply the voltage of the power supply line VSSL to the node NE3.

[0235] The first signal processor 230 may control the voltage of the node NE1 corresponding to (eg, according to) the voltage of the node NE2. To this end, the first signal processor 230 may include a transistor Q12 and a capacitor CE3.

[0236] The transistor Q12 may be connected between the power supply line VDDL and the node NE1. In addition, a gate electrode of the transistor Q12 may be connected to the node NE2. The transistor Q12 may be turned on or off corresponding to (eg, according to) a voltage of the node NE2.

[0237] The capacitor CE3 may be connected between the power supply line VDDL and the node NE1. The capacitor CE3 may maintain a voltage applied to the node NE1.

[0238] The second signal processor 240 may be connected to the node NE5 and may control the voltage of the node NE1 corresponding to (eg, according to) a signal supplied to the third input terminal 103. To this end, the second signal processor 240 may include transistors Q5 and Q6, capacitors CE1 and CE2.

[0239] The capacitor CE1 may be connected between the node NE2 and the third input terminal 103. The capacitor CE1 may maintain a voltage difference between the third input terminal 103 and the node NE2.

[0240] A first electrode of the capacitor CE2 may be connected to the node NE5 , and a second electrode of the capacitor CE2 may be connected to the transistor Q5 .

[0241] The transistor Q5 may be connected between the second electrode of the capacitor CE2 and the node NE1. In addition, the gate electrode of the transistor Q5 may be connected to the third input terminal 103. When the clock signal is supplied to the third input terminal 103, the transistor Q5 may be turned on to electrically connect the second electrode of the capacitor CE2 and the node NE1.

[0242] The transistor Q6 may be connected between the second electrode of the capacitor CE2 and the third input terminal 103. In addition, a gate electrode of the transistor Q6 may be connected to the node NE5.

[0243] The third signal processor 250 may control the voltage of the node NE4 corresponding to (eg, according to) the voltage of the node NE3 and the signal supplied to the third input terminal 103. To this end, the third signal processor 250 may include transistors Q3 and Q4.

[0244] The transistor Q3 and the transistor Q4 may be connected in series between the power supply line VDDL and the node NE4. The gate electrode of the transistor Q3 may be connected to the node NE3. In addition, the gate electrode of the transistor Q4 may be connected to the third input terminal 103.

[0245] The first stabilizer 260 may be connected between the second signal processor 240 and the input unit 210. The first stabilizer 260 may limit a voltage drop width of the node NE3 and the node NE4. The first stabilizer 260 may include a transistor Q1 and a transistor Q2.

[0246] The transistor Q1 may be connected between the node NE3 and the node NE1. In addition, the gate electrode of the transistor Q1 may be connected to the power supply line VSSL. The transistor Q2 may be connected between the node NE2 and the node NE4. In addition, the gate electrode of the transistor Q2 may be connected to the power supply line VSSL.

[0247] Meanwhile, the configuration of the second transmitting stage EST12 may be substantially the same as that of the first transmitting stage EST11 except for signals supplied to the first, second and third input terminals 101, 102 and 103. Therefore, an overlapping description of the second transmitting stage EST12 may not be repeated.

[0248] Fig. 20 It is shown Fig.19 FIG. 4 is a diagram of a driving method of an emitter stage shown in FIG.

[0249] exist Fig. 20 In the following, the operation process will be described based on the first transmitting stage EST11.

[0250] refer to Fig. 20 , each of the pulses of the clock signal ECK1 and the clock signal ECK2 has a period of two horizontal periods 2H, and the pulses of the clock signal ECK1 and the pulses of the clock signal ECK2 are generated in different horizontal periods. For example, the pulse of the clock signal ECK2 may be a signal shifted by half a period (for example, one horizontal period 1H) relative to the pulse of the clock signal ECK1.

[0251] The first emission stop signal ELM1 having an off level (high level) supplied to the first input terminal 101 is set to overlap at least once with the clock signal ECK1 having a pulse of an on level (low level) supplied to the second input terminal 102. To this end, the first emission stop signal ELM1 may be supplied during a width wider than that of the clock signal ECK1 (e.g., a longer time). For example, the first emission stop signal ELM1 may be supplied within four horizontal periods 4H. In addition, the first emission signal E1 having a pulse of an off level (high level) supplied to the first input terminal 101 of the second emission stage EST12 may overlap at least once with the clock signal ECK2 having a pulse of an on level (low level) supplied to the second input terminal 102 of the second emission stage EST12.

[0252] First, at time t1b, the clock signal ECK1 having a low level is supplied to the second input terminal 102. For example, a pulse may be generated in the clock signal ECK1. Therefore, the transistor Q7 and the transistor Q9 may be turned on.

[0253] When the transistor Q7 is turned on, the first input terminal 101 and the node NE4 may be electrically connected to each other. Since the transistor Q2 maintains the on state, the first input terminal 101 may be electrically connected to the node NE2 via the node NE4. At time t1b, the start pulse having a high level is not supplied to the first input terminal 101, and therefore, the voltage VNE4 of the node NE4 and the voltage VNE2 of the node NE2 may be set to a low level.

[0254] When a voltage having a low level is supplied to the node NE2 and the node NE4 , the transistor Q8 , the transistor Q11 , and the transistor Q12 may be turned on.

[0255] When the transistor Q12 is turned on, the voltage of the power supply line VDDL may be supplied so that the voltage VNE1 of the node NE1 is set to a high level. Therefore, the transistor Q10 may be turned off.

[0256] When the transistor Q11 is turned on, the voltage of the power supply line VSSL can be supplied to the output terminal 104. Therefore, at time t1b, the emission signal E1 having an on level (low level) can be supplied to the emission line EL1.

[0257] When the transistor Q8 is turned on, the clock signal ECK1 is supplied to the node NE3. Since the transistor Q1 is kept in the on state, the clock signal ECK1 can be supplied to the node NE5 via the node NE3.

[0258] Meanwhile, when transistor Q9 is turned on, the voltage of the power supply line VSSL is supplied to node NE3 and node NE5. Clock signal ECK1 may have a low level, and therefore, voltage VNE3 of node NE3 and voltage VNE5 of node NE5 may be set to a low level. Therefore, transistor Q3 and transistor Q6 are turned on.

[0259] When transistor Q6 is turned on, clock signal ECK2 having a high level is supplied to the second electrode of capacitor CE2 from third input terminal 103. Since transistor Q5 is in an off state, node NE1 can maintain the voltage of power line VDDL regardless of the voltages of node NE5 and the second electrode of capacitor CE2.

[0260] When the transistor Q3 is turned on, the voltage of the power supply line VDDL may be supplied to the transistor Q4. The transistor Q4 may be in a turned-off state, and thus, the node NE4 may maintain a low level.

[0261] At time t2b, the clock signal ECK1 having a high level is supplied to the second input terminal 102. For example, a pulse may disappear in the clock signal ECK1. Therefore, the transistor Q7 and the transistor Q9 may be turned off. The previous voltage of the node NE2 and the node NE1 may be maintained by the capacitor CE1 and the capacitor CE3, and the transistor Q8, the transistor Q11, and the transistor Q12 may maintain a conducting state.

[0262] When the transistor Q8 is turned on, the clock signal ECK1 having a high level is supplied to the node NE3 and the node NE5 from the second input terminal 102. Therefore, the transistor Q3 and the transistor Q6 are set to a cut-off state.

[0263] At time t3b, the clock signal ECK2 having a low level is supplied to the third input terminal 103. For example, a pulse is generated in the clock signal ECK2. Therefore, the transistor Q4 and the transistor Q5 are turned on.

[0264] When the transistor Q5 is turned on, the second electrode of the capacitor CE2 and the node NE1 are electrically connected to each other. Since the transistor Q12 is in an on state, the node NE1 maintains the voltage of the power supply line VDDL.

[0265] When the transistor Q4 is turned on, the second electrode of the transistor Q3 and the node NE2 are electrically connected to each other. Since the transistor Q3 is in an off state, the voltage of the power supply line VDDL is not supplied to the node NE4 and the node NE2.

[0266] When the clock signal ECK2 having a low level is supplied to the third input terminal 103, the node NE2 drops to a voltage lower than the voltage of the power supply line VSSL due to the coupling of the capacitor CE1. Therefore, the voltages of the gate electrodes of the transistors Q11 and Q12 are lower than the voltage of the power supply line VSSL, so that the driving characteristics of these transistors can be improved.

[0267] Regardless of the voltage drop of the node NE2, the node NE4 can approximately maintain the voltage of the power supply line VSSL due to the transistor Q2. For example, because the voltage of the power supply line VSSL is continuously applied to the gate electrode of the transistor Q2, the voltage of the node NE4 corresponding to the source electrode of the transistor Q2 does not drop below the value obtained by adding the threshold voltage value to the voltage of the power supply line VSSL. Therefore, the voltage difference between the first electrode and the second electrode of the transistor Q7 is minimized or reduced, so that the characteristics of the transistor Q7 can be prevented from being changed, or the change of the characteristics of the transistor Q7 can be reduced or minimized.

[0268] At time t4b, the first emission stop signal ELM1 having an off level (high level) is supplied to the first input terminal 101, and the clock signal ECK1 having a low level is supplied to the second input terminal 102. For example, a pulse is generated in the clock signal ECK1. Therefore, the transistor Q7 and the transistor Q9 are turned on.

[0269] When the transistor Q7 is turned on, the first input terminal 101 is electrically connected to the node NE4 and the node NE2. Therefore, the node NE4 and the node NE2 are charged with a voltage of a high level, and the transistors Q8, Q11, and Q12 are turned off.

[0270] When the transistor Q9 is turned on, the voltage of the power supply line VSSL is supplied to the node NE3 and the node NE5, and the transistor Q3 and the transistor Q6 are turned on. Since the transistor Q4 is turned off even when the transistor Q3 is turned on, the voltage of the node NE4 is maintained.

[0271] When the transistor Q6 is turned on, the second electrode of the capacitor CE2 and the third input terminal 103 are electrically connected to each other. Since the transistor Q5 is in the off state, the node NE1 maintains a high level.

[0272] At t5b time, the clock signal ECK2 having a low level is supplied to the third input terminal 103. For example, a pulse is generated in the clock signal ECK2. Therefore, the transistor Q4 and the transistor Q5 are turned on. Since the node NE3 and the node NE5 are in a state where they are charged with the voltage of the power supply line VSSL, the transistor Q3 and the transistor Q6 are in a conducting state.

[0273] The clock signal ECK2 having a low level is applied to the node NE1 via the turned-on transistors Q5 and Q6, and the transistor Q10 is turned on. When the transistor Q10 is turned on, the voltage of the power supply line VDDL is supplied as the emission signal E1 to the output terminal 104. Therefore, the emission signal E1 having a cut-off level (high level) can be supplied to the emission line EL1.

[0274] When the transistor Q3 and the transistor Q4 are turned on, the voltage of the power supply line VDDL is supplied to the node NE4 and the node NE2. Therefore, the transistor Q8 and the transistor Q11 can stably maintain the off state.

[0275] At the same time, when the clock signal ECK2 having a low level is supplied to the second electrode of the capacitor CE2, the voltage of the node NE5 drops to a voltage lower than the voltage of the power supply line VSSL due to the coupling of the capacitor CE2. Therefore, the voltage applied to the gate electrode of the transistor Q6 drops to a voltage lower than the voltage of the power supply line VSSL, and the driving characteristics of the transistor Q6 can be improved.

[0276] Regardless of the voltage of the node NE5, the voltage of the node NE3 can approximately maintain the voltage of the power line VSSL through the transistor Q1. For example, because the voltage of the power line VSSL is continuously applied to the gate electrode of the transistor Q1, the voltage of the node NE3 corresponding to the source electrode of the transistor Q1 does not drop below the value obtained by adding the threshold voltage value (e.g., the threshold voltage value of the transistor Q1) to the voltage of the power line VSSL. Therefore, regardless of the voltage drop of the node NE5, the node NE3 can approximately maintain the voltage of the power line VSSL. The voltage difference between the source electrode and the drain electrode of the transistor Q8 is minimized or reduced, so that the characteristics of the transistor Q8 can be prevented from being changed, or the change of the characteristics of the transistor Q8 can be reduced or minimized.

[0277] At time t6b, the clock signal ECK1 having a low level is supplied to the second input terminal 102. For example, a pulse may be generated in the clock signal ECK1. Therefore, the transistor Q7 and the transistor Q9 are turned on.

[0278] When the transistor Q7 is turned on, the node NE4 and the node NE2 are electrically connected to the first input terminal 101, and thus, a voltage having a low level is supplied to the node NE4 and the node NE2 from the first input terminal 101. Therefore, the transistor Q8, the transistor Q11, and the transistor Q12 are turned on.

[0279] When the transistor Q8 is turned on, the clock signal ECK1 having a low level is supplied to the node NE3 and the node NE5.

[0280] When the transistor Q12 is turned on, the voltage of the power supply line VDDL is supplied to the node NE1, and the transistor Q10 is turned off.

[0281] When the transistor Q11 is turned on, the voltage of the power supply line VSSL is supplied to the output terminal 104. Therefore, the emission signal E1 having an on level (low level) can be supplied to the emission line EL1.

[0282] At the same time, by repeating the above process, the second transmitting stage EST12 supplied with the transmission signal E1 having the cut-off level from the output terminal 104 of the first transmitting stage EST11 supplies the transmission signal E2 having the cut-off level to the transmission line EL2. For example, by repeating the above process, the transmitting stages EST11 to EST14 according to the embodiment of the present disclosure can supply the transmission signal to the transmission lines EL1 to EL4.

[0283] Fig.21 is a diagram illustrating a second emission driver according to an embodiment of the present disclosure.

[0284] refer to Fig.21, the second emission driver 42 may include a plurality of emission stages EST21 to EST24. Fig.21 Four transmitting stages EST21 to EST24 are shown in FIG. The transmitting stages EST21 to EST24 may be connected to corresponding transmitting lines EL(p+1) to EL(p+4), respectively, and may be commonly connected to an transmitting clock line ECKLS. The transmitting stages EST21 to EST24 may have substantially the same circuit structure.

[0285] Each of the transmitting stages EST21 to EST24 may include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 .

[0286] The first input terminal 101 may receive an output signal (e.g., an emission signal or a carry signal) of a previous emission stage or a second emission stop signal ELM2. In an example, the first input terminal 101 of the first emission stage EST21 may be connected to the second emission stop line ELML2, and the first input terminal 101 of each of the other emission stages EST22 to EST24 may be connected to the emission line of the previous emission stage.

[0287] The second input terminal 102 of the hth (h is an odd or even number) emitting stage may be connected to the clock line ECKL1, and the third input terminal 103 of the hth emitting stage may be connected to the clock line ECKL2. Fig.21 As shown in , h may be an odd number. In addition, the second input terminal 102 of the (h+1)th transmitting stage may be connected to the clock line ECKL2, and the third input terminal 103 of the (h+1)th transmitting stage may be connected to the clock line ECKL1. For example, the clock line ECKL1 and the clock line ECKL2 may be alternately connected to the second input terminal 102 and the third input terminal 103 of each transmitting stage.

[0288] The pulse of the clock signal ECK1 applied to the clock line ECKL1 and the pulse of the clock signal ECK2 applied to the clock line ECKL2 do not overlap each other in time. Each pulse may have an on level.

[0289] The transmitting stages EST21 to EST24 may be connected to a power line VDDL and a power line VSSL. The voltage of the power line VDDL may be set to a cut-off level, and the voltage of the power line VSSL may be set to a turn-on level. The voltage level of the transmitting signal may be set based on the voltage of one of the power lines VDDL and VSSL.

[0290] The circuit configuration of the transmitting stages EST21 to EST24 can be Fig.18The circuit configurations of the transmitting stages EST11 to EST14 shown in FIG. 1 are the same or substantially the same, and therefore, overlapping descriptions may not be repeated.

[0291] Fig. 22 and Fig.23 This is a diagram showing a case where data writing frames are continuous.

[0292] refer to Fig. 22 , for the convenience of description, a plurality of pixels PX1 to PX6 connected to the first data line DL1 are shown as an example. For the convenience of description, the plurality of pixels PX1 to PX6 are described based on the scan lines GWPL1, GWPL2, GWPLp, GWPL(p+1), GWPL(p+2), and GWPLq connected to the gate electrodes of the transistors T2 of the corresponding pixels PX1 to PX6 among the scan lines connected to the corresponding pixels PX1 to PX6. For example, the pixels PX1 to PX6 are described based on the scan lines GWPL1 to GWPLq connected to the first scan driver 30P1 and the second scan driver 30P2.

[0293] Hereinafter, the “first scan line” may refer to a scan line to which a scan signal having a first on level is supplied after the first scan start signal FLM1 having an on level is generated, among the scan lines connected to the first scan driver 30P1. Fig. 22 In the embodiment shown in , the first scan line may refer to the first scan line GWPL1. In addition, the "last scan line" may refer to a scan line connected to the second scan driver 30P2 and supplied with a scan signal having a last on-level after the second scan start signal FLM2 is generated. Fig. 22 In the embodiment shown in , the last scan line may represent the sixth scan line GWPLq. The "next scan line" of the reference scan line may represent a scan line to which a scan signal with an on-level is supplied at the closest time after a scan signal with an on-level is supplied to the reference scan line (e.g., the next time during the time during which the scan signal is supplied to the scan line). The "previous scan line" of the reference scan line may represent a scan line to which a scan signal with an on-level is supplied at the closest time before a scan signal with an on-level is supplied to the reference scan line (e.g., the previous time during the time during which the scan signal is supplied to the scan line). The above description is based on the case where one on-level pulse is supplied in a frame including a data write period WP. When two or more pulses with an on-level are continuously supplied to the scan line in each frame, the above description may be applied based on the last pulse.

[0294] The first pixel PX1 may be connected to the first data line DL1, the first scan line GWPL1, the first emission line EL1, and the scan lines GIL1, GWNL1, and GBL1. The first scan line GWPL1 may be connected to the first scan driver 30P1. The first scan line GWPL1 may be a first scan line.

[0295] The second pixel PX2 may be connected to the first data line DL1, the second scan line GWPL(p+1), the second emission line EL(p+1), and the scan lines GIL(p+1), GWNL(p+1), and GBL(p+1). The second scan line GWPL(p+1) may be connected to the second scan driver 30P2.

[0296] The third pixel PX3 may be connected to the first data line DL1, the third scan line GWPL2, the third emission line EL2, and the scan lines GIL2, GWNL2, and GBL2. The third scan line GWPL2 may be connected to the first scan driver 30P1. The third scan line GWPL2 may be the next scan line of the first scan line GWPL1.

[0297] The fourth pixel PX4 may be connected to the first data line DL1, the fourth scan line GWPL(p+2), the fourth emission line EL(p+2), and the scan lines GIL(p+2), GWNL(p+2), and GBL(p+2). The fourth scan line GWPL(p+2) may be connected to the second scan driver 30P2. The fourth scan line GWPL(p+2) may be the next scan line of the second scan line GWPL(p+1).

[0298] The fifth pixel PX5 may be connected to the first data line DL1, the fifth scan line GWPLp, the fifth emission line ELp, and the scan lines GILp, GWNLp, and GBLp. The fifth scan line GWPLp may be connected to the first scan driver 30P1. The fifth scan line GWPLp may be a previous scan line of the second scan line GWPL(p+1).

[0299] The sixth pixel PX6 may be connected to the first data line DL1, the sixth scan line GWPLq, the sixth emission line ELq, and the scan lines GILq, GWNLq, and GBLq. The sixth scan line GWPLq may be connected to the second scan driver 30P2. The sixth scan line GWPLq may be the last scan line.

[0300] The emission lines EL1, EL2, and ELp may be connected to the first emission driver 41. The emission lines EL(p+1), EL(p+2), and ELq may be connected to the second emission driver 42. The scan lines GWNL1, GWNL2, GWNLp, GWNL(p+1), GWNL(p+2), and GWNLq may be connected to the third scan driver 30N.

[0301] refer to Fig.23 , shows an example two frame periods when the display device is driven in the first display mode. The first frame period may sequentially include a first vertical blanking period and a first valid data period ADPN. The second frame period, which is the next frame period of the first frame period, may sequentially include a second vertical blanking period VBP(N+1) and a second valid data period ADP(N+1).

[0302] The "valid data period" may be a supply period of grayscale values ​​constituting an image frame to be displayed by the pixel unit 50. The "vertical blanking period" may be a transition period between the valid data period of the previous image frame and the valid data period of the current image frame. Clock training, frame setting, and dummy data supply may be performed during the vertical blanking period. The pulse of the vertical synchronization signal may be generated during the vertical blanking period and may not be generated during the valid data period. The pulse of the horizontal synchronization signal may be generated in both the vertical blanking period and the valid data period.

[0303] Before the first data writing period WPN, the pixels PX1 to PX6 may emit light during the emission period EP(N-1) based on the data voltage written in the previous data writing period. The data writing period and the emission period may be changed in units of pixel rows.

[0304] Based on each pixel row, the first valid data period ADPN may sequentially include a first data write period WPN and a first emission period EPN. In the first data write period WPN, data voltages may be sequentially written to pixels PX1 to PX6. During the first emission period EPN, pixels PX1 to PX6 may emit light based on the data voltages written in the first data write period WPN.

[0305] Clock training, frame setting, and dummy data supply may be performed during the second vertical blanking period VBP(N+1). In the second vertical blanking period VBP(N+1), the pixels PX1 to PX6 may maintain an emission state based on the data voltage written in the first data writing period WPN.

[0306] Based on each pixel row, the second effective data period ADP(N+1) may include a second data write period WP(N+1) and a second emission period EP(N+1). In the second data write period WP(N+1), data voltages may be sequentially written to pixels PX1 to PX6. During the second emission period EP(N+1), pixels PX1 to PX6 may emit light based on the data voltages written in the second data write period WP(N+1).

[0307] The scan clock signal PCKS can be applied to Fig. 9The scan clock signal PCKS corresponds to the first scan clock signal or the second scan clock signal described above. Fig.23 The scan clock signal PCKS shown in FIG. 1 is simply shown to describe the first period PP1 and may have a waveform different from the actual waveform (e.g., different from Fig.23 ) of the waveform shown in FIG.

[0308] The scan clock signal NCKS can be applied to Fig. 9 The scanning clock line NCKLS shown in FIG. Fig.23 The scanning clock signal NCKS shown in FIG. 1 is simply shown to describe whether the scanning clock signal NCKS is to be supplied, and may have a waveform different from that of an actual waveform (eg, Fig.23 Since it is necessary for the third scan driver 30N to sequentially supply the scan signal having the on level during the data writing periods WPN and WP(N+1), the scan clock signal NCKS having the on level may also be supplied in a specific period.

[0309] The transmit clock signal ECKS can represent the Fig.17 The transmit clock signal of the clock line in the transmit clock line ECKLS shown in FIG. The transmit clock signal ECKS may correspond to the first transmit clock signal or the second transmit clock signal described above. Fig.23 The transmission clock signal ECKS shown in FIG. 1 is simply shown to describe the third period EP1 and may have a waveform different from the actual waveform (for example, different from Fig.23 ) of the waveform shown in FIG.

[0310] At time t1c, the first scan start signal FLM1 having an on level may be supplied. In synchronization with the supply of the first scan start signal FLM1 having an on level, the third scan start signal FLM3 having an on level and the first emission stop signal ELM1 having an off level may be supplied.

[0311] At time t2c, the scanning stage PST11 may supply the first scanning signal GWP1 having a turn-on level (low level).

[0312] At time t3c, the second scan start signal FLM2 having the on level may be supplied. In synchronization with the supply of the second scan start signal FLM2 having the on level, the second emission stop signal ELM2 having the off level may be supplied.

[0313] At time t4c, the scanning stage PST21 may supply the second scanning signal GWP(p+1) having a turn-on level.

[0314] Operations of the scan driver 30 and the emission driver 40 at the above times t1c, t2c, t3c and t4c of the first frame period are the same as operations of the scan driver 30 and the emission driver 40 at times t5c, t6c, t7c and t8c of the second frame period, and therefore, overlapping descriptions may not be repeated.

[0315] In the first frame period and the second frame period, the scan clock signal PCKS may have a first period PP1. In addition, in the first frame period and the second frame period, the emission clock signal ECKS may have a third period EP1.

[0316] Figure 24 to Figure 26 This is a diagram showing a case where a data writing frame and a bias refresh frame are consecutive.

[0317] refer to Fig.24 , shows an example two frame periods when the display device is displayed in the second display mode. The first frame period may sequentially include a first vertical blanking period and a first valid data period ADPN. The second frame period, which is the next frame period of the first frame period, may sequentially include a second vertical blanking period VBP(N+1) and a second dummy data period DDP(N+1).

[0318] The "dummy data period" may correspond to the "valid data period". For example, the length of the "dummy data period" may be equal to the length of the "valid data period" (for example, equal to the length of the first valid data period ADPN). However, the grayscale values ​​constituting the image frame may not be supplied in the "dummy data period".

[0319] The operations of the scan driver 30 and the emission driver 40 at times t1d, t2d, t3d, and t4d of the first frame period in the second display mode may be the same as the operations of the scan driver 30 and the emission driver 40 at times t1c, t2c, t3c, and t4c of the first frame period in the first display mode, and therefore, the overlapping descriptions may not be repeated. The difference between the time t3d when the second scan start signal FLM2 having the on level is supplied and the time t1d when the first scan start signal FLM1 having the on level is supplied may be defined as the first period.

[0320] When the number of pixels connected to the first data line DL1 between the first pixel PX1 and the second pixel PX2 is X and the horizontal period is Y, the first period may correspond to (X+1)×Y.

[0321] According to an embodiment of the present disclosure, in the second frame period, a difference between time t5d when the first scan start signal FLM1 having an on level is supplied and time t5d when the second scan start signal FLM2 having an on level is supplied may correspond to a second period. The second period may be shorter than the first period.

[0322] exist Fig.24 In the embodiment shown in , the first scan start signal FLM1 having an on level and the second scan start signal FLM2 having an on level may be supplied concurrently or simultaneously. Fig.24 In the second frame period shown in , the first scanning start signal FLM1 and the second scanning start signal FLM2 may be supplied concurrently or simultaneously. Therefore, the second period may be 0 (0 seconds).

[0323] Based on each pixel row connected to the first scan driver 30P1, the second dummy data period DDP (N + 1) may sequentially include a first bias refresh period BP1 (N + 1) and a first emission period EP1 (N + 1). In addition, based on each pixel row connected to the second scan driver 30P2, the second dummy data period DDP (N + 1) may sequentially include a second bias refresh period BP2 (N + 1) and a second emission period EP2 (N + 1).

[0324] According to the present embodiment, at least portions of the first bias refresh period BP1(N+1) and the second bias refresh period BP2(N+1) may overlap each other. Fig.24 In the embodiment shown in , the first bias refresh period BP1(N+1) and the second bias refresh period BP2(N+1) may be the same. Therefore, the first emission period EP1(N+1) and the second emission period EP2(N+1) may be the same.

[0325] For example, according to the present embodiment, the first scan driver 30P1 and the second scan driver 30P2 may be operated concurrently or simultaneously, and therefore, the scan clock signal PCKS may have a second period PP2. The second period PP2 may be longer than the first period PP1. For example, the frequency of the scan clock signal PCKS in the second frame period may be lower than the frequency of the scan clock signal PCKS in the first frame period, and therefore, power consumption may be reduced.

[0326] refer to Figure 7 and Figure 8 In the driving method shown in FIG. 1 , the supply of the first emission stop signal ELM1 having an off level must be synchronized with the supply of the first scan start signal FLM1 having an on level. In addition, the supply of the second emission stop signal ELM2 having an off level must be synchronized with the supply of the second scan start signal FLM2 having an on level.

[0327] In the first frame period, the difference between the time when the second emission stop signal ELM2 having the cut-off level is supplied and the time when the first emission stop signal ELM1 having the cut-off level is supplied may be defined as a third period. In addition, in the second frame period, the difference between the time when the second emission stop signal ELM2 having the cut-off level is supplied and the time when the first emission stop signal ELM1 having the cut-off level is supplied may be defined as a fourth period. The fourth period may be shorter than the third period.

[0328] For example, according to the present embodiment, the first emission driver 41 and the second emission driver 42 may operate concurrently or simultaneously, and therefore, the emission clock signal ECKS may have a fourth period EP2. The fourth period EP2 may be longer than the third period EP1. For example, the frequency of the emission clock signal ECKS in the second frame period may be lower than the frequency of the emission clock signal ECKS in the first frame period, and thus power consumption may be reduced.

[0329] refer to Figure 7 and Figure 8 In the driving method shown in FIG. 1 , the third scan driver 30N does not supply a scan signal having an on level during the second frame period. Therefore, the third scan driver 30N does not need to supply a scan clock signal NCKS having an on level at a specific cycle during the second frame period. Moreover, the third scan driver 30N does not supply a third scan start signal FLM3 having an on level during the second frame period.

[0330] refer to Fig.25 In the second display mode, a portion of the valid data period ADPN and a portion of the dummy data period DDP(N+1) are compared with each other. For example, the valid data period ADPN and the dummy data period DDP(N+1) may be compared based on times t2d and t6d when the first scan signal GWP1 having a turn-on level is supplied.

[0331] In the first frame period, a difference between a time t2d when the first scan signal GWP1 having an on level is applied to the first scan line GWPL1 and a time t2.1d when the third scan signal GWP2 having an on level is applied to the third scan line GWPL2 may be defined as a third period.

[0332] In addition, in the second frame period, a difference between a time t6d when the first scan signal GWP1 having an on level is applied and a time t6.1d when the third scan signal GWP2 having an on level is applied may be defined as a fourth period. The fourth period may be longer than the third period.

[0333] This driving characteristic is a phenomenon that occurs because the second period PP2 of the scan clock signal PCKS supplied to the first scan driver 30P1 and the second scan driver 30P2 is longer than the first period PP1.

[0334] At the same time, reference Fig. 22 and Fig.24 , in the first frame period, the time when the fifth scan signal GWPp having the on level is applied to the fifth scan line GWPLp may be earlier than the time t4d when the second scan signal GWP(p+1) having the on level is applied. Meanwhile, in the second frame period, the time when the fifth scan signal GWPp having the on level is applied may be later than the time t6d when the second scan signal GWP(p+1) having the on level is applied.

[0335] refer to Fig.26 , shows a case where, in the second frame period, a second period PSD which is a difference between a time when the first scan start signal FLM1 having an on level is supplied and a time when the second scan start signal FLM2′ having an on level is supplied is not 0 (0 seconds).

[0336] For example, at least portions of the first bias refresh period BP1(N+1) and the second bias refresh period BP2(N+1)' may overlap with each other, but the first bias refresh period BP1(N+1) and the second bias refresh period BP2(N+1)' may not be completely identical (e.g., may not completely overlap). Therefore, at least portions of the emission periods EP1(N+1) and EP2(N+1)' may overlap with each other, but the emission periods EP1(N+1) and EP2(N+1)' may not be completely identical (e.g., may not completely overlap).

[0337] For example, the minimum value of the second period PSD may be 0 (0 seconds), and the maximum value of the second period PSD may correspond to the second vertical blanking period VBP (N + 1). The second period PSD is set to the maximum value or less so that the bias refresh periods BP1 (N + 1) and BP2 (N + 1)' do not overlap with the adjacent data write period WPN.

[0338] Similarly, in the second frame period, the fourth period ESD which is a difference between the time when the first emission stop signal ELM1 having the turn-off level is supplied and the time when the second emission stop signal ELM2 ′ having the turn-off level is supplied may not be 0 (0 seconds).

[0339] exist Fig.26, a case where the second scan start signal FLM2′ having an on level is supplied earlier than the first scan start signal FLM1 having an on level in the second frame period is shown. However, in another embodiment, the first scan start signal FLM1 having an on level is supplied earlier than the second scan start signal FLM2′ having an on level. For example, the time when the first scan start signal FLM1 having an on level is supplied may occur during the second vertical blanking period VBP(N+1).

[0340] Similarly, in Fig.26 , a case where the time when the second emission stop signal ELM2′ having the cut-off level is supplied in the second frame period is earlier than the time when the first emission stop signal ELM1 having the cut-off level is supplied. However, in another embodiment, the time when the first emission stop signal ELM1 having the cut-off level is supplied may be earlier than the time when the second emission stop signal ELM2′ having the cut-off level is supplied. For example, the time when the first emission stop signal ELM1 having the cut-off level is supplied may occur during the second vertical blanking period VBP(N+1).

[0341] In the display device and the driving method thereof according to the present disclosure, the frequency of a clock signal is controlled according to the type of a frame, so that power consumption can be reduced.

[0342] Example embodiments have been disclosed herein, and although example terms are used, they are used and interpreted only in a general and descriptive sense, and they are not intended for limiting purposes. In some cases, as will be apparent to one of ordinary skill in the art upon effective filing of this application, features, characteristics, and / or elements described in conjunction with one embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with another embodiment, unless specifically noted otherwise. Therefore, it will be understood by those skilled in the art that various suitable changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and the second scan line; a first scan driver connected to the first scan start line and the first scan line; as well as a second scan driver connected to the second scan start line and the second scan line, wherein, in a first frame period, after a first period of time has passed since a first scan start signal having an on level is supplied to the first scan start line, a second scan start signal having an on level is supplied to the second scan start line, wherein, in the second frame period, a difference between a time when the first scan start signal having the on level is supplied and a time when the second scan start signal having the on level is supplied corresponds to a second period, wherein the second period is shorter than the first period, wherein, in the first frame period, the first scan clock signal supplied to the first scan driver has a first cycle, and In which, in the second frame period, the first scan clock signal has a second period that is longer than the first period.

2. The display device according to claim 1, wherein: In the first frame period, the second scan clock signal supplied to the second scan driver has the first cycle, and In which, during the second frame period, the second scanning clock signal has the second period.

3. The display device according to claim 2, further comprising: a first transmit driver connected to the first transmit stop line and the first transmit line; as well as a second emission driver connected to the second emission stop line and the second emission line, wherein the first pixel is connected to the first emission line, wherein the second pixel is connected to the second emission line, wherein, in the first frame period, after a third period has passed after a first emission stop signal having an off level is supplied to the first emission stop line, a second emission stop signal having an off level is supplied to the second emission stop line, wherein, in the second frame period, a difference between a time when the first emission stop signal having the cut-off level is supplied and a time when the second emission stop signal having the cut-off level is supplied corresponds to a fourth period, and The fourth time period is shorter than the third time period.

4. The display device according to claim 3, wherein: In the first frame period, the first emission clock signal supplied to the first emission driver has a third cycle, In which, in the second frame period, the first transmission clock signal has a fourth period that is longer than the third period.

5. The display device according to claim 4, wherein: In the first frame period, the second emission clock signal supplied to the second emission driver has the third cycle, In which, in the second frame period, the second transmit clock signal has the fourth period.

6. The display device according to claim 1, wherein: A minimum value of the second period is 0 seconds, and a maximum value of the second period corresponds to a vertical blanking period.

7. The display device according to claim 1, wherein: When the number of pixels connected to the first data line between the first pixel and the second pixel is X and a horizontal period is Y, the first period corresponds to (X+1)×Y.

8. A display device comprising: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and the second scan line; a first scan driver connected to the first scan start line and the first scan line; a second scan driver connected to the second scan start line and the second scan line; as well as a third pixel connected to the first data line and a third scan line which is a scan line next to the first scan line, wherein, in a first frame period, after a first period of time has passed since a first scan start signal having an on level is supplied to the first scan start line, a second scan start signal having an on level is supplied to the second scan start line, wherein, in the second frame period, a difference between a time when the first scan start signal having the on level is supplied and a time when the second scan start signal having the on level is supplied corresponds to a second period, wherein the second period is shorter than the first period, wherein the third scan line is connected to the first scan driver, wherein, in the first frame period, a difference between a time when the first scan signal having an on level is applied to the first scan line and a time when the third scan signal having an on level is applied to the third scan line corresponds to a third period, wherein, in the second frame period, the difference between the time when the first scan signal having the on level is applied and the time when the third scan signal having the on level is applied corresponds to a fourth period, and The fourth time period is longer than the third time period.

9. The display device according to claim 8, further comprising: a fourth pixel connected to the first data line and a fourth scan line which is a scan line next to the second scan line, wherein the fourth scan line is connected to the second scan driver, wherein, in the first frame period, a difference between a time when the second scan signal having an on level is applied to the second scan line and a time when the fourth scan signal having an on level is applied to the fourth scan line corresponds to the third period, Wherein, in the second frame period, the difference between the time when the second scan signal having the on level is applied and the time when the fourth scan signal having the on level is applied corresponds to the fourth period.

10. The display device according to claim 9, further comprising: a fifth pixel connected to the first data line and a fifth scan line which is a previous scan line of the second scan line, wherein the fifth scan line is connected to the first scan driver, wherein, in the first frame period, the time when the fifth scan signal having the on level is applied to the fifth scan line is earlier than the time when the second scan signal having the on level is applied, In which, in the second frame period, the time at which the fifth scan signal having the on-level is applied is later than the time at which the second scan signal having the on-level is applied.

11. A method for driving a display device, the method comprising: In a first frame period, supplying a first scan start signal having an on level to a first scan start line connected to the first scan driver; in the first frame period, after a first period has passed after the first scan start signal having the on level is supplied, supplying a second scan start signal having the on level to a second scan start line connected to a second scan driver; as well as in a second frame period which is a next frame period of the first frame period, supplying the first scanning start signal having the on level and the second scanning start signal having the on level with a time difference of a second period, wherein the second period is shorter than the first period, wherein, in the first frame period, the first scan clock signal supplied to the first scan driver has a first cycle, and In which, in the second frame period, the first scan clock signal has a second period that is longer than the first period.

Images