Emission driver and display device

Abstract

Embodiments of the present disclosure relate to an emission driver and a display device, the emission driver including multiple stages that output emission control signals. At least one of the multiple stages includes: an input circuit that controls the voltage of a first node and a voltage of a second node; an output circuit that supplies the voltage of a first power supply or a second power supply to an output terminal as the emission control signal in response to the voltage of a third node and a voltage of a fourth node; a first signal processor that controls the voltage of the fourth node; a second signal processor that controls the voltage of the fourth node; and a third signal processor that controls the voltage of a third node electrically connected to the first node in response to a signal supplied to the second input terminal, a signal supplied to the third input terminal, and the voltage of the first node.

Description

[0001] This application claims priority to and has all benefits of Korean Patent Application No. 10-2019-0173289, filed on December 23, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device including an emission driver. Background Art

[0003] The display device includes a data driver for supplying data signals to data lines, a scan driver for supplying scan signals to scan lines, an emission driver for supplying emission control signals to emission control lines, and pixels positioned to be connected to the data lines, scan lines, and emission control lines.

[0004] In display devices that have been studied recently, in order to improve resolution, realize stereoscopic images (e.g., high-frequency driving or high-speed driving), and reduce power consumption when displaying still images (e.g., low-frequency driving or low-speed driving), it is necessary to develop scan drivers and emission drivers corresponding to various driving frequencies.

[0005] Specifically, during high frequency driving, the falling time of the scan signal and / or the emission control signal transitioning from a logic high level to a logic low level may directly affect the image quality of the pixel. Summary of the Invention

[0006] The present disclosure provides an emission driver including a third signal processor that controls a falling step of an output signal, and provides a display device including the emission driver.

[0007] However, the objects of the present disclosure are not limited to those described above, and can be variously expanded within a range not departing from the spirit and scope of the present disclosure.

[0008] To achieve the purpose of the present disclosure, an emission driver according to an embodiment of the present disclosure may include: a plurality of stages configured to output emission control signals, and at least one of the plurality of stages may include: an input circuit configured to control a voltage of a first node and a voltage of a second node in response to a signal supplied to a first input terminal and a signal supplied to a second input terminal; an output circuit configured to supply a voltage of a first power supply or a voltage of a second power supply to an output terminal as the emission control signal in response to a voltage of a third node and a voltage of a fourth node; a first signal processor connected to a fifth node electrically connecting the second node and the fourth node and configured to control the voltage of the fourth node based on a signal supplied to the third input terminal and the voltage of the fifth node; a second signal processor configured to control the voltage of the fourth node based on the voltage of the first node; and a third signal processor configured to control the voltage of the third node electrically connected to the first node in response to the signal supplied to the second input terminal and the signal supplied to the third input terminal and the voltage of the first node.

[0009] In an embodiment, the third signal processor may control a voltage change of the third node based on the voltage of the second power supply or the voltage of the transmission control signal.

[0010] In an embodiment, the third signal processor may include: a first transistor connected between the second power supply and a sixth node and having a gate electrode connected to the third input terminal; a second transistor and a third transistor connected in series to the second transistor, the second transistor and the third transistor being connected to the sixth node and the output terminal, respectively; and a first capacitor connected between the sixth node and the third node, the gate electrode of the second transistor being connectable to the first node, and the gate electrode of the third transistor being connectable to the second input terminal.

[0011] In an embodiment, the voltage of the sixth node may be determined according to the voltage of the second power supply or the voltage of the output terminal.

[0012] In an embodiment, the third signal processor may control the voltage of the third node by utilizing coupling of the first capacitor according to a voltage change of the sixth node.

[0013] In an embodiment, the emission control signal may transition to a low level in synchronization with voltage drops of the third node and the sixth node.

[0014] In an embodiment, the input circuit may include: a fourth transistor connected between the first input terminal and the first node and having a gate electrode connected to the second input terminal; a fifth transistor connected between the second input terminal and the second node and having a gate electrode connected to the first node; and a sixth transistor connected between the first power supply and the second node and having a gate electrode connected to the second input terminal.

[0015] In an embodiment, the fifth transistor may include at least two sub-transistors connected to each other in series, and each of the at least two sub-transistors may include a gate electrode commonly connected to the first node.

[0016] In an embodiment, the output circuit may include: a seventh transistor connected between the first power supply and the output terminal and having a gate electrode connected to the third node; and an eighth transistor connected between the second power supply and the output terminal and having a gate electrode connected to the fourth node.

[0017] In an embodiment, each of the plurality of stages may further include: a stabilizer electrically connected between the input circuit and the output circuit and configured to limit a voltage drop at the first node and a voltage drop at the second node.

[0018] In an embodiment, the stabilizer may include: a twelfth transistor connected between the second node and the fifth node and having a gate electrode connected to the first power supply and receiving the voltage of the first power supply; and a thirteenth transistor connected between the first node and the third node and having a gate electrode connected to the first power supply and receiving the voltage of the first power supply.

[0019] In an embodiment, the first signal processor may include: a second capacitor having a first terminal connected to the fifth node; a ninth transistor connected between the second terminal of the second capacitor and the fourth node and having a gate electrode connected to the third input terminal; and a tenth transistor connected between the second terminal of the second capacitor and the third input terminal and having a gate electrode connected to the fifth node.

[0020] In an embodiment, the second signal processor may include: an eleventh transistor connected between the second power supply and the fourth node and having a gate electrode electrically connected to the first node; and a third capacitor connected between the second power supply and the fourth node.

[0021] In an embodiment, the second signal processor may include: an eleventh transistor connected between the second power supply and the fourth node and having a gate electrode electrically connected to the third node; and a third capacitor connected between the second power supply and the fourth node.

[0022] In an embodiment, the first input terminal may receive an output signal of a previous stage or a start pulse.

[0023] In an embodiment, the second input terminal may receive a first clock signal, and the third input terminal may receive a second clock signal obtained by shifting the first clock signal.

[0024] To achieve the purpose of the present disclosure, a display device according to an embodiment of the present disclosure may include: a plurality of pixels; a scan driver configured to supply a scan signal to the plurality of pixels through a scan line; a data driver configured to supply a data signal to the plurality of pixels through a data line; and an emission driver including a plurality of stages to supply an emission control signal to the plurality of pixels through an emission control line, and each of the plurality of stages may include: an input circuit configured to control a voltage of a first node and a voltage of a second node in response to a signal supplied to a first input terminal and a signal supplied to a second input terminal; an output circuit configured to control a voltage of a first power supply terminal and a voltage of a third node in response to a voltage of a fourth node. the voltage of the first power supply or the voltage of the second power supply is supplied to the output terminal as the emission control signal; a first signal processor is connected to a fifth node electrically connecting the second node and the fourth node to each other, and is configured to control the voltage of the fourth node based on the signal supplied to the third input terminal and the voltage of the fifth node; a second signal processor is configured to control the voltage of the fourth node based on the voltage of the third node; and a third signal processor is configured to control the voltage of the third node electrically connected to the first node in response to the signal supplied to the second input terminal and the signal supplied to the third input terminal and the voltage of the first node.

[0025] In an embodiment, each of the plurality of pixels may include an N-type transistor including an oxide semiconductor.

[0026] In an embodiment, the scan driver may include a scan stage outputting an N-type scan signal for controlling the N-type transistor, and the scan stage may have the same configuration as the at least one of the plurality of stages.

[0027] In an embodiment, the third signal processor may control a voltage change of the third node based on the voltage of the first power supply or the voltage of the transmission control signal.

[0028] In an embodiment, the third signal processor may include: a first transistor connected between the second power supply and a sixth node and having a gate electrode connected to the third input terminal; a second transistor and a third transistor connected in series to the second transistor, the second transistor and the third transistor being connected to the sixth node and the output terminal, respectively; and a first capacitor connected between the sixth node and the third node, the gate electrode of the second transistor being connectable to the first node, and the gate electrode of the third transistor being connectable to the second input terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0031] Figure 2 It shows that the Figure 1 a circuit diagram of an example of a pixel in a display device;

[0032] Figure 3 It shows Figure 2 A timing diagram of an example of driving a pixel;

[0033] Figure 4 is a block diagram illustrating a gate driver according to an embodiment of the present disclosure;

[0034] Figure 5A is shown from the included Figure 1 A timing diagram illustrating an example of an emission control signal output by an emission driver in a display device;

[0035] Figure 5B is shown from the included Figure 1 A timing diagram showing an example of a scan signal output by a scan driver in a display device;

[0036] Figure 6 It shows that the Figure 4 A circuit diagram of an example of a stage in a gate driver;

[0037] Figure 7 It shows Figure 6 A timing diagram illustrating an example of the operation of the stage;

[0038] Figure 8 It shows that the Figure 4 A circuit diagram of another example of a stage in a gate driver of FIG. 1 ; and

[0039] Figure 9is a block diagram illustrating a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and repeated description of the same components is omitted.

[0041] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0042] Reference Figure 1 The display device 1000 may include a display unit 100, a first scan driver 200 (or a first gate driver), a second scan driver 300 (or a second gate driver), an emission driver 400 (or a third gate driver), a data driver 500, and a timing controller 600.

[0043] The display device 1000 can display images at various drive frequencies (or image refresh rates or screen refresh rates) depending on the driving conditions. The drive frequency is the frequency at which data signals are essentially written to the drive transistors of the pixels PX. For example, the drive frequency is also referred to as the screen scan rate and screen refresh rate, and represents the frequency at which the display screen is reproduced within one second. The display device 1000 can display images at various drive frequencies ranging from 1 Hz to 120 Hz.

[0044] The display unit 100 displays an image. The display unit 100 includes pixels PX positioned to be connected to a data line D, scan lines S1 and S2, and an emission control line E. The pixels PX may receive a voltage of a first driving power source VDD, a voltage of a second driving power source VSS, and a voltage of an initialization power source Vint from an external source (not shown).

[0045] When a scan signal is supplied to the scan lines S1 and S2 connected to the pixel PX (e.g., the i-th first scan line S1i and the i-th second scan line S2i), each pixel PX is selected to receive a data signal from the data line D (e.g., the j-th data line Dj). The pixel PX controls the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element based on the data signal. The light-emitting element generates light of a predetermined brightness based on the amount of current. The emission time of each pixel PX is controlled by an emission control signal supplied from the emission control line E connected to the pixel PX.

[0046] In addition, the pixel PX may be connected to one or more first scan lines S1 , second scan lines S2 , and emission control lines E according to the pixel circuit structure.

[0047] The timing controller 600 may receive an input control signal and / or an input image signal from an image source, such as an external graphics device. Based on the input image signal, the timing controller 600 generates image data RGB corresponding to the operating conditions of the display unit 100 and provides the image data RGB to the data driver 500. Based on the input control signal, the timing controller 600 may generate a first drive control signal SCS1 for controlling the drive timing of the first scan driver 200, a second drive control signal SCS2 for controlling the drive timing of the second scan driver 300, a third drive control signal ECS for controlling the drive timing of the emission driver 400, and a fourth drive control signal DCS for controlling the drive timing of the data driver 500. The timing controller 600 may provide the first drive control signal SCS1, the second drive control signal SCS2, the third drive control signal ECS, and the fourth drive control signal DCS to the first scan driver 200, the second scan driver 300, the emission driver 400, and the data driver 500, respectively.

[0048] The first drive control signal SCS1 may include a first scan start pulse and a clock signal. The first scan start pulse may control a first timing of the first scan signal. The clock signal is used to shift the first scan start pulse.

[0049] The second drive control signal SCS2 may include a second scan start pulse and a clock signal. The second scan start pulse may control the first timing of the second scan signal. The clock signal is used to shift the second scan start pulse.

[0050] The third drive control signal ECS may include an emission control start pulse and a clock signal. The emission control start pulse may control the first timing of the emission control signal. The clock signal is used to shift the emission control start pulse.

[0051] The fourth drive control signal DCS may include a source start pulse and a clock signal. The source start pulse may control the start time of data sampling. The clock signal is used to control the sampling operation.

[0052] The first scan driver 200 may receive a first driving control signal SCS1 from the timing controller 600. The first scan driver 200 may supply a scan signal to the first scan line S1 in response to the first driving control signal SCS1.

[0053] The second scan driver 300 may receive a second driving control signal SCS2 from the timing controller 600. The second scan driver 300 may supply a scan signal to the second scan line S2 in response to the second driving control signal SCS2.

[0054] The emission driver 400 may receive a third driving control signal ECS from the timing controller 600. The emission driver 400 may supply an emission control signal to the emission control line E in response to the third driving control signal ECS.

[0055] The data driver 500 may receive a fourth driving control signal DCS from the timing controller 600. The data driver 500 may supply a data signal (data voltage) in an analog format to the data line D in response to the fourth driving control signal DCS.

[0056] Figure 2 It shows that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0057] exist Figure 2 , for convenience of description, a pixel PXij located in an i-th horizontal line (or i-th pixel row) and connected to a j-th data line Dj will be shown (wherein i and j are natural numbers).

[0058] Reference Figure 2 The pixel PXij may include a light emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, and a storage capacitor Cst.

[0059] The first electrode (anode electrode or cathode electrode) of the light emitting element LD is connected to the fourth connection point PN4, and the second electrode (anode electrode or cathode electrode) is connected to the second driving power supply VSS. The light emitting element LD generates light of predetermined brightness according to the amount of current supplied from the first transistor M1.

[0060] In an embodiment, the light-emitting element LD may be an organic light-emitting diode including an organic light-emitting layer. In another embodiment, the light-emitting element LD may be an inorganic light-emitting element formed of an inorganic material. Alternatively, the light-emitting element LD may include a plurality of inorganic light-emitting elements connected in parallel and / or in series between the second driving power supply VSS and the fourth connection point PN4.

[0061] A first electrode of the first transistor M1 (or driving transistor) is connected to a first connection point PN1, and a second electrode is connected to a third connection point PN3. A gate electrode of the first transistor M1 is connected to a second connection point PN2. The first transistor M1 can control the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD based on the voltage at the second connection point PN2. To this end, the first driving power supply VDD can be set to a voltage higher than the voltage of the second driving power supply VSS.

[0062] The second transistor M2 is connected between the data line Dj and the first connection point PN1. The gate electrode of the second transistor M2 is connected to the i-th first scan line S1i. When the first scan signal is supplied to the i-th first scan line S1i, the second transistor M2 is turned on to electrically connect the data line Dj and the first connection point PN1 to each other.

[0063] The third transistor M3 is connected between the second electrode (i.e., the third connection point PN3) and the second connection point PN2 of the first transistor M1. The gate electrode of the third transistor M3 is connected to the i-th second scan line S2i. When the second scan signal is supplied to the i-th second scan line S2i, the third transistor M3 is turned on to electrically connect the second electrode of the first transistor M1 and the second connection point PN2 to each other. Therefore, when the third transistor M3 is turned on, the first transistor M1 is connected in a diode-type manner.

[0064] The fourth transistor M4 is connected between the second connection point PN2 and the first initialization power source Vint1. The gate electrode of the fourth transistor M4 is connected to the (i-1)th second scan line S2i-1. When the second scan signal is supplied to the (i-1)th second scan line S2i-1, the fourth transistor M4 is turned on to supply the voltage of the first initialization power source Vint1 to the second connection point PN2. Here, the voltage of the first initialization power source Vint1 is set to a voltage lower than the voltage of the data signal supplied to the data line Dj.

[0065] Therefore, the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power supply Vint1 by turning on the fourth transistor M4, and the first transistor M1 can have an on-bias state (ie, the first transistor M1 is initialized to the on-bias state).

[0066] The fifth transistor M5 is connected between the first driving power supply VDD and the first connection point PN1. The gate electrode of the fifth transistor M5 is connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the fifth transistor M5 is turned off, and in other cases, the fifth transistor M5 is turned on.

[0067] The sixth transistor M6 is connected between the second electrode of the first transistor M1 (i.e., the third connection point PN3) and the first electrode of the light-emitting element LD (i.e., the fourth connection point PN4). The gate electrode of the sixth transistor M6 is connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the sixth transistor M6 is turned off, and in other cases, the sixth transistor M6 is turned on.

[0068] The seventh transistor M7 is connected between the first electrode of the light-emitting element LD (i.e., the fourth connection point PN4) and the second initialization power supply Vint2. The gate electrode of the seventh transistor M7 is connected to the i-th first scan line S1i. When the first scan signal is supplied to the i-th first scan line S1i, the seventh transistor M7 is turned on to supply the voltage of the second initialization power supply Vint2 to the first electrode of the light-emitting element LD.

[0069] However, this is an example, and the gate electrode of the seventh transistor M7 may be connected to the (i-1)th first scan line S1i-1 (not shown) or the (i+1)th first scan line S1i+1 (not shown).

[0070] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. Because the residual voltage charged in the parasitic capacitor is discharged (removed), unexpected micro-emissions can be prevented. Therefore, the black rendering capability of the pixel PXij can be improved.

[0071] Meanwhile, the first initialization power source Vint1 and the second initialization power source Vint2 may generate different voltages, that is, the voltage for initializing the second connection point PN2 and the voltage for initializing the fourth connection point PN4 may be set differently.

[0072] For example, in a low-frequency driven display device, a voltage of the first initialization power source Vint1 higher than a voltage of the second driving power source VSS may be required.

[0073] However, when the voltage of the second initialization power supply Vint2 supplied to the fourth connection point PN4 becomes higher than a predetermined reference, the voltage of the parasitic capacitor of the light emitting element LD may be charged rather than discharged. Therefore, the voltage of the second initialization power supply Vint2 can be set to a voltage lower than the voltage of the second driving power supply VSS.

[0074] The storage capacitor Cst is connected between the first driving power source VDD and the second connection point PN2. The storage capacitor Cst may store a voltage applied to the second connection point PN2.

[0075] At the same time, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be formed by polycrystalline silicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may include a polycrystalline silicon semiconductor layer formed as an active layer (channel) by a low-temperature polycrystalline silicon (LTPS) process. In addition, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be P-type transistors. Therefore, the gate-on voltage for turning on the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be a logic low level.

[0076] Since the polysilicon semiconductor transistor has an advantage of fast response speed, the polysilicon semiconductor transistor can be applied to a switching element that requires fast switching.

[0077] The third transistor M3 and the fourth transistor M4 may be formed of oxide semiconductor transistors. For example, the third transistor M3 and the fourth transistor M4 may be N-type oxide semiconductor transistors and may include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage for turning on the third transistor M3 and the fourth transistor M4 may be a logic high level.

[0078] Compared to polysilicon semiconductor transistors, oxide semiconductor transistors are capable of low-temperature processes and have low charge mobility. That is, oxide semiconductor transistors are excellent in terms of off-current characteristics. Therefore, when the third transistor M3 and the fourth transistor M4 are formed of oxide semiconductor transistors, the leakage current from the second connection point PN2 can be minimized, so that the display quality can be improved.

[0079] Figure 3 It shows Figure 2 A timing diagram showing an example of driving a pixel.

[0080] Reference Figure 1 、 Figure 2 and Figure 3 , the pixels PXij can receive signals for displaying an image during the non-emission period NEP and emit light based on these signals during the emission period EP.

[0081] The gate-on voltage of the second scan signal supplied to the i-th second scan line S2i and the (i-1)-th second scan line S2i-1 connected to the third transistor M3 and the fourth transistor M4, which are N-type transistors, is a logic high level. The gate-on voltage of the first scan signal supplied to the i-th first scan line S1i, which are connected to the first transistor M1, the second transistor M2, and the seventh transistor M7, which are P-type transistors, is a logic low level. The gate-on voltage of the emission control signal supplied to the i-th emission control line Ei, which is connected to the fifth transistor M5 and the sixth transistor M6, which are P-type transistors, is a logic low level.

[0082] First, the emission control signal is supplied to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the fifth transistor M5 and the sixth transistor M6 are turned off. When the fifth transistor M5 and the sixth transistor M6 are turned off, the pixel PXij is set to a non-emission state.

[0083] Afterwards, the second scan signal is supplied to the (i-1)th second scan line S2i-1. When the second scan signal is supplied to the (i-1)th second scan line S2i-1, the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the voltage of the first initialization power supply Vint1 is supplied to the second connection point PN2.

[0084] Afterwards, the first scan signal and the second scan signal are supplied to the i-th first scan line S1i and the i-th second scan line S2i, respectively. When the second scan signal is supplied to the i-th second scan line S2i, the third transistor M3 is turned on. When the third transistor M3 is turned on, the first transistor M1 is connected in the form of a diode, and the threshold voltage of the first transistor M1 can be compensated.

[0085] When the first scan signal is supplied to the i-th first scan line S1i, the second transistor M2 is turned on. When the second transistor M2 is turned on, the data signal from the data line Dj is supplied to the first connection point PN1. At this time, because the second connection point PN2 is initialized to a voltage of the first initialization power supply Vint1 lower than the data signal (for example, initialized to a conduction bias state), the first transistor M1 is turned on.

[0086] When the first transistor M1 is turned on, the data signal supplied to the first connection point PN1 is supplied to the second connection point PN2 via the first transistor M1 connected in the form of a diode. Then, a voltage corresponding to the data signal and the threshold voltage of the first transistor M1 is applied to the second connection point PN2. At this time, the storage capacitor Cst stores the voltage of the second connection point PN2.

[0087] In addition, when the first scan signal is supplied to the i-th first scan line S1i, the seventh transistor M7 is turned on. When the seventh transistor M7 is turned on, the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD (i.e., the fourth connection point PN4). Therefore, the residual voltage remaining in the parasitic capacitor of the light-emitting element LD can be discharged.

[0088] Afterwards, the emission control signal is stopped from being supplied to the i-th emission control line Ei. When the emission control signal is stopped, the fifth transistor M5 and the sixth transistor M6 are turned on. At this time, the first transistor M1 controls the drive current flowing to the light-emitting element LD based on the voltage at the second connection point PN2. The light-emitting element LD then emits light with a brightness corresponding to the amount of current.

[0089] In an embodiment, the width of the second scan signal can be greater than the width of the first scan signal to ensure sufficient threshold voltage compensation time under high-speed driving with a short horizontal period. On the other hand, according to the configuration of the conventional second scan driver 300 and the emission driver 400, the falling time of the output signal from the logic high level to the logic low level increases or the falling of the output signal is performed in a step-by-step manner (for example, a two-step falling). That is, as the gate voltage of the pull-down transistor responsible for the output of the logic low level decreases step by step, a step is generated in the falling of the output signal, and the falling speed is reduced.

[0090] For example, when the falling edge of the second scan signal transitions in a step-like manner or the falling time increases, the turn-off operation of the third transistor M3 may become unstable. When the turn-off operation of the third transistor M3 is unstable, the threshold voltage compensation may proceed to an undesirable level, and thus image quality may be degraded.

[0091] Similarly, when the falling edge of the emission control signal transitions in a step-wise manner or the falling edge time increases, the start of the emission period EP may become unstable and image quality may deteriorate.

[0092] The second scan driver 300 and / or the emission driver 400 according to an embodiment of the present disclosure may include a configuration for removing a falling step of an output signal and controlling a falling speed to increase.

[0093] Figure 4 is a block diagram illustrating a gate driver according to an embodiment of the present disclosure.

[0094] exist Figure 4 , for convenience of description, four stages and gate signals output therefrom will be shown.

[0095] Reference Figure 1 and Figure 4The gate driver 10 may include a plurality of stages ST1, ST2, ST3, and ST4. For example, the first stage ST1, the second stage ST2, the third stage ST3, and the fourth stage ST4 may be connected to predetermined gate lines G1, G2, G3, and G4, respectively, and output gate signals according to clock signals CLK1 and CLK2. The stages ST1, ST2, ST3, and ST4 may be implemented using substantially the same circuit.

[0096] In an embodiment, the gate driver 10 may be configured with reference to Figure 1 The emission driver 400 and / or the second scan driver 300 are described. For example, the gate lines G1, G2, G3, and G4 may be understood as emission control lines (eg, Figure 5A E1, E2, E3 and E4) or the second scan line (e.g., Figure 5B S2_1, S2_2, S2_3 and S2_4).

[0097] In an embodiment, the first stage ST1, the second stage ST2, the third stage ST3, and the fourth stage ST4 can each be connected to at least one gate line G1, G2, G3, and G4. For example, the first stage ST1 can be connected to the first gate line G1 and the second gate line G2 to supply gate signals to the first gate line G1 and the second gate line G2. However, this is an example, and the connection relationship between the stages ST1, ST2, ST3, and ST4 and the gate lines can be changed differently according to the pixel structure and driving method of the display device 1000.

[0098] Stages ST1 , ST2 , ST3 , and ST4 may each include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 .

[0099] The first input terminal 101 may receive an output signal of a previous stage (e.g., an emission control signal or a second scan signal) or a start pulse SSP (e.g., an emission control start pulse or a second scan start pulse). For example, the first input terminal 101 of the first stage ST1 may receive the start pulse SSP, and the first input terminal 101 of the second stage ST2 may receive a gate signal output from the first stage ST1.

[0100] In an embodiment, the second input terminal 102 of the kth (where k is a natural number) stage may receive the first clock signal CLK1, and the third input terminal 103 may receive the second clock signal CLK2. On the other hand, the second input terminal 102 of the (k+1)th stage may receive the second clock signal CLK2, and the third input terminal 103 may receive the first clock signal CLK1.

[0101] The first clock signal CLK1 and the second clock signal CLK2 may have the same period, and the phases of the first clock signal CLK1 and the second clock signal CLK2 do not overlap each other. For example, the second clock signal CLK2 may be set to a signal shifted from the first clock signal CLK1 by about half a period.

[0102] In addition, stages ST1, ST2, ST3 and ST4 receive the voltage of the first power supply VGL and the voltage of the second power supply VGH. The voltage of the first power supply VGL and the voltage of the second power supply VGH may have a DC voltage level. The voltage of the second power supply VGH may be set to be greater than the voltage of the first power supply VGL.

[0103] The voltage of the first power supply VGL can be set to a gate-off level, and the voltage of the second power supply VGH can be set to a gate-on level. For example, when the pixel PX is configured by an N-channel metal oxide semiconductor (NMOS) transistor, the voltage of the first power supply VGL (i.e., the gate-off level) can correspond to a logic low level, and the voltage of the second power supply VGH (i.e., the gate-on level) can correspond to a logic high level. However, this is an example, and the first power supply VGL and the second power supply VGH are not limited. For example, the voltage of the first power supply VGL and the voltage of the second power supply VGH can be set according to the type of transistor, the use environment of the display device, etc.

[0104] Figure 5A is shown from the included Figure 1 FIG. 1 is a timing diagram illustrating an example of emission control signals output by an emission driver in a display device.

[0105] Reference Figure 1 、 Figure 4 and Figure 5A , the gate driver 10 may be implemented as the emission driver 400. The first stage ST1, the second stage ST2, the third stage ST3, and the fourth stage ST4 may sequentially output emission control signals, respectively.

[0106] In an embodiment, within one frame period, the emission control start pulse SSP1 may include a plurality of gate-on periods and a plurality of gate-off periods of the first clock signal CLK1 and the second clock signal CLK2. The first stage ST1 may output an emission control signal to the first emission control line E1 based on the emission control start pulse SSP1 and the first clock signal CLK1 and the second clock signal CLK2.

[0107] The second stage ST2 can output an emission control signal in which the emission control signal output to the first emission control line E1 is shifted by a predetermined horizontal period to the second emission control line E2. Similarly, the third stage ST3 and the fourth stage ST4 can sequentially output emission control signals at predetermined intervals based on the first clock signal CLK1 and the second clock signal CLK2, respectively.

[0108] Figure 5B is shown from the included Figure 1 1 is a timing diagram showing an example of scan signals output by a scan driver in a display device.

[0109] Reference Figure 1 、 Figure 3 、 Figure 4 and Figure 5B , the gate driver 10 may be implemented as the second scan driver 300. The first stage ST1, the second stage ST2, the third stage ST3, and the fourth stage ST4 may sequentially output the second scan signals, respectively.

[0110] In an embodiment, within one frame period, the second scan start pulse SSP2 may include a plurality of gate-on periods and a plurality of gate-off periods of the first clock signal CLK1 and the second clock signal CLK2. The first stage ST1 may output the second scan signal to the first second scan line S2_1 based on the second scan start pulse SSP2 and the first clock signal CLK1 and the second clock signal CLK2.

[0111] The second stage ST2 may output a second scan signal to the second second scan line S2_2, wherein the second scan signal output to the first second scan line S2_1 is shifted by a predetermined horizontal period. Similarly, the third stage ST3 and the fourth stage ST4 may sequentially output the second scan signal at predetermined intervals based on the first clock signal CLK1 and the second clock signal CLK2, respectively.

[0112] Figure 6 It shows that the Figure 4 FIG1 is a circuit diagram of an example of a gate driver stage.

[0113] Reference Figure 4 and Figure 6 The i-th stage STi (where i is a natural number) may include an input circuit 11, an output circuit 12, a first signal processor 13, a second signal processor 14, and a third signal processor 15. The i-th stage STi may further include a stabilizer 16.

[0114] Based on the i-th stage STi (for example, an odd-numbered stage) in which the first clock signal CLK1 is supplied to the second input terminal 102 and the second clock signal CLK2 is supplied to the third input terminal 103, referring to Figure 6However, this is an example, and in the (i+1)th stage (eg, an even-numbered stage), the second clock signal CLK2 may be supplied to the second input terminal 102 and the first clock signal CLK1 may be supplied to the third input terminal 103 .

[0115] In an embodiment, the start pulse SSP may be supplied to the first input terminal 101 of the i-th stage STi, and the gate signal of the previous gate line (eg, the i-1-th gate line Gi-1) may be supplied to the first input terminals 101 of the remaining stages.

[0116] The input circuit 11 may control the voltage of the first node N1 and the voltage of the second node N2 in response to a signal supplied to the first input terminal 101 and a signal supplied to the second input terminal 102. In an embodiment, the input circuit 11 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0117] The fourth transistor T4 may be connected between the first input terminal 101 and the first node N1. The fourth transistor T4 may include a gate electrode connected to the second input terminal 102. When the first clock signal CLK1 has a gate-on level, the fourth transistor T4 may be turned on to electrically connect the first input terminal 101 and the first node N1 to each other.

[0118] The fifth transistor T5 may be connected between the second input terminal 102 and the second node N2. The fifth transistor T5 may include a gate electrode connected to the first node N1. The fifth transistor T5 may be turned on or off based on the voltage of the first node N1.

[0119] In an embodiment, the fifth transistor T5 may include sub-transistors T5-1 and T5-2 connected in series. Each of the sub-transistors T5-1 and T5-2 may include a gate electrode commonly connected to the first node N1. Therefore, current leakage caused by the fifth transistor T5 can be minimized.

[0120] The sixth transistor T6 may be connected between the first power supply VGL and the second node N2. A gate electrode of the sixth transistor T6 may be connected to the second input terminal 102. When the first clock signal CLK1 is supplied to the second input terminal 102, the sixth transistor T6 may be turned on to supply the voltage of the first power supply VGL to the second node N2.

[0121] The output circuit 12 can supply the voltage of the first power supply VGL or the voltage of the second power supply VGH to the output terminal 104 in response to the voltage of the third node N3 and the voltage of the fourth node N4. The voltage of the first power supply VGL may correspond to the logic low level of the gate signal (hereinafter referred to as the gate signal) supplied to the i-th gate line Gi, and the voltage of the second power supply VGH may correspond to the logic high level of the gate signal. In the display device, the gate signal may be determined as an emission control signal or a scan signal.

[0122] In an embodiment, the output circuit 12 may include a seventh transistor T7 and an eighth transistor T8 .

[0123] The seventh transistor T7 may be connected between the first power supply VGL and the output terminal 104. A gate electrode of the seventh transistor T7 may be connected to the third node N3. The seventh transistor T7 may be turned on or off in response to the voltage of the third node N3. Here, when the seventh transistor T7 is turned on, the gate signal supplied to the output terminal 104 may have a logic low level (e.g., a gate-off voltage of an N-type transistor).

[0124] The eighth transistor T8 may be connected between the second power supply VGH and the output terminal 104. The gate electrode of the eighth transistor T8 may be connected to the fourth node N4. The eighth transistor T8 may be turned on or off in response to the voltage of the fourth node N4. Here, when the eighth transistor T8 is turned on, the gate signal supplied to the output terminal 104 may have a logic high level (e.g., a gate turn-on voltage of an N-type transistor).

[0125] The first signal processor 13 may include a fifth node N5 electrically connecting the second node N2 and the fourth node N4 to each other. The first signal processor 13 may control the voltage of the fourth node N4 based on the second clock signal CLK2 supplied to the third input terminal 103 and the voltage of the fifth node N5. For example, when the voltage of the second node N2 has a logic high level, the first signal processor 13 may completely turn off the eighth transistor T8 by stably allowing the voltage of the fourth node N4 to have a gate-off level.

[0126] In an embodiment, the first signal processor 13 may include a ninth transistor T9 , a tenth transistor T10 , and a second capacitor C2 .

[0127] A first terminal of the second capacitor C2 may be connected to the fifth node N5 .

[0128] The ninth transistor T9 may be connected between the second terminal of the second capacitor C2 and the fourth node N4. A gate electrode of the ninth transistor T9 may be connected to the third input terminal 103. The ninth transistor T9 may be turned on in response to a gate-on level (e.g., a logic low level) of the second clock signal CLK2 supplied to the third input terminal 103.

[0129] The tenth transistor T10 may be connected between the second terminal of the second capacitor C2 and the third input terminal 103. A gate electrode of the tenth transistor T10 may be connected to the fifth node N5. The tenth transistor T10 may be turned on or off in response to a voltage of the fifth node N5.

[0130] The second signal processor 14 can control the voltage of the fourth node N4 in response to the voltage of the first node N1. For example, when the first node N1 has a logic low level, the second signal processor 14 can completely turn off the eighth transistor T8 of the output circuit 12 by stably making the voltage of the fourth node N4 have a logic high level. In an embodiment, the second signal processor 14 may include an eleventh transistor T11 and a third capacitor C3.

[0131] The eleventh transistor T11 may be connected between the second power source VGH and the fourth node N4. A gate electrode of the eleventh transistor T11 may be connected to the first node N1. The eleventh transistor T11 may be turned on or off in response to a voltage of the first node N1.

[0132] The third capacitor C3 may be connected between the second power source VGH and the fourth node N4. The third capacitor C3 may charge a voltage applied to the fourth node N4 and stably maintain the voltage of the fourth node N4.

[0133] For example, when the seventh transistor T7 is turned on by the voltage of the first node N1 and / or the voltage of the third node N3 , the eleventh transistor T11 may be turned on, and thus the voltage of the second power supply VGH may be supplied to the fourth node N4 .

[0134] The stabilizer 16 may be electrically connected between the input circuit 11 and the output circuit 12. The stabilizer 16 may limit a voltage drop of the first node N1 and a voltage drop of the second node N2.

[0135] In the embodiment, since the voltage of the fifth node N5 is rapidly dropped to the second low level (see Figure 7 When the voltage is 2L, the stabilizer 16 acts as a resistor, so voltage distribution occurs, and the stabilizer 16 can prevent the drain-source voltage of the fifth transistor T5 and the drain-source voltage of the sixth transistor T6 from changing rapidly. Therefore, the fifth transistor T5 and the sixth transistor T6 can be protected.

[0136] In addition, when the voltage of the third node N3 quickly drops to the second low level, the stabilizer 16 may protect the fourth transistor T4 by functioning as a resistor.

[0137] In an embodiment, the stabilizer 16 may include a twelfth transistor T12 and a thirteenth transistor T13 .

[0138] The gate electrode of the thirteenth transistor T13 can be connected to the first power supply VGL. Therefore, the thirteenth transistor T13 can always be in the on state. When the voltage of the third node N3 quickly drops to the second low level, the voltage distribution occurs due to the thirteenth transistor T13, and the rapid change of the drain-source voltage of the fourth transistor T4 can be prevented.

[0139] The twelfth transistor T12 may be connected between the second node N2 and the fifth node N5. The gate electrode of the twelfth transistor T12 may be connected to the first power supply VGL. Therefore, the twelfth transistor T12 may always be in an on state. The twelfth transistor T12 may prevent the drain-source voltage of the fifth transistor T5 and the drain-source voltage of the sixth transistor T6 from changing rapidly according to the rapid voltage change of the fifth node N5 or the fourth node N4.

[0140] The third signal processor 15 may control a voltage of a third node N3 electrically connected to the first node N1 in response to signals (e.g., the first clock signal CLK1 and the second clock signal CLK2) supplied to the second input terminal 102 and the third input terminal 103 and the voltage of the first node N1. The third signal processor 15 may control a voltage variation of the third node N3 based on a voltage of the second power supply VGH or a voltage of a gate signal.

[0141] In an embodiment, the third signal processor 15 may include first, second, and third transistors T1, T2, and T3, and a first capacitor C1.

[0142] The first transistor T1 may be connected between the second power supply VGH and the sixth node N6. The gate electrode of the first transistor T1 may be connected to the third input terminal 103. The first transistor T1 may be turned on in response to the gate-on level of the second clock signal CLK2. When the first transistor T1 is turned on, the voltage of the second power supply VGH may be supplied to the sixth node N6.

[0143] The second transistor T2 and the third transistor T3 may be connected in series and respectively connected to the sixth node N6 and the output terminal 104. The gate electrode of the second transistor T2 may be connected to the first node N1, and the gate electrode of the third transistor T3 may be connected to the second input terminal 102.

[0144] The second transistor T2 can be turned on or off in response to the voltage of the first node N1. The third transistor T3 can be turned on in response to the gate-on level of the first clock signal CLK1. When the second transistor T2 and the third transistor T3 are turned on at the same time, the voltage of the gate signal can be supplied to the sixth node N6. The voltage of the sixth node N6 can be determined by the voltage of the second power supply VGH (i.e., a logic high level) or the voltage of the output terminal 104.

[0145] The first capacitor C1 can be connected between the sixth node N6 and the third node N3. The third signal processor 15 can control the voltage of the third node N3 by utilizing the coupling of the first capacitor C1 based on the voltage change of the sixth node N6. For example, when the voltage of the sixth node N6, which has a logic high level, drops to a logic low level of the gate signal due to the conduction of the second transistor T2 and the third transistor T3, the voltage of the third node N3 can quickly drop to a second low level due to the coupling of the first capacitor C1. As a result, the seventh transistor T7 is fully turned on. As a result, the falling speed of the gate signal can be increased, the falling time can be minimized, and the falling step of the output gate signal can be eliminated or reduced.

[0146] Figure 7 It shows Figure 6 A timing diagram of an example of the operation of the stage.

[0147] Reference Figure 6 and Figure 7 The first clock signal CLK1 and the second clock signal CLK2 are supplied at different timings. For example, the second clock signal CLK2 is set to a signal shifted from the first clock signal CLK1 by half a period (for example, one horizontal period 1H).

[0148] The logic high level (or high voltage) of the start pulse SSP may correspond to the voltage of the second power supply VGH, and the logic low level or low voltage of the start pulse SSP may correspond to the voltage of the first power supply VGL. However, this is an example, and the voltage level of the start pulse SSP is not limited.

[0149] In an embodiment, the start pulse SSP may have a Figure 5A The output waveform of the emission control signal or for Figure 5B That is, the start pulse SSP and the gate signal during one frame period may include a plurality of gate-on periods and gate-off periods of the clock signals CLK1 and CLK2.

[0150] Hereinafter, a description will be given based on an embodiment in which, when the clock signals CLK1 and CLK2 are supplied, the voltage of the first power supply VGL is supplied to each of the second input terminal 102 and the third input terminal 103, and when the clock signals CLK1 and CLK2 are not supplied, the voltage of the second power supply VGH is supplied to the second input terminal 102 and the third input terminal 103.

[0151] The start pulse SSP has a logic low level at the first, second, third, and seventh time points t1, t2, t3, and t7, and has a logic high level at the fourth, fifth, and sixth time points t4, t5, and t6.

[0152] The second clock signal CLK2 may be supplied to the third input terminal 103 at a first time point t1. The first transistor T1 may be turned on in response to the second clock signal CLK2 at a first time point t1. When the first transistor T1 is turned on, the voltage of the second power supply VGH may be supplied to the sixth node N6 (i.e., one terminal of the first capacitor C1). Therefore, the voltage of the third node N3 may rise to a first low level L. The voltage of the first node N1, the voltage of the second node N2, the voltage of the fourth node N4, and the voltage of the fifth node N5 may maintain the level of the previous state. The changed voltage of the third node N3 and the changed voltage of the sixth node N6 may be substantially maintained until the second time point t2.

[0153] The first clock signal CLK1 may be supplied to the second input terminal 102 at the second time point t2. The third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned on at the second time point t2 in response to the first clock signal CLK1. Therefore, when the fourth transistor T4 is turned on, the logic low level of the start pulse SSP may be supplied to the first node N1, and when the sixth transistor T6 is turned on, the voltage of the first power supply VGL may be supplied to the second node N2.

[0154] The voltage of the second node N2 may be transferred to the fifth node N5 through the twelfth transistor T12 .

[0155] In addition, the second transistor T2 and the eleventh transistor T11 can be turned on by the voltage of the first node N1 at the second time point t2. When the second transistor T2 and the third transistor T3 are turned on together, the logic low level of the gate signal of the output terminal 104 can be supplied to the sixth node N6. Because the voltage of the first node N1 and the voltage of the sixth node N6 have a logic low level, the voltage of the third node N3 can drop to the second low level 2L.

[0156] When the eleventh transistor T11 is turned on, the voltage of the second power source VGH may be supplied to the fourth node N4. Therefore, the fourth node N4 may maintain a voltage of a logic high level. A voltage corresponding to the second power source VGH may be charged in the third capacitor C3.

[0157] At a third time point t3, the supply of the first clock signal CLK1 may be stopped. The first clock signal CLK1 and the second clock signal CLK2 may both have a logic high level. Therefore, the fourth transistor T4 and the sixth transistor T6 may be turned off. At this time, the first node N1, the third node N3, and the fourth node N4 may maintain the voltage of the previous cycle via the first capacitor C1 and the third capacitor C3.

[0158] When the fifth transistor T5 is turned on by the voltage of the first node N1 of the logic low level at the third time point t3, the logic high level from the second input terminal 102 may be supplied to the second node N2 and the fifth node N5. Then, the tenth transistor T10 may be turned off.

[0159] While maintaining the logic low state of the start pulse SSP, the operations at the first time point t1, the second time point t2, and the third time point t3 can be repeated. At this time, the voltage of the fourth node N4 can be maintained at a logic high level, and thus the eighth transistor T8 can be set to an off state. In addition, the voltage of the third node N3 can repeat the state of the first low level L and the state of the second low level 2L. Because the seventh transistor T7 is turned on by the first low level L and the second low level 2L, the gate signal can be output as a logic low level corresponding to the first power supply VGL.

[0160] At the same time, during the period in which the gate signal is output as a logic low level, whenever the first clock signal CLK1 is supplied, a logic low level is supplied to the sixth node N6. Therefore, a logic low level is periodically supplied to the third node N3 and the first node N1, and thus refresh is performed. Therefore, the seventh transistor T7 can maintain a stable on-state. Therefore, the logic low level of the gate signal can be stably output.

[0161] After that, the start pulse SSP transitions to a logic high level.

[0162] The second clock signal CLK2 may be supplied to the third input terminal 103 at a fourth time point t4. The first transistor T1 may be turned on in response to the second clock signal CLK2. When the first transistor T1 is turned on, the voltage of the second power supply VGH may be supplied to the sixth node N6. Therefore, the voltage of the third node N3 may rise to the first low level L.

[0163] The first clock signal CLK1 may be supplied to the second input terminal 102 at a fifth time point t5. The third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned on in response to the first clock signal CLK1. When the fourth transistor T4 is turned on, the logic high level of the start pulse SSP may be supplied to the first node N1. When the sixth transistor T6 is turned on, the voltage of the first power supply VGL may be supplied to the second node N2, and the fifth node N5 may have a voltage of the first low level L.

[0164] At this time, the voltage of the third node N3 may rise to a high level H by coupling of the first capacitor C1 according to the voltage rise of the first node N1. Therefore, the seventh transistor T7 may be turned off by the high level H voltage of the third node N3.

[0165] In addition, the tenth transistor T10 may be turned on by the voltage of the fifth node N5 at the fifth time point t5 , and the logic high level of the second clock signal CLK2 may be supplied to the second terminal of the second capacitor C2 .

[0166] At this time, since the ninth transistor T9 is turned off, the voltage of the fourth node N4 may maintain the voltage of the second power supply VGH regardless of the voltage of the second terminal of the second capacitor C2.

[0167] The second clock signal CLK2 may be supplied to the third input terminal 103 at a sixth time point t6. The first transistor T1 may be turned on in response to the second clock signal CLK2. When the first transistor T1 is turned on, the voltage of the second power supply VGH may be supplied to the sixth node N6. Therefore, the voltage of the third node N3 may be maintained at a high level H. The seventh transistor T7 may be kept in an off state by the high level H voltage of the third node N3.

[0168] In addition, the first node N1 and the second node N2 may maintain the voltage of the previous cycle.

[0169] In addition, the ninth transistor T9 can be turned on in response to the second clock signal CLK2. Because the voltage of the second terminal of the second capacitor C2 drops by the second clock signal CLK2 at the fifth time point t5, the voltage of the fifth node N5 can drop to the second low level 2L due to the coupling of the second capacitor C2. Therefore, the voltage of the fourth node N4 drops, and the eighth transistor T8 can be turned on by the voltage of the fourth node N4.

[0170] When the eighth transistor T8 is turned on, the voltage of the second power supply VGH may be supplied to the output terminal 104. Therefore, the gate signal may be output as a logic high level.

[0171] Thereafter, the i-th stage STi may output a gate signal of a logic high level during a period in which the start pulse SSP is supplied as a logic high level.

[0172] At the seventh time point t7, the start pulse SSP may have a logic low level again, and the first clock signal CLK1 may be supplied. The third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned on in response to the first clock signal CLK1. When the fourth transistor T4 is turned on, the logic low level of the start pulse SSP may be supplied to the first node N1, and when the sixth transistor T6 is turned on, the voltage of the first power supply VGL may be supplied to the second node N2.

[0173] The voltage of the second node N2 may be transferred to the fifth node N5 through the twelfth transistor T12 .

[0174] In addition, the eleventh transistor T11 may be turned on by the voltage of the first node N1 at the seventh time point t7. When the eleventh transistor T11 is turned on, the voltage of the second power supply VGH may be supplied to the fourth node N4, and the eighth transistor T8 may be turned off.

[0175] In addition, the second transistor T2 can be turned on by the voltage of the first node N1 at the seventh time point t7. When the second transistor T2 and the third transistor T3 are turned on together, the logic low level of the gate signal of the output terminal 104 can be supplied to the sixth node N6. Because the voltage of the first node N1 and the voltage of the sixth node N6 are charged to the logic low level, the voltage of the third node N3 can be very quickly dropped from the high level H to the second low level 2L through the coupling of the first capacitor C1.

[0176] Therefore, the absolute value of the gate-source voltage of the seventh transistor T7 can become very large. Therefore, the falling speed of the gate signal output from the output terminal 104 becomes very high, and the falling step of the gate signal can be removed. For example, the gate signal (that is, the gate signal or emission control signal supplied to the i-th gate line Gi) can be synchronously converted to a low level with the voltage drop of the third node N3 and the voltage drop of the sixth node N6.

[0177] As described above, the gate driver (or Figure 1 The emission driver 400) and the gate driver (or Figure 1 A display device (emission driver 400) includes the third signal processor 15 in the i-th stage STi. Therefore, the falling speed of the gate signal can be increased, and the falling step can be substantially eliminated. Therefore, the driving reliability and image quality in the high-speed driving method of the display device can be improved.

[0178] Figure 8 It shows that the Figure 4 FIG1 is a circuit diagram of another example of a stage in a gate driver.

[0179] exist Figure 8 In the Figure 6 In addition to the configuration of the eleventh transistor T11, Figure 8 The level can have Figure 6 The configurations of the levels are basically equal or similar configurations.

[0180] Reference Figure 8 The second signal processor 14 may supply the voltage of the second power source VGH to the fourth node N4 in response to the voltage of the third node N3. The second signal processor 14 may include a third capacitor C3 and an eleventh transistor T11.

[0181] In an embodiment, a gate electrode of the eleventh transistor T11 may be connected to the third node N3. Therefore, the eleventh transistor T11 may operate in response to the voltage of the third node N3.

[0182] Figure 9 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0183] exist Figure 9 The same reference numerals are used to refer to Figure 1 Components described, and repeated description of such components will be omitted. In addition, in addition to the configuration of the display control driver 700, Figure 9 The display device 1001 may have Figure 1 The configuration of the display device 1000 is substantially equal to or similar to the configuration.

[0184] Reference Figure 9 The display device 1001 may include a display unit 100, a first scan driver 200 (or a first gate driver), a second scan driver 300 (or a second gate driver), an emission driver 400 (or a third gate driver), and a display control driver 700.

[0185] The display control driver 700 may receive an input control signal and an input image signal from an image source such as an external graphics device. The display control driver 700 may generate a first drive control signal SCS1, a second drive control signal SCS2, and a third drive control signal ECS based on the input control signal, and provide the first drive control signal SCS1, the second drive control signal SCS2, and the third drive control signal ECS to the first scan driver 200, the second scan driver 300, and the emission driver 400, respectively. In addition, the display control driver 700 may supply an analog format data signal (data voltage) to the data line D based on the input control signal and the input image signal.

[0186] In other words, the display control driver 700 may include Figure 1 In an embodiment, the display control driver 700 may be mounted on the panel of the display device 1001 in the form of a single driver chip (e.g., a timing controller embedded driver (TED) IC) including the functions of the timing controller 600 and the data driver 500. Therefore, the dead space of the display device 1001 may be reduced.

[0187] However, this is an example, and the configuration of the display control driver 700 is not limited. For example, the display control driver 700 may further include the configuration or function of at least a portion of the first scan driver 200, the second scan driver 300, and the emission driver 400. In addition, the display control driver 700 may supply at least one of the voltage of the first driving power supply VDD, the voltage of the second driving power supply VSS, and the voltage of the initialization power supply Vint to the display unit 100.

[0188] As described above, the emission driver (or gate driver) and the display device including the emission driver (or gate driver) according to embodiments of the present disclosure include a third signal processor in the stage, thereby increasing the falling speed of the emission control signal (or gate signal) and substantially eliminating the falling step. Therefore, it is possible to improve driving reliability and image quality in a high-speed driving method of the display device.

[0189] In addition, by periodically supplying a logic low level to the first node and the third node for refresh during a period in which the emission control signal is output at a logic low level, the logic low level of the emission control signal may be stably output.

[0190] However, the effects of the present disclosure are not limited to those described above, and various extensions can be made within a range that does not depart from the spirit and scope of the present disclosure.

[0191] Although the present disclosure has been described with reference to the embodiments, it will be appreciated by those skilled in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

Claims

1. A transmission driver, wherein: The transmit driver includes: Multiple stages, configured to output emission control signals, Wherein, at least one of the plurality of stages comprises: an input circuit configured to control a voltage of a first node and a voltage of a second node in response to a signal supplied to the first input terminal and a signal supplied to the second input terminal; an output circuit configured to supply a voltage of the first power supply or a voltage of the second power supply as the emission control signal to an output terminal in response to a voltage of the third node and a voltage of the fourth node; a first signal processor connected to a fifth node electrically connecting the second node and the fourth node together and configured to control the voltage of the fourth node based on a signal supplied to a third input terminal and the voltage of the fifth node; a second signal processor configured to control the voltage of the fourth node based on the voltage of the first node; and a third signal processor configured to control the voltage of the third node electrically connected to the first node in response to the signal supplied to the second input terminal and the signal supplied to the third input terminal and the voltage of the first node, Wherein, the third signal processor includes: a first capacitor connected between the sixth node and the third node; a first transistor connected between the second power supply and the sixth node and having a gate electrode connected to the third input terminal; and a second transistor and a third transistor connected in series to the second transistor, the second transistor and the third transistor being connected to the sixth node and the output terminal, respectively, wherein the gate electrode of the second transistor is connected to the first node, a gate electrode of the third transistor connected to the second input terminal, The voltage of the sixth node is determined according to the voltage of the second power supply or the voltage of the output terminal. Wherein, the output circuit includes: A seventh transistor is connected between the first power source and the output terminal and has a gate electrode connected to the third node.

2. The transmit driver according to claim 1, wherein: The third signal processor controls a voltage change of the third node based on the voltage of the second power source or the voltage of the emission control signal.

3. The transmit driver according to claim 1, wherein: The third signal processor controls the voltage of the third node by utilizing coupling of the first capacitor according to a voltage change of the sixth node.

4. The transmit driver according to claim 1, wherein: The emission control signal transitions to a low level in synchronization with voltage drops of the third node and the sixth node.

5. The transmit driver according to claim 1, wherein: The input circuit comprises: a fourth transistor connected between the first input terminal and the first node and having a gate electrode connected to the second input terminal; a fifth transistor connected between the second input terminal and the second node and having a gate electrode connected to the first node; and A sixth transistor is connected between the first power source and the second node and has a gate electrode connected to the second input terminal.

6. The transmit driver according to claim 5, wherein: The fifth transistor includes at least two sub-transistors connected in series with each other, and Each of the at least two sub-transistors includes a gate electrode commonly connected to the first node.

7. The transmit driver according to claim 1, wherein: The output circuit further includes: An eighth transistor is connected between the second power supply and the output terminal and has a gate electrode connected to the fourth node.

8. The transmit driver according to claim 1, wherein: The at least one of the plurality of stages further comprises: A stabilizer is electrically connected between the input circuit and the output circuit and configured to limit a voltage drop at the first node and a voltage drop at the second node.

9. The transmit driver according to claim 8, wherein: The stabilizer comprises: a twelfth transistor connected between the second node and the fifth node and having a gate electrode connected to the first power source and receiving the voltage of the first power source; and A thirteenth transistor is connected between the first node and the third node and has a gate electrode connected to the first power source and receiving the voltage of the first power source.

10. The transmit driver according to claim 8, wherein: The first signal processor comprises: a second capacitor having a first terminal connected to the fifth node; a ninth transistor connected between the second terminal of the second capacitor and the fourth node and having a gate electrode connected to the third input terminal; and A tenth transistor is connected between the second terminal of the second capacitor and the third input terminal and has a gate electrode connected to the fifth node.

11. The transmit driver according to claim 8, wherein: The second signal processor comprises: an eleventh transistor connected between the second power supply and the fourth node and having a gate electrode electrically connected to the first node; and The third capacitor is connected between the second power source and the fourth node.

12. The transmit driver according to claim 8, wherein: The second signal processor comprises: an eleventh transistor connected between the second power supply and the fourth node and having a gate electrode electrically connected to the third node; and The third capacitor is connected between the second power source and the fourth node.

13. The transmit driver according to claim 1, wherein: The first input terminal receives an output signal of a previous stage or a start pulse, the second input terminal receives a first clock signal, and the third input terminal receives a second clock signal obtained by shifting the first clock signal.

14. A display device, wherein: The display device includes: Multiple pixels; a scan driver configured to supply a scan signal to the plurality of pixels through the scan lines; a data driver configured to supply data signals to the plurality of pixels through the data lines; and an emission driver including a plurality of stages to supply emission control signals to the plurality of pixels through emission control lines, Wherein, at least one of the plurality of stages comprises: an input circuit configured to control a voltage of a first node and a voltage of a second node in response to a signal supplied to the first input terminal and a signal supplied to the second input terminal; an output circuit configured to supply a voltage of the first power supply or a voltage of the second power supply as the emission control signal to an output terminal in response to a voltage of the third node and a voltage of the fourth node; a first signal processor connected to a fifth node electrically connecting the second node and the fourth node to each other and configured to control the voltage of the fourth node based on a signal supplied to a third input terminal and the voltage of the fifth node; a second signal processor configured to control the voltage of the fourth node based on the voltage of the third node; and a third signal processor configured to control the voltage of the third node electrically connected to the first node in response to the signal supplied to the second input terminal and the signal supplied to the third input terminal and the voltage of the first node, Wherein, the third signal processor includes: a first capacitor connected between the sixth node and the third node; a first transistor connected between the second power supply and the sixth node and having a gate electrode connected to the third input terminal; and a second transistor and a third transistor connected in series to the second transistor, the second transistor and the third transistor being connected to the sixth node and the output terminal, respectively, wherein the gate electrode of the second transistor is connected to the first node, a gate electrode of the third transistor connected to the second input terminal, The voltage of the sixth node is determined according to the voltage of the second power supply or the voltage of the output terminal. Wherein, the output circuit includes: A seventh transistor is connected between the first power source and the output terminal and has a gate electrode connected to the third node.

15. The display device according to claim 14, wherein Each of the plurality of pixels includes an N-type transistor including an oxide semiconductor.

16. The display device according to claim 15, wherein The scan driver includes a scan stage that outputs an N-type scan signal for controlling the N-type transistor, and The scanning stage has the same configuration as the at least one of the plurality of stages.

17. The display device according to claim 14, wherein: The third signal processor controls a voltage change of the third node based on the voltage of the first power source or the voltage of the emission control signal.

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