Semiconductor device and method of forming the same

Abstract

The method includes: providing a first channel layer and a second channel layer in a p-type region and an n-type region respectively; forming a gate dielectric layer around the first channel layer and the second channel layer; and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in the spaces between the first channel layers and the spaces between the second channel layers. The method further includes: etching the sacrificial layer so that only the portions of the sacrificial layer located in the spaces between the first channel layers and the spaces between the second channel layers are retained; forming a mask that covers the p-type region and exposes the n-type region; removing the sacrificial layer from the n-type region; removing the mask; and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and above the gate dielectric layer and the sacrificial layer in the p-type region. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The electronics industry has an ever-increasing demand for smaller and faster electronic devices that can simultaneously support more and more complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to fabricate low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing the size of the ICs (e.g., the minimum IC component size), thereby increasing production efficiency and reducing associated costs. However, such scaling also increases the complexity of the IC manufacturing process. Thus, achieving continued progress in IC devices and their performance requires similar progress in IC manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control. It has been observed that multi-gate devices can increase gate-channel coupling, reduce OFF-state current, and / or reduce short-channel effects (SCEs). One such multi-gate device is the gate-all-around (GAA) device, which includes a gate structure that can partially or fully extend around a channel region to provide access to the channel region located on at least two sides. GAA devices can enable IC technology to scale down on a large scale, thereby maintaining gate control and reducing SCEs while seamlessly integrating with conventional IC manufacturing processes. As GAA devices continue to scale down, challenges have emerged when fabricating gate structures for GAA devices (including n-metal gates that share a boundary with p-metal gates), and it has been observed that these challenges can degrade the performance of GAA devices and increase GAA processing complexity. Thus, while existing GAA devices and methods for fabricating such devices are generally sufficient for their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, including: providing a structure having a p-type region and an n-type region, the p-type region having a first channel layer and the n-type region having a second channel layer; forming a gate dielectric layer around the first channel layer and around the second channel layer; forming a sacrificial layer around the gate dielectric layer in the p-type region and in the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and merges in the spaces between the second channel layers; etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; forming a first mask covering the p-type region and exposing the n-type region; using the first mask in place to remove the sacrificial layer from the n-type region; removing the first mask; and after removing the first mask, forming an n-type work function metal layer around the gate dielectric layer in the n-type region and above the gate dielectric layer and the sacrificial layer in the p-type region.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, including: providing a structure having a first channel layer in a p-type region and a second channel layer in an n-type region; forming a high-k dielectric layer around the first channel layer and around the second channel layer; forming a sacrificial layer around the high-k dielectric layer in the p-type region and in the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and merges in the spaces between the second channel layers; etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; forming a first mask covering the p-type region and exposing the n-type region; using the first mask in place to remove the sacrificial layer from the n-type region; removing the first mask; after removing the first mask, forming an n-type work function metal layer around the high-k dielectric layer in the n-type region and above the high-k dielectric layer and the sacrificial layer in the p-type region; and forming a passivation layer above the n-type work function metal layer in the n-type region and in the p-type region, wherein the passivation layer merges in the spaces between the second channel layers.

[0006] Some further embodiments of the present application provide a semiconductor device, comprising: a substrate having a p-type region and an n-type region; a first channel layer located above the p-type region and a second channel layer located above the n-type region; a gate dielectric layer located around the first channel layer and around the second channel layer; an n-type work function metal layer located around the gate dielectric layer around the second channel layer, wherein the n-type work function metal layer is not disposed above the gate dielectric layer around the first channel layer; and a p-type work function metal layer located around the gate dielectric layer around the first channel layer and above the n-type work function metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A and Figure 1B are flowcharts of methods for manufacturing multi-gate devices in accordance with various aspects of the present invention.

[0009] Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A and Figure 17A are partial schematic top views of portions of multi-gate devices at various manufacturing stages (such as those associated with the methods in Figure 1A and Figure 1B ).

[0010] Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 9B-1 、 Figure 10B 、 Figure 10B-1 、 Figure 11B 、 Figure 12B 、 Figure 13B 、Figure 14B , Figure 15B , Figure 16B and Figure 17B are partial schematic cross - sectional views of portions of a multi - gate device at various manufacturing stages (such as those associated with the methods in Figure 1A and Figure 1B ).

[0011] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C and Figure 17C are partial schematic cross - sectional views of portions of a multi - gate device at various manufacturing stages (such as those associated with the methods in Figure 1A and Figure 1B ).

[0012] Figure 2D , Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D are partial schematic cross - sectional views of portions of a multi - gate device at various manufacturing stages (such as those associated with the methods in Figure 1A and Figure 1B ).

[0013] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B and Figure 19C are partial schematic views of portions of a multi - gate device according to various aspects of the present invention. Detailed Description

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or characters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Further, in view of the specific technologies disclosed herein, and according to the knowledge of those skilled in the art, unless otherwise stated, when a numerical value or numerical range is described using "about", "approximately", etc., the term is intended to cover values within certain ranges (such as + / - 10%) of the described numerical value. For example, the term "about 5 nm" may cover a size range from 4.5 nm to 5.5 nm.

[0016] The present invention generally relates to integrated circuit devices, and more particularly, to multi-gate devices, such as all-around gate (GAA) devices. More specifically, the present invention relates to patterning a gate work function (WF) metal layer for GAA devices to provide appropriate threshold voltages (Vt) for NMOS and PMOS GAA devices, respectively. For many applications, it is desirable to provide multiple threshold voltages in a process. However, because the spacing between adjacent channel semiconductor layers is narrow, patterning the gate WF metal layer (or gate patterning) is challenging for GAA devices. Considerations for gate patterning include variations in Vt caused by metal diffusion between n-type and p-type work function metals, as well as metal residues resulting from the patterning process. The object of the present invention is to provide a gate patterning method that reduces Vt variations and is compatible with existing CMOS process flows.

[0017] Figure 1A and Figure 1BFIG. 0 is a flowchart of a method 100 for manufacturing a multi-gate device according to various aspects of the present invention. In some embodiments, method 100 manufactures a multi-gate device including p-type GAA transistors and n-type GAA transistors. Method 100 is briefly described below.

[0018] In operation 102, an initial structure is provided. The initial structure includes a first channel semiconductor layer (or first channel layer) suspended between a pair of p-type source / drain (S / D) components in a p-type device region and a second channel semiconductor layer (or second channel layer) suspended between a pair of n-type source / drain (S / D) components in an n-type device region. The first channel layer and the second channel layer are exposed in a gate trench due to the removal of a dummy gate. In operation 104, a gate dielectric layer is formed in the gate trench around the first channel layer and around the second channel layer. The gate dielectric layer may include an interface layer and a high-k dielectric layer. The gate dielectric layer partially fills the gaps between adjacent first channel layers and the gaps between adjacent second channel layers. In operation 106, a sacrificial layer is formed over the gate dielectric layer in the gate trenches in the p-type device region and the n-type device region. The sacrificial layer completely fills any remaining portions of the gaps between adjacent first channel layers and the gaps between adjacent second channel layers. In operation 108, the sacrificial layer is etched such that it is removed except for portions of the sacrificial layer in the gaps between adjacent first channel layers, the gaps between adjacent second channel layers, the gap between the first channel layer and the substrate, and the gap between the second channel layer and the substrate.

[0019] In operation 110, a first mask is formed that covers the structure in the p-type device region and exposes the structure in the n-type device region. In operation 112, using the first mask in place, the sacrificial layer is etched and completely removed from the n-type device region. In operation 114, the first mask is removed.

[0020] In operation 116, an n-type work function metal layer is formed in the gate trenches over the gate dielectric layer in the p-type device region and the n-type device region. The n-type work function metal layer may partially or completely fill the gaps between adjacent second channel layers and the gap between the second channel layer and the substrate in the n-type device region. In the p-type device region, the sacrificial layer still fills the gaps between adjacent first channel layers and the gap between the first channel layer and the substrate. In operation 118, a passivation layer is formed over the n-type work function metal layer in the p-type device region and the n-type device region. The passivation layer is optional. However, having a passivation layer improves the Vt uniformity in the n-type GAA transistor. Since the passivation layer is formed directly over the n-type work function metal layer, it is also referred to as NMG passivation.

[0021] In operation 120, a second mask is formed that covers the structures in the n-type device region and exposes the structures in the p-type device region. With the second mask in place, operation 122 removes the NMG passivation from the p-type device region, operation 124 removes the n-type work function metal layer from the p-type device region, and operation 126 removes the sacrificial layer from the p-type device region. The second mask is then removed in operation 128.

[0022] In operation 130, a p-type work function metal layer is formed in the gate trench over the gate dielectric layer in the p-type device region and over the n-type work function metal layer and the optional NMG passivation layer in the n-type device region. Another optional passivation layer (PMG passivation) may be formed over the p-type work function metal layer in the p-type device region and the n-type device region. In operation 132, a bulk metal layer is formed in the gate trench over the p-type work function layer and the optional PMG passivation in the n-type device region and the p-type device region. A planarization process may be performed on the bulk metal layer, the optional PMG passivation, the p-type work function layer, the optional NMG passivation, the n-type work function layer, and the gate dielectric layer, thereby forming a p-metal gate in the p-type device region and an n-metal gate in the n-type device region. Then, the method 100 enters box 134 to perform further steps, such as forming contacts. Embodiments of the method 100 may form a p-metal gate without any residual n-type work function layer, thereby improving Vt uniformity in p-type GAA transistors. In addition, embodiments of method 100 can form an n-metal gate having an n-type work function layer uniformly distributed around each of the second channel layers, thereby improving Vt uniformity in n-type GAA transistors. The present invention contemplates additional processing. Additional steps can be provided before, during, and after method 100, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method 100. The subsequent discussion illustrates various embodiments of nanofilm-based integrated circuit devices that can be manufactured according to method 100.

[0023] Figures 2A to 17A , Figures 2B to 17B , Figures 2C to 17C and Figures 2D to 17D According to various aspects of the present invention, at various stages of manufacture (such as Figure 1A and Figure 1B 100) are partially or completely schematic diagrams of a multi-gate (or multi-gate) device 200. Specifically, Figures 2A to 17A is a top view of the multi-gate device 200 in the XY plane; Figures 2B to 17B are respectively along Figures 2A to 17A A schematic cross-sectional view of the multi-gate device 200 in the XZ plane along line BB′ of FIG. Figures 2C to 17C are respectively along Figures 2A to 17ASchematic cross-sectional view of a multi-gate device 200 in the Y-Z plane of line C-C'; and Figures 2D to 17D is a schematic cross-sectional view of the multi-gate device 200 in the Y-Z plane along line D-D' respectively. Figures 2A to 17A

[0024] The multi-gate device 200 may be included in a microprocessor, a memory, and / or other IC devices. In some embodiments, the multi-gate device 200 is part of an IC chip, a system-on-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide semiconductor field-effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the multi-gate device 200 is included in a non-volatile memory such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof. For clarity, Figures 2A to 17A 、 Figures 2B to 17B 、 Figures 2C to 17C and Figures 2D to 17D have been simplified to better understand the inventive concept of the present invention. Additional components may be added to the multi-gate device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200. The fabrication of the device 200 is described below in connection with embodiments of the method 100.

[0025] In operation 102, the method 100 ( Figure 1A ) provides an initial structure of the device 200. Go to Figures 2A to 2D ​, device 200 includes a substrate (e.g., a wafer) 202. In the described embodiments, substrate 202 includes silicon. Optionally or additionally, substrate 202 includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Optionally, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods. Substrate 202 can include various doped regions, depending on the design requirements of device 200. In the described embodiments, substrate 202 includes a p-type doped region 204A (e.g., a p-well), which can be configured for n-type GAA transistors, and an n-type doped region 204B (e.g., an n-well), which can be configured for p-type GAA transistors. N-type doped regions (such as n-well 204B) are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. P-type doped regions (such as p-well 204A) are doped with p-type dopants, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, substrate 202 includes a doped region formed by a combination of p-type and n-type dopants. Various doped regions can be formed directly on and / or in substrate 202, e.g., to provide a p-well structure, an n-well structure, a dual-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be implemented to form the various doped regions. Device 200 includes a region 240-1 for forming an n-type GAA device and a region 240-2 for forming a p-type GAA device. Thus, region 240-1 is also referred to as the n-type device region 240-1, and region 240-2 is also referred to as the p-type device region 240-2.

[0026] Device 200 also includes an n-type source / drain component 260A located in the n-type device region 240-1 and a p-type source / drain component 260B located in the p-type device region 240-2. Each of the source / drain components 260A and 260B can be formed by epitaxially growing a semiconductor material (e.g., Si, SiGe) to fill a trench in device 200, for example, using a CVD deposition technique (e.g., vapor phase epitaxy), molecular beam epitaxy, other suitable epitaxial growth processes, or a combination thereof. The source / drain components 260A and 260B are doped with a suitable n-type dopant and / or p-type dopant. For example, the source / drain component 260A can include silicon and be doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof; and the source / drain component 260B can include silicon germanium or germanium and be doped with boron, other p-type dopants, or a combination thereof.

[0027] Device 200 also includes a stack of semiconductor layers 215 suspended between a pair of source / drain components 260A in the n-type device region 240-1 and another stack of semiconductor layers 215 suspended between a pair of source / drain components 260B in the p-type device region 240-2. The stack of semiconductor layers 215 located in the n-type device region 240-1 serves as a transistor channel for an n-type GAA device, and the stack of semiconductor layers 215 located in the p-type device region 240-2 serves as a transistor channel for a p-type GAA device. Thus, the semiconductor layer 215 is also referred to as the channel layer 215. The channel layer 215 is exposed in the gate trench 275 created by removing the dummy gate therein. The channel layer 215 can include single-crystalline silicon. Optionally, the channel layer 215 can include germanium, silicon germanium, or another suitable semiconductor material. Initially, the channel layer 215 is formed as part of a stack of semiconductor layers (including the channel layer 215 and another semiconductor layer of a different material). One or more lithography processes, including a double patterning or multiple patterning process, are used to pattern the stack of semiconductor layers into a fin shape protruding above the substrate 202. After forming the gate trench 275, the stack of semiconductor layers is selectively etched to remove the other semiconductor layers, leaving the channel layer 215 suspended above the substrate 202 and located between the corresponding source / drain components 260A, 260B.

[0028] The channel layers 215 located in the n-type device region 240-1 are separated from each other and from the substrate 202 by gaps 277A. The channel layers 215 located in the p-type device region 240-2 are separated from each other and from the substrate 202 by gaps 277B. A spacing s1 is defined between the channel layers 215 in the n-type gate region 240-1 along the z direction, and a spacing s2 is defined between the channel layers 215 in the p-type gate region 240-2 along the z direction. The spacing s1 and the spacing s2 correspond to the widths of the gaps 277A and 277B, respectively. In the described embodiment, the spacing s1 is approximately equal to s2, but the present invention contemplates embodiments where the spacing s1 is different from the spacing s2. Additionally, the channel layers 215 located in the n-type gate region 240-1 have a length l1 along the x direction and a width w1 along the y direction, and the channel layers 215 located in the p-type gate region 240-2 have a length l2 along the y direction and a width w2 along the x direction. In the described embodiment, the length l1 is approximately equal to the length l2, and the width w1 is approximately equal to the width w2, but the present invention contemplates embodiments where the length l1 is different from the length l2 and / or the width w1 is different from the width w2. In some embodiments, the length l1 and / or the length l2 is from about 10 nm to about 50 nm. In some embodiments, the width w1 and / or the width w2 is from about 4 nm to about 10 nm. In some embodiments, each channel layer 215 has nanoscale dimensions and can be referred to as a "nanowire", which generally refers to a channel layer suspended in such a way as to allow a metal gate to physically contact at least two sides of the channel layer, and in a GAA transistor, would allow a metal gate to physically contact at least four sides of the channel layer (i.e., surrounding the channel layer). In such an embodiment, a vertical stack of suspended channel layers can be referred to as a nanostructure. In some embodiments, the channel layer 215 can be cylindrical (e.g., nanowire), rectangular (e.g., nanorod), sheet-shaped (e.g., nanosheet), etc., or have other suitable shapes.

[0029] The device 200 further includes isolation components 230 to isolate the respective regions, such as the respective doped regions 204A and 204B. The isolation components 230 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. The isolation components 230 can include different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure. The isolation components 230 can include a multi-layer insulating material.

[0030] Device 200 also includes gate spacers 247 adjacent to source / drain components 260A, 260B. The gate spacers 247 may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxynitridecarbonitride (SiOCN)). In some embodiments, the gate spacers 247 include a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. Device 200 also includes internal spacers 255 vertically located between adjacent channel layers 215 and adjacent to source / drain components 260A, 260B. The internal spacers 255 may include a dielectric material, including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride). In some embodiments, the internal spacers 255 include a low-k dielectric material. The gate spacers 247 and the internal spacers 255 are formed by deposition (e.g., CVD, PVD, ALD, etc.) and etching processes (e.g., dry etching). Gate trenches 275 are provided between opposing gate spacers 247 and opposing internal spacers 255.

[0031] Device 200 also includes an interlayer dielectric (ILD) layer 270 located above isolation components 230, epitaxial source / drain components 260A, 260B, and gate spacers 247. The ILD layer 270 may be formed by a deposition process such as CVD, flowable CVD (FCVD), or other suitable methods. The FCVD process may include depositing a flowable material (such as a liquid compound) above device 200 and converting the flowable material to a solid material by thermal annealing and / or ultraviolet radiation treatment. The ILD layer 270 includes a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, low-k dielectric materials, other suitable dielectric materials, or combinations thereof. The ILD layer 270 may include a multi-layer structure having multiple dielectric materials. In some embodiments, a contact etch stop layer (CESL) (not shown) is provided between the ILD layer 270 and isolation components 230, epitaxial source / drain components 260A, 260B, and gate spacers 247. The CESL includes a dielectric material different from the ILD layer 270. For example, where the ILD layer 270 includes a low-k dielectric material, the CESL includes silicon and nitrogen, such as silicon nitride or silicon oxynitride.

[0032] In operation 104, method 100 ( Figure 1A ) forms a gate dielectric layer 279 around channel layer 215. Go to Figures 3A to 3D, in the described embodiment, the gate dielectric layer 279 includes an interface layer 280 located above the channel layer 215 and a high-k dielectric layer 282 located above the interface layer 280. To further describe the embodiment, the interface layer 280 and the high-k dielectric layer 282 partially fill the gap 277A and partially fill the gap 277B. In some embodiments, the interface layer 280 and / or the high-k dielectric layer 282 are also disposed on the substrate 202, the isolation member 230, and / or the gate spacer 247. The interface layer 280 includes a dielectric material, such as SiO 2 , HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The high-k dielectric layer 282 includes a high-k dielectric material, such as HfO 2 , HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO 2 , ZrSiO 2 , AlO, AlSiO, Al 2 O 3 , TiO, TiO 2 , LaO, LaSiOTa 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba, Sr)TiO 3 (BST), Si 3 N 4 , hafnium oxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloy, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials having a high dielectric constant. For example, the dielectric constant is greater than the dielectric constant of silicon oxide (k≈3.9). The interface layer 280 is formed by any process described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. In some embodiments, the interface layer 280 has a thickness of about 0.5 nm to about 3 nm. The high-k dielectric layer 282 is formed by any process described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. In some embodiments, the high-k dielectric layer 282 has a thickness of about 1 nm to about 2 nm. In an alternative embodiment, the gate dielectric layer 279 may include additional dielectric layers, or the interface layer 280 may be omitted.

[0033] In operation 106, method 100 ( Figure 1A ) forms a sacrificial layer (or pseudo hard mask) 284 over the gate dielectric layer 279. Go to Figures 4A to 4D , in the described embodiment, the sacrificial layer 284 partially fills the gate trench 275 and wraps (surrounds) the channel layer 215 located in the n-type device region 240-1 and the p-type device region 240-2. The sacrificial layer 284 can be deposited on the gate dielectric layer 279 by any process described herein (such as ALD, CVD, PVD, other suitable processes, or combinations thereof). The thickness of the sacrificial layer 284 is configured to fill any remaining portions of the gaps 277A between adjacent channel layers 215 located in the n-type device region 240-1 and the gaps 277B between adjacent channel layers 215 located in the p-type device region 240-2, without filling the gate trench 275 (i.e., any portion of the gaps 277A, 277B is not filled by the gate dielectric layer 279). In some embodiments, the thickness of the sacrificial layer 284 is from about 0.5 nm to about 5 nm.

[0034] The sacrificial layer 284 includes a material different from the high-k dielectric material to achieve an etch selectivity between the sacrificial layer 284 and the high-k dielectric layer 282 during an etching process, such that the high-k dielectric layer 282 can be etched minimally (to not at all) while selectively etching the sacrificial layer 284. The material of the sacrificial layer 284 is also different from the material of the n-type work function metal layer (such as Figure 9B the n-type work function metal layer 340 therein) to achieve an etch selectivity between the sacrificial layer 284 and the n-type work function layer during an etching process, such that the n-type work function layer can be etched minimally (to not at all) while selectively etching the sacrificial layer 284, and vice versa. In some embodiments, the material of the sacrificial layer 284 is also different from the material of the passivation layer (e.g., Figure 10B the passivation layer 342 located above the n-type work function metal layer 340 therein) located above the n-type work function metal layer to achieve an etch selectivity between the sacrificial layer 284 and the passivation layer during an etching process, such that the passivation layer can be etched minimally (to not at all) while selectively etching the sacrificial layer 284, and vice versa. The material of the sacrificial layer 284 can also be different from the low-k dielectric material to achieve an etch selectivity between the sacrificial layer 284 and the low-k dielectric material (such as the low-k dielectric material of the ILD layer 270) during an etching process, such that the ILD layer 270 can be etched minimally (to not at all) while selectively etching the sacrificial layer 284. Additionally, the material of the sacrificial layer 284 is designed to be easily etched by a wet etchant. In some embodiments, the sacrificial layer 284 includes metal and oxygen (and can thus be referred to as a metal oxide layer), such as aluminum and oxygen (e.g., AlO x or aluminum oxide (Al 2 O3 ). In some embodiments, the sacrificial layer 284 includes titanium nitride (TiN) or silicon oxycarbide (SiOC). The present disclosure contemplates the sacrificial layer 284 including other semiconductor materials and / or other dielectric materials that can provide the desired etch selectivity as described herein.

[0035] In operation 108, method 100 ( Figure 1A ) etches and partially removes the sacrificial layer 284. Turning to Figures 5A to 5D , the sacrificial layer 284 is partially removed, and the remaining portion of the sacrificial layer 284 becomes a sacrificial (dummy) component 284' located between the channel layers 215 in the n-type device region 240-1 and the p-type device region 240-2 and between the channel layer 215 and the substrate 202. For convenience, the sacrificial (dummy) component 284' is sometimes referred to as the sacrificial (dummy) layer 284. In some embodiments, the etching process is a wet etching process that uses an etching solution having a high etch selectivity with respect to the high-k dielectric layer 282 for the sacrificial layer 284. In some embodiments, the etching solution exhibits an etch selectivity of about 10 to about 100 (i.e., the ratio of the etch rate of the sacrificial layer 284 to the etching solution to the etch rate of the high-k dielectric layer 282 to the etching solution). In some embodiments, the etch selectivity is greater than or equal to 100.

[0036] In some embodiments, the wet etching process in operation 108 implements an NH 4 OH-based wet etching solution. In some embodiments, the wet etching process in operation 108 implements a digital etching process including self-limiting oxidation followed by an oxide removal process. For example, self-limiting oxidation can be implemented with HPM (a mixture of HCl, H 2 O 2 and H 2 O), H 2 O 2 or ozonated deionized (DI) water (DI-O 3 ); and the oxide removal process can use HCl, NH 4OH, dilute HF, or other suitable chemicals. Control the parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) to remove the sacrificial layer 284 from the sidewalls of the channel layer 215 and above the isolation component 230 while minimizing (to not) etching the high-k dielectric layer 282. For example, adjust the etching time (i.e., how long the sacrificial layer 284 is exposed to the ammonia-based wet etching solution) to remove the sacrificial layer 284 along the sidewalls of the channel layer 215 and along the very top of the high-k dielectric layer 282 (i.e., the portion of the high-k dielectric layer 282 disposed above the top surface of the topmost channel layer 215). To further describe the example, further adjust the etching time to achieve lateral etching of the sacrificial layer 284 (e.g., in the x direction and / or y direction) until the width of the sacrificial component 284' (here, in the x direction) is less than the sum of the width of the channel layer 215 and the thickness of the gate dielectric (here, the sum of the thickness of the interface layer 282 and the thickness of the high-k dielectric layer 284). In some embodiments, the width of the sacrificial component 284' is substantially equal to the width of the channel layer 215. The sidewalls of the sacrificial component 284' are thus recessed by a distance d in the x direction relative to the sidewalls of the high-k dielectric layer 282. In some embodiments, the distance d is greater than 0, e.g., from about 0.5 nm to about 5 nm. In some embodiments, the sidewalls are not recessed in the x direction relative to the sidewalls of the high-k dielectric layer 282, such that the distance d is equal to 0.

[0037] Then, method 100 ( Figure 1A ) proceeds to operations 110, 112, and 114 to completely remove the sacrificial layer 284 (i.e., the sacrificial component 284') from the n-type device region 240-1 while retaining the sacrificial component 284' in the p-type device region 240-2.

[0038] Go to Figures 6A to 6D , in operation 110, method 100 ( Figure 1A)Form a mask (or etch mask) 290 having one or more openings 292. The mask 290 covers the p-type GAA transistor region including the p-type device region 240-2 and exposes the n-type GAA transistor region including the n-type device region 240-1 through the openings 292. The mask 290 includes a material different from that of the sacrificial component 284' to achieve etch selectivity during the removal of the sacrificial component 284'. For example, the mask 290 may include a resist material (and thus may be referred to as a patterned resist layer and / or a patterned photoresist layer). In some embodiments, the mask 290 has a multi-layer structure, such as a resist layer disposed above an anti-reflection coating (ARC) layer. The present invention contemplates other materials for the mask 290 as long as etch selectivity is achieved during the removal of the sacrificial component 284'. In some embodiments, operation 110 includes a lithography process, including forming a resist layer (e.g., by spin coating) above the device 200, implementing a pre-exposure bake process, implementing an exposure process using a photomask, implementing a post-exposure bake process, and developing the exposed resist layer in a developer solution. After development, the patterned resist layer (e.g., the patterned mask 290) includes a resist pattern corresponding to the photomask, wherein the patterned resist layer covers the p-type GAA transistor region including the p-type device region 240-2 and exposes the n-type GAA transistor region including the n-type device region 240-1. Optionally, the exposure process may be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or a combination thereof.

[0039] Go to Figures 7A to 7D , in operation 112, method 100 ( Figure 1A ) etches the sacrificial component 284' located in the n-type device region 240-1 through the opening 292 of the mask 290. The sacrificial component 284' in the p-type device region 240-2 is protected by the mask 290 from the etching process. The etching process completely removes the sacrificial component 284' between the channel layers 215 in the n-type device region 240-1 and between the channel layer 215 and the substrate 202, thereby exposing the gate dielectric layer 279 (including the high-k dielectric layer 282) in the n-type device region 240-1. The etching process substantially re-obtains or re-forms a portion of the gap 277A in the n-type device region 240-1. In some embodiments, the etching process is a wet etching process that uses an etching solution having a high etch selectivity with respect to the high-k dielectric layer 282 for the sacrificial component 284'. In some embodiments, the etching solution exhibits an etch selectivity of about 10 to about 100. In some embodiments, the etch selectivity is greater than or equal to 100. In some embodiments, the wet etching process is implemented based on NH 4A wet etching solution for OH. Control the parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) to ensure complete removal of the sacrificial component 284' in the n-type device region 240-1. For example, adjust the etching time (i.e., how long the sacrificial component 284' is exposed to the ammonia-based wet etching solution) to completely remove the sacrificial component 284' while minimally (to not) etching the high-k dielectric layer 282. In some embodiments, the etching solution has an etching selectivity for the sacrificial component 284' relative to the mask 290. In some embodiments, the etching process partially etches the mask 290.

[0040] After the etching process, for example, in operation 114 of method 100, the mask 290 is removed by a resist stripping process or other suitable process ( Figure 1A ). Go to Figures 8A to 8D , the sacrificial component 284' remains between the channel layers 215 in the p-type device region 240-2 and between the channel layer 215 and the substrate 202, and is not retained in the n-type device region 240-1.

[0041] Go to Figures 9A to 9D , in operation 116, method 100 ( Figure 1A ) forms an n-type work function metal layer 340 over the gate dielectric layer 279 (including layers 280 and 282 in this embodiment) and over the sacrificial component 284'. Specifically, the n-type work function metal layer 340 wraps (surrounds) each channel layer 215 in the n-type device region 240-1. In the p-type device region 240-2, due to the sacrificial component 284', the n-type work function metal layer 340 does not wrap any channel layer 215. Additionally, in Figure 9B and Figure 9C the described embodiment, the thickness of the n-type work function metal layer 340 is designed such that it does not completely fill the gap 277A between adjacent channel layers 215 in the n-type device region 240-1 and between the channel layer 215 and the substrate 202. This allows each channel layer 215 in the n-type device region 240-1 to be surrounded by the n-type work function metal layer 340 of the same thickness, thereby improving the uniformity of Vt between the channel layers 215. In Figure 9B-1In the described alternative embodiments, the thickness of the n-type work function metal layer 340 is designed such that it completely fills the gaps 277A between adjacent channel layers 215 in the n-type device region 240-1 and between the channel layer 215 and the substrate 202. In some embodiments, the n-type work function metal layer 340 has a thickness of about 1 nm to about 5 nm, such as about 2 nm to about 4 nm. The n-type work function metal layer 340 includes any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function materials, or combinations thereof. In the described embodiments, the n-type work function metal layer 340 includes aluminum. For example, the n-type work function metal layer 340 includes TiAl, TiAlC, TaAlC, TiSiAlC, or a bilayer of TiAlC and TiN. The n-type work function metal layer 340 can be formed using another suitable deposition process (such as CVD, PVD, ALD, other deposition processes, or combinations thereof).

[0042] Turning to Figures 10A to 10D , in operation 118, method 100 ( Figure 1A ) forms a passivation layer 342 over the n-type work function metal layer 340. Specifically, in Figure 10B the described embodiments, the passivation layer 342 wraps (surrounds) each of the channel layers 215 and fills the remaining spaces in the gaps 277A between adjacent channel layers 215 in the n-type device region 240-1 and between the channel layer 215 and the substrate 202. The material of the passivation layer 342 is selected to protect the n-type work function metal layer 340, for example, by preventing materials from diffusing into the n-type work function metal layer 340. In addition, it also prevents materials (especially aluminum) from diffusing out of the n-type work function metal layer 340. This stabilizes the n-type work function metal layer 340 and ensures Vt uniformity between the channel layers 215 located in the n-type device region 240-1. Further, the material of the passivation layer 342 has a high etch selectivity for the sacrificial component 284' as previously discussed. In some embodiments, the passivation layer 342 includes a semiconductor material, a dielectric material, a bilayer of a semiconductor material and a dielectric material, or other suitable materials. For example, the passivation layer 342 can include a silicon layer (such as polysilicon or amorphous silicon), a silicon dioxide layer, a bilayer having a silicon layer and a silicon dioxide layer, an aluminum oxide layer, or other suitable materials. The passivation layer 342 is deposited on the sidewalls of the gate trench 275 and over the n-type work function metal layer 340 with a substantially uniform thickness. The passivation layer 342 can have a thickness of about 1 nm to 2 nm. In an embodiment, the passivation layer 342 and the n-type work function metal layer 340 are formed in-situ (i.e., in the same process chamber or in the same cluster tool).

[0043] In an alternative embodiment where the n-type work function metal layer 340 completely fills the gaps 277A between adjacent channel layers 215 in the n-type device region 240-1 and between the channel layer 215 and the substrate 202, a passivation layer 342 is deposited over the n-type work function metal layer 340 and does not wrap each of the channel layers 215, as Figure 10B-1 shown. However, compared to the embodiment of Figure 10B-1 , having a passivation layer 342 that wraps each of the channel layers 215 located in the n-type device region 240-1 (e.g., Figure 10B ) generally improves the Vt uniformity between the channel layers 215 (substantially, each channel layer 215 turns on / off with approximately the same threshold voltage). In some embodiments, method 100 omits operation 118 and does not form a passivation layer 342 over the n-type work function metal layer 340 (e.g., as Figure 18D shown). However, compared to the embodiment that omits the passivation layer 342, having the passivation layer 342 generally improves the Vt uniformity between the channel layers 215 located in the n-type device region 240-1.

[0044] Then, method 100 ( Figure 1A ) proceeds to operations 120, 122, 124, 126, and 128 to remove the passivation layer 342, the n-type work function metal layer 340, and the sacrificial component 284' from the p-type device region 240-2.

[0045] Turning to Figures 11A to 11D , in operation 120, method 100 ( Figure 1B)Form a mask (or etch mask) 345 having one or more openings 346. The mask 345 covers the n-type GAA transistor region including the n-type device region 240-1 and exposes the p-type GAA transistor region including the p-type device region 240-2 through the opening 346. The mask 345 includes a material different from the corresponding materials of the sacrificial component 284’, the passivation layer 342, and the n-type work function metal layer 340 to achieve etch selectivity during the removal of the layers 284’, 342, and 340. For example, the mask 345 may include a resist material (and thus may be referred to as a patterned resist layer and / or a patterned photoresist layer). In some embodiments, the mask 345 has a multi-layer structure, such as a resist layer disposed above an anti-reflection coating (ARC) layer. The present invention contemplates other materials for the mask 345 as long as etch selectivity is achieved during the removal of the layers 284’, 340, and 342 as discussed above. In some embodiments, operation 120 includes a lithography process, including forming a resist layer (e.g., by spin coating) over the device 200, performing a pre-exposure bake process, performing an exposure process using a photomask, performing a post-exposure bake process, and developing the exposed resist layer in a developer solution. After development, the patterned resist layer (e.g., the patterned mask 345) includes a resist pattern corresponding to the photomask, where the patterned resist layer covers the n-type GAA transistor region including the n-type device region 240-1 and exposes the p-type GAA transistor region including the p-type device region 240-2. Optionally, the exposure process may be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or a combination thereof.

[0046] Go to Figures 12A to 12D , in operation 122, method 100 ( Figure 1B ) uses one or more etching processes to remove the passivation layer 342 from the p-type device region through the opening 346. For example, operation 122 may implement a dry etching process, a wet etching process, or a combination thereof. The etchant is adjusted to remove the material of the passivation layer 342 but does not (or does not significantly) etch the mask 345.

[0047] Go to Figures 13A to 13D , in operation 124, method 100 ( Figure 1B ) uses one or more etching processes to remove the n-type work function metal layer 340 from the p-type device region through the opening 346. For example, operation 124 may implement a dry etching process, a wet etching process, or a combination thereof. The etchant is adjusted to remove the material of the n-type work function metal layer 340 but does not (or does not significantly) etch the mask 345.

[0048] For operations 122 and 124, the dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF6 , CH 2 F 2 , CHF 3 and / or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl3, CCl 4 and / or BCl 3 ), bromine-containing gas (e.g., HBr and / or CHBR 3 ), iodine-containing gas, other suitable gas and / or plasma and / or their combination. In addition, the wet etching process may include etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ), and / or acetic acid (CH 3 COOH); or other suitable wet etchant.

[0049] In some embodiments, operations 122 and 124 may be combined into one etching process for etching the passivation layer 342 and the n-type work function metal layer 340. In addition, operations 122 and 124 are controlled such that there is minimal or no lateral over-etching of the passivation layer 342 and the n-type work function metal layer 340 located under the mask 345. Due to operations 122 and 124, the gate dielectric layer 279 (including the high-k dielectric layer 282 and the interface layer 280) and the sacrificial member 284' are exposed in the gate trench 275 and through the opening 346 in the p-type device region 240-2.

[0050] Go to Figures 14A to 14D , in operation 126, method 100 ( Figure 1B ) removes the sacrificial member 284' from the p-type device region 240-2 through the opening 346. Operation 126 may use the same etching process as the etching process used in operation 112. Optionally, operation 126 may use an etching process different from the etching process used in operation 112. The etching process completely removes the sacrificial member 284' between the channel layers 215 in the p-type device region 240-2 and between the channel layer 215 and the substrate 202, thereby exposing the gate dielectric layer 279 (which includes the high-k dielectric layer 282) in the p-type device region 240-2. The etching process substantially re-obtains or re-forms a portion of the gap 277B in the p-type device region 240-2. As Figure 14B and Figure 14DAs described, the gap 277B reappears between adjacent channel layers 215 in the p-type device region 240-2 and between the channel layer 215 and the substrate 202. In some embodiments, the etching process is a wet etching process using an etching solution that has a high etching selectivity with respect to the high-k dielectric layer 282 for the sacrificial component 284'. In some embodiments, the etching solution exhibits an etching selectivity of about 10 to about 100. In some embodiments, the etching selectivity is greater than or equal to 100. In some embodiments, the wet etching process implements a wet etching solution based on NH 4 OH. The parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or a combination thereof) are controlled to ensure complete removal of the sacrificial component 284' in the p-type device region 240-2. For example, the etching time (i.e., how long the sacrificial component 284' is exposed to the ammonia-based wet etching solution) is adjusted to completely remove the sacrificial component 284' while minimally (to not) etching the high-k dielectric layer 282. In some embodiments, the etching solution also has an etching selectivity with respect to the mask 345 for the sacrificial component 284'.

[0051] In addition, operation 126 is controlled such that there is minimal or no lateral over-etching of the passivation layer 342 and the n-type work function metal layer 340 located under the mask 345. In some embodiments, the lateral grooves of the passivation layer 342 and the n-type work function metal layer 340 located under the mask 345 are 5 nm or less. In any case, the ends of the passivation layer 342 and the n-type work function metal layer 340 still remain directly above the top of the isolation component 230. Compared with the method in which the gap 277B is filled with an n-type work function metal layer instead of the sacrificial component 284', this embodiment can reduce the lateral grooves of the passivation layer 342 and the n-type work function metal layer 340 located under the mask 345 because the work function metal layer is generally more difficult to etch than the material of the sacrificial component 284'. In addition, this embodiment does not leave any residue of the n-type work function metal layer in the gap 277B. The residue of the n-type work function metal layer usually contains aluminum and can diffuse into the p-type work function metal layer subsequently deposited in the gap 277B. The absence of such residues improves the Vt uniformity in the p-type GAA device.

[0052] After the etching process, the mask 345 is removed, for example, by a resist stripping process or other suitable process in operation 128 of method 100 ( Figure 1B ). Proceed to Figures 15A to 15D, in the p-type device region 240-2, the gate dielectric layer 279 is exposed in the gate trench 275, and the gap 277B appears between adjacent channel layers 215 and between the channel layer 215 and the substrate 202. In the n-type device region 240-1, the n-type work function metal layer 340 and the passivation layer 342 are exposed in the gate trench 275. In addition, the n-type work function metal layer 340 and the passivation layer 342 wrap (surround) the channel layer 215 and fill the spaces between adjacent channel layers 215 and between the channel 215 and the substrate 202.

[0053] Go to Figures 16A to 16D , in operation 130, method 100 ( Figure 1B ) forms a p-type work function metal layer 300 over the gate dielectric layer 279 (including layers 280 and 282 in this embodiment) in the p-type device region 240-2 and over the n-type work function metal layer 340 and the passivation layer 342 in the n-type device region 240-1. Specifically, the p-type work function metal layer 300 wraps (surrounds) each channel layer 215 located in the p-type device region 240-2 and fills any remaining portion of the gap 277B between adjacent channel layers 215 and between the channel layer 215 and the substrate 202. In the n-type device region 240-1, since the n-type work function metal layer 340 and the passivation layer 342 have filled the gap 277A, the p-type work function metal layer 300 is deposited only on the bottom and sidewall surfaces of the gate trench 275 and on the top and side surfaces of the n-type work function metal layer 340 and the passivation layer 342. In some embodiments, the p-type work function metal layer 300 has a thickness of about 2 nm to about 5 nm. The p-type work function metal layer 300 includes any suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , other p-type work function materials or combinations thereof. In the described embodiment, the p-type work function metal layer 300 includes titanium and nitrogen, such as TiN. Any suitable deposition process (such as CVD, PVD, ALD, or combinations thereof) can be used to form the p-type work function metal layer 300. Figure 16B A step 301 of the p-type work function metal layer 300 above the isolation component 230 at the boundary between the n-type and p-type device regions is shown. The height of the step 301 (the distance from the upper surface of the step 301 in the n-type device region 240-1 to the upper surface of the step 301 in the p-type device region 240-2) is approximately equal to the thickness of the n-type work function metal layer 340 (about 1 nm to 5 nm, such as from 2 nm to 4 nm) and the thickness of the passivation layer 342 (about 1 nm to 2 nm).

[0054] Go to Figures 17A to 17D , in operation 132, method 100( Figure 1B ) forms a bulk metal layer 350 over the p-type work function layer 300 in the n-type device region 240-1 and the p-type device region 240-2. For example, a CVD process or a PVD process deposits the bulk metal layer 350 such that it fills any remaining portions of the gate trenches 275. The bulk metal layer 350 includes a suitable conductive material such as Al, W, and / or Cu. The bulk metal layer 350 may additionally or jointly include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some embodiments, prior to forming the bulk metal layer 350, a passivation layer (or barrier layer) 352 (e.g., as shown in Figure 18B ) is optionally formed (e.g., by ALD) over the p-type work function layer 300 such that the bulk metal layer 350 is disposed on the barrier layer. The passivation layer 352 may have a substantially uniform thickness and includes a material that blocks and / or reduces diffusion between the gate layers such as the bulk metal layer 350 and the p-type work function metal layer 300. In some embodiments, operation 132 is omitted and the bulk metal layer 350 is not deposited and is omitted in the device 200.

[0055] After depositing the bulk metal layer 350, a planarization process may then be implemented to remove excess gate material from the device 200. For example, a CMP process is implemented until the top surface of the ILD layer 270 is exposed. In the described embodiments, thus, the device 200 is configured to have two different metal gate portions (an n-metal gate 360A in the n-type device region 240-1 and a p-metal gate 360B in the p-type device region 240-2). The top surfaces of the gates 360A and 360B are substantially planar with the top surface of the ILD layer 270. The n-metal gate 360A includes a gate dielectric layer 279 (e.g., including an interface layer 280 and a high-k dielectric layer 282) and a gate electrode (e.g., including an n-type work function metal layer 340, a passivation layer 342, a p-type work function metal layer 300, and a bulk metal layer 350). The p-metal gate 360B includes a gate dielectric layer 279 (e.g., including an interface layer 280 and a high-k dielectric layer 282) and a gate electrode (e.g., including a p-type work function metal layer 300 and a bulk metal layer 350). Thus, the device 200 includes: an n-type GAA transistor having a metal gate 360A that wraps around a corresponding channel layer 215 and is disposed between corresponding epitaxial source / drain components 260A; and a p-type GAA transistor having a metal gate 360B that wraps around a corresponding channel layer 215 and is disposed between corresponding epitaxial source / drain components 260B.

[0056] Figures 18A to 18D Shows various embodiments of the device 200 along the Figure 17A B-B' line.Figure 18A Also shown are the respective layers 215, 280, 282, 340, 342, and 300 located in the n-type device region 240-1 and the p-type device region 240-2, as discussed above. For example, with reference to Figure 16B . Figure 18B Shown is Figure 18A the same structure as shown in, and also shown are a bulk metal layer 350 and a passivation layer 352 located between the p-type work function metal layer 300 and the bulk metal layer 350. The passivation layer 352 may include the same or similar material as the passivation layer 342. In Figure 18B the described embodiment, the passivation layer 352 is formed to wrap (or surround) each channel layer 215 in the p-type device region 240-2. In an alternative embodiment (not shown), the p-type work function metal layer 300 completely fills any gaps between adjacent channel layers 215 and between the channel layer 215 and the substrate 202 (such as Figure 16B shown in), and the passivation layer 352 is formed above the p-type work function metal layer 300 but does not wrap the channel layer 215.

[0057] Figure 18C Shown is an embodiment in which the n-type work function metal layer 340 completely fills any gaps between adjacent channel layers 215 in the n-type device region 240-1 and between the channel layer 215 and the substrate 202. Accordingly, the passivation layer 342 is formed above the n-type work function metal layer 340 but does not wrap the channel layer 215. Figure 18D Shown is an embodiment in which the passivation layer 342 is omitted in the device 200. Figure 18D Other aspects of Figure 18C are the same as those of

[0058] Figures 19A to 19B More details are shown of various embodiments of the device 200 along the Figure 17A C-C' line of Figure 19A is Figure 17C a partial view of the embodiment shown in. With reference to Figure 19A , the channel layer 215 is suspended between a pair of source / drain components 260A and is connected to the pair of source / drain components 260A. The internal spacers 255 are vertically disposed between the channel layers 215 and are laterally disposed between the source / drain components 260A and the n-metal gate 360A (including the interface layer 280, the high-k dielectric layer 282, the n-type work function metal layer 340, and the passivation layer 342). The layers 280, 282, 340, and 342 together fill the space between the two channel layers 215. In Figure 19B the described embodiment, the passivation layer 342 is omitted, and the layers 280, 282, and 340 together fill the space between the two channel layers 215. Figure 19B The embodiment shown corresponds to Figure 18CThe embodiment shown in Figure 19C shows in more detail an embodiment of device 200 along Figure 17A the D-D' line. Figure 19C is Figure 17D a partial view of the embodiment shown in Figure 19C . Referring to , the channel layer 215 is suspended between a pair of source / drain components 260B and is connected to the pair of source / drain components 260B. The internal spacers 255 are vertically disposed between the channel layers 215 and are laterally disposed between the source / drain components 260B and the p-metal gate 360B (including the interface layer 280, the high-k dielectric layer 282, and the p-type work function metal layer 300). The layers 280, 282, and 300 together fill the space between the two channel layers 215.

[0059] Method 100 ( Figure 1B ) may implement further manufacturing steps in operation 134. For example, various contacts may be formed to facilitate the operation of the n-type GAA transistor and the p-type GAA transistor. For example, one or more ILD layers similar to the ILD layer 270 and / or the CESL layer may be formed above the substrate 202 (specifically, above the ILD layer 270 and the gate structures 360A, 360B). Then, contacts may be formed in the ILD layer 270 and / or the ILD layer disposed above the ILD layer 270. For example, the contacts are electrically and / or physically coupled to the gate structures 360A, 360B and the source / drain regions of the n-type GAA transistor and the p-type GAA transistor (specifically, the epitaxial source / drain components 260A, 260B), respectively. The contacts include a conductive material such as a metal. The metal includes aluminum, aluminum alloy (such as aluminum / silicon / copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, the ILD layer disposed above the ILD layer 270 and the contacts (e.g., extending through the ILD layer 270 and / or other ILD layers) is part of a multi-level interconnect component.

[0060] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices and their formation. For example, embodiments of the present invention provide a process for patterning n-type metal gates and p-type metal gates for CMOS devices. The process forms a sacrificial component that fills the gaps between adjacent channel layers and the gap between the channel layer and the substrate. Then, before depositing the p-type work function metal layer, the n-type work function metal layer is deposited and patterned. This prevents the metal in the n-type work function metal layer from diffusing into the p-type work function metal layer and affecting the threshold voltage of the p-type device. This embodiment can be easily integrated into existing CMOS manufacturing processes.

[0061] In an exemplary aspect, the present invention is directed to a method. The method includes: providing a structure having a p-type region and an n-type region, the p-type region having a first channel layer and the n-type region having a second channel layer. The method further includes: forming a gate dielectric layer around the first channel layer and around the second channel layer, and forming a sacrificial layer around the gate dielectric layer in the p-type region and the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and in the spaces between the second channel layers. The method further includes: etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; forming a first mask that covers the p-type region and exposes the n-type region; using the first mask in place to remove the sacrificial layer from the n-type region; and removing the first mask. After removing the first mask, the method further includes: forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.

[0062] In some embodiments, the method further includes: after forming the n-type work function metal layer, forming a second mask that covers the n-type region and exposes the p-type region, and using the second mask in place to remove the n-type work function metal layer from the p-type region and to remove the sacrificial layer from the p-type region. The method further includes: removing the second mask, and forming a p-type work function metal layer over the n-type work function metal layer in the n-type region and around the gate dielectric layer in the p-type region. In a further embodiment, the method further includes: forming a gate electrode over the p-type work function metal layer in the n-type region and the p-type region. In another further embodiment, the method further includes: after forming the n-type work function metal layer, forming a passivation layer over the n-type work function metal layer in the n-type region and the p-type region, and removing the passivation layer from the p-type region before or simultaneously with removing the n-type work function metal layer from the p-type region. In some embodiments, the passivation layer includes an alumina layer, a silicon layer, a silicon dioxide layer, or a silicon dioxide layer over the silicon layer. In some embodiments, the passivation layer merges in the spaces between the second channel layers.

[0063] In some embodiments of the method, the gate dielectric layer includes an interface layer and a high-k dielectric layer over the interface layer. In some embodiments of the method, the sacrificial layer includes alumina, titanium nitride, or silicon oxycarbide. In some embodiments of the method, the n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bilayer of TiAlC and TiN.

[0064] In another exemplary aspect, the present invention is directed to a method. The method includes: providing a structure having a first channel layer located in a p-type region and a second channel layer located in an n-type region; forming a high-k dielectric layer around the first channel layer and around the second channel layer; forming a sacrificial layer around the high-k dielectric layer in the p-type region and in the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and merges in the spaces between the second channel layers; etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; and forming a first mask that covers the p-type region and exposes the n-type region. The method further includes: removing the sacrificial layer from the n-type region; removing the first mask; forming an n-type work function metal layer around the high-k dielectric layer in the n-type region and over the high-k dielectric layer and the sacrificial layer in the p-type region; and forming a passivation layer over the n-type work function metal layer in the n-type region and in the p-type region, wherein the passivation layer merges in the spaces between the second channel layers.

[0065] In some embodiments of the method, the n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bilayer of TiAlC and TiN. In further embodiments, the passivation layer includes a silicon layer, a silicon dioxide layer, or a silicon dioxide layer over the silicon layer. In some embodiments of the method, the sacrificial layer includes aluminum oxide, titanium nitride, or silicon oxycarbide.

[0066] In some embodiments, the method further includes: after forming the passivation layer, forming a second mask that covers the n-type region and exposes the p-type region; removing the passivation layer, the n-type work function metal layer, and the sacrificial layer from the p-type region; removing the second mask; and forming a p-type work function metal layer over the n-type work function metal layer in the n-type region and around the high-k dielectric layer in the p-type region.

[0067] In some embodiments, the method further includes: before forming the high-k dielectric layer, forming an interface layer around the first channel layer and around the second channel layer, wherein the high-k dielectric layer is formed around the interface layer.

[0068] In yet another exemplary aspect, the present invention is directed to a device, including: a substrate having a p-type region and an n-type region; a first channel layer located over the p-type region; a second channel layer located over the n-type region; a gate dielectric layer located around the first channel layer and around the second channel layer; an n-type work function metal layer located around the gate dielectric layer around the second channel layer, wherein the n-type work function metal layer is not disposed over the gate dielectric layer around the first channel layer; and a p-type work function metal layer located around the gate dielectric layer around the first channel layer and over the n-type work function metal layer.

[0069] In some embodiments, the device further includes: a passivation layer located between the n-type work function metal layer and the p-type work function metal layer, wherein the passivation layer merges in the intervals located between the second channel layers. In a further embodiment, the passivation layer includes an alumina layer, a silicon layer, a silicon dioxide layer, or a silicon dioxide layer located above the silicon layer.

[0070] In some embodiments of the device, the p-type work function metal layer merges in the intervals between the first channel layers. In some embodiments of the device, the n-type work function metal layer merges in the intervals between the second channel layers.

[0071] Some embodiments of the present application provide a method of forming a semiconductor device, including: providing a structure having a p-type region and an n-type region, the p-type region having a first channel layer and the n-type region having a second channel layer; forming a gate dielectric layer around the first channel layer and around the second channel layer; forming a sacrificial layer around the gate dielectric layer in the p-type region and in the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and merges in the spaces between the second channel layers; etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; forming a first mask covering the p-type region and exposing the n-type region; using the first mask in place to remove the sacrificial layer from the n-type region; removing the first mask; and after removing the first mask, forming an n-type work function metal layer around the gate dielectric layer in the n-type region and above the gate dielectric layer and the sacrificial layer in the p-type region. In some embodiments, the method further includes: after forming the n-type work function metal layer, forming a second mask covering the n-type region and exposing the p-type region; using the second mask in place to remove the n-type work function metal layer from the p-type region; using the second mask in place to remove the sacrificial layer from the p-type region; removing the second mask; and after removing the second mask, forming a p-type work function metal layer above the n-type work function metal layer in the n-type region and around the gate dielectric layer in the p-type region. In some embodiments, the method further includes: forming a gate electrode above the p-type work function metal layer in the n-type region and in the p-type region. In some embodiments, the method further includes: after forming the n-type work function metal layer, forming a passivation layer above the n-type work function metal layer in the n-type region and in the p-type region; and removing the passivation layer from the p-type region before or simultaneously with removing the n-type work function metal layer from the p-type region. In some embodiments, the passivation layer includes an alumina layer, a silicon layer, a silicon dioxide layer, or a silicon dioxide layer above a silicon layer. In some embodiments, the passivation layer merges in the spaces between the second channel layers. In some embodiments, the gate dielectric layer includes an interface layer and a high-k dielectric layer above the interface layer. In some embodiments, the sacrificial layer includes alumina, titanium nitride, or silicon oxycarbide. In some embodiments, the n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bilayer of TiAlC and TiN.

[0072] Some other embodiments of the present application provide a method of forming a semiconductor device, including: providing a structure having a first channel layer in a p-type region and a second channel layer in an n-type region; forming a high-k dielectric layer around the first channel layer and around the second channel layer; forming a sacrificial layer around the high-k dielectric layer in the p-type region and in the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and merges in the spaces between the second channel layers; etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; forming a first mask covering the p-type region and exposing the n-type region; using the first mask in place to remove the sacrificial layer from the n-type region; removing the first mask; after removing the first mask, forming an n-type work function metal layer around the high-k dielectric layer in the n-type region and above the high-k dielectric layer and the sacrificial layer in the p-type region; and forming a passivation layer above the n-type work function metal layer in the n-type region and in the p-type region, wherein the passivation layer merges in the spaces between the second channel layers. In some embodiments, the n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bilayer of TiAlC and TiN. In some embodiments, the passivation layer includes a silicon layer, a silicon dioxide layer, or a silicon dioxide layer above the silicon layer. In some embodiments, the method further includes: after forming the passivation layer, forming a second mask covering the n-type region and exposing the p-type region; using the second mask in place to remove the passivation layer, the n-type work function metal layer, and the sacrificial layer from the p-type region; removing the second mask; and after removing the second mask, forming a p-type work function metal layer above the n-type work function metal layer in the n-type region and around the high-k dielectric layer in the p-type region. In some embodiments, the sacrificial layer includes aluminum oxide or titanium nitride or silicon oxycarbide. In some embodiments, the method further includes: before forming the high-k dielectric layer, forming an interface layer around the first channel layer and around the second channel layer, wherein the high-k dielectric layer is formed around the interface layer.

[0073] Some other embodiments of the present application provide a semiconductor device, including: a substrate having a p-type region and an n-type region; a first channel layer and a second channel layer, the first channel layer being located above the p-type region, and the second channel layer being located above the n-type region; a gate dielectric layer located around the first channel layer and around the second channel layer; an n-type work function metal layer located around the gate dielectric layer around the second channel layer, wherein the n-type work function metal layer is not disposed above the gate dielectric layer around the first channel layer; and a p-type work function metal layer located around the gate dielectric layer around the first channel layer and above the n-type work function metal layer. In some embodiments, the semiconductor device further includes: a passivation layer located between the n-type work function metal layer and the p-type work function metal layer, wherein the passivation layer merges in the spaces between the second channel layers. In some embodiments, the passivation layer includes an alumina layer, a silicon layer, a silicon dioxide layer, or a silicon dioxide layer located above the silicon layer. In some embodiments, the p-type work function metal layer merges in the spaces between the first channel layers. In some embodiments, the n-type work function metal layer merges in the spaces between the second channel layers.

[0074] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising: providing a structure having a p-type region and an n-type region, the p-type region having a first channel layer and the n-type region having a second channel layer; forming a gate dielectric layer around the first channel layer and around the second channel layer; forming a sacrificial layer around the gate dielectric layer in the p-type region and the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and merges in the spaces between the second channel layers; etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; forming a first mask covering the p-type region and exposing the n-type region; using the first mask in place to remove the sacrificial layer from the n-type region; removing the first mask; and after removing the first mask, forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region; the method further includes forming a p-type work function metal layer; wherein, after forming the n-type work function metal layer and before forming the p-type work function metal layer, a passivation layer is formed over the n-type work function metal layer in the n-type region and the p-type region, wherein the passivation layer includes an alumina layer, a silica layer, or a bilayer having a silicon layer and a silica layer.

2. The method according to claim 1, further comprising: after forming the n-type work function metal layer, forming a second mask covering the n-type region and exposing the p-type region; using the second mask in place to remove the n-type work function metal layer from the p-type region; using the second mask in place to remove the sacrificial layer from the p-type region; removing the second mask; and after removing the second mask, forming the p-type work function metal layer over the n-type work function metal layer in the n-type region and around the gate dielectric layer in the p-type region.

3. The method according to claim 2, further comprising: forming a gate electrode over the p-type work function metal layer in the n-type region and the p-type region.

4. The method according to claim 2, further comprising: removing the passivation layer from the p-type region before or simultaneously with removing the n-type work function metal layer from the p-type region.

5. The method according to claim 4, wherein, the thickness of the n-type work function metal layer is in the range of 1 nm to 5 nm.

6. The method according to claim 4, wherein, the passivation layer merges in the spaces between the second channel layers.

7. The method according to claim 1, wherein, the gate dielectric layer includes an interface layer and a high-k dielectric layer located above the interface layer.

8. The method according to claim 1, wherein, the sacrificial layer includes alumina, titanium nitride, or silicon oxycarbide.

9. The method according to claim 1, wherein, The n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bilayer of TiAlC and TiN.

10. A method of forming a semiconductor device, comprising: providing a structure having a first channel layer in a p-type region and a second channel layer in an n-type region; forming a high-k dielectric layer around the first channel layer and around the second channel layer; forming a sacrificial layer around the high-k dielectric layer in the p-type region and the n-type region, wherein the sacrificial layer merges in the spaces between the first channel layers and in the spaces between the second channel layers; etching the sacrificial layer such that only the portions of the sacrificial layer located in the spaces between the first channel layers and in the spaces between the second channel layers are retained; forming a first mask covering the p-type region and exposing the n-type region; using the first mask in place to remove the sacrificial layer from the n-type region; removing the first mask; after removing the first mask, forming an n-type work function metal layer around the high-k dielectric layer in the n-type region and above the high-k dielectric layer and the sacrificial layer in the p-type region; and the method further includes forming a p-type work function metal layer; wherein, after forming the n-type work function metal layer and before forming the p-type work function metal layer, a passivation layer is formed above the n-type work function metal layer in the n-type region and the p-type region, wherein the passivation layer merges in the spaces between the second channel layers, and wherein the passivation layer includes an aluminum oxide layer, a silicon dioxide layer, or a bilayer having a silicon layer and a silicon dioxide layer.

11. The method according to claim 10, wherein, the n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bilayer of TiAlC and TiN.

12. The method according to claim 11, wherein, the p-type work function metal layer includes titanium and nitrogen.

13. The method according to claim 10, further comprising: after forming the passivation layer, forming a second mask covering the n-type region and exposing the p-type region; using the second mask in place to remove the passivation layer, the n-type work function metal layer, and the sacrificial layer from the p-type region; removing the second mask; and after removing the second mask, forming the p-type work function metal layer above the n-type work function metal layer in the n-type region and around the high-k dielectric layer in the p-type region.

14. The method according to claim 10, wherein, the sacrificial layer includes aluminum oxide, titanium nitride, or silicon oxycarbide.

15. The method according to claim 10, further comprising: before forming the high-k dielectric layer, forming an interface layer around the first channel layer and around the second channel layer, wherein the high-k dielectric layer is formed around the interface layer.

16. A semiconductor device, comprising: a substrate having a p-type region and an n-type region; A first channel layer and a second channel layer, the first channel layer being located above the p-type region and the second channel layer being located above the n-type region; A gate dielectric layer, located around the first channel layer and around the second channel layer; An n-type work function metal layer, located around the gate dielectric layer around the second channel layer, wherein the n-type work function metal layer is not disposed above the gate dielectric layer around the first channel layer; and A p-type work function metal layer, located around the gate dielectric layer around the first channel layer and above the n-type work function metal layer; A passivation layer, located between the n-type work function metal layer and the p-type work function metal layer, wherein the passivation layer merges in the space between the second channel layers; Wherein the passivation layer comprises an alumina layer, a silica layer or a bilayer having a silicon layer and a silica layer.

17. The semiconductor device according to claim 16, Wherein, The thickness of the n-type work function metal layer is in the range of 1 nm to 5 nm.

18. The semiconductor device according to claim 17, Wherein, The p-type work function metal layer comprises titanium and nitrogen.

19. The semiconductor device according to claim 16, Wherein, The p-type work function metal layer merges in the space between the first channel layers.

20. The semiconductor device according to claim 16, Wherein, The n-type work function metal layer merges in the space between the second channel layers.

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