Packaging structure, packaging component and method for forming the same
By using multi-layer redistribution structure and local interconnect components in semiconductor packages, the problems of thermal expansion coefficient mismatch and warpage mismatch in semiconductor packages are solved, communication bandwidth and reliability are improved, and higher density and miniaturization are achieved. package.
Patent Information
- Application Number
- CN202110060927.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-07-17
- Filing Date
- 2021-01-18
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2041-01-18
AI Technical Summary
It is difficult for existing semiconductor packaging technologies to achieve high-density integration and miniaturization, especially in stacked packaging (PoP) technology, where thermal expansion coefficient mismatch and warpage mismatch are problems, affecting the reliability of the packaging and communication bandwidth.
Using a multi-layer redistribution structure, including a dielectric layer and a metallization layer, local interconnect components are embedded to provide electrical connections, and the interposer layer is reduced through solderless connections, eliminating thermal expansion coefficient mismatch, and improving communication bandwidth.
It improves the communication bandwidth and reliability between integrated circuit dies, reduces the mismatch of thermal expansion coefficients of the package structure, and enhances the stability and flexibility of the package.
Smart Images

Figure CN113113382B_ABST
