Chip power management method and circuit

Abstract

The chip power management scheme provided by the embodiment of the present application has the power switch arranged between the powered functional device and the power voltage converter, the power switch can control the on-off of the power supply path between the power voltage converter and the powered functional device according to the instruction of the PMU, and the output voltage of each voltage output end of the power voltage converter remains consistent in at least two power modes, so that when the chip switches between the two power modes, as long as the state switching of the power switch is completed, the compensation voltage value does not need to be adjusted again, and the appropriate voltage can be directly obtained and transmitted to the powered functional device, the switching of the chip power mode tends to be closer to the ideal state, the delay time of the switching between modes is greatly shortened, the chip power consumption is effectively reduced, and energy is saved.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a chip power management method and circuit. Background Technology

[0002] Currently, in energy-efficient IoT applications, wake-up mechanisms drive all applications. Both CPUs and peripherals have clock gating and power gating to save power. When the CPU is idle, the PMU (Power Management Unit) drives the subsystem into a low-power state. Existing power management schemes provide lower power in data retention mode and shut down the power in power-down mode. When the chip switches between different power modes, the power supply needs time to reach a preset steady state. For example, returning from data retention mode or power-down mode to operating mode requires a long wake-up time, and this delay between mode switches naturally leads to energy waste. Frequent mode switching by the chip results in even more energy waste. Summary of the Invention

[0003] The chip power management method and circuit provided in this invention mainly solve the technical problem of: solving the problem of huge power consumption caused by the delay time between mode switching when the chip switches between different power modes in the prior art.

[0004] To solve the above technical problems, embodiments of the present invention provide a chip power management circuit, including a power management unit (PMU), a power-to-voltage converter, and m powered functional devices. The chip power management circuit also includes n power switches corresponding to the m powered functional devices, where 2 ≤ n ≤ m.

[0005] The power switch is connected to the PMU and receives control from the PMU. The power switch is located between the voltage output terminal of the power voltage converter and the corresponding powered functional device, and controls the on / off of the corresponding power supply path according to the PMU's instructions. The output voltage of each voltage output terminal of the power voltage converter remains consistent in at least two power modes of the chip. The number of power switches disconnected is different in different power modes.

[0006] Optionally, the output voltage of each voltage output terminal of the power supply voltage converter remains consistent across all power supply modes of the chip.

[0007] Optionally, the power supply voltage converter performs voltage compensation based on the process and temperature of the powered functional device.

[0008] Optionally, if the chip's current power mode is the operating mode and the target power mode to be switched to is the low-power mode, the PMU controls some power switches to be turned off according to the number of power switches required to be turned off in the low-power mode.

[0009] Optionally, if the chip's current power mode is power-off mode and the target power mode is operating mode, the PMU controls at least some of the originally disconnected power switches to close according to the number of power switches to be disconnected as required by the operating mode.

[0010] Optionally, the power supply voltage converter includes a voltage source and a voltage converter DC-DC converter. The voltage source is capable of outputting at least two different reference voltages to the DC-DC converter. The PMU is communicatively connected to the voltage source and controls the reference voltages output by the voltage source.

[0011] This invention also provides a chip power management method, comprising:

[0012] The PMU monitors the power mode switching signal and determines the target power mode the chip needs to switch into. In addition to the PMU, the chip includes a power-to-voltage converter, m powered functional devices, and n power switches corresponding to the m powered functional devices, where 2 ≤ n ≤ m. The power switches are located between the voltage output terminals of the power-to-voltage converter and the corresponding powered functional devices. The powered functional devices are all devices except the PMU. The output voltage of each voltage output terminal of the power-to-voltage converter remains consistent in at least two power modes of the chip. The number of power switches disconnected differs depending on the power mode.

[0013] The PMU switches the chip to the target power mode by controlling the power switch.

[0014] Optionally, the output voltage of each voltage output terminal of the power supply voltage converter remains consistent across all power supply modes of the chip.

[0015] Optionally, if the chip's current power mode is operating mode and the target power mode is low-power mode, then switching the chip to the target power mode by controlling the state of the power voltage converter and the power switch includes:

[0016] The PMU controls the power switches to turn off based on the number of power switches required to be disconnected in low-power mode.

[0017] Optionally, if the chip's current power mode is power-down mode and the target power mode is operating mode, switching the chip to the target power mode by controlling the state of the power voltage converter and the power switch includes:

[0018] The PMU controls at least some of the power switches that were originally off to close, based on the number of power switches that should be disconnected according to the operating mode requirements.

[0019] The beneficial effects of this invention are:

[0020] In the chip power management scheme provided by this invention, the chip power management circuit includes a power management unit (PMU), a power switch, a power-to-voltage converter, and a powered functional device. The output voltage of each voltage output terminal of the power-to-voltage converter remains consistent in at least two power modes of the chip. The power switch is communicatively connected to the PMU and receives control from the PMU. The power switch is positioned between the power-to-voltage converter and the powered functional device, controlling the on / off state of the power supply path between them according to PMU instructions. Because a power switch is positioned between the powered functional device and the power-to-voltage converter, the power switch can control the on / off state of the power supply path according to PMU instructions. Therefore, whether the power-to-voltage converter supplies power to the powered functional device can be directly determined by the closing or opening of the power switch, without needing to turn the power-to-voltage converter on or off. Meanwhile, because the output voltage of each voltage output terminal of the power supply voltage converter remains consistent in at least two power modes, the power supply voltage converter remains enabled and outputs the same in both power modes. Thus, when the chip switches between these two power modes, as long as the state of the control power switch is switched, there is no need to spend time adjusting the compensation voltage value. The appropriate voltage can be directly obtained and delivered to the powered functional device. This makes the switching of the chip's power mode closer to the ideal state, greatly shortens the delay time between modes, effectively reduces chip power consumption, and saves energy.

[0021] Other features and corresponding beneficial effects of the present invention will be described in the latter part of the specification, and it should be understood that at least some of the beneficial effects will become obvious from the description in the specification. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a power mode switching method based on process voltage compensation in the prior art, as shown in Embodiment 1 of the present invention.

[0023] Figure 2 This is a schematic diagram of a power mode switching method based on temperature-based voltage compensation in the prior art, as shown in Embodiment 1 of the present invention.

[0024] Figure 3 This is a schematic diagram illustrating a chip switching power modes under ideal conditions, as shown in Embodiment 1 of the present invention.

[0025] Figure 4 This is a schematic diagram of a power mode switching scheme based on the prior art, as shown in Embodiment 1 of the present invention.

[0026] Figure 5 This is a schematic diagram of the chip power management circuit provided in Embodiment 1 of the present invention;

[0027] Figure 6 This is another schematic diagram of the chip power management circuit provided in Embodiment 1 of the present invention.

[0028] Figure 7 This is a flowchart of a chip power management method provided in Embodiment 1 of the present invention;

[0029] Figure 8 This is a schematic diagram of the chip power management circuit provided in Embodiment 2 of the present invention;

[0030] Figure 9 A timing diagram for power mode switching in an existing power management scheme;

[0031] Figure 10 This is a timing diagram for power mode switching based on the chip power management scheme provided in this embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0033] Example 1:

[0034] Ultra-low-power IoT (Internet of Things) systems focus on driving applications through low-power wake-up: Most of the time, the IoT system operates in low-power mode. When computational needs arise, the IoT system is woken up and enters the working state; after completing the processing, the IoT system returns to sleep mode, entering low-power mode again. To maximize power savings, multiple low-power modes are designed for the IoT system. Therefore, the energy-saving capability of the IoT system greatly depends on the speed of switching between different power modes (or power consumption modes).

[0035] In low-power mode, existing power management schemes will either shut down the power supply or reduce the supply voltage to just enough to retain data. In either case, upon wake-up, the PMU must switch the power supply back to the operating mode voltage. Figure 1 This illustrates a scenario where the operating mode uses a process-compensated voltage. The PMU can switch the chip to a low-power mode, where the voltage is lower than the rated value. Alternatively, the PMU can switch the chip to a power-down mode, where the power supply is shut off. In both cases, the power supply voltage needs to be restored to the process-compensated voltage before switching the chip back to the operating mode, but this takes time. Figure 1In the diagram, a solid horizontal line indicates HP (High Power), and a dashed horizontal line indicates LP (Low Power). Figure 2 This illustrates another scenario where the chip uses a temperature-compensated voltage in operating mode. The PMU can also switch the chip's voltage to a lower voltage or the voltage value corresponding to the power-down mode. Figure 2 In the diagram, a solid horizontal line represents HP, and a dashed horizontal line represents LP.

[0036] Figure 3 The diagram illustrates the ideal state of chip mode switching: when the chip switches from one power mode to another, there is no delay time, for example... Figure 3 In this process, the chip can switch from a low-power mode to a high-power mode instantly. There is no wake-up time when switching between power modes, so the state switching does not lead to energy waste.

[0037] exist Figure 4 The diagram shown illustrates the mode switching process of a chip in the prior art. Figure 4 As can be seen, when a chip switches from a low-power mode to a high-power operating mode, the transition cannot be instantaneous; that is, the delay between mode switches must be a non-zero value. Understandably, switching from a power-down mode to an operating mode will have a greater delay and result in more energy waste than switching from a low-power mode to an operating mode.

[0038] To address the issue of excessive power consumption caused by long switching delays during power mode transitions, this embodiment provides a chip power management solution. Please refer to [link to relevant documentation]. Figure 5 The diagram shows a schematic of a chip power management circuit: the chip power management circuit 50 includes a PMU 51, a power receiving device 52, a power voltage converter 53, and a power switch 54. Figure 5 In the diagram, thin solid lines represent power supply lines, and thick solid lines represent control lines.

[0039] PMU 51 is communicatively connected to power switch 54 and can control the opening and closing of power switch 54. Power voltage converter 53 includes voltage output terminals for providing operating voltage to various powered devices on the chip. Typically, power voltage converter 53 has more than one voltage output terminal, and the voltage values ​​of each voltage output terminal can be completely different. Of course, in some examples, some voltage output terminals may output the same voltage value.

[0040] It should be understood that the devices on the chip that require power include not only the power receiving device 52, but also the PMU 51. Figure 5The power supply voltage converter 53 is shown to include only two voltage output terminals that output voltage to the powered functional device 52, but those skilled in the art will understand that in other examples, the power supply voltage converter 53 may have more voltage output terminals corresponding to the powered functional device 52.

[0041] A power switch 54 is positioned between the powered functional device 52 and the voltage output terminal of the power voltage converter 53. It receives commands from the PMU 51 and controls the power voltage converter 53 to switch the power supply path to the powered functional device 52 on and off according to the received commands. Figure 5 The diagram shows two powered functional devices 52 and two power switches 54, but this does not mean that the number of power switches 54 is the same as the number of powered functional devices 52. In some examples of this embodiment, the chip power management circuit 50 includes m powered functional devices 52, where m is greater than or equal to 2. The power switches 54 are used to control the on / off of the power supply path from the power voltage converter 53 to these powered functional devices 52; therefore, the number of power switches 54, n, is less than or equal to m. In some cases, a corresponding power switch 54 can be provided for each powered functional device 52, that is, a one-to-one correspondence between powered functional devices 52 and power switches 54. Of course, several powered functional devices can also share one power switch 54. For example, in one example, the peripheral device and the CPU, two powered functional devices, can share one power switch. In another example, regardless of how many powered functional devices are included in the chip power management circuit 50, only one power switch is provided. Typically, the number of power switches 54 in the chip power management circuit 50 provided in this embodiment is greater than or equal to 2, that is, it includes at least two power switches 54.

[0042] In this embodiment, the voltage output terminals of the power voltage converter 53 output the same voltage value in at least two power modes of the chip. It is understood that the power voltage converter 53 may have two or more voltage output terminals. The phrase "the voltage output is the same in at least two power modes of the chip" does not mean that the voltage values ​​output by each voltage output terminal are identical to each other, but rather that the voltage value output by the same voltage output terminal is identical in at least two power modes. Undoubtedly, the power voltage converter 53 remains enabled in all these power modes. Furthermore, because the power voltage converter 53 requires voltage compensation when supplying power to the powered functional device 52, in this embodiment, the power voltage converter 53 remains enabled, performs voltage compensation, and maintains the same output voltage in at least two power modes of the chip. For example, in one example of this embodiment, the chip includes seven power modes, and the power voltage converter 53 can remain enabled, perform voltage compensation, and maintain the same output voltage in six of these power modes. In this way, when the chip's power mode switches between these six modes, the power voltage converter 53 can output a suitable voltage simply by adjusting the state of the power switch 54, without having to go through the process of re-determining the compensation voltage value.

[0043] In some examples of this embodiment, the power voltage converter 53 can maintain a consistent output voltage across all power modes of the chip. That is, the power voltage converter 53 performs voltage compensation in all power modes. For instance, in one example of this embodiment, the power voltage converter 53 can support three states, which may correspond to multiple power modes of the chip. The power voltage converter remains enabled and performs voltage compensation in all three states. This ensures that regardless of which two power modes the chip switches between, the corresponding delay time is minimized, reducing energy waste caused by mode switching to the greatest extent possible.

[0044] In this embodiment, under different power modes, PMU 51 can control different numbers of power switches 54 to be in the off state. Conversely, different numbers of power switches 54 in the off state indicate different power modes of the chip. Therefore, the power mode of the chip is related to the number of power switches 54 in the off state. For example, in some examples of this embodiment, the chip includes three power modes: operating mode, low-power mode, and power-off mode. The chip includes three power switches 54. In this example, the number of power switches 54 disconnected in operating mode is defined as 0, the number of power switches 54 disconnected in low-power mode is 1 or 2, and in power-off mode, all power switches 54 are in the off state. Therefore, when controlling the power mode switching, PMU 51 only needs to control the state of each power switch 54 according to the requirement of the number of power switches 54 disconnected for the target power mode.

[0045] In some examples of this embodiment, the power supply voltage converter 53 can perform voltage compensation based on the process and temperature of the powered functional device. In other examples of this embodiment, the power supply voltage converter 53 can also perform voltage compensation based on either the process or temperature of the powered functional device. Of course, in other examples, the method of voltage compensation by the power supply voltage converter 53 can also be determined based on other feasible factors.

[0046] In some examples of this embodiment, the power supply voltage converter 53 includes a voltage source and a DC-DC converter, wherein the voltage source is capable of providing at least two different reference voltages to the DC-DC converter, for example... Figure 6 In some examples of this embodiment, the voltage source 531 can provide a reference voltage including a bandgap reference voltage (BANDGAP VREF) and a low-power reference voltage (LOW POWER VREF). The voltage source 531 is communicatively connected to the PMU 51, and the PMU 51 can select and control the reference voltage output by the voltage source 531 to the DC-DC converter 532.

[0047] This embodiment also provides a chip power management method, which will be described below in conjunction with... Figure 7 The flowchart shown illustrates the method:

[0048] S702: The PMU monitors the power mode switching signal and determines the target power mode that the chip is about to switch into.

[0049] The chip's power modes can include operating mode, low-power mode, and power-down mode. In some examples of this embodiment, the low-power mode can be further divided into two or more types based on power consumption. The power mode switching signals can also include various types. For example, in some examples, the power mode switching signals can be divided into signals driven by the CPU on the chip and signals driven by peripherals. Signals driven by the CPU can include sleep signals (SLEEP), deep sleep signals (SLEEPDEEP), etc. Signals driven by peripherals include wake-up signals (WAKEUP), etc.

[0050] After the PMU 51 detects the power mode switching signal, it can determine the target power mode that the chip is about to switch into based on the type of the power mode switching signal. For example, if the PMU 51 detects a deep sleep signal driven by the CPU on the chip, it can determine that the target power mode that the chip is about to switch into is the power-down mode; if the power mode switching signal detected by the PMU 51 is a wake-up signal driven by a peripheral device, it can determine that the target power mode that the chip is about to switch into is the operating mode.

[0051] S704: The PMU switches the chip to the target power mode by controlling the state of the power voltage converter and the power switch.

[0052] Based on the chip power management scheme provided in this embodiment, since a power switch 54 capable of being controlled by a PMU 51 is provided between the power voltage converter 53 and the powered functional device 52 in the chip power management circuit 50, the PMU 51 does not need to turn off the power voltage converter 53 when controlling the power mode switching, but can achieve this by controlling the power switch 54.

[0053] Assuming the chip's current power mode is the operating mode and the target power mode is the low-power mode, the PMU 51 can control some power switches to be turned off according to the number of power switches required to be turned off in the low-power mode.

[0054] Assuming the current power mode of the chip is power-down mode and the target power mode is operating mode, the PMU 51 can control at least some of the originally disconnected power switches to close based on the number of power switches to be disconnected as required by the operating mode.

[0055] The chip power management method and circuit provided in this invention provide a power switch between the powered functional device and the power voltage converter. Simultaneously, the power voltage converter is kept enabled in at least two or even all power modes, maintaining a consistent voltage output. This ensures that when the chip switches between these power modes, the voltage supplied to the powered functional device by the power voltage converter is the appropriate value as soon as the power switch is completed, eliminating the need to spend time starting the power voltage converter and waiting for voltage compensation. This allows the output voltage to return to its rated value, shortening the power mode switching delay and reducing power consumption caused by power mode switching.

[0056] Example 2:

[0057] In existing power management schemes, under normal operating conditions, the PMU controls the power voltage converter to provide a margin of compensation voltage to the CPU and peripherals. In low-power mode, the PMU controls the power voltage converter to provide a voltage lower than its rated voltage. In power-down mode, the power voltage converter is turned off. When returning to normal operating conditions, the voltage provided by the power voltage converter must return to the rated voltage range of the normal operating mode. This adjustment process takes time, thus increasing the latency of switching between different modes and wasting energy.

[0058] To overcome the above drawbacks, this invention proposes a power mode-aware voltage compensation technique: in all modes, the power voltage converter remains enabled and maintains voltage compensation, which helps reduce the delay time of power mode switching. To enable those skilled in the art to better understand the advantages and details of the solution provided in this invention, this embodiment will further illustrate the chip power management scheme with examples:

[0059] Figure 8 A schematic diagram of a chip power management circuit is shown: The chip power management circuit 80 includes a voltage source 81, a DC-DC converter 82, a clock generator 83, a first power switch SW1, a second power switch SW2, a power unit 84, a first power receiving device 85a, and a second power receiving device 85b.

[0060] Among them, voltage source 81 and DC-DC converter 82 are components of the power supply voltage converter. Voltage source 81 can provide a bandgap reference voltage and a low-power reference voltage to DC-DC converter 82. The bandgap reference voltage of voltage source 81 can be used during the power-on phase of the powered device. Subsequently, the PMU can switch the reference voltage provided by voltage source 81 to a low-power reference voltage. All power supplies have high-power mode, medium-power (MP) mode, and low-power mode. When the chip is active, it is set to high-power mode; when the chip is in standby mode, all power supplies are set to low-power mode to obtain minimum quiescent current; when the load is between active and standby states, the power supply can be set to medium-power mode accordingly.

[0061] Because the CPU and memory power supplies require external bypass capacitors, the charging and discharging during mode switching typically takes on the order of microseconds. To reduce the mode switching latency and improve energy efficiency, the power supplies for the CPU and memory are designed to be very similar under all PVT (Process Voltage Temperature) boundary conditions for LP, MP, and HP modes.

[0062] Clock generator 83 includes three clock sources: a high-frequency clock source, a medium-frequency clock source, and a low-frequency clock source. Clock generator 83 can output clock frequencies to voltage source 81, DC-DC converter 82, and PMU 84.

[0063] Voltage source 81 and clock generator 83 are communicatively connected to PMU 84 and receive control from PMU 84, outputting corresponding reference voltage and clock frequency according to PMU 84's instructions. DC-DC converter 82 operates based on the reference voltage provided by voltage source 81 and the clock frequency provided by clock generator 83, converting the reference voltage into a voltage for use by the powered devices. In this embodiment, DC-DC converter 82 supplies a near-threshold rated voltage of 600mV to the first powered device 85a, which may include a CPU and peripherals. The second powered device 85b, such as a memory macroblock (SRAM, EFLASH), uses a 900mV power supply from DC-DC converter 82. In this embodiment, PMU 84, as an uninterruptible power supply (UPS), can also use the near-threshold rated voltage of 900mV provided by DC-DC converter 82.

[0064] The first power switch SW1 is located between the DC-DC converter 82 and the first power receiving device 85a, and the first power switch SW1 is communicatively connected to the PMU 84 and is controlled by the PMU 84; the second power switch SW2 is located between the DC-DC converter 82 and the second power receiving device 85b, and the second power switch SW2 is communicatively connected to the PMU 84 and is controlled by the PMU 84.

[0065] For the power supply schemes mentioned above, the supply voltage has the same nominal range in standby and operating modes, and the switching between standby and operating states is instantaneous. The time-division multiplexing control of the DC-DC 82 comes from the clock generator 83, which adjusts the output clock frequency according to the load of each power rail (represented by various power modes). The PMU 84 controls the power output to each functional module by controlling the first power switch SW1 and the second power switch SW2.

[0066] Therefore, in this embodiment, the DC-DC 82 performs voltage compensation based on process and temperature to meet conventional frequency requirements under all operating conditions.

[0067] Temperature and process boundary conditions can be obtained through on-chip process monitoring circuitry. In this embodiment, power mode-aware compensation is introduced for all PVT deviations, meaning that in medium and low power modes, the process and temperature compensation voltages are maintained at the source power rail.

[0068] Figure 9 This diagram illustrates a timing diagram for power mode switching in an existing power management scheme: In power-down mode, the PMU shuts down the voltage source, using pmu_sys_clk as its operating clock. When the CPU drives the SLEEPDEEP signal, the PMU shuts down the power-intensive high-frequency clock source. Then, via the control signal pmu_DCDC_en, the voltage source is shut down; voltage sources VDDD0P6 and VDDD0P9 require a time Tdcdcsw to complete their discharge. Once the peripheral device drives the WAKEUP signal, the DC-DC converter needs to be turned on again, which requires another Tdcdcsw for the DC-DC output voltage to return to its set value.

[0069] Figure 10This diagram illustrates a power mode switching scenario based on the chip power management scheme provided in this embodiment. In all power modes, the DC-DC converter 82 is enabled. In all power modes, the DC-DC converter 82 maintains the compensation voltages VDDD0P6 and VDDD0P9 output. The CPU drives the SLEEPDEEP signal, and the PMU 84 shuts down the high-power-consuming high-frequency clock source, selecting a lower-power-consuming clock source for clock frequency output. The PMU 104 controls the power supply to VDDD0P6_SW and VDDD0P9_SW via pmu_sw1_en_n and pmu_sw2_en_n, quickly shutting down the power supply to the digital logic. Entering the power-down mode requires only the minimum switching time (Tpsw). After the power supply is controlled, the DC-DC converter 82 enters a low-power state. The time required for this process is called Tmdsw, which is much shorter than the time Tdcdcsw for shutting down the power voltage converter. VDDD0P6 and VDDD0P9 maintain voltage compensation in all power modes. Once the WAKEUP signal is activated, the power mode of the DC-DC 82 is quickly switched back, the power switch closes, and power is instantly transferred to the digital logic.

[0070] In the chip power management scheme provided in this embodiment, all power modes maintain the compensation voltage output. Therefore, when switching power modes, the conversion can be completed instantaneously, with very little energy waste and reduced power consumption. This has broad application prospects in ultra-low power IoT systems.

[0071] It should be noted that the chip power management scheme provided in this embodiment is only one example of implementation. In other examples, the chip power management circuit may include fewer (e.g., no clock generator) or more devices, and the chip power management method may include fewer or more steps. Therefore, those skilled in the art should not assume that the specific implementation of the chip power management scheme provided in this embodiment is limited to the description in this embodiment.

[0072] Obviously, those skilled in the art will understand that all or some of the steps, systems, or devices disclosed above, and their functional modules / units, can be implemented as software (which can be implemented using computer device executable program code), firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, executed by a computing device, and in some cases, the steps shown or described may be performed in a different order than those presented herein. The computer-readable medium may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium. Therefore, this invention is not limited to any particular hardware and software combination.

[0073] The above description, in conjunction with specific implementation methods, provides a further detailed explanation of the embodiments of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A chip power management circuit, characterized by, The chip power management circuit comprises a power management unit (PMU), a power voltage converter, m powered functional devices, and n power switches corresponding to the m powered functional devices, 2≤n≤m; The power switches are in communication connection with the PMU and controlled by the PMU; the power switches are arranged between the voltage output ends of the power voltage converter and the corresponding powered functional devices, and control the on-off of the corresponding power supply paths according to the instructions of the PMU; the output voltages of each voltage output end of the power voltage converter remain consistent in at least two power modes of the chip; the number of power switches disconnected in different power modes is different; The output voltages of each voltage output end of the power voltage converter remain consistent in all power modes of the chip; the consistent output voltages include compensation voltages, so that the power voltage converter performs voltage compensation in all power modes; The power voltage converter performs voltage compensation based on the process and temperature of the powered functional devices.

2. The chip power management circuit of claim 1, wherein, If the current power mode of the chip is the working mode and the target power mode to be switched into is the low-power consumption mode, the PMU controls part of the power switches to be disconnected according to the number of power switches required to be disconnected in the low-power consumption mode.

3. The chip power management circuit of claim 1, wherein, If the current power mode of the chip is the power-off mode and the target power mode is the working mode, the PMU controls at least part of the originally disconnected power switches to be closed according to the number of power switches required to be disconnected in the working mode.

4. The chip power management circuit of claim 1, wherein, The power voltage converter comprises a voltage source and a voltage converter DCDC, the voltage source can output at least two different reference voltages to the DCDC, and the PMU is in communication connection with the voltage source and controls the reference voltages output by the voltage source.

5. A chip power management method, characterized by, The chip comprises a PMU, a power voltage converter, m powered functional devices, and n power switches corresponding to the m powered functional devices, 2≤n≤m; the power switches are arranged between the voltage output ends of the power voltage converter and the corresponding powered functional devices, the powered functional devices are devices other than the PMU; the output voltages of each voltage output end of the power voltage converter remain consistent in at least two power modes of the chip, and the consistent output voltages include compensation voltages; the number of power switches disconnected in different power modes is different; The PMU switches the chip to the target power mode by controlling the power switches; The output voltages of each voltage output end of the power voltage converter remain consistent in all power modes of the chip; the voltage values output by each voltage output end of the power voltage converter in at least two power modes of the chip are the same; The power voltage converter performs voltage compensation based on the process and temperature of the powered functional devices. ​ 6. The chip power management method of claim 5, wherein, If the current power mode of the chip is the working mode and the target power mode is the low power mode, switching the chip to the target power mode by controlling the state of the power voltage converter and the power switches comprises: The PMU controls some of the power switches to be opened according to the number of power switches required to be opened in the low power mode.

7. The chip power management method according to claim 5 or 6, wherein If the current power mode of the chip is the power-off mode and the target power mode is the working mode, switching the chip to the target power mode by controlling the state of the power voltage converter and the power switches comprises: The PMU controls at least some of the power switches originally opened to be closed according to the number of power switches required to be closed in the working mode.

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