Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device includes a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, and a second memory on the first memory, the first memory including a first stack structure having first electrode layers stacked on each other with first inter-electrode dielectric layers therebetween, a first planarization dielectric layer covering an end of the first stack structure, and a through-penetrating piece penetrating the end of the first stack structure, the through-penetrating piece electrically connected to one of the decoder circuits, the second memory including a second stack structure having second electrode layers stacked on each other with second inter-electrode dielectric layers therebetween, a second planarization dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through-penetrating piece.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0005350, filed on January 15, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to three-dimensional semiconductor memory devices, and more specifically, to three-dimensional semiconductor memory devices with enhanced reliability. Background Technology

[0004] Semiconductor devices are highly integrated to meet consumer expectations for high performance and low manufacturing costs. Because the integration of semiconductor devices is a significant factor in determining product price, the demand for high integration is increasing. The integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a single memory cell, making its integration susceptible to the level of technology used to form fine patterns. However, the expensive processing required to increase pattern fineness sets practical limitations on increasing the integration of two-dimensional or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide three-dimensional semiconductor memory devices with enhanced reliability and increased integration.

[0006] One aspect of the present invention is not limited to what has been described above, and those skilled in the art should clearly understand from the following description other aspects not described above.

[0007] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: a first peripheral circuit including a plurality of different decoder circuits; a first memory on the first peripheral circuit; and a second memory on the first memory. The first memory includes: a first stacked structure having a plurality of first electrode layers stacked on top of each other and a plurality of first inter-electrode dielectric layers between the first electrode layers; a first planarized dielectric layer covering an end of the first stacked structure; and a first through-hole penetrating the first planarized dielectric layer and the end of the first stacked structure, the first through-hole being insulated from the plurality of first electrode layers and electrically connected to one of the plurality of different decoder circuits. The second memory includes: a second stacked structure having a plurality of second electrode layers stacked on top of each other and a plurality of second inter-electrode dielectric layers between the second electrode layers; a second planarized dielectric layer covering an end of the second stacked structure; and a first unit contact plug penetrating the second planarized dielectric layer, the first unit contact plug electrically connecting one of the plurality of second electrode layers to the first through-hole.

[0008] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: a peripheral circuit including a plurality of different decoder circuits; a first memory on the peripheral circuit, the first memory including a first stacked structure and a second stacked structure spaced apart from each other in a first direction parallel to the top surface of the peripheral circuit, the first stacked structure including a plurality of first electrode layers stacked on top of each other, the plurality of first electrode layers being electrically connected to a first decoder circuit in a plurality of different decoder circuits, the second stacked structure including a plurality of second electrode layers stacked on top of each other; and a second memory on the first memory, the second memory including a third stacked structure and a fourth stacked structure spaced apart from each other in the first direction, the third stacked structure including a plurality of third electrode layers stacked on top of each other, the plurality of third electrode layers being electrically connected to a second decoder circuit in a plurality of different decoder circuits, the fourth stacked structure including a plurality of fourth electrode layers stacked on top of each other.

[0009] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: peripheral circuitry including a first decoder circuit and a second decoder circuit, the first decoder circuit and the second decoder circuit being arranged side by side in a first direction and being different from each other; a first memory on the peripheral circuitry, the first memory including a first stacked structure electrically connected to the first decoder; and a second memory on the first memory, the second memory including a second stacked structure electrically connected to the second decoder circuit, a portion of the second stacked structure protruding beyond the first stacked structure.

[0010] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: a first peripheral circuit including a plurality of different decoder circuits, the plurality of different decoder circuits including a first decoder circuit, a second decoder circuit, a third decoder circuit, and a fourth decoder circuit; a first memory on the first peripheral circuit, the first memory including a first stacked structure and a second stacked structure spaced apart from each other; and a second memory on the first memory, the second memory including a third stacked structure and a fourth stacked structure spaced apart from each other, the first stacked structure and the third stacked structure overlapping at least one of the first decoder circuit or the third decoder circuit, the second stacked structure and the fourth stacked structure overlapping at least one of the second decoder circuit or the fourth decoder circuit.

[0011] According to some exemplary embodiments of the present invention, a three-dimensional semiconductor memory device may include: peripheral circuitry including a first decoder circuit and a second decoder circuitry different from the first decoder circuitry; a first memory on the peripheral circuitry; and a second memory on the first memory. The first memory includes: a first stacked structure having a plurality of first electrode layers stacked on top of each other and a plurality of first inter-electrode dielectric layers between the first electrode layers, the plurality of first electrode layers being connected to the first decoder circuitry; a plurality of first vertical patterns penetrating the first stacked structure; a first gate dielectric layer between the plurality of first vertical patterns and the first stacked structure; and a first planarization dielectric layer covering the ends of the first stacked structure. The second memory includes: a second stacked structure having a plurality of second electrode layers stacked on top of each other and a plurality of second inter-electrode dielectric layers between the second electrode layers, the plurality of second electrode layers being electrically connected to the second decoder circuitry; a plurality of second vertical patterns penetrating the second stacked structure; a second gate dielectric layer between the plurality of second vertical patterns and the second stacked structure; and a second planarization dielectric layer covering the ends of the second stacked structure. Attached Figure Description

[0012] Figure 1A A block diagram illustrating some example embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention is shown.

[0013] Figure 1B Circuit diagrams illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention are shown.

[0014] Figure 2A The following is a demonstration Figure 1A A plan view of the logic chip.

[0015] Figure 2B The following is a demonstration Figure 1A A plan view of the first memory chip.

[0016] Figure 2C The following is a demonstration Figure 1A A plan view of the second memory chip.

[0017] Figure 3A It shows along Figure 2A or Figure 2B A sectional view taken by line A-A'.

[0018] Figure 3B It shows along Figure 2B or Figure 2C The sectional view taken by line B-B'.

[0019] Figure 3C It shows along Figure 2B or Figure 2C A sectional view taken by line C-C'.

[0020] Figure 4A The following is a demonstration Figure 3A An enlarged view of block P1.

[0021] Figure 4B The following is a demonstration Figure 3A An enlarged view of block P2.

[0022] Figure 4C The following is a demonstration Figure 3C An enlarged view of block P3.

[0023] Figure 4D The following is a demonstration Figure 3A An enlarged view of block P10.

[0024] Figure 5 It shows Figure 1A Detailed perspective view.

[0025] Figure 6A The following is a demonstration Figure 1A A plan view of the logic chip.

[0026] Figure 6B The following is a demonstration Figure 1A A plan view of the first memory chip.

[0027] Figure 6C The following is a demonstration Figure 1A A plan view of the second memory chip.

[0028] Figure 7A It shows along Figure 6B or Figure 6C A sectional view taken by line A-A'.

[0029] Figure 7B It shows along Figure 6B or Figure 6C The sectional view taken by line B-B'.

[0030] Figure 8 It shows Figure 1A Detailed perspective view.

[0031] Figure 9A The following is a demonstration Figure 1A A plan view of the first memory chip.

[0032] Figure 9B The following is a demonstration Figure 1A A plan view of the second memory chip.

[0033] Figure 10 It shows along Figure 9A or Figure 9B The sectional view taken by line B-B'.

[0034] Figure 11 It shows Figure 1A Detailed perspective view.

[0035] Figure 12 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0036] Figure 13A It shows along Figure 12 A sectional view taken by line A-A'.

[0037] Figure 13B It shows along Figure 12 The sectional view taken by line B-B'.

[0038] Figure 14 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0039] Figure 15 It shows along Figure 14 The sectional view taken by line B-B'.

[0040] Figure 16 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0041] Figure 17 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0042] Figure 18 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0043] Figure 19A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0044] Figure 20 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0045] Figure 21 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0046] Figure 22A A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0047] Figure 22B The following is a demonstration Figure 22A A plan view of the logic chips included in a three-dimensional semiconductor memory device.

[0048] Figure 22C The following is a demonstration Figure 22A A plan view of the first memory chip and the third memory chip included in the three-dimensional semiconductor memory device.

[0049] Figure 22D The following is a demonstration Figure 22A A plan view of the second and fourth memory chips included in the three-dimensional semiconductor memory device.

[0050] Figure 22E The following is a demonstration Figure 22C A magnified plan view of block P4.

[0051] Figure 22F The following is a demonstration Figure 22B An enlarged plan view of the first decoder circuit section.

[0052] Figure 23 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0053] Figure 24 and Figure 25 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0054] Figure 26 It shows along Figure 2B or Figure 2C A sectional view taken by line C-C'.

[0055] Figure 27 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0056] Figure 28 It shows along Figure 27 A sectional view taken by line A-A'.

[0057] Figure 29 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0058] Figure 30 and Figure 31 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0059] Figure 32 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0060] Figure 33 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0061] Figure 34 A perspective view is shown of the end of a first stacked structure illustrating some exemplary embodiments of the concept according to the present invention.

[0062] Figure 35 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown. Detailed Implementation

[0063] Now, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings to help clearly illustrate the inventive concept.

[0064] Figure 1A A block diagram illustrating some example embodiments of a three-dimensional semiconductor memory device according to a concept of the present invention is shown.

[0065] Reference Figure 1A A three-dimensional semiconductor memory device 1000 according to some exemplary embodiments of the present invention may include a plurality of memory chips 200 and 300 sequentially stacked on a logic chip 100. For example, memory chips 200 and 300 may include a first memory chip 200 and a second memory chip 300 (hereinafter, memory chips may also be referred to as memory devices, memory blocks and / or memories).

[0066] The logic chip 100 may include a decoder circuit section, a page buffer circuit section, and / or a control circuit.

[0067] The first memory chip 200 may include multiple memory blocks, such as a first memory block BLK1 and a second memory block BLK2. The second memory chip 300 may include multiple memory blocks, such as a third memory block BLK3 and a fourth memory block BLK4. Each of the memory blocks BLK1 to BLK4 may include an array of memory cells with a three-dimensional structure (or a vertical structure). Although Figure 1A Four memory blocks BLK1 to BLK4 are simply shown, but the number of memory blocks is not limited to this and can be greater than four. According to the present invention, the driver circuits (e.g., decoder circuit portions and page buffer circuit portions) used to drive the memory blocks BLK1 to BLK4 included in the memory chips 200 and 300 can be spaced apart from each other, thereby increasing the performance of the three-dimensional semiconductor memory device 1000 and providing the advantage of high integration.

[0068] Figure 1B Circuit diagrams illustrating some exemplary embodiments of a three-dimensional semiconductor memory device according to the present invention are shown.

[0069] Reference Figure 1B Each of the memory blocks BLK1 through BLK4 can be configured such that the cell strings CSTR are arranged two-dimensionally along a first direction D1 and a second direction D2 and extend along a third direction D3. Multiple cell strings CSTR can be connected in parallel with each of the bit lines BL0 through BL2. Multiple cell strings CSTR can be connected together to the common source line CSL.

[0070] Bit lines BL0 to BL2 can be arranged in a two-dimensional configuration, and multiple cell strings (CSTRs) can be connected in parallel with each of the bit lines BL0 to BL2. Multiple cell strings (CSTRs) can be connected together to a common-source line (CSL). For example, multiple cell strings (CSTRs) can be arranged between a common-source line (CSL) and multiple bit lines BL0 to BL2. The common-source line (CSL) can be configured as multiple lines arranged in a two-dimensional configuration. The common-source lines (CSLs) can be supplied with the same or similar voltages, or they can be electrically controlled independently of each other.

[0071] In some example embodiments, each of the cell strings CSTRs may include series-connected string select transistors SST21 and SST11, series-connected memory cell transistors MCTs, and a ground select transistor GST. Each of the memory cell transistors MCTs may include a data storage element. One of the cell strings CSTRs may also include a pseudo-cell DMC between the string select transistor SST11 and the memory cell transistor MCT, and between the ground select transistor GST and the memory cell transistor MCT. Other cell strings CSTRs may have the same or similar structures as described above.

[0072] The string select transistor SST21 can be coupled to the first bit line BL1, and the ground select transistor GST can be coupled to the common source line CSL. The memory cell transistor MCT connected to a cell string CSTR can be connected in series, for example, between the string select transistor SST11 and the ground select transistor GST.

[0073] Alternatively, in each of the cell strings CSTRs, the ground selection transistor GST may include multiple MOS transistors connected in series, similar to the string selection transistors SST21 and SST11. The difference is that each of the cell strings CSTRs may include one string selection transistor.

[0074] In some example embodiments, the string select transistor SST11 can be controlled by the string select line SSL11, and the string select transistor SST21 can be controlled by the string select line SSL21. The memory cell transistor MCT can be controlled by multiple word lines WL0 to WLn, and the pseudo-cell DMC can be controlled by the pseudo-word line DWL. The ground select transistor GST can be controlled by the ground select line GSL. The common source line CSL can be connected to the source of the ground select transistor GST. The ground select lines GSL0 to GSL2 can be connected to each other to operate simultaneously or concurrently, or they can be separated to operate independently.

[0075] A cell string (CSTR) can include multiple memory cell transistors (MCTs) located at different distances from the common-source line (CSL). Multiple word lines (WL0 to WLn) and pseudo-word lines (DWL) can be configured between the common-source line (CSL) and bit lines (BL0 to BL2).

[0076] A memory cell transistor (MCT) may include a gate electrode located at the same or substantially the same distance from the common-source line (CSL), and the gate electrode may be connected to one of the word lines WL0 to WLn and the pseudo-word line DWL, thus having the same or similar potential states. Alternatively, although the gate electrode of the MCT is located at the same or substantially the same distance from the common-source line (CSL), gate electrodes located in different rows or columns can be controlled independently of each other.

[0077] The following will describe Figure 1B Operation of a three-dimensional semiconductor memory device.

[0078] For example, during a write operation, when one of the memory blocks BLK1 through BLK4 is selected by address, the decoder circuit (also referred to herein as the decoder circuit section) can apply a programming voltage to the selected word line of the selected memory block and can apply a pass voltage to the unselected word line of the selected memory block. The decoder circuit section can apply a cutoff voltage to the ground select lines GSL0 through GSL2 of the selected memory block and can apply a pass voltage to the pseudo-word line DWL and the serial select lines SSL11 through SSL13 and SSL21 through SSL23.

[0079] During a read operation, when one of the memory blocks BLK1 to BLK4 is selected by address, the decoder circuitry can apply the selected read voltage to the selected word line of the selected memory block, and can apply the unselected read voltage to the unselected word line of the selected memory block. The decoder circuitry can apply the on-state voltage to the serial select lines SSL11 to SSL13 and SSL21 to SSL23, the pseudo-word line DWL, and the ground select lines GSL0 to GSL2 of the selected memory block.

[0080] During the erase operation, when one of the memory blocks BLK1 through BLK4 is selected by address, the decoder circuitry can apply an erase voltage (e.g., ground voltage or a lower voltage similar to ground) to the word line of the selected memory block. The decoder circuitry can electrically float the serial select lines SSL11 through SSL13 and SSL21 through SSL23, the pseudo-word line DWL, and the ground select lines GSL0 through GSL2 of the selected memory block.

[0081] The page buffer circuit (also referred to as the page buffer circuit section in this document) can be connected to the memory cell array via multiple bit lines BL0 to BL2. The page buffer circuit section can be connected to the data input / output circuit. The page buffer circuit section can operate under the control of the logic circuit.

[0082] During a write operation, the page buffer circuitry can store the data to be written to the memory cell. Based on the stored data, the page buffer circuitry can apply voltage to multiple bit lines BL0 to BL2. In a verification read operation used for read, write, or erase operations, the page buffer circuitry can detect the voltage on bit lines BL0 to BL2 and store the verification result.

[0083] Figure 2A The following is a demonstration Figure 1A A plan view of the logic chip. Figure 2B The following is a demonstration Figure 1A A plan view of the first memory chip. Figure 2C The following is a demonstration Figure 1A A plan view of the second memory chip. Figure 3A It shows along Figure 2A or Figure 2B A sectional view taken by line A-A'. Figure 3B It shows along Figure 2B or Figure 2C The sectional view taken by line B-B'. Figure 3C It shows along Figure 2B or Figure 2C A sectional view taken by line C-C'. Figure 4A The following is a demonstration Figure 3A An enlarged view of block P1. Figure 4B The following is a demonstration Figure 3A An enlarged view of block P2. Figure 4C The following is a demonstration Figure 3C An enlarged view of block P3. Figure 5 It shows Figure 1A Detailed perspective view. Figure 4D The following is a demonstration Figure 3A An enlarged view of block P10.

[0084] Reference Figure 2A , Figure 3A and Figure 3BThe logic chip 100 may include a logic substrate 103. For example, the logic substrate 103 may be a single-crystal silicon substrate or a silicon-on-insulator (SOI) substrate. A device isolation layer 105 defining an active region may be disposed in the logic substrate 103. The device isolation layer 105 may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. A plurality of logic transistors PST1 to PST4 and PTR may be disposed on the active region. Each of the logic transistors PST1 to PST4 and PTR may be one or more of a planar MOSFET, a FinFET, an MBCFET, and a VFET. The logic transistors PST1 to PST4 and PTR may be covered by an inter-logic dielectric layer 107. The inter-logic dielectric layer 107 may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a porous dielectric layer, and a low-k dielectric layer. The inter-logic dielectric layer 107 may have multiple layers of logic lines 109 therein. Logic transistors PST1 to PST4 and PTR, along with logic line 109, can constitute the first decoder circuit section DCR1 to the fourth decoder circuit section DCR4 and the page buffer circuit section PB. Logic transistors PST1 to PST4 and PTR can include the first transfer transistor PST1 to the fourth transfer transistor PST4 and the bit line selection transistor PTR. The first transfer transistor PST1 to the fourth transfer transistor PST4 can be respectively included in the first decoder circuit section DCR1 to the fourth decoder circuit section DCR4. The bit line selection transistor PTR can be included in the page buffer circuit section PB. Logic connection terminal 150 can be disposed on the top of the inter-logic dielectric layer 107. Logic connection terminal 150 can be electrically connected to logic line 109. The page buffer circuit section PB can be disposed in the middle of the logic chip 100. The first decoder circuit section DCR1 and the fourth decoder circuit section DCR4 can be adjacent to one side of the page buffer circuit section PB. The second decoder circuit section DCR2 and the third decoder circuit section DCR3 can be adjacent to the other side of the page buffer circuit section PB.

[0085] Reference Figure 2B , Figure 3A and Figure 3B The first memory chip 200 may include a first memory substrate 201. The first memory chip 200 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in a first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. The cell array region CAR may overlap with the page buffer circuit portion PB of the logic chip 100. The first connection region CNR1 may overlap with the first decoder circuit portion DCR1 and the fourth decoder circuit portion DCR4. The second connection region CNR2 may overlap with the second decoder circuit portion DCR2 and the third decoder circuit portion DCR3.

[0086] For example, the first memory substrate 201 may be a single-crystal silicon substrate or a silicon-on-insulator (SOI) substrate. The first memory substrate 201 may be a semiconductor layer or a dielectric layer. The first memory substrate 201 may have a first surface 201a and a second surface 201b that are opposite to each other. The first surface 201a of the first memory substrate 201 may face the logic chip 100. The source layer SCL may be disposed on the first surface 201a of the first memory substrate 201.

[0087] A first stacked structure ST1 and a second stacked structure ST2, spaced apart from each other in the second direction D2, can be disposed on the source layer SCL. The first stacked structure ST1 can be... Figure 1A This corresponds to a portion of the first memory block BLK1 shown. The second stack structure ST2 can be associated with... Figure 1A This corresponds to a portion of the second memory block BLK2 shown. For example... Figure 2B As shown, the second stacked structure ST2 can have the same or similar shape as the shape obtained when the first stacked structure ST1 is rotated about 180 degrees.

[0088] The first stacked structure ST1 may include a stacked first electrode layer EL1 and an inter-electrode dielectric layer 12 between the first electrode layers EL1. The first electrode layer EL1 may contain a metal such as tungsten. For example, the inter-electrode dielectric layer 12 may include a silicon oxide layer. In the first electrode layer EL1, the first electrode layer EL1 closest to the logic chip 100 can be divided into multiple wires by separating the dielectric pattern 9 and the recess region GR. The wires can be connected to the first memory block BLK1. Figure 1B The serial select lines SSL11 to SSL13 and SSL21 to SSL23 shown correspond to one of them. Within the first electrode layer EL1, the first electrode layer EL1 closest to the source layer SCL can be divided into multiple conductors by another separate dielectric pattern (not shown), and these conductors can be connected to the first memory block BLK1. Figure 1B The ground selection lines GSL0 to GSL2 shown correspond to one of them. The first electrode layer EL1, other than the first electrode layer EL1 described above, can be... Figure 1B The character lines WL0 to WLn correspond to each other.

[0089] The first stacked structure ST1 may have stepped ends on the first connection region CNR1 and the second connection region CNR2. The ends of the first stacked structure ST1 may be covered by a planarized dielectric layer 20. The first stacked structure ST1 may include a recessed region GR extending in a first direction D1 on each of the cell array region CAR and the first connection region CNR1. The first electrode layer EL1 of the first stacked structure ST1 may include a corresponding first recess RC1 on the second connection region CNR2 (e.g., at the end of the first stacked structure ST1). The inner walls of the first recesses RC1 may be aligned with each other.

[0090] The second stacked structure ST2 may include an inter-electrode dielectric layer 12 between the stacked second electrode layers EL2 and the second electrode layers EL2. The second electrode layers EL2 may contain a metal such as tungsten. In the second electrode layers EL2, the one closest to the logic chip 100 can be divided into multiple wires by separating the dielectric pattern 9 and the recessed region GR. The wires can be connected to the second memory block BLK2. Figure 1B The serial select lines SSL11 to SSL13 and SSL21 to SSL23 shown correspond to one of them. In the second electrode layer EL2, the second electrode layer EL2 closest to the source layer SCL can be divided into multiple wires by another discrete dielectric pattern (not shown), and the wires can be connected to the second memory block BLK2. Figure 1B The ground selection lines GSL0 to GSL2 shown correspond to one of them. The second electrode layer EL2, other than the aforementioned second electrode layer EL2, can be... Figure 1B The character lines WL0 to WLn correspond to each other.

[0091] The second stacked structure ST2 may have stepped ends on the first connection region CNR1 and the second connection region CNR2. Both ends of the second stacked structure ST2 may be covered by a planarized dielectric layer 20. According to some example embodiments, the planarized dielectric layer 20 covering the ends of the first stacked structure ST1 may extend to cover the ends of the second stacked structure ST2. The second stacked structure ST2 may include a recessed region GR extending in a first direction D1 on each of the cell array region CAR and the second connection region CNR2. The second electrode layer EL2 of the second stacked structure ST2 may include a corresponding second recess RC2 on the first connection region CNR1 (e.g., at the end of the second stacked structure ST2). The sidewalls of the second recess RC2 may be aligned with each other.

[0092] The first recess RC1 and the second recess RC2 can be filled with the residual sacrificial pattern 18. The residual sacrificial pattern 18 can be formed of a material that has etch selectivity relative to the inter-electrode dielectric layer 12, such as a silicon nitride layer.

[0093] On the cell array region CAR, multiple cell vertical patterns VS can penetrate each of the first stack structure ST1 and the second stack structure ST2. The ends of the cell vertical patterns VS can be connected by a first layer bit line L1BL. The first layer bit line L1BL can extend in the second direction D2 and can be parallel to each other. A single first layer bit line L1BL can simultaneously connect the ends of cell vertical patterns VS that penetrate the first stack structure ST1 and the second stack structure ST2 and are arranged in a straight line along the second direction D2. Although for simplicity, Figure 2B The first layer bit line L1BL is shown in part, but the first layer bit line L1BL can be set on the entire cell array region CAR.

[0094] On the cell array region CAR, the first cell through-hole component CTHV1 can penetrate the first stacked structure ST1 and the first memory substrate 201, and the second cell through-hole component CTHV2 can penetrate the second stacked structure ST2 and the first memory substrate 201. Viewed in plan view, the first cell through-hole component CTHV1 and the second cell through-hole component CTHV2 can be located between the first layered bit lines L1BL. Both the first cell through-hole component CTHV1 and the second cell through-hole component CTHV2 can be electrically connected to one of the first layered bit lines L1BL via a bit line connection line BLCP. In the first memory chip 200, the bit line connection line BLCP can be a lateral protrusion of the first layered bit line L1BL or a conductive pattern located at a height different from the height of the first layered bit line L1BL.

[0095] Reference Figure 2B , Figure 3A and Figure 5 On the second connection region CNR2, the first edge through-hole ETHV1 can penetrate the first stacked structure ST1 and the first memory substrate 201. The first edge through-hole ETHV1 can be disposed in the first recess RC1. The first edge through-hole ETHV1 can penetrate the planarized dielectric layer 20, the inter-electrode dielectric layer 12, and the residual sacrificial pattern 18.

[0096] On the first connection region CNR1, the second edge through-hole ETHV2 can penetrate the second stacked structure ST2 and the first memory substrate 201. The second edge through-hole ETHV2 can be disposed in the second recess RC2. The second edge through-hole ETHV2 can penetrate the planarized dielectric layer 20, the inter-electrode dielectric layer 12, and the residual sacrificial pattern 18. The first edge through-hole ETHV1 and the second edge through-hole ETHV2 may not be electrically connected to the first electrode layer EL1 and the second electrode layer EL2. When viewed in a planar view, the first edge through-hole ETHV1 and the second edge through-hole ETHV2 can be arranged in a zigzag pattern along the first direction D1, or they can be arranged in a straight line along the first direction D1.

[0097] Reference Figure 2B , Figure 3A and Figure 4A The first through-hole element CTHV1 and the second through-hole element CTHV2, as well as the first edge through-hole element ETHV1 and the second edge through-hole element ETHV2, can all be surrounded by the through-hole element dielectric layer 16. For example, the through-hole element dielectric layer 16 may include a silicon oxide layer. The through-hole element dielectric layer 16 may have a first thickness TK1 parallel to the first direction D1. One of the inter-electrode dielectric layers 12 may have a second thickness TK2 parallel to a third direction D3 perpendicular to the first direction D1. When the through-hole element dielectric layer 16 comprises the same or similar material as the inter-electrode dielectric layer 12, the first thickness TK1 may be equal to or greater than the second thickness TK2. Therefore, even when voltage is applied to the first cell through-hole CTHV1 and the second cell through-hole CTHV2, as well as the first edge through-hole ETHV1 and the second edge through-hole ETHV2, (for example, since each of the first cell through-hole CTHV1 and the second cell through-hole CTHV2, as well as the first edge through-hole ETHV1 and the second edge through-hole ETHV2, provides insulation with the dielectric layer 16 between the first electrode layers EL1 and EL2) can reduce or prevent signal interference between the first electrode layers EL1 and EL2 and the first edge through-hole ETHV1 and the second edge through-hole ETHV2.

[0098] On the first connection region CNR1, each first unit contact plug CC1 can penetrate the planarized dielectric layer 20 and one or more inter-electrode dielectric layers 12, thereby contacting an end of one of the first electrode layers EL1. On the second connection region CNR2, each second unit contact plug CC2 can penetrate the planarized dielectric layer 20 and one or more inter-electrode dielectric layers 12, thereby contacting an end of one of the second electrode layers EL2. Both the first unit contact plug CC1 and the second unit contact plug CC2 can be surrounded by a contact dielectric layer 14. For example, the contact dielectric layer 14 may include a silicon nitride layer or a silicon oxide layer. The contact dielectric layer 14 may have a third thickness TK3 parallel to a third direction D3. The third thickness TK3 may be less than the first thickness TK1.

[0099] Reference Figure 2B and Figure 3CA first source contact plug CSPLG1 can be disposed at the separation region SR between the first stacked structure ST1 and the second stacked structure ST2. A second source contact plug CSPLG2 can be disposed in the recessed region GR. The first source contact plug CSPLG1 and the second source contact plug CSPLG2 can be spaced apart from each other and can penetrate the first stacked structure ST1 and the second stacked structure ST2, thereby being adjacent to the first memory substrate 201. A dielectric spacer SP can be disposed between each of the first source contact plug CSPLG1 and the second source contact plug CSPLG2 and each of the first stacked structure ST1 and the second stacked structure ST2.

[0100] A central pseudo-vertical pattern CDVS can be disposed between the separated dielectric patterns 9. The central pseudo-vertical pattern CDVS can be disposed along a straight line in the first direction D1. The central pseudo-vertical pattern CDVS can be not electrically connected to the first layer bit line L1BL. On the first connection region CNR1 and the second connection region CNR2, the edge pseudo-vertical pattern EDVS can penetrate the planarized dielectric layer 20 and the first stacked structure ST1 and the second stacked structure ST2.

[0101] The unit vertical pattern VS, the center pseudo-vertical pattern CDVS, and the edge pseudo-vertical pattern EDVS can all have a hollow cup shape, with the empty space inside filled with the embedded dielectric pattern 29. For example, the embedded dielectric pattern 29 may include a silicon oxide layer.

[0102] The bit line conductive pads 34 can be correspondingly disposed on the unit vertical pattern VS, the center pseudo-vertical pattern CDVS, and the edge pseudo-vertical pattern EDVS. The bit line conductive pads 34 can be doped regions or can be formed of conductive materials.

[0103] like Figure 4A or Figure 4CAs shown, a gate dielectric layer GO can be disposed between each of the vertical patterns VS, CDVS, and EDVS and each of the first stacked structure ST1 and the second stacked structure ST2. The gate dielectric layer GO may include a tunnel dielectric layer TL, a charge storage layer SN, and a barrier dielectric layer BCL. The charge storage layer SN may be a trap dielectric layer comprising conductive nanodots, a floating gate electrode, or a dielectric layer. For example, the charge storage layer SN may include one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer. The tunnel dielectric layer TL may include a material with a band gap larger than that of the charge storage layer SN, and the barrier dielectric layer BCL may include a high-k dielectric layer such as an alumina layer or a hafnium oxide layer. The gate dielectric layer GO may also include a high-k dielectric layer HL. The high-k dielectric layer HL may be located between the barrier dielectric layer BCL and each of the electrode layers EL1 and EL2. The high-k dielectric layer HL may also be located between the inter-electrode dielectric layer 12 and each of the electrode layers EL1 and EL2. High-k dielectric layers (HL) can include metal oxide layers with dielectric constants greater than those of silicon oxide layers, such as hafnium oxide or aluminum oxide layers.

[0104] Reference Figure 3C and Figure 4C The source layer SCL may include a first source pattern SC1 and a second source pattern SC2. For example, both the first source pattern SC1 and the second source pattern SC2 may include a polycrystalline silicon pattern or a monocrystalline silicon pattern doped with impurities having a first conductivity type. The second source pattern SC2 may penetrate the tunnel dielectric layer TL, the charge storage layer SN, and the barrier dielectric layer BCL to contact the sidewalls of the vertical patterns VS, CDVS, and EDVS.

[0105] Reference Figure 3A and Figure 4B The first interlayer dielectric layer 3 can cover the second surface 201b of the first memory substrate 201. The second interlayer dielectric layer 30 and the third interlayer dielectric layer 40 can be sequentially stacked on the bottom surface of the planar dielectric layer 20. On the cell array region CAR, the first layer bit line L1BL can be disposed between the second interlayer dielectric layer 30 and the third interlayer dielectric layer 40. On the first connection region CNR1 and the second connection region CNR2, the first edge through-hole ETHV1 and the second edge through-hole ETHV2, as well as the first cell contact plug CC1 and the second cell contact plug CC2, can be electrically connected to the corresponding first conductive pattern VPa. The first conductive pattern VPa can be disposed between the second interlayer dielectric layer 30 and the third interlayer dielectric layer 40.

[0106] The first unit through-hole CTHV1 and the second unit through-hole CTHV2, as well as the first edge through-hole ETHV1 and the second edge through-hole ETHV2, can be electrically connected to the corresponding second conductive pattern VPb disposed on the second surface 201b of the first memory substrate 201.

[0107] The first interlayer dielectric layer 3 of the first memory chip 200 can contact the third interlayer dielectric layer 40 of the second memory chip 300. Alternatively, such as Figure 4B As shown, the first passivation layer 242 can be formed on the first interlayer dielectric layer 3, and the second passivation layer 342 can be formed on the bottom surface of the third interlayer dielectric layer 40. For example, the first passivation layer 242 and the second passivation layer 342 can be formed of silicon oxide layers. The first passivation layer 242 and the second passivation layer 342 can be in contact with each other.

[0108] The first memory chip 200 may further include a first connection terminal 50a disposed at the bottom end of the third interlayer dielectric layer 40 and a second connection terminal 50b disposed at the top end of the first interlayer dielectric layer 3. The first connection terminal 50a and the second connection terminal 50b may comprise metals such as copper, aluminum, tungsten, nickel, or tin. For example, the first connection terminal 50a and the second connection terminal 50b may be formed of copper. According to some example embodiments, the first connection terminal 50a and the second connection terminal 50b may also be referred to as a first conductive pattern 50a and a second conductive pattern 50b. Figure 4B As shown, the first connecting terminal 50a and the second connecting terminal 50b can be in contact with each other. Alternatively, the first connecting terminal 50a and the second connecting terminal 50b can be merged to form a single shape without boundaries between them. The first conductive pattern VPa and the second conductive pattern VPb can be electrically connected to the first connecting terminal 50a and the second connecting terminal 50b respectively via a through-hole CT.

[0109] Reference Figure 4D Each of the first stacked structure ST1 and the second stacked structure ST2 may include a first sub-stacked structure SBST1 and a second sub-stacked structure SBST2. These descriptions also apply to the third stacked structure ST3 and the fourth stacked structure ST4, which will be described below. The second sub-stacked structure SBST2 may be closer to the source layer SCL than the first sub-stacked structure SBST1. The first sub-stacked structure SBST1 may be closer to the logic chip 100 than the second sub-stacked structure SBST2. The inflection points (SIPs) of the sidewalls of the vertical patterns VS, CDVS, and EDVS may be adjacent to the boundary between the first sub-stacked structure SBST1 and the second sub-stacked structure SBST2. Additionally, the sidewalls of the gate dielectric layer GO may have inflection points adjacent to the boundary between the first sub-stacked structure SBST1 and the second sub-stacked structure SBST2.

[0110] Reference Figure 3A and Figure 3B None of the through-holes CTHV1, CTHV2, ETHV1, and ETHV2 can penetrate the source layer SCL. A first dielectric pattern IP1 may be located between the source layer SCL and each of the through-hole dielectric layers 16 covering the sidewalls of the first cell through-hole CTHV1 and the second cell through-hole CTHV2. A second dielectric pattern IP2 may be located between the source layer SCL and each of the through-hole dielectric layers 16 covering the sidewalls of the first edge through-hole ETHV1 and the second edge through-hole ETHV2 adjacent to the cell array region CAR. For example, the first dielectric pattern IP1 and the second dielectric pattern IP2 may be formed of a silicon oxide layer. According to some example embodiments, a vertical pattern VS can penetrate and contact the source layer SCL.

[0111] Reference Figure 2C , Figure 3A and Figure 3B The second memory chip 300 may include a second memory substrate 301. The second memory chip 300 may have a structure similar to that of the first memory chip 200. The second memory substrate 301 may have a first surface 301a facing the logic chip 100. The source layer SCL may be disposed on the first surface 301a of the second memory substrate 301.

[0112] A third stacked structure ST3 and a fourth stacked structure ST4, spaced apart from each other in the second direction D2, can be disposed on the source layer SCL. The third stacked structure ST3 can be... Figure 1B This corresponds to a portion of the third memory block BLK3 shown. The fourth stack structure ST4 can be associated with... Figure 1B This corresponds to a portion of the fourth memory block BLK4 shown. The fourth stack structure ST4 may have the same or similar shape as the shape obtained when the third stack structure ST3 is rotated approximately 180 degrees.

[0113] The third stacked structure ST3 may include stacked third electrode layers EL3 and an inter-electrode dielectric layer 12 between the third electrode layers EL3. The fourth stacked structure ST4 may include stacked fourth electrode layers EL4 and an inter-electrode dielectric layer 12 between the fourth electrode layers EL4. Each of the third stacked structure ST3 and the fourth stacked structure ST4 may have stepped ends on the first connection region CNR1 and the second connection region CNR2. The total number of third electrode layers EL3 may be the same as or different from the total number of fourth electrode layers EL4. The total number of third electrode layers EL3 may be the same as or different from the total number of first electrode layers EL1. Unlike the first electrode layer EL1, the third electrode layer EL3 may not have a first recess RC1. Unlike the second electrode layer EL2, the fourth electrode layer EL4 may not have a second recess RC2.

[0114] On the cell array region CAR, multiple vertical cell patterns VS can penetrate each of the third stack structure ST3 and the fourth stack structure ST4. The ends of the vertical cell patterns VS can be connected via a second layer bit line L2BL. The second layer bit line L2BL can extend in the second direction D2 and can be parallel to each other. In the second memory chip 300, the bit line connection line BLCP can be a lateral protrusion of the second layer bit line L2BL, or a conductive pattern located at a height different from the height of the second layer bit line L2BL.

[0115] On the cell array region CAR, the third cell through-hole CTHV3 can penetrate the third stacked structure ST3 and the second memory substrate 301, and the fourth cell through-hole CTHV4 can penetrate the fourth stacked structure ST4 and the second memory substrate 301. Both the third cell through-hole CTHV3 and the fourth cell through-hole CTHV4 can be electrically connected to one of the second layered bit lines L2BL via bit line connection lines BLCP. The second memory chip 300 may not include the edge through-holes ETHV1 and ETHV2 of the first memory chip 200.

[0116] On the second connection region CNR2, each of the third unit contact plugs CC3 can penetrate the planarized dielectric layer 20 and one or more inter-electrode dielectric layers 12, thereby contacting an end of one of the third electrode layers EL3. On the first connection region CNR1, each of the fourth unit contact plugs CC4 can penetrate the planarized dielectric layer 20 and one or more inter-electrode dielectric layers 12, thereby contacting an end of one of the fourth electrode layers EL4. Both the third unit contact plugs CC3 and the fourth unit contact plugs CC4 can be surrounded by a contact dielectric layer 14. Other structural features may be the same as or similar to those of the first memory chip 200.

[0117] Reference Figure 3A and Figure 5 The ends of the first stacked structures ST1 to ST4 may have a stepped shape, and the distance from the ends to the logic chip 100 gradually increases in the first direction D1. The first electrode layer EL1 of the first stacked structure ST1 included in the first memory chip 200 can be electrically connected to the corresponding first transmission transistor PST1 of the first decoder circuit section DCR1 through the first cell contact plug CC1, the first conductive pattern VPa, the first connection terminal 50a, and the logic connection terminal 150. For example, Figure 1A The ground selection lines included in the first memory block BLK1 (see...) Figure 1B GSL0 to GSL2), word lines (see GSL0 to GSL2) Figure 1B WL0 to WLn), pseudo-character lines (see WL0 to WLn) Figure 1B DWL) and serial select line (see DWL) and serial select line (see DWL) Figure 1BSSL11 to SSL13 and SSL21 to SSL23 can be electrically connected to the corresponding first transmission transistor PST1 of the first decoder circuit section DCR1.

[0118] Reference Figure 3B and Figure 5 The second electrode layer EL2 of the second stacked structure ST2 included in the first memory chip 200 can be electrically connected to the corresponding second transmission transistor PST2 of the second decoder circuit section DCR2 through the second unit contact plug CC2, the first conductive pattern VPa, the first connection terminal 50a, and the logic connection terminal 150. For example, Figure 1A The ground selection lines included in the second memory block BLK2 (see...) Figure 1B GSL0 to GSL2), word lines (see GSL0 to GSL2) Figure 1B WL0 to WLn), pseudo-character lines (see WL0 to WLn) Figure 1B DWL) and serial select line (see DWL) and serial select line (see DWL) Figure 1B SSL11 to SSL13 and SSL21 to SSL23 can be electrically connected to the corresponding second transmission transistor PST2 of the second decoder circuit section DCR2.

[0119] Return to reference Figure 3A and Figure 5 The third electrode layer EL3 of the third stacked structure ST3 included in the second memory chip 300 can be electrically connected to the corresponding third transmission transistor PST3 of the third decoder circuit section DCR3 through the third unit contact plug CC3, the first conductive pattern VPa, the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the first edge through-hole ETHV1, and the logic connection terminal 150. For example, Figure 1A The ground selection line included in the third memory block BLK3 (see...) Figure 1B GSL0 to GSL2), word lines (see GSL0 to GSL2) Figure 1B WL0 to WLn), pseudo-character lines (see WL0 to WLn) Figure 1B DWL) and serial select line (see DWL) and serial select line (see DWL) Figure 1B SSL11 to SSL13 and SSL21 to SSL23 can be electrically connected to the corresponding third transmission transistor PST3 in the third decoder circuit section DCR3.

[0120] Return to reference Figure 3B and Figure 5The fourth electrode layer EL4 of the fourth stacked structure ST4 included in the second memory chip 300 can be electrically connected to the corresponding fourth transmission transistor PST4 of the fourth decoder circuit section DCR4 through the fourth cell contact plug CC4, the first conductive pattern VPa, the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the second edge through-hole ETHV2, and the logic connection terminal 150. For example, Figure 1A The ground selection line included in the fourth memory block BLK4 (see...) Figure 1B GSL0 to GSL2), word lines (see GSL0 to GSL2) Figure 1B WL0 to WLn), pseudo-character lines (see WL0 to WLn) Figure 1B DWL) and serial select line (see DWL) and serial select line (see DWL) Figure 1B SSL11 to SSL13 and SSL21 to SSL23 can be electrically connected to the corresponding fourth transmission transistor PST4 in the fourth decoder circuit section DCR4.

[0121] In conventional three-dimensional semiconductor memory devices, stacked memory chips share a common transmission transistor. Therefore, the common transmission transistor applies electrical signals to all electrode layers of all memory blocks within the stacked memory chips. As a result, conventional three-dimensional semiconductor memory devices have increased memory blocks and tie-in blocks, leading to an overall increase in memory device size and a decrease in memory device performance. Furthermore, when all memory blocks are interconnected, it is possible to increase signal transmission paths, which may increase noise or potentially degrade semiconductor device performance.

[0122] According to some exemplary embodiments of the present invention, the three-dimensional semiconductor memory device 1000 can be configured to separately divide areas where decoder circuit portions DCR1 to DCR4 or transmission transistors PST1 to PST4 are provided, and can be configured to independently apply electrical signals to the first electrode layers EL1 to the fourth electrode layers EL4. According to this configuration, compared to a case where all memory blocks of a memory chip are connected to a single decoder circuit portion and operate simultaneously, an effect of increased actual storage space can be achieved. Therefore, some exemplary embodiments of the present invention enable a reduction in memory blocks and repair blocks, and a reduction in the size of all memory blocks and the semiconductor memory device, thereby improving the performance of the three-dimensional semiconductor memory device 1000 relative to conventional memory devices. Furthermore, some exemplary embodiments of the present invention can provide reduced signal noise relative to conventional memory devices, thus increasing the reliability of the semiconductor device.

[0123] The following will explain the manufacturing reference. Figures 2A to 5A method for constructing a three-dimensional semiconductor memory device 1000 is discussed. Logic chip 100, first memory chip 200, and second memory chip 300 can be manufactured independently of each other. Logic chip 100, first memory chip 200, and second memory chip 300 can be positioned to allow connection terminals 150, 50a, and 50b to correspond to each other, and then a thermoforming process can be performed to bond chips 100, 200, and 300 to each other. Although not shown, bumps or solder balls can be placed between connection terminals 150, 50a, and 50b, and in this case, passivation layers 242 and 342 can be spaced apart from each other. Although... Figure 5 It is not shown in the figure, but the additional first memory chip and second memory chip can be repeatedly and alternately stacked on the second memory chip 300.

[0124] Figure 6A The following is a demonstration Figure 1A A plan view of the logic chip. Figure 6B The following is a demonstration Figure 1A A plan view of the first memory chip. Figure 6C The following is a demonstration Figure 1A A plan view of the second memory chip. Figure 7A It shows along Figure 6B or Figure 6C A sectional view taken by line A-A'. Figure 7B It shows along Figure 6B or Figure 6C The sectional view taken by line B-B'. Figure 8 It shows Figure 1A Detailed perspective view.

[0125] Reference Figure 6AThe logic chip 100 may include a logic substrate 103. First decoder circuit portions DCR1 to fourth decoder circuit portions DCR4 and a page buffer circuit portion PB may be disposed on the logic substrate 103. In this specification, the term "decoder circuit portion" may be referred to as a decoder region. Alternatively, in this specification, the term "decoder circuit portion" may be referred to as a region provided with transfer transistors connected to the electrode layer. The first decoder circuit portions DCR1 to fourth decoder circuit portions DCR4 and the page buffer circuit portion PB may be spaced apart from each other in a first direction D1. The page buffer circuit portion PB may be disposed in the middle of the logic chip 100. The third decoder circuit portion DCR3 and the fourth decoder circuit portion DCR4 may be spaced apart from each other across the page buffer circuit portion PB. The first decoder circuit portion DCR1 may be disposed between the third decoder circuit portion DCR3 and the page buffer circuit portion PB. The second decoder circuit portion DCR2 may be disposed between the fourth decoder circuit portion DCR4 and the page buffer circuit portion PB. Other structural features may be the same as or similar to those discussed above.

[0126] Reference Figure 6B , Figure 7A , Figure 7B and Figure 8 The first memory chip 200 may include a first stacked structure ST1 and a second stacked structure ST2 spaced apart from each other in a second direction D2. The second stacked structure ST2 may have a shape obtained when the first stacked structure ST1 is rotated approximately 180 degrees. The first memory chip 200 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. In some example embodiments, the cell array region CAR may overlap with the page buffer circuit portion PB of the logic chip 100. The first connection region CNR1 may overlap with the second decoder circuit portion DCR2 and the fourth decoder circuit portion DCR4. The second connection region CNR2 may overlap with the first decoder circuit portion DCR1 and the third decoder circuit portion DCR3.

[0127] Although Figure 6B The first stacked structure ST1 on the first connection region CNR1 is omitted from the diagram, but the first stacked structure ST1 on the first connection region CNR1 may have the same or similar shape as the second stacked structure ST2 on the second connection region CNR2. Similarly, although Figure 6BThe second stacked structure ST2 on the first connection region CNR1 is omitted from the diagram, but the second stacked structure ST2 on the first connection region CNR1 may have the same or similar shape as the first stacked structure ST1 on the second connection region CNR2. The first stacked structure ST1 may have a first electrode layer EL1 and a first recess RC1 on the first connection region CNR1. The second stacked structure ST2 may have a second electrode layer EL2 and a second recess RC2 on the second connection region CNR2.

[0128] On the second connection region CNR2, the first electrode layer EL1 can be connected to the corresponding first unit contact plug CC1. The first unit contact plug CC1 can be connected to the corresponding first electrode connection line VPa_E1. On the first connection region CNR1, the second electrode layer EL2 can be connected to the corresponding second unit contact plug CC2. The second unit contact plug CC2 can be connected to the corresponding second electrode connection line VPa_E2. The first electrode connection line VPa_E1 and the second electrode connection line VPa_E2 can extend in the second direction D2. In the first memory chip 200, the first electrode connection line VPa_E1 and the second electrode connection line VPa_E2 can be located at the same height or a similar height as the first conductive pattern VPa. On the second connection region CNR2, the second edge through-hole ETHV2 can be closer to the second stacked structure ST2 than the first stacked structure ST1, and the second edge through-hole ETHV2 can be disposed outside the second stacked structure ST2. On the first connection region CNR1, the first edge through-hole ETHV1 can be closer to the first stacked structure ST1 than the second stacked structure ST2, and the first edge through-hole ETHV1 can be positioned outside the first stacked structure ST1. The first edge through-hole ETHV1 may not penetrate the first stacked structure ST1, and the second edge through-hole ETHV2 may not penetrate the second stacked structure ST2. The first edge through-hole ETHV1 and the second edge through-hole ETHV2 can penetrate the planarized dielectric layer 20 and the first memory substrate 201. Other structural features may be the same as or similar to those discussed above.

[0129] Reference Figure 6C , Figure 7A , Figure 7B and Figure 8 The second memory chip 300 may include a third stacked structure ST3 and a fourth stacked structure ST4 spaced apart from each other in the second direction D2. The third stacked structure ST3 may have a shape obtained when the fourth stacked structure ST4 is rotated approximately 180 degrees. Although Figure 6CThe third stacked structure ST3 on the first connection region CNR1 is omitted from the diagram, but the third stacked structure ST3 on the first connection region CNR1 may have the same or similar shape as the fourth stacked structure ST4 on the second connection region CNR2. Similarly, although Figure 6C The fourth stacked structure ST4 on the first connection region CNR1 is omitted from the diagram, but the fourth stacked structure ST4 on the first connection region CNR1 may have the same or similar shape as the third stacked structure ST3 on the second connection region CNR2. The third stacked structure ST3 may have a third electrode layer EL3 and a third recess RC3 on the first connection region CNR1. The fourth stacked structure ST4 may have a fourth electrode layer EL4 and a fourth recess RC4 on the second connection region CNR2.

[0130] On the second connection area CNR2, the third electrode layer EL3 can be connected to the corresponding third unit contact plug CC3. The third unit contact plug CC3 can be connected to the corresponding third electrode connection line VPa_E3. On the first connection area CNR1, the fourth electrode layer EL4 can be connected to the corresponding fourth unit contact plug CC4. The fourth unit contact plug CC4 can be connected to the corresponding fourth electrode connection line VPa_E4. The third electrode connection line VPa_E3 and the fourth electrode connection line VPa_E4 can extend in the second direction D2. In the second memory chip 300, the third electrode connection line VPa_E3 and the fourth electrode connection line VPa_E4 can be located at the same or similar height as the first conductive pattern VPa. The second edge through-hole ETHV2 can be electrically connected to the corresponding third electrode connection line VPa_E3. The first edge through-hole ETHV1 can be electrically connected to the corresponding fourth electrode connection line VPa_E4.

[0131] Reference Figure 8On the first connection region CNR1 and the second connection region CNR2, the third stacked structure ST3 may have a laterally protruding end beyond the opposite end of the first stacked structure ST1. On the first connection region CNR1 and the second connection region CNR2, the fourth stacked structure ST4 may have a laterally protruding end beyond the opposite end of the second stacked structure ST2. The third electrode layer EL3 and the fourth electrode layer EL4 may be longer than the first electrode layer EL1 and the second electrode layer EL2 in the first direction D1. Each of the first stacked structure ST1 and the second stacked structure ST2 may have a first maximum width MAXW1 parallel to the first direction D1 (as described herein, maximum width may refer to an upper limit width). Each of the third stacked structure ST3 and the fourth stacked structure ST4 may have a second maximum width MAXW2 parallel to the first direction D1. The second maximum width MAXW2 may be greater than the first maximum width MAXW1. Each of the third stacked structure ST3 and the fourth stacked structure ST4 may have a minimum width parallel to the first direction D1 (as described herein, minimum width may refer to a lower limit width), which is greater than the first maximum width MAXW1. Other structural features may be the same as or similar to those discussed above.

[0132] Reference Figure 7A , Figure 7B and Figure 8 The first electrode layer EL1 of the first stacked structure ST1 included in the first memory chip 200 can be electrically connected to the corresponding first transmission transistor PST1 of the first decoder circuit part DCR1 through the first unit contact plug CC1, the first electrode connection line VPa_E1, the first connection terminal 50a and the logic connection terminal 150.

[0133] Return to reference Figure 8 The second electrode layer EL2 of the second stacked structure ST2 included in the first memory chip 200 can be electrically connected to the corresponding second transmission transistor PST2 of the second decoder circuit section DCR2 through the second unit contact plug CC2, the second electrode connection line VPa_E2, the first connection terminal 50a and the logic connection terminal 150.

[0134] Return to reference Figure 7A , Figure 7B and Figure 8 The third electrode layer EL3 of the third stacked structure ST3 included in the second memory chip 300 can be electrically connected to the corresponding third transmission transistor PST3 of the third decoder circuit section DCR3 through the third unit contact plug CC3, the third electrode connection line VPa_E3, the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the second edge through-hole ETHV2 and the logic connection terminal 150.

[0135] Refer to Figure 8 The fourth electrode layer EL4 of the fourth stacked structure ST4 included in the second memory chip 300 can be electrically connected to the corresponding fourth transmission transistor PST4 of the fourth decoder circuit section DCR4 through the fourth unit contact plug CC4, the fourth electrode connection line VPa_E4, the first connection terminal 50a, the second conductive pattern VPb, the second connection terminal 50b, the first edge through-hole ETHV1 and the logic connection terminal 150.

[0136] Figure 9A The following is a demonstration Figure 1A A plan view of the first memory chip. Figure 9B The following is a demonstration Figure 1A A plan view of the second memory chip. Figure 10 It shows along Figure 9A or Figure 9B The sectional view taken by line B-B'. Figure 11 It shows Figure 1A Detailed perspective view. Figure 11 A simplified shape of the stacked structure is shown. Additionally, for clarity, Figure 11 Only one of the multiple contact plugs and one of the multiple through-holes is shown as an example.

[0137] Along Figure 9A or Figure 9B The cross section intercepted by line A-A' can be compared with... Figure 7A Their cross-sections are the same or similar.

[0138] Reference Figures 9A to 11 The first memory chip 200 may further include a first layered edge through-hole L1ETHV. On the second connection region CNR2 of the first memory chip 200, the first electrode connection line VPa_E1 may have an end that contacts one of the first layered edge through-holes L1ETHV. The first layered edge through-hole L1ETHV may be disposed in a second recess RC2. The first layered edge through-hole L1ETHV may be spaced apart from the second edge through-hole ETHV2.

[0139] On the first connection area CNR1 of the first memory chip 200, the second electrode connection line VPa_E2 may have an end that contacts another of the first layered edge through-hole members L1ETHV. The first layered edge through-hole member L1ETHV may be disposed in the first recess RC1. The first layered edge through-hole member L1ETHV may be spaced apart from the first edge through-hole member ETHV1.

[0140] The third electrode layer EL3 of the third stacked structure ST3 included in the second memory chip 300 may have a third recess RC3 on the first connection region CNR1. The width of the third recess RC3 parallel to the first direction D1 may be greater than the width of the first recess RC1 of the first electrode layer EL1 included in the first stacked structure ST1 parallel to the first direction D1. The fourth electrode layer EL4 of the fourth stacked structure ST4 may have a fourth recess RC4 on the second connection region CNR2. The width of the fourth recess RC4 parallel to the first direction D1 may be greater than the width of the second recess RC2 of the second electrode layer EL2 included in the second stacked structure ST2 parallel to the first direction D1.

[0141] The second memory chip 300 may further include a second layered edge through-hole L2ETHV. On the second connection region CNR2 of the second memory chip 300, the third electrode connection line VPa_E3 may have an end that contacts one of the second layered edge through-holes L2ETHV. The second layered edge through-hole L2ETHV may be disposed in a fourth recess RC4. The second layered edge through-hole L2ETHV may be spaced apart from the third cell contact plug CC3.

[0142] On the first connection area CNR1 of the second memory chip 300, the fourth electrode connection line VPa_E4 may have an end that contacts one of the second layered edge through-pieces L2ETHV. The second layered edge through-pieces L2ETHV may be disposed in the third recess RC3. Other structural features may be the same as or similar to those discussed above.

[0143] The first layered edge pass-through L1ETHV and the second layered edge pass-through L2ETHV can be configured to allow the first electrode layer EL1 to the fourth electrode layer EL4 of the first stacked structure ST1 to the fourth stacked structure ST4 to be connected to at least one memory chip or wiring additionally disposed on the second memory chip 300. The first layered edge pass-through L1ETHV and the second layered edge pass-through L2ETHV can be used to change the interconnection relationship of the three-dimensional semiconductor memory device in different ways.

[0144] Figure 12 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown. Figure 13A It shows along Figure 12 A sectional view taken by line A-A'. Figure 13B It shows along Figure 12 The sectional view taken by line B-B'.

[0145] Reference Figure 12 , Figure 13A and Figure 13BThe logic chip 100 may include a first decoder circuit section DCR1 to a sixth decoder circuit section DCR6 and a page buffer circuit section PB. The first decoder circuit sections DCR1 to DCR6 and the page buffer circuit section PB may be spaced apart from each other in a first direction D1. The page buffer circuit section PB may be disposed in the middle of the logic chip 100. The sixth decoder circuit section DCR6 and the fifth decoder circuit section DCR5 may be spaced apart from each other across the page buffer circuit section PB. The fourth decoder circuit section DCR4 may be disposed between the sixth decoder circuit section DCR6 and the page buffer circuit section PB. The second decoder circuit section DCR2 may be disposed between the fourth decoder circuit section DCR4 and the page buffer circuit section PB. The third decoder circuit section DCR3 may be disposed between the fifth decoder circuit section DCR5 and the page buffer circuit section PB. The first decoder circuit section DCR1 may be disposed between the third decoder circuit section DCR3 and the page buffer circuit section PB.

[0146] and Figure 2B As shown in the illustration, each of the first to third memory chips 200, 300, and 400 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. In some example embodiments, the cell array region CAR may overlap with the page buffer circuit portion PB of the logic chip 100. The first connection region CNR1 may overlap with the second decoder circuit portion DCR2, the fourth decoder circuit portion DCR4, and the sixth decoder circuit portion DCR6. The second connection region CNR2 may overlap with the first decoder circuit portion DCR1, the third decoder circuit portion DCR3, and the fifth decoder circuit portion DCR5.

[0147] A third memory chip 400 may be disposed on the second memory chip 300. The third memory chip 400 may include a fifth stacked structure ST5 and a sixth stacked structure ST6 spaced apart from each other in the second direction D2. The sixth stacked structure ST6 may have a shape obtained when the fifth stacked structure ST5 is rotated approximately 180 degrees. The fifth stacked structure ST5 may include a fifth electrode layer EL5 and an inter-electrode dielectric layer 12 between the fifth electrode layers EL5. The sixth stacked structure ST6 may include a sixth electrode layer EL6 and an inter-electrode dielectric layer 12 between the sixth electrode layers EL6.

[0148] The maximum width of each of the fifth stack structure ST5 and the sixth stack structure ST6 parallel to the first direction D1 can be greater than the maximum width of each of the third stack structure ST3 and the fourth stack structure ST4 parallel to the first direction D1. The minimum width of each of the fifth stack structure ST5 and the sixth stack structure ST6 parallel to the first direction D1 can be greater than the maximum width of each of the third stack structure ST3 and the fourth stack structure ST4 parallel to the first direction D1.

[0149] The fifth electrode layer EL5 of the fifth stacked structure ST5 may have a fifth recess RC5 on the first connection region CNR1. The sixth electrode layer EL6 of the sixth stacked structure ST6 may have a sixth recess RC6 on the second connection region CNR2.

[0150] On the cell array region CAR, multiple cell vertical patterns VS can penetrate each of the fifth stack structure ST5 and the sixth stack structure ST6. The third layer bit line L3BL can connect the ends of the cell vertical patterns VS. A fifth cell through-hole CTHV5 penetrating the fifth stack structure ST5 can be disposed between the cell vertical patterns VS. The fifth cell through-hole CTHV5 can be electrically connected to one of the third layer bit lines L3BL. A sixth cell through-hole CTHV6 penetrating the sixth stack structure ST6 can be disposed between the cell vertical patterns VS. The sixth cell through-hole CTHV6 can be electrically connected to one of the third layer bit lines L3BL.

[0151] On the second connection area CNR2, the fifth electrode layer EL5 can be connected to the corresponding fifth unit contact plug CC5. The fifth unit contact plug CC5 can be connected to the corresponding fifth electrode connection line VPa_E5. On the first connection area CNR1, the sixth electrode layer EL6 can be connected to the corresponding sixth unit contact plug. The sixth unit contact plug can be connected to the corresponding sixth electrode connection line (see...). Figure 14 (VPa_E6). According to some example embodiments, the fifth unit contact plug CC5 and the sixth unit contact plug CC6 may correspond to the third unit contact plug CC3 and the fourth unit contact plug CC4 described above.

[0152] The first memory chip 200 may include first layered edge pass-throughs L1ETHV. Some of the first layered edge pass-throughs L1ETHV may be related to a reference. Figures 2A to 11 The first edge pass-through element ETHV1 and the second edge pass-through element ETHV2 discussed correspond to each other. The second memory chip 300 may include a second layered edge pass-through element L2ETHV.

[0153] The first electrode layer EL1 of the first stacked structure ST1 included in the first memory chip 200 can be electrically connected to the corresponding first transmission transistor of the first decoder circuit section DCR1 through the first unit contact plug CC1 and the first electrode connection line VPa_E1. The second electrode layer EL2 of the second stacked structure ST2 included in the first memory chip 200 can be electrically connected to the corresponding second transmission transistor of the second decoder circuit section DCR2 through the second unit contact plug and the second electrode connection line.

[0154] The third electrode layer EL3 of the third stacked structure ST3 included in the second memory chip 300 can be electrically connected to the corresponding third transmission transistor of the third decoder circuit section DCR3 through the third unit contact plug CC3, the third electrode connection line VPa_E3, and some of the first layered edge through-holes L1ETHV. The fourth electrode layer EL4 of the fourth stacked structure ST4 included in the second memory chip 300 can be electrically connected to the corresponding fourth transmission transistor of the fourth decoder circuit section DCR4 through the fourth unit contact plug, the fourth electrode connection line, and some of the first layered edge through-holes L1ETHV.

[0155] The fifth electrode layer EL5 of the fifth stacked structure ST5 included in the third memory chip 400 can be electrically connected to the corresponding fifth transmission transistor of the fifth decoder circuit section DCR5 through the fifth unit contact plug CC5, the fifth electrode connection line VPa_E5, some of the second layer edge through-holes L2ETHV and some of the first layer edge through-holes L1ETHV. The sixth electrode layer EL6 of the sixth stacked structure ST6 included in the third memory chip 400 can be electrically connected to the corresponding sixth transmission transistor of the sixth decoder circuit section DCR6 through the sixth unit contact plug, the sixth electrode connection line VPa_E6, some of the second layer edge through-holes L2ETHV and some of the first layer edge through-holes L1ETHV.

[0156] Figure 14 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown. Figure 15 It shows along Figure 14 A sectional view taken along line B-B'. Figure 14 The sectional view intercepted by line A-A' can be compared with Figure 13B The same or similar.

[0157] Reference Figure 13B , Figure 14 and Figure 15 The first memory chip 200 may include a plurality of first layered edge through-holes L1ETHV penetrating each of the first stacked structure ST1 and the second stacked structure ST2. The second memory chip 300 may include a plurality of second layered edge through-holes L2ETHV penetrating each of the third stacked structure ST3 and the fourth stacked structure ST4. The third memory chip 400 may include a plurality of third layered edge through-holes L3ETHV penetrating each of the fifth stacked structure ST5 and the sixth stacked structure ST6. The first layered edge through-holes L1ETHV, the second layered edge through-holes L2ETHV, and the third layered edge through-holes L3ETHV may be configured to allow the first stacked structures ST1 to the sixth stacked structures ST6 to be connected to at least one memory chip or wiring additionally disposed on the third memory chip 400. Other structural features may be referenced above. Figures 10 to 12 The structural features discussed are the same or similar.

[0158] Figure 16 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0159] Reference Figure 16 The first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 can be sequentially stacked on the logic chip 100. The logic chip 100 may include a first decoder circuit section DCR1 to an eighth decoder circuit section DCR8 and a page buffer circuit section PB. The first decoder circuit sections DCR1 to DCR8 and the page buffer circuit section PB can be spaced apart from each other in a first direction D1. The page buffer circuit section PB can be disposed in the middle of the logic chip 100. The second decoder circuit section DCR2, the fourth decoder circuit section DCR4, the sixth decoder circuit section DCR6, and the eighth decoder circuit section DCR8 can be sequentially moved away from one side of the page buffer circuit section PB. The first decoder circuit section DCR1, the third decoder circuit section DCR3, the fifth decoder circuit section DCR5, and the seventh decoder circuit section DCR7 can be sequentially moved away from the other side of the page buffer circuit section PB.

[0160] and Figure 2BSimilar to those shown, each of the first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. In some example embodiments, the cell array region CAR may overlap with the page buffer circuit portion PB of the logic chip 100. The first connection region CNR1 may overlap with the second decoder circuit portion DCR2, the fourth decoder circuit portion DCR4, the sixth decoder circuit portion DCR6, and the eighth decoder circuit portion DCR8. The second connection region CNR2 may overlap with the first decoder circuit portion DCR1, the third decoder circuit portion DCR3, the fifth decoder circuit portion DCR5, and the seventh decoder circuit portion DCR7.

[0161] The fourth memory chip 500 may include a seventh stacked structure ST7 and an eighth stacked structure ST8 spaced apart from each other in the second direction D2. The minimum width of each of the seventh stacked structure ST7 and the eighth stacked structure ST8 parallel to the first direction D1 may be greater than the maximum width of each of the fifth stacked structure ST5 and the sixth stacked structure ST6 parallel to the first direction D1. The first stacked structure ST1, the third stacked structure ST3, the fifth stacked structure ST5, and the seventh stacked structure ST7 may include recessed RCs in the first connection region CNR1. The second stacked structure ST2, the fourth stacked structure ST4, the sixth stacked structure ST6, and the eighth stacked structure ST8 may include recessed RCs in the second connection region CNR2. Some of the recessed RCs may be related to a reference... Figures 2A to 15 The first recess RC1 to the sixth recess RC6 are discussed. The fourth memory chip 500 may also include a fourth layered edge pass-through L4ETHV. The electrode layers of the first stacked structures ST1 to the eighth stacked structures ST8 can be electrically connected to the first decoder circuit section DCR1 to the eighth decoder circuit section DCR8 through the cell contact plug CC, the first layered electrode connection line VPa_L1 to the fourth layered electrode connection line VPa_L4, and the edge pass-through L1ETHV to L4ETHV. The detailed shape of the cell contact plug CC can be compared with the reference. Figure 3A , Figure 3B , Figure 7A or Figure 13A The unit contact plugs CC1 to CC6 discussed have the same or similar shapes. The detailed shapes of the edge through-hole pieces L1ETHV to L4ETHV can be found in the reference. Figure 3A , Figure 7A or Figure 10 The edge through-pieces ETHV1 and ETHV2 discussed have the same or similar shapes.

[0162] Figure 17 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0163] Reference Figure 17 The first memory chip 200, the second memory chip 300, and the third memory chip 400 can be stacked sequentially on the logic chip 100. The logic chip 100 may include a first decoder circuit section DCR1 to a sixth decoder circuit section DCR6 and a page buffer circuit section PB. The page buffer circuit section PB can be positioned adjacent to the center of the logic chip 100. The fifth decoder circuit section DCR5 and the sixth decoder circuit section DCR6 can be positioned adjacent to one side of the page buffer circuit section PB. The fifth decoder circuit section DCR5 and the sixth decoder circuit section DCR6 can be arranged side-by-side along the second direction D2. The third decoder circuit section DCR3 and the fourth decoder circuit section DCR4 can be spaced apart from the page buffer circuit section PB. The third decoder circuit section DCR3 and the fourth decoder circuit section DCR4 can be arranged side-by-side along the second direction D2. The first decoder circuit section DCR1 can be arranged between the third decoder circuit section DCR3 and the page buffer circuit section PB. The second decoder circuit section DCR2 can be arranged between the fourth decoder circuit section DCR4 and the page buffer circuit section PB.

[0164] and Figure 2B As shown, each of the first memory chip 200, the second memory chip 300, and the third memory chip 400 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. In some example embodiments, the cell array region CAR may overlap with the page buffer circuit portion PB of the logic chip 100. The first connection region CNR1 may overlap with the fifth decoder circuit portion DCR5 and the sixth decoder circuit portion DCR6. The second connection region CNR2 may overlap with the first decoder circuit portions DCR1 to the fourth decoder circuit portions DCR4.

[0165] The width of each of the first stacked structures ST1 and ST2 included in the first memory chip 200 may be the same as or similar to the width of each of the fifth stacked structures ST5 and ST6 included in the third memory chip 400. The maximum width of the third stacked structures ST3 and ST4 included in the second memory chip 300 may be greater than the maximum width of each of the first stacked structures ST1 and ST2 included in the first memory chip 200. The third stacked structures ST3 and ST4 of the second memory chip 300 may laterally protrude beyond the first stacked structures ST1 and ST2 of the first memory chip 200. On the first connection area CNR1, the ends of the first stacked structures ST1, ST3, and ST5 may be aligned with each other.

[0166] All of the first stacked structures ST1 to the fourth stacked structure ST4 may include recessed RC on the first connection area CNR1. The fifth stacked structure ST5 and the sixth stacked structure ST6 may not have recessed RC. The electrode layers of the first stacked structures ST1 to the sixth stacked structure ST6 can be electrically connected to the first decoder circuit section DCR1 to the sixth decoder circuit section DCR6 through the cell contact plug CC and the edge through-holes L1ETHV and L2ETHV.

[0167] Figure 18 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0168] Reference Figure 18 The first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 can be stacked sequentially on the logic chip 100. The logic chip 100 may include a first decoder circuit section DCR1 to a fourth decoder circuit section DCR4 and a page buffer circuit section PB. The page buffer circuit section PB may be located in the middle of the logic chip 100, or adjacent to the middle. The second decoder circuit section DCR2 and the fourth decoder circuit section DCR4 can be sequentially moved away from one side of the page buffer circuit section PB. The first decoder circuit section DCR1 and the third decoder circuit section DCR3 can be sequentially moved away from the other side of the page buffer circuit section PB.

[0169] and Figure 2BAs shown, each of the first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. The first connection region CNR1 may overlap with the second decoder circuit portion DCR2 and the fourth decoder circuit portion DCR4. The second connection region CNR2 may overlap with the first decoder circuit portion DCR1 and the third decoder circuit portion DCR3. The first memory chip 200 may include a first stacking structure ST1 and a second stacking structure ST2, whose structures are the same as or similar to the fifth stacking structure ST5 and the sixth stacking structure ST6 of the third memory chip 400. The second memory chip 300 may include a third stacking structure ST3 and a fourth stacking structure ST4, whose structures are the same as or similar to the seventh stacking structure ST7 and the eighth stacking structure ST8 of the fourth memory chip 500. The first stacked structure ST1 and the fifth stacked structure ST5 may each include a first electrode layer EL1 and a fifth electrode layer EL5. The first electrode layer EL1 and the fifth electrode layer EL5 are connected to the first decoder circuit section DCR1 via a cell contact plug CC, a first layered electrode connection line VPa_L1 and a third layered electrode connection line VPa_L3, and a first layered edge pass-through L1ETHV and a second layered edge pass-through L2ETHV. For example, the first stacked structure ST1 and the fifth stacked structure ST5 can operate simultaneously or concurrently like a memory block. The third stacked structure ST3 and the seventh stacked structure ST7 may each include a third electrode layer EL3 and a seventh electrode layer EL7. The third electrode layer EL3 and the seventh electrode layer EL7 are connected to the third decoder circuit section DCR3 via a cell contact plug CC, a second layered electrode connection line VPa_L2 and a fourth layered electrode connection line VPa_L4, and a first layered edge pass-through L1ETHV, a second layered edge pass-through L2ETHV, and a third layered edge pass-through L3ETHV. For example, the third stack structure ST3 and the seventh stack structure ST7 can operate simultaneously or concurrently like a memory block.

[0170] Similarly, the second stacked structure ST2 and the sixth stacked structure ST6 may each include a second electrode layer EL2 and a sixth electrode layer EL6, respectively. The second electrode layer EL2 and the sixth electrode layer EL6 are connected to the second decoder circuit section DCR2 via cell contact plugs CC and first layer edge pass-throughs L1ETHV and second layer edge pass-throughs L2ETHV. For example, the second stacked structure ST2 and the sixth stacked structure ST6 can operate simultaneously or concurrently like a memory block. The fourth stacked structure ST4 and the eighth stacked structure ST8 may each include a fourth electrode layer EL4 and an eighth electrode layer EL8, respectively. The fourth electrode layer EL4 and the eighth electrode layer EL8 are connected to the fourth decoder circuit section DCR4 via cell contact plugs CC and first layer edge pass-throughs L1ETHV, second layer edge pass-throughs L2ETHV, and third layer edge pass-throughs L3ETHV. For example, the fourth stacked structure ST4 and the eighth stacked structure ST8 can operate simultaneously or concurrently like a memory block. The semiconductor memory device according to some example embodiments can be configured such that a decoder circuit section is connected to two stacked structures, thereby reducing the number of decoder circuit sections and reducing the size of the logic chip 100.

[0171] Furthermore, when additional memory chips are stacked on Figure 18 When the fourth memory chip 500 is used, the stacked structure of odd-numbered memory chips can be connected to each other, and the stacked structure of even-numbered memory chips can be connected to each other.

[0172] Figure 19 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0173] Reference Figure 19 The first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 can be stacked sequentially on the logic chip 100. The logic chip 100 may include a first decoder circuit section DCR1 to an eighth decoder circuit section DCR8 and a page buffer circuit section PB. The page buffer circuit section PB may be disposed in the middle of the logic chip 100 or placed adjacent to the middle. The fourth decoder circuit section DCR4 and the eighth decoder circuit section DCR8 may be spaced apart from one side of the page buffer circuit section PB and may be arranged side by side in the second direction D2. The second decoder circuit section DCR2 may be disposed between the fourth decoder circuit section DCR4 and the page buffer circuit section PB on the same side. The sixth decoder circuit section DCR6 may be disposed between the eighth decoder circuit section DCR8 and the page buffer circuit section PB on the same side.

[0174] The third decoder circuit section DCR3 and the seventh decoder circuit section DCR7 can be spaced apart from the other side of the page buffer circuit section PB, and can be arranged side by side in the second direction D2. The first decoder circuit section DCR1 can be disposed between the third decoder circuit section DCR3 and the other side of the page buffer circuit section PB, wherein the other side is opposite to the first side of the page buffer circuit section PB. The fifth decoder circuit section DCR5 can be disposed between the seventh decoder circuit section DCR7 and the other side of the page buffer circuit section PB.

[0175] and Figure 2B As shown, each of the first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. The first connection region CNR1 may overlap with the second decoder circuit portion DCR2, the fourth decoder circuit portion DCR4, the sixth decoder circuit portion DCR6, and the eighth decoder circuit portion DCR8. The second connection region CNR2 may overlap with the first decoder circuit portion DCR1, the third decoder circuit portion DCR3, the fifth decoder circuit portion DCR5, and the seventh decoder circuit portion DCR7.

[0176] The first stacked structure ST1, the third stacked structure ST3, the fifth stacked structure ST5, and the seventh stacked structure ST7 may have recessed RC on the first connection area CNR1. The second stacked structure ST2, the fourth stacked structure ST4, the sixth stacked structure ST6, and the eighth stacked structure ST8 may have recessed RC on the second connection area CNR2. The first stacked structure ST1 to the eighth stacked structure ST8 may be connected to the first decoder circuit section DCR1 to the eighth decoder circuit section DCR8 via cell contact plugs CC and edge through-holes L1ETHV to L3ETHV.

[0177] Figure 20 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0178] Reference Figure 20The first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 can be sequentially stacked on the logic chip 100. The first memory chip 200 may include a first cell through-hole component CTHV1 and a first layered edge through-hole component L1ETHV. The second memory chip 300 may include a third cell through-hole component CTHV3 and a second layered edge through-hole component L2ETHV. The third memory chip 400 may include a fifth cell through-hole component CTHV5 and a third layered edge through-hole component L3ETHV. For example... Figure 20 As shown, when no additional memory chip is provided on the fourth memory chip 500, or when no additional electrical connection is required on the top surface of the fourth memory chip 500, the fourth memory chip 500 may not include cell through-holes or edge through-holes. Other structural features may be the same as or similar to those discussed above.

[0179] Figure 21 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0180] Reference Figure 21 The first memory chip 200, the second memory chip 300, and the third memory chip 400 can be stacked sequentially on the logic chip 100. The logic chip 100 may include a first decoder circuit section DCR1 to a sixth decoder circuit section DCR6 and a page buffer circuit section PB. The page buffer circuit section PB may be disposed in the middle of the logic chip 100 or placed adjacent to the middle. The second decoder circuit section DCR2, the fourth decoder circuit section DCR4, and the sixth decoder circuit section DCR6 may be adjacent to one side of the page buffer circuit section PB. The second decoder circuit section DCR2 may be located below the far end of the second stack structure ST2. The second decoder circuit section DCR2, the fourth decoder circuit section DCR4, and the sixth decoder circuit section DCR6 may be arranged sequentially side by side along a direction opposite to the second direction D2. The first decoder circuit section DCR1, the third decoder circuit section DCR3, and the fifth decoder circuit section DCR5 may be adjacent to the other side of the page buffer circuit section PB. The first decoder circuit section DCR1, the third decoder circuit section DCR3, and the fifth decoder circuit section DCR5 can be arranged side by side in sequence along the second direction D2.

[0181] and Figure 2BAs shown, each of the first memory chip 200, the second memory chip 300, and the third memory chip 400 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. The first connection region CNR1 may overlap with the second decoder circuit portion DCR2, the fourth decoder circuit portion DCR4, and the sixth decoder circuit portion DCR6. The second connection region CNR2 may overlap with the first decoder circuit portion DCR1, the third decoder circuit portion DCR3, and the fifth decoder circuit portion DCR5.

[0182] The first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5 may include recessed RCs on the first connection area CNR1 and may have the same or similar shapes. The second stacked structure ST2, the fourth stacked structure ST4, and the sixth stacked structure ST6 may include recessed RCs on the second connection area CNR2 and may have the same or similar shapes. The shapes of the second stacked structure ST2, the fourth stacked structure ST4, and the sixth stacked structure ST6 may be obtained by rotating the first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5 by approximately 180 degrees. The first stacked structure ST1 to the sixth stacked structure ST6 may be connected to the first decoder circuit section DCR1 to the sixth decoder circuit section DCR6 respectively via cell contact plugs CC and edge through-holes L1ETHV and L2ETHV. A recessed RC may have a first layered edge through-hole L1ETHV, which is connected to each of the other different stacked structures (e.g., the first stacked structure ST1 and the third stacked structure ST3).

[0183] Figure 22A A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown. Figure 22B The following is a demonstration Figure 22A A plan view of the logic chips included in a three-dimensional semiconductor memory device. Figure 22C The following is a demonstration Figure 22A A plan view of the first memory chip and the third memory chip included in the three-dimensional semiconductor memory device. Figure 22D The following is a demonstration Figure 22A A plan view of the second and fourth memory chips included in the three-dimensional semiconductor memory device. Figure 22E The following is a demonstration Figure 22C An enlarged view of block P4. Figure 22F The following is a demonstration Figure 22B An enlarged plan view of the first decoder circuit section.

[0184] Reference Figures 22A to 22F The first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 can be stacked sequentially on the logic chip 100. The logic chip 100 may include a first decoder circuit section DCR1 to a fourth decoder circuit section DCR4 and a page buffer circuit section PB. The page buffer circuit section PB may be disposed in the middle of the logic chip 100 or placed adjacent to the middle. The first decoder circuit section DCR1 and the fourth decoder circuit section DCR4 may be adjacent to one side of the page buffer circuit section PB. The first decoder circuit section DCR1 and the fourth decoder circuit section DCR4 may be sequentially arranged side-by-side in the second direction D2. The second decoder circuit section DCR2 and the third decoder circuit section DCR3 may be adjacent to the other side of the page buffer circuit section PB. The second decoder circuit section DCR2 and the third decoder circuit section DCR3 may be sequentially arranged side-by-side in a direction opposite to the second direction D2.

[0185] and Figure 2B As shown, each of the first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. The first connection region CNR1 may overlap with the first decoder circuit portion DCR1 and the fourth decoder circuit portion DCR4. The second connection region CNR2 may overlap with the second decoder circuit portion DCR2 and the third decoder circuit portion DCR3.

[0186] The first electrode layer EL1 of the first stacked structure ST1 included in the first memory chip 200 can be electrically connected to the first decoder circuit section DCR1 through the first unit contact plug CC1 and the first layered electrode connection line VPa_L1. The fifth electrode layer EL5 of the fifth stacked structure ST5 included in the third memory chip 400 can be electrically connected to the first decoder circuit section DCR1 through the fifth unit contact plug CC5, the third layered electrode connection line VPa_L3, the second layered edge through-hole L2ETHV and the first layered edge through-hole L1ETHV.

[0187] Similarly, the second electrode layer EL2 of the second stacked structure ST2 included in the first memory chip 200 can be electrically connected to the second decoder circuit section DCR2, and the sixth electrode layer EL6 of the sixth stacked structure ST6 included in the third memory chip 400 can be electrically connected to the second decoder circuit section DCR2.

[0188] The fourth electrode layer EL4 of the fourth stacked structure ST4 included in the second memory chip 300 can be electrically connected to the fourth decoder circuit section DCR4 via the fourth unit contact plug CC4, the second layered electrode connection line VPa_L2, and the first layered edge pass-through L1ETHV. The eighth electrode layer EL8 of the eighth stacked structure ST8 included in the fourth memory chip 500 can be electrically connected to the fourth decoder circuit section DCR4 via the eighth unit contact plug CC8, the fourth layered electrode connection line VPa_L4, the third layered edge pass-through L3ETHV, the second layered edge pass-through L2ETHV, and the first layered edge pass-through L1ETHV.

[0189] Similarly, the third electrode layer EL3 of the third stacked structure ST3 included in the second memory chip 300 can be electrically connected to the third decoder circuit section DCR3, and the seventh electrode layer EL7 of the seventh stacked structure ST7 included in the fourth memory chip 500 can be electrically connected to the third decoder circuit section DCR3.

[0190] Reference Figure 22C , Figure 22D and Figure 22E Electrode connection lines VPa_L1 to VPa_L4 allow the electrode layers EL1 to EL8 of the stacked structures ST1 to ST8 to be connected to the corresponding edge through-holes L1ETHV to L4ETHV. When viewed in a plan view, electrode connection lines VPa_L1 to VPa_L4 can be I-shaped, L-shaped, C-shaped, N-shaped, or W-shaped, but any other suitable shape is acceptable as needed.

[0191] Reference Figure 22A and Figure 22E The first electrode layer EL1 may include the first string select lines SSL1 to the fourth string select lines SSL4 closest to the logic chip 100. The first string select lines SSL1 to the fourth string select lines SSL4 may be spaced apart from each other in the second direction D2. The first electrode layer EL1 may include the ground select line GSL furthest from the logic chip 100. The first electrode layer EL1 may include word lines WL0 to WLn located between the ground select line GSL and the string select lines SSL1 to SSL4. The string select lines SSL1 to SSL4, the word lines WL0 to WLn, and the ground select line GSL may be connected one-to-one via the first layered electrode connection line VPa_L1 and the first layered edge pass-through L1ETHV.

[0192] Reference Figure 22F For example, the first decoder circuit section DCR1 may include transmission transistors PST11 to PST19. The active region AR may be disposed on a logic substrate (see...). Figure 3ADevice isolation layer 105 is defined in (103). Transmission transistors PST11 to PST19 can be disposed on the corresponding active regions AR. The first decoder circuit portion DCR1 can be configured such that the source / drain regions of the active regions AR are located on one side of the active regions AR of the corresponding one of the transmission transistors PST11 to PST19. First peripheral contact plugs PCT1 to ninth peripheral contact plugs PCT9 can be disposed on the corresponding source / drain regions.

[0193] Reference Figure 22E and Figure 22F The first select line SSL1 can be electrically connected to the source / drain region of the transmission transistor PST11 via one of the first unit contact plugs CC1, one of the first layered electrode connection lines VPa_L1, and the first peripheral contact plug PCT1. Similarly, the second select lines SSL2 to the fourth select lines SSL4 can be electrically connected to the corresponding source / drain regions of the transmission transistors PST12 to PST14 via the second peripheral contact plugs PCT2 to the fourth peripheral contact plug PCT4. Similarly, the word lines WL0 to WLn can be electrically connected to the corresponding source / drain regions of the transmission transistors PST15 to PST18 via the fifth peripheral contact plug PCT5 to the eighth peripheral contact plug PCT8. In addition, the ground select line GSL can be electrically connected to the source / drain region of the transmission transistor PST19 via the ninth peripheral contact plug PCT9.

[0194] Reference Figure 22C , Figure 22D and Figure 22E The fifth electrode layer EL5 may include serial select lines SSL1 to SSL4, word lines WL0 to WLn, and ground select line GSL. The fifth electrode layer EL5 (e.g., the serial select lines SSL1 to SSL4, word lines WL0 to WLn, and ground select line GSL included in the fifth stack structure ST5) can be connected one-to-one to the first peripheral contact plugs PCT1 to the ninth peripheral contact plugs PCT9 of the first decoder circuit section DCR1 through the fifth unit contact plug CC5, the third layer electrode connection line VPa_L3, and the third layer edge pass-through L3ETHV.

[0195] Similarly, the second electrode layer EL2 may include serial select lines SSL1 to SSL4, word lines WL0 to WLn, and ground select line GSL, and this description applies to the third electrode layers EL3 through the eighth electrode layers EL8. The serial select lines SSL1 to SSL4, word lines WL0 to WLn, and ground select line GSL included in the second electrode layer EL2 may be electrically connected to the corresponding source / drain regions of the transmission transistors disposed on the second decoder circuit section DCR2, and this description applies to the sixth electrode layer EL6. The serial select lines SSL1 to SSL4, word lines WL0 to WLn, and ground select line GSL included in the third electrode layer EL3 may be electrically connected to the corresponding source / drain regions of the transmission transistors disposed on the third decoder circuit section DCR3, and this description applies to the seventh electrode layer EL7. The serial select lines SSL1 to SSL4, word lines WL0 to WLn, and ground select line GSL included in the fourth electrode layer EL4 can be electrically connected to the corresponding source / drain regions of the transmission transistors disposed on the fourth decoder circuit section DCR4, and this description also applies to the eighth electrode layer EL8.

[0196] Figure 23 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0197] Reference Figure 23 The first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 can be stacked sequentially on the logic chip 100. The logic chip 100 may include a first decoder circuit section DCR1 to an eighth decoder circuit section DCR8 and a page buffer circuit section PB. The page buffer circuit section PB may be disposed in the middle of the logic chip 100 or placed adjacent to the middle. The second decoder circuit section DCR2, the fourth decoder circuit section DCR4, the sixth decoder circuit section DCR6, and the eighth decoder circuit section DCR8 may be adjacent to one side of the page buffer circuit section PB. The second decoder circuit section DCR2, the fourth decoder circuit section DCR4, the sixth decoder circuit section DCR6, and the eighth decoder circuit section DCR8 may be arranged sequentially in a direction opposite to the second direction D2. The first decoder circuit section DCR1, the third decoder circuit section DCR3, the fifth decoder circuit section DCR5, and the seventh decoder circuit section DCR7 may be adjacent to the other side of the page buffer circuit section PB. The first decoder circuit section DCR1, the third decoder circuit section DCR3, the fifth decoder circuit section DCR5, and the seventh decoder circuit section DCR7 can be arranged sequentially in the second direction D2.

[0198] and Figure 2BSimilarly, each of the first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 may include a first connection region CNR1 and a second connection region CNR2 spaced apart from each other in the first direction D1, and may also include a cell array region CAR located between the first connection region CNR1 and the second connection region CNR2. The first connection region CNR1 may overlap with the second decoder circuit portion DCR2, the fourth decoder circuit portion DCR4, the sixth decoder circuit portion DCR6, and the eighth decoder circuit portion DCR8. The second connection region CNR2 may overlap with the first decoder circuit portion DCR1, the third decoder circuit portion DCR3, the fifth decoder circuit portion DCR5, and the seventh decoder circuit portion DCR7.

[0199] The first stack structure ST1 to the eighth stack structure ST8 can be connected to the first decoder circuit section DCR1 to the eighth decoder circuit section DCR8 via the cell contact plug CC and the edge through-hole L1ETHV to L3ETHV respectively.

[0200] Figure 24 and Figure 25 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0201] Reference Figure 24 The first memory chip 200, the second memory chip 300, the third memory chip 400, and the fourth memory chip 500 can be sequentially stacked on the logic chip 100. The logic chip 100 may include multiple page buffer circuit sections that are different from each other. One of the page buffer circuit sections may be a first page buffer circuit section PB1. The first page buffer circuit section PB1 may be different from the other page buffer circuit sections. The first memory chip 200 may include a first cell pass-through CTHV1 that penetrates the first stacked structure ST1. The second memory chip 300 may include a third cell pass-through CTHV3 that penetrates the third stacked structure ST3. The third memory chip 400 may include a fifth cell pass-through CTHV5 that penetrates the fifth stacked structure ST5. The fourth memory chip 500 may include a seventh cell pass-through CTHV7 that penetrates the seventh stacked structure ST7. The first unit through-hole component CTHV1, the third unit through-hole component CTHV3, the fifth unit through-hole component CTHV5, and the seventh unit through-hole component CTHV7 can be vertically overlapped and electrically connected to each other. The first unit through-hole component CTHV1, the third unit through-hole component CTHV3, the fifth unit through-hole component CTHV5, and the seventh unit through-hole component CTHV7 can be electrically connected to the bit line selection transistor PTR of the first page buffer circuit portion PB1 included in the logic chip 100.

[0202] The seventh unit through-hole component CTHV7 can be connected to the fourth bit line connection line BLCP4, which is electrically connected to one of the fourth layer bit lines L4BL. The third unit through-hole component CTHV3 can be connected to the second bit line connection line BLCP2, which is electrically connected to one of the second layer bit lines L2BL. On the other hand, the first unit through-hole component CTHV1, which is connected to the third unit through-hole component CTHV3, can be decoupled from the first layer bit line L1BL. Furthermore, the fifth unit through-hole component CTHV5, which is connected to the seventh unit through-hole component CTHV7, can be decoupled from the third layer bit line L3BL.

[0203] The semiconductor memory device according to some example embodiments can be configured such that the bit lines of the second memory chip 300 and the fourth memory chip 500 can be connected to the first page buffer circuit portion PB1. The bit lines of the first memory chip 200 and the third memory chip 400 may not be connected to the first page buffer circuit portion PB1, but to a page buffer circuit portion different from the first page buffer circuit portion PB1.

[0204] Alternatively, refer to Figure 25 The seventh cell pass-through CTHV7 of the fourth memory chip 500 can be electrically connected to only one of the fourth layer bit lines L4BL. The first cell pass-through CTHV1, third cell pass-through CTHV3, and fifth cell pass-through CTHV5 connected to the seventh cell pass-through CTHV7 can be left unconnected to any one of the first layer bit lines L1BL, second layer bit lines L2BL, and third layer bit lines L3BL. For example, only the fourth layer bit line L4BL of the fourth memory chip 500 can be electrically connected to the first page buffer circuit section PB1. The bit lines of the first memory chip 200, second memory chip 300, and third memory chip 400 can be left unconnected to the first page buffer circuit section PB1, but connected to a page buffer circuit section different from the first page buffer circuit section PB1.

[0205] like Figure 24 and Figure 25 As shown, when multiple memory chips are stacked, the connections between bit lines can be separated from each other to reduce the total resistance of each bit line and the parasitic capacitance between bit lines, which can lead to improved performance of the semiconductor memory device.

[0206] Figure 26 It shows along Figure 2B or Figure 2C A sectional view taken by line C-C'.

[0207] Reference Figure 26Each of the first stacked structures ST1 to the fourth stacked structure ST4 may include a first sub-stacked structure SBST1 and a second sub-stacked structure SBST2. The second sub-stacked structure SBST2 may be closer to the source layer SCL than the first sub-stacked structure SBST1. The first sub-stacked structure SBST1 may be closer to the logic chip 100 than the second sub-stacked structure SBST2. The inflection points (SIPs) of the sidewalls of the vertical patterns VS, CDVS, and EDVS may be adjacent to the boundary between the first sub-stacked structure SBST1 and the second sub-stacked structure SBST2. Additionally, the inflection points of the sidewalls of the gate dielectric layer GO may be adjacent to the boundary between the first sub-stacked structure SBST1 and the second sub-stacked structure SBST2. Other structural features may be referenced above. Figure 3C The structural features discussed are the same or similar.

[0208] Figure 27 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown. Figure 28 It shows along Figure 27 A sectional view taken by line A-A'.

[0209] Reference Figure 27 and Figure 28 The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a can be stacked sequentially. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a can be coupled to each other. The first semiconductor chip 100a can be electrically connected to the second semiconductor chip 200a. On the other hand, in some example embodiments, the second semiconductor chip 200a may not be electrically connected to the third semiconductor chip 300a.

[0210] The first semiconductor chip 100a may correspond to the aforementioned logic chip 100. The first semiconductor chip 100a may include a first decoder circuit section DCR1, a first page buffer circuit section PB1, and a second decoder circuit section DCR2 arranged side-by-side in the first direction D1. The first decoder circuit section DCR1 may include a plurality of first transmission transistors PST1. The second decoder circuit section DCR2 may include a plurality of second transmission transistors PST2. The first page buffer circuit section PB1 may include a plurality of first bit line selection transistors PTR1.

[0211] The second semiconductor chip 200a may correspond to the first memory chip 200 described above. The second semiconductor chip 200a may include a first stacked structure ST1 and a second stacked structure ST2 arranged side-by-side in the second direction D2. The first stacked structure ST1 may include a stacked first electrode layer EL1. The second stacked structure ST2 may include a stacked second electrode layer EL2. The distance between the stepped ends of the first stacked structure ST1 and the second stacked structure ST2 and the first semiconductor chip 100a may gradually increase in the first direction D1. The end of the first electrode layer EL1 of the first stacked structure ST1 can be electrically connected to the first transmission transistor PST1 of the first decoder circuit section DCR1 via a first unit contact plug CC1, a first conductive pattern VPa, and a logic connection terminal 150. The end of the second electrode layer EL2 of the second stacked structure ST2 can be electrically connected to the second transmission transistor PST2 of the second decoder circuit section DCR2 via a second unit contact plug CC2, a first conductive pattern VPa, and a logic connection terminal 150.

[0212] The first unit through-hole component CTHV1 can penetrate the first electrode layer EL1. The second unit through-hole component CTHV2 can penetrate the second electrode layer EL2. The first layer bit line L1BL can be connected to the first unit through-hole component CTHV1 and the second unit through-hole component CTHV2. The first layer bit line L1BL can be electrically connected to the first bit line select transistor PTR1 of the first page buffer circuit section PB1 through the first conductive pattern VPa and the logic connection terminal 150.

[0213] The third semiconductor chip 300a may have a cell-on-periphery (COP) structure in which the memory cell array is disposed on a peripheral circuit block (the peripheral circuit block may also be referred to as peripheral circuitry). For example, the third semiconductor chip 300a may include a third substrate 311; a third decoder circuit portion DCR3, a second page buffer circuit portion PB2, and a fourth decoder circuit portion DCR4 arranged side by side on the third substrate 311 along a first direction D1; and a third stacked structure ST3 and a fourth stacked structure ST4 spaced apart from each other on the third decoder circuit portion DCR3, the second page buffer circuit portion PB2, and the fourth decoder circuit portion DCR4 in a second direction D2. For example, the third substrate 311 may be a single-crystal silicon substrate or a silicon-on-insulator (SOI) substrate. A third device isolation layer 303 defining an active region may be disposed in the third substrate 311.

[0214] The third substrate 311 may include a third transmission transistor PST3, a fourth transmission transistor PST4, and a second bit line select transistor PTR2. The third substrate 311 may be covered by a circuit dielectric layer 307. The circuit dielectric layer 307 may have a single-layer or multi-layer structure including one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous dielectric layer. The circuit dielectric layer 307 may include multiple layers of third wiring 309. Some of the third wiring 309 and the third transmission transistor PST3 may constitute a third decoder circuit portion DCR3. Other third wiring 309 and the fourth transmission transistor PST4 may constitute a fourth decoder circuit portion DCR4. Still some of the third wiring 309 and the second bit line select transistor PTR2 may constitute a second page buffer circuit portion PB2.

[0215] The third stacked structure ST3 may include a stacked third electrode layer EL3. The fourth stacked structure ST4 may include a stacked fourth electrode layer EL4. The distance between the stepped ends of the third stacked structure ST3 and the fourth stacked structure ST4 and the first semiconductor chip 100a may gradually increase in the first direction D1. The end of the third electrode layer EL3 of the third stacked structure ST3 may be electrically connected to the third transmission transistor PST3 of the third decoder circuit section DCR3 via the third unit contact plug CC3, the second layer electrode connection line VPa_L2, the second layer edge through-hole L2ETHV, and the third wiring 309. The end of the fourth electrode layer EL4 of the fourth stacked structure ST4 may be electrically connected to the fourth transmission transistor PST4 of the fourth decoder circuit section DCR4 via the fourth unit contact plug CC4, the second layer electrode connection line VPa_L2, the second layer edge through-hole L2ETHV, and the third wiring 309. According to some example embodiments, the third semiconductor chip 300a may be insulated from the first semiconductor chip 100a and the second semiconductor chip 200a.

[0216] The third unit through-hole component CTHV3 can penetrate the third electrode layer EL3. The fourth unit through-hole component CTHV4 can penetrate the fourth electrode layer EL4. The second layer bit line L2BL can be connected to the third unit through-hole component CTHV3 and the fourth unit through-hole component CTHV4. The second layer bit line L2BL can be electrically connected to the second bit line selection transistor PTR2 of the second page buffer circuit section PB2 through the third unit through-hole component CTHV3 and the fourth unit through-hole component CTHV4 and the third wiring 309. Other structural features may be the same as or similar to those discussed above.

[0217] Figure 29 A perspective view of a three-dimensional semiconductor memory device illustrating some example embodiments of the concept according to the present invention is shown.

[0218] Reference Figure 29 The first semiconductor chip 100a to the fifth semiconductor chip 500a can be stacked sequentially. The first semiconductor chip 100a to the fifth semiconductor chip 500a can be bonded to each other. The second semiconductor chip 200a and the third semiconductor chip 300a can be electrically connected to the first semiconductor chip 100a. The fourth semiconductor chip 400a can be electrically connected to the fifth semiconductor chip 500a. There may be no electrical connection between the third semiconductor chip 300a and the fourth semiconductor chip 400a.

[0219] The first semiconductor chip 100a may correspond to the logic chip 100 discussed above. The first semiconductor chip 100a may include a first decoder circuit portion DCR1 and a fourth decoder circuit portion DCR4 disposed on one side of the first page buffer circuit portion PB1, and may also include a second decoder circuit portion DCR2 and a third decoder circuit portion DCR3 disposed on the other side of the first page buffer circuit portion PB1.

[0220] The second semiconductor chip 200a, the third semiconductor chip 300a, and the fourth semiconductor chip 400a can correspond to the first memory chip 200, the second memory chip 300, and the third memory chip 400 discussed above, respectively. The second semiconductor chip 200a may include a first stacked structure ST1 and a second stacked structure ST2 spaced apart from each other in the second direction D2. The third semiconductor chip 300a may include a third stacked structure ST3 and a fourth stacked structure ST4 spaced apart from each other in the second direction D2. The fourth semiconductor chip 400a may include a fifth stacked structure ST5 and a sixth stacked structure ST6 spaced apart from each other in the second direction D2.

[0221] With reference Figure 27 and Figure 28 Similar to the third semiconductor chip 300a discussed, the fifth semiconductor chip 500a may have a cell-on-periphery (COP) structure. The fifth semiconductor chip 500a may include a second page buffer circuit portion PB2 disposed on a fifth substrate 501, a fifth decoder circuit portion DCR5 and an eighth decoder circuit portion DCR8 disposed on one side of the second page buffer circuit portion PB2, and a sixth decoder circuit portion DCR6 and a seventh decoder circuit portion DCR7 disposed on the other side of the second page buffer circuit portion PB2. The fifth semiconductor chip 500a may also include a seventh stacked structure ST7 and an eighth stacked structure ST8 disposed on the second page buffer circuit portion PB2 and spaced apart from each other in the second direction D2.

[0222] The first stacked structure ST1 may include a first electrode layer EL1 connected to the first decoder circuit section DCR1 via a first unit contact plug CC1 and a first layered electrode connection line VPa_L1. The second stacked structure ST2 may include a second electrode layer EL2 connected to the second decoder circuit section DCR2 via a second unit contact plug CC2 and a first layered electrode connection line VPa_L1. The third stacked structure ST3 may include a third electrode layer EL3 connected to the third decoder circuit section DCR3 via a third unit contact plug CC3, a second layered electrode connection line VPa_L2, and a first layered edge pass-through L1ETHV. The fourth stacked structure ST4 may include a fourth electrode layer EL4 connected to the fourth decoder circuit section DCR4 via a fourth unit contact plug CC4, a second layered electrode connection line VPa_L2, and a first layered edge pass-through L1ETHV.

[0223] The fifth stack structure ST5 may include a fifth electrode layer EL5 connected to the fifth decoder circuit section DCR5 via a fifth unit contact plug CC5, a third layer electrode connection line VPa_L3, a third layer edge pass-through L3ETHV, and a fourth layer edge pass-through L4ETHV. The sixth stack structure ST6 may include a sixth electrode layer EL6 connected to the sixth decoder circuit section DCR6 via a sixth unit contact plug CC6, a third layer electrode connection line VPa_L3, a third layer edge pass-through L3ETHV, and a fourth layer edge pass-through L4ETHV. The seventh stack structure ST7 may include a seventh electrode layer EL7 connected to the seventh decoder circuit section DCR7 via a seventh unit contact plug CC7, a fourth layer electrode connection line VPa_L4, and a fourth layer edge pass-through L4ETHV. The eighth stack structure ST8 may include an eighth electrode layer EL8 connected to the eighth decoder circuit section DCR8 via an eighth unit contact plug CC8, a fourth layer electrode connection line VPa_L4, and a fourth layer edge pass-through L4ETHV. Other structural features may be the same as or similar to those discussed above.

[0224] In reference Figures 1A to 26 In the three-dimensional semiconductor memory device discussed, the logic chip 100 can be referred to as a peripheral circuit block or peripheral circuit region. The memory chip can be referred to as a memory block or memory region.

[0225] In reference Figures 1A to 26 In the three-dimensional semiconductor memory device discussed, the logic chip 100 and the first memory chip 200 can be included in a single semiconductor chip having a cell-on-periphery (COP) structure. Reference will be made below. Figure 30 and Figure 31 An example describing this situation.

[0226] Figure 30 and Figure 31 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0227] Reference Figure 30 The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a can be stacked sequentially. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a can be connected to each other. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a can be electrically connected to each other.

[0228] The first semiconductor chip 100a may have a reference Figure 22A The structures of the logic chip 100 and the first memory chip 200 are discussed. The first semiconductor chip 100a may have a cell-on-periphery (COP) structure. For example, the first semiconductor chip 100a may include a first substrate 103a; a first decoder circuit portion DCR1, a page buffer circuit portion PB, and a third decoder circuit portion DCR3 arranged side by side along a first direction D1; and a first stacked structure ST1 disposed on the first decoder circuit portion DCR1, the page buffer circuit portion PB, and the third decoder circuit portion DCR3. Although not shown, the first semiconductor chip 100a may include a second decoder circuit portion DCR2, a fourth decoder circuit portion DCR4, and a second stacked structure ST2. The first decoder circuit portions DCR1 to the fourth decoder circuit portions DCR4 may be covered by a circuit dielectric layer 107a.

[0229] The second semiconductor chip 200a and the third semiconductor chip 300a can be respectively compared with reference to Figure 22A The second memory chip 300 and the third memory chip 400 discussed correspond to each other. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a may include a first stacked structure ST1 to a sixth stacked structure ST6, each of which includes, as shown in the example... Figure 22A The recessed RC is shown on its opposite side. Conversely, Figure 30 Each of the first stacked structures ST1 to the sixth stacked structure ST6 shown can have the following properties: Figure 22A The structure obtained by inverting one of the first stacked structures ST1 to the sixth stacked structure ST6 shown. For example, the distance from the top surface of the stepped end of the first stacked structure ST1 to the sixth stacked structure ST6 to the first substrate 103a can gradually decrease in the first direction D1.

[0230] Figure 31Three-dimensional semiconductor memory devices can have Figure 30 The second semiconductor chip 200a and the third semiconductor chip 300a are arranged in an upside-down configuration. Other structural features can be referenced above. Figure 30 The structural features discussed are the same or similar.

[0231] like Figure 30 or Figure 31 As shown in block P5, it can be determined that one of the first electrode layers EL1 and one of the fifth electrode layers EL5 are electrically connected to one of the first transmission transistors PST1. As... Figure 30 or Figure 31 As shown in block P6, it can be determined that one of the third electrode layers EL3 is electrically connected to one of the third transmission transistors PST3. Apart from the seventh stack structure ST7 and the eighth stack structure ST8, Figure 30 or Figure 31 The connection relationship between the first stacked structure ST1 to the sixth stacked structure ST6 can be the same as or similar to the connection relationship shown in Figure 22.

[0232] exist Figure 30 In a three-dimensional semiconductor memory device, a first semiconductor chip 100a, a second semiconductor chip 200a, and a third semiconductor chip 300a can be included in a single semiconductor chip. The following will refer to... Figure 32 An example to explain this situation.

[0233] Figure 32 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0234] Reference Figure 32 The semiconductor chip 100b may include a first substrate 103a, and may further include a first decoder circuit portion DCR1, a page buffer circuit portion PB, and a third decoder circuit portion DCR3 arranged side-by-side along a first direction D1 on the first substrate 103a. Although not shown, the semiconductor chip 100b may also include a second decoder circuit portion DCR2 and a fourth decoder circuit portion DCR4. The first decoder circuit portions DCR1 to the fourth decoder circuit portions DCR4 may be covered by a circuit dielectric layer 107a. A first stacked structure ST1, a third stacked structure ST3, and a fifth stacked structure ST5 may be sequentially stacked on the circuit dielectric layer 107a. Although not shown, a second stacked structure ST2, a fourth stacked structure ST4, and a sixth stacked structure ST6 may be sequentially stacked on the circuit dielectric layer 107a, spaced apart from the first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5, respectively, along a second direction D2.

[0235] The first layered edge through-hole component L1ETHV, the second layered edge through-hole component L2ETHV, and the third layered edge through-hole component L3ETHV can penetrate the ends of the first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5, respectively. The first layered electrode connection line VPa_L1, the second layered electrode connection line VPa_L2, and the third layered electrode connection line VPa_L3 can be respectively disposed on the first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5, thereby allowing the first unit contact plug CC1, the third unit contact plug CC3, and the fifth unit contact plug CC5 to connect with one of the corresponding first layered edge through-hole components L1ETHV, L2ETHV, and L3ETHV.

[0236] On the cell array region CAR, the first cell through-hole component CTHV1, the third cell through-hole component CTHV3, and the fifth cell through-hole component CTHV5 can penetrate the first stack structure ST1, the third stack structure ST3, and the fifth stack structure ST5, respectively. The first cell through-hole component CTHV1, the third cell through-hole component CTHV3, and the fifth cell through-hole component CTHV5 can be connected to the first layer bit line L1BL, the second layer bit line L2BL, and the third layer bit line L3BL respectively disposed on the first stack structure ST1, the third stack structure ST3, and the fifth stack structure ST5.

[0237] The inter-stacking dielectric layer (STL) can be located between some of the stacked structures, namely the first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5. The STL can have a single-layer or multi-layer structure including one or more of silicon oxide, silicon nitride, and silicon oxynitride layers. The STL may include a connecting through-hole plug (CVA), through which the first layer edge through-hole L1ETHV, the second layer edge through-hole L2ETHV, and the third layer edge through-hole L3ETHV are electrically connected to each other. Additionally, the first unit through-hole CTHV1, the third unit through-hole CTHV3, and the fifth unit through-hole CTHV5 can be electrically connected to each other through some of the connecting through-hole plugs (CVA). Other structural features are consistent with those described above. Figure 30 The structural features discussed are the same or similar.

[0238] Figure 33 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0239] Reference Figure 33The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a can be stacked sequentially. The first semiconductor chip 100a, the second semiconductor chip 200a, and the third semiconductor chip 300a can be connected to each other. The first semiconductor chip 100a and the second semiconductor chip 200a can be electrically connected to each other, but can be insulated from the third semiconductor chip 300a. Figure 33 The first semiconductor chip 100a and the second semiconductor chip 200a can be respectively connected to Figure 31 The first semiconductor chip 100a corresponds to the second semiconductor chip 200a, and their structure and connection relationship can be compared with... Figure 31 The connection relationship between the first semiconductor chip 100a and the second semiconductor chip 200a is the same or similar. Figure 33 The third semiconductor chip 300a can be with Figure 28 The third semiconductor chip 300a is configured in the same or similar manner. Both the first semiconductor chip 100a and the third semiconductor chip 300a may have a peripheral upper unit (COP) structure. Figure 33 The example shown can be compared with Figure 31 and Figure 28 Examples of combinations of some example embodiments are shown. According to some example embodiments, the memory cell array of the third semiconductor chip 300a is electrically connected to the peripheral circuit block of the third semiconductor chip 300a and is insulated from the first semiconductor chip 100a and the second semiconductor chip 200a.

[0240] Figure 34 A perspective view is shown of the end of a first stacked structure illustrating some exemplary embodiments of the concept according to the present invention.

[0241] Reference Figure 3A and Figure 34 The first electrode layer EL1 included in the first stacked structure ST1 may have pad portions ELPa and ELPb that contact the first cell contact plug CC1 on the first connection region CNR1. For example, the odd-numbered first electrode layer EL1 stacked on the first memory substrate 201 may have a first pad portion ELPa. The even-numbered first electrode layer EL1 may have a second pad portion ELPb. The first pad portion ELPa may not overlap with the second pad portion ELPb. The first pad portion ELPa may protrude laterally from the second pad portion ELPb (e.g., in the second direction D2). When viewed along the second direction D2, a step difference may be formed between the first pad portion ELPa and the second pad portion ELPb. The first cell contact plug CC1 may penetrate the inter-electrode dielectric layer 12 and may contact some of the first pad portion ELPa and the second pad portion ELPb.

[0242] The structure of the first electrode layer EL1 on the second connection region CNR2 can also be the same as or similar to the structure on the first connection region CNR1. Furthermore, in reference... Figures 1A to 33 In the discussed three-dimensional semiconductor memory device, the structure of the ends of the second electrode layer EL2 to the eighth electrode layer EL8 can be the same as or similar to that described above. The position of the pad portion can be as described above, thus preventing or reducing bridging between cell contact plugs and increasing the degree of freedom in wiring. Therefore, the reliability of the three-dimensional semiconductor memory device can be increased.

[0243] Figure 34 The example shown illustrates that the positions of the pads on odd-numbered electrode layers differ from those on even-numbered electrode layers. However, the pads of three or more electrode layers can form a single group protruding in the second direction D2 to create a stepped shape.

[0244] Figure 35 A cross-sectional view of a three-dimensional semiconductor memory device illustrating some exemplary embodiments of the concept according to the present invention is shown.

[0245] Reference Figure 35 The first electrode layer EL1, the third electrode layer EL3, and the fifth electrode layer EL5 included in the first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5, respectively, can have different total numbers. For example, the total number of third electrode layers EL3 can be less than the total number of first electrode layers EL1, but greater than the total number of fifth electrode layers EL5. Therefore, the vertical lengths (or thicknesses) of the first stacked structure ST1, the third stacked structure ST3, and the fifth stacked structure ST5 can be different from each other. For example, the third stacked structure ST3 can be thinner than the first stacked structure ST1 and thicker than the fifth stacked structure ST5. Similarly, the edge through-holes L1ETHV, L2ETHV, and L3ETHV, as well as the vertical pattern VS, can have different vertical lengths. Other structural features and connection relationships can be referenced. Figure 30 The structural features and connections discussed are the same or similar.

[0246] A three-dimensional semiconductor memory device conceived according to the present invention may include multiple memory chips stacked on a logic chip, and may be spaced apart from multiple driver circuits (e.g., transfer transistors or bit line select transistors) that operate the memory blocks included in each memory chip. Therefore, the reliability of the three-dimensional semiconductor memory device can be increased, and it can have the advantage of high integration.

[0247] According to some example embodiments, a three-dimensional semiconductor memory device can be electrically connected to another device (e.g., a memory controller) and configured to communicate with another device (e.g., a memory controller). The other device can be implemented using processing circuitry. For example, the term 'processing circuitry' as used herein can refer to hardware including logic circuitry; a hardware / software combination such as a processor executing software; or a combination thereof. For example, processing circuitry can more specifically include (but is not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. According to some example embodiments, the circuitry described herein (e.g., decoder circuitry, page buffer circuitry, control circuitry, driver circuitry, data input / output circuitry, logic circuitry, peripheral circuitry, etc.) can be executed by processing circuitry.

[0248] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” are used herein to describe the relationship between one element or feature and another shown in the accompanying drawings. For example, as described herein, the terms “above,” “above,” “on,” and / or “top” may refer to an element or feature further away in a third direction D3 (as shown in Figure 2) relative to other elements or features, while the terms “below” and / or “under” may refer to an element or feature further away in a direction opposite to the third direction D3 relative to other elements or features. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures were inverted, an element described as “below” or “under” would then be oriented “above” the other elements or features. Thus, the term “below” can cover both the orientations above and below. The device may be in other orientations (rotated 90 degrees or located in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0249] It should be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected to or coupled to said other element, or there may be an intermediate element. As used herein, the term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0250] Some example embodiments are described herein with reference to schematic illustrations as ideal exemplary diagrams. Therefore, variations relative to the illustrated shape can be anticipated, for example, due to manufacturing techniques and / or variations. Thus, some example embodiments should not be considered limited to the specific shape of the area shown herein, but rather include shape differences due to, for example, manufacturing processes.

[0251] Although the inventive concept has been described with reference to some exemplary embodiments shown in the accompanying drawings, those skilled in the art should understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. Those skilled in the art should recognize that various substitutions, modifications, and changes can be made to the inventive concept without departing from its scope and spirit. For example, references may exist. Figures 1A to 35 Various combinations of some example embodiments are discussed.

Claims

1. A three-dimensional semiconductor memory device, comprising: The first peripheral circuit includes multiple different decoder circuits; The first memory on the first peripheral circuit, the first memory comprising: A first stacked structure having a plurality of first electrode layers stacked on top of each other and a plurality of first inter-electrode dielectric layers between the first electrode layers. A first planarized dielectric layer covers the ends of the first stacked structure, and A first through-hole penetrates the first planarized dielectric layer and the end of the first stacked structure. The first through-hole is insulated from the plurality of first electrode layers and electrically connected to one of the plurality of different decoder circuits. One of the plurality of first electrode layers is electrically connected to another of the plurality of different decoder circuits. A second memory on the first memory, the second memory comprising: The second stacked structure has a plurality of second electrode layers stacked on top of each other and a plurality of second electrode inter-dielectric layers between the second electrode layers. A second planarized dielectric layer covers the ends of the second stacked structure, and The first unit contact plug penetrates the second planarized dielectric layer and electrically connects one of the plurality of second electrode layers to the first through-hole.

2. The three-dimensional semiconductor memory device according to claim 1, wherein, The first memory includes a first through-hole dielectric layer surrounding the first through-hole element; The second memory includes a first contact dielectric layer surrounding the first cell contact plug; and The thickness of the first through dielectric layer is greater than the thickness of the first contact dielectric layer.

3. The three-dimensional semiconductor memory device according to claim 1, wherein, The first memory includes a first through-hole dielectric layer surrounding the first through-hole element; The first through-dielectric layer has a first thickness parallel to a first direction, which is parallel to the top surface of the first peripheral circuit. One of the plurality of dielectric layers between first electrodes has a second thickness parallel to a second direction, which is perpendicular to the top surface of the first peripheral circuit. and The first thickness is equal to or greater than the second thickness.

4. The three-dimensional semiconductor memory device according to claim 1, wherein, The plurality of first electrode layers include a plurality of first recesses at the ends of the first stacked structure, the inner walls of the plurality of first recesses being vertically aligned with each other; The first stacked structure includes a plurality of first residual sacrificial patterns that fill the plurality of first recesses; and The first penetrating element penetrates one of the plurality of first residual sacrificial patterns.

5. The three-dimensional semiconductor memory device according to claim 1, wherein, The plurality of different decoder circuits include a first decoder circuit and a second decoder circuit, the first decoder circuit and the second decoder circuit being spaced apart from each other in a first direction parallel to the top surface of the first peripheral circuit; and One of the plurality of second electrode layers is electrically connected to the second decoder circuit through the first unit contact plug and the first through-hole.

6. The three-dimensional semiconductor memory device according to claim 5, wherein, The first memory further includes: A second unit contact plug penetrates the first planarized dielectric layer, and the second unit contact plug electrically connects one of the plurality of first electrode layers to the first decoder circuit.

7. The three-dimensional semiconductor memory device according to claim 5, wherein, The plurality of different decoder circuits further include a third decoder circuit, the second decoder circuit and the third decoder circuit being adjacent in a second direction, the second direction being parallel to the top surface of the first peripheral circuit and intersecting the first direction; The first memory includes a third stacked structure spaced apart from the first stacked structure in the second direction; The third stacked structure includes a plurality of third electrode layers stacked on top of each other and a plurality of third electrode inter-electrode dielectric layers between the third electrode layers; The first planarized dielectric layer extends to cover the ends of the third stacked structure; and The first memory includes a third unit contact plug that penetrates the first planarized dielectric layer, the third unit contact plug electrically connecting one of the plurality of third electrode layers to the third decoder circuit.

8. The three-dimensional semiconductor memory device according to claim 7, wherein, The third stacked structure is located at a first distance from the first peripheral circuit, and the first distance is the same as the second distance between the first stacked structure and the first peripheral circuit.

9. The three-dimensional semiconductor memory device according to claim 8, wherein, The third stacked structure has the shape obtained when the first stacked structure is rotated 180 degrees.

10. The three-dimensional semiconductor memory device according to claim 1, wherein, The first stacked structure has a first maximum width parallel to a first direction, which is parallel to the top surface of the first peripheral circuit. The second stacking structure has a second maximum width parallel to the first direction; and The second maximum width is greater than the first maximum width.

11. The three-dimensional semiconductor memory device according to claim 1, wherein, The end of the second stacked structure protrudes laterally beyond the end of the first stacked structure.

12. The three-dimensional semiconductor memory device according to claim 1, further comprising: The third memory on the second memory, in, The plurality of different decoder circuits include a first decoder circuit and a second decoder circuit. The third memory includes: A third stacked structure having a plurality of third electrode layers stacked on top of each other and a plurality of inter-electrode dielectric layers between the third electrode layers; and A third planarized dielectric layer covers the ends of the third stacked structure. The plurality of third electrode layers and the plurality of first electrode layers are electrically connected to the first decoder circuit, and The plurality of second electrode layers are electrically connected to the second decoder circuit.

13. The three-dimensional semiconductor memory device according to claim 1, wherein, The first memory includes: Multiple first vertical patterns penetrating the multiple first electrode layers, and Multiple first line segments that are connected to the ends of the first vertical patterns in the plurality of first vertical patterns and are parallel to each other; The second memory includes: Multiple second vertical patterns penetrating the multiple second electrode layers, and Multiple second position lines that are connected to the ends of the second vertical patterns in the plurality of second vertical patterns and are parallel to each other; The first peripheral circuit includes multiple page buffer circuits; The plurality of first bit lines are connected to one of the plurality of page buffer circuits; and The plurality of second bit lines are not connected to one of the plurality of page buffer circuits.

14. The three-dimensional semiconductor memory device according to claim 13, further comprising: The third memory on the second memory, The third memory includes: The third stacked structure includes a plurality of third electrode layers stacked on top of each other and a plurality of inter-third electrode dielectric layers between the third electrode layers, and A third planarized dielectric layer covers the ends of the third stacked structure. Multiple third vertical patterns penetrating the multiple third electrode layers, and Multiple third position lines connect to the ends of the third vertical patterns in the plurality of third vertical patterns and are parallel to each other. The plurality of third bit lines are connected to one of the plurality of page buffer circuits.

15. The three-dimensional semiconductor memory device according to claim 1, further comprising: The third memory on the second memory; as well as The second peripheral circuit on the third memory The third memory is electrically connected to the second peripheral circuit and is insulated from the first peripheral circuit, the first memory, and the second memory.

16. A three-dimensional semiconductor memory device, comprising: The peripheral circuitry includes multiple different decoder circuits. The first memory on the peripheral circuit includes a first stacked structure and a second stacked structure spaced apart from each other in a first direction parallel to the top surface of the peripheral circuit. The first stacked structure includes a plurality of first electrode layers stacked on top of each other, the plurality of first electrode layers being electrically connected to a first decoder circuit in the plurality of different decoder circuits. The second stacked structure includes a plurality of second electrode layers stacked on top of each other. as well as The second memory on the first memory includes a third stacked structure and a fourth stacked structure spaced apart from each other in the first direction. The third stacked structure includes a plurality of third electrode layers stacked on top of each other, which are electrically connected to a second decoder circuit in the plurality of different decoder circuits. The fourth stacked structure includes a plurality of fourth electrode layers stacked on top of each other.

17. The three-dimensional semiconductor memory device according to claim 16, wherein, The second decoder circuit is spaced apart from the first decoder circuit in a second direction, which is parallel to the top surface of the peripheral circuit and intersects with the first direction. and The three-dimensional semiconductor memory device further includes: A plurality of first unit contact plugs are provided, each contacting a corresponding first electrode layer among the plurality of first electrode layers, thereby connecting the plurality of first electrode layers to the first decoder circuit. Multiple second unit contact plugs, which contact corresponding third electrode layers among the multiple third electrode layers, and A plurality of first through-holes connect the plurality of second unit contact plugs to the second decoder circuit, the plurality of first through-holes being insulated from the plurality of first electrode layers.

18. The three-dimensional semiconductor memory device according to claim 16, wherein, The plurality of second electrode layers are electrically connected to the third decoder circuit portion in the plurality of different decoder circuits; and The plurality of fourth electrode layers are electrically connected to the fourth decoder circuit in the plurality of different decoder circuits.

19. A three-dimensional semiconductor memory device, comprising: The peripheral circuit includes a first decoder circuit and a second decoder circuit, which are arranged side by side in a first direction and are different from each other. The first memory on the peripheral circuit includes a first stacked structure electrically connected to the first decoder; as well as A second memory on the first memory, the second memory including a second stacked structure electrically connected to the second decoder circuitry, a portion of the second stacked structure protruding beyond the first stacked structure. The peripheral circuit includes a third decoder circuit spaced apart from the first decoder circuit in a direction opposite to the first direction. The first stacked structure has a first recess on the third decoder circuit; The second stacked structure has a second recess on the third decoder circuit; and The three-dimensional semiconductor memory device further includes: A third memory on the second memory and including a third stacked structure, The unit contact plug contacts the third stacked structure on the third decoder circuit. A first through-hole member, which is located in the first recess and electrically connected to the unit contact plug, and The second through member is located in the second recess and is electrically connected to the unit contact plug.

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