Display device

Abstract

Embodiments relate to a display device including a substrate including a display area and a non-display area adjacent to the display area; a pixel disposed in the display area; a first voltage line disposed in the non-display area and supplying a first power voltage to the pixel; a second voltage line disposed in the non-display area and supplying a second power voltage to the pixel, the second voltage line being separated from the first voltage line; and a metal pattern disposed between the first voltage line and the second voltage line. A shortest distance between the first voltage line and the second voltage line is greater than a width of the metal pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0178503, filed on December 30, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device. Background Technology

[0004] Mobile display devices are widely used. In addition to small electronic devices such as mobile phones, tablet PCs are also widely used as mobile display devices.

[0005] These mobile display devices support a variety of functions. The display device can include a display area to provide users with visual information such as images or videos. As the size of the components of the display device, such as those used to drive the display device, decreases, the display area of ​​the display device increases. Display structures that allow the display device to bend at an angle from a flat state have also been developed.

[0006] High-brightness display devices have been developed to achieve brighter screens, enhancing visibility even in outdoor environments with high levels of external light.

[0007] It will be understood that this background section is partly intended to provide a useful context for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were known or understood prior to the corresponding valid application date of the subject matter disclosed herein by a person skilled in the art. Summary of the Invention

[0008] One or more embodiments may relate to a display device in which a brighter screen can be achieved, such that visibility can be enhanced even in outdoor environments with high external light levels, and flicker caused by external light or external light reflection in non-display areas adjacent to the display area can be minimized.

[0009] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0010] According to one or more embodiments, a display device may include: a substrate including a display area and a non-display area adjacent to the display area; a pixel disposed in the display area; a first voltage line disposed in the non-display area and supplying a first power supply voltage to the pixel. The display device may also include: a second voltage line disposed in the non-display area and supplying a second power supply voltage to the pixel, the second voltage line being separated from the first voltage line; and a metal pattern disposed between the first voltage line and the second voltage line. The shortest distance between the first voltage line and the second voltage line may be greater than the width of the metal pattern.

[0011] The distance between the first voltage line and the metal pattern can be from about 1 μm to about 50 μm.

[0012] The distance between the second voltage line and the metal pattern can be from about 1 μm to about 50 μm.

[0013] At least a portion of the first voltage line may overlap with a first virtual line parallel to one side of the display area, and the second voltage line may surround at least a portion of the display area.

[0014] The width of the first voltage line can be smaller than the width of the second voltage line.

[0015] The first voltage line can be electrically connected to a first driving voltage line in a first direction in the display area and a second driving voltage line in a second direction that intersects with the first driving voltage line.

[0016] The first voltage line may include a first lower voltage line and a first upper voltage line on the first lower voltage line.

[0017] The metal pattern and the first lower voltage line or the first upper voltage line can be disposed on the same layer.

[0018] The metal pattern may include a lower metal pattern and an upper metal pattern. The lower metal pattern and the first lower voltage line may be disposed on the same layer, and the upper metal pattern and the first upper voltage line may be disposed on the same layer.

[0019] The first lower voltage line and the first upper voltage line can be electrically connected to each other via contact holes in the insulating layer between the first lower voltage line and the first upper voltage line.

[0020] The display device may also include a cover film in the non-display area.

[0021] The covering film may overlap with the first voltage line or the second voltage line.

[0022] The cover film can be separated from the metal pattern in a direction that separates the cover film from the display area.

[0023] The metallic pattern can be disposed between the cover film and the display area.

[0024] The first voltage line or the second voltage line may include a hole.

[0025] According to one or more embodiments, a display device may include: a substrate including a display area and a non-display area adjacent to the display area; a cover film in the non-display area; a pixel disposed in the display area; a first voltage line disposed between the substrate and the cover film and electrically connected to the pixel, wherein at least a portion of the first voltage line may overlap with a first virtual line parallel to one side of the display area; a second voltage line disposed between the substrate and the cover film and electrically connected to the pixel, the second voltage line being separated from the first voltage line; and a metal pattern disposed between the first voltage line and the second voltage line, wherein the metal pattern may be disposed along the first virtual line.

[0026] The metallic pattern can be disposed between the display area and the cover film.

[0027] The distance between the first voltage line or the second voltage line and the metal pattern can be from about 1 μm to about 50 μm.

[0028] The second voltage line may extend along the outside of the display area.

[0029] The width of the first voltage line can be smaller than the width of the second voltage line.

[0030] The first voltage line or the second voltage line may include a hole. Attached Figure Description

[0031] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a schematic perspective view of a display device according to one embodiment;

[0033] Figure 2 This is a schematic equivalent circuit diagram of pixels included in a display device according to one embodiment;

[0034] Figure 3This is a schematic plan view of the display panel and cover film of a display device according to one embodiment;

[0035] Figure 4 yes Figure 3 An enlarged schematic diagram of region IV;

[0036] Figures 5 to 7 The display device according to one embodiment is along Figure 3 The line A-A' and Figure 4 A schematic cross-sectional view of line B-B';

[0037] Figure 8 This is a schematic plan view of the display panel and cover film of a display device according to another embodiment; and

[0038] Figure 9 yes Figure 8 A magnified view of region IX. Detailed Implementation

[0039] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, in which similar reference numerals consistently denote similar elements. In this regard, embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, only embodiments are described below with reference to the accompanying drawings to explain various aspects of the description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0040] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as the ways in which these effects and features are achieved, will become apparent from the embodiments described in detail later with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be implemented in various forms.

[0041] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another.

[0042] As used herein, the singular forms “a, an” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0043] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for purposes of meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood as equivalent to "and / or".

[0044] It will also be understood that terms such as “comprises,” “has,” “have,” and “includes” as used herein specify the presence of the stated feature or component, but do not preclude the presence or addition of one or more other features or components.

[0045] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, the layer, region, or component may be formed directly or indirectly on the other layer, region, or component. For example, intermediate layers, intermediate regions, or intermediate components may exist.

[0046] For ease of explanation, the dimensions and thicknesses of the elements in the accompanying drawings may be enlarged or reduced. In other words, since the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0047] When an embodiment can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially at the same time or in the reverse order of the described sequence.

[0048] It will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, the layer, region, or component can be directly or indirectly connected to the other layer, region, or component. For example, intermediate layers, intermediate regions, or intermediate components may exist. It will also be understood that when a layer, region, or component is referred to as being "electrically connected to" another layer, region, or component, the layer, region, or component can be directly or indirectly electrically connected to the other layer, region, or component. For example, intermediate layers, intermediate regions, or intermediate components may exist.

[0049] The term “overlapping with” can include layering, stacking, facing, extending above, extending below, covering, or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art. The phrase “not overlapping with” can include “separated from”, “separated from”, “offset from”, or any other suitable equivalent that will be understood and appreciated by one of ordinary skill in the art.

[0050] Taking into account the measurements discussed and the errors associated with the measurement of specific quantities (i.e., the limitations of the measurement system), the term "approximately" as used herein includes the stated value and means within an acceptable range of deviation for a specific value as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, or ±5% of the stated value.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined in the specification, terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an ideal or excessive form.

[0052] Display devices, which can be means for displaying images, can be mobile devices such as game consoles, multimedia devices, or mini-personal computers (PCs). Examples of display devices described below may include liquid crystal display (LCD) devices, electrophoretic display devices, organic light-emitting display devices, inorganic light-emitting display devices, field emission display devices, surface conduction electron emission display devices, quantum dot display devices, plasma display devices, and cathode ray display devices. In the following description, organic light-emitting display devices will be used as examples of display devices according to one embodiment. However, various types of display devices, such as those described above, can be used in one or more embodiments of this disclosure.

[0053] Figure 1 This is a schematic perspective view of a display device 1 according to one embodiment.

[0054] refer to Figure 1 The display device 1 may include a display panel 100, a display area DA and a non-display area NDA, wherein the display area DA and the non-display area NDA can be provided on the display panel 100.

[0055] An image can be implemented in the display area DA. Pixel P can be set in the display area DA. An image can be provided from the display area DA by using multiple beams of light emitted from pixel P.

[0056] The non-display area NDA can be an area where no image is provided. For example, pixel P may not be located in the non-display area NDA. The non-display area NDA may completely surround the display area DA. A driver for providing electrical signals or power to pixel P may be located in the non-display area NDA. Pad components (not shown) may be provided in the non-display area NDA; the pad components may be areas where electronic devices or printed circuit boards can be electrically connected.

[0057] Figure 2 This is a schematic equivalent circuit diagram of a pixel P included in a display device 1 according to an embodiment.

[0058] refer to Figure 2 Pixel P may include: pixel circuitry PC and a display element, such as an organic light-emitting diode (OLED), electrically connected to the pixel circuitry PC. Pixel circuitry PC may include: a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red, green, or blue light, or red, green, blue, or white light from the OLED.

[0059] The second thin-film transistor T2 can be a switching thin-film transistor and can be electrically connected to the scan line SL and the data line DL. Based on the switching voltage, switching signal, or scan signal Sn input from the scan line SL, the second thin-film transistor T2 can send the data voltage or data signal Dm input from the data line DL to the first thin-film transistor T1. The storage capacitor Cst can be electrically connected to the second thin-film transistor T2 and the drive voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the second thin-film transistor T2 and the first power supply voltage ELVDD supplied to the drive voltage line PL.

[0060] The first thin-film transistor T1 can be a driving thin-film transistor and can be electrically connected to the driving voltage line PL and the storage capacitor Cst. The first thin-film transistor T1 can control the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) in accordance with the value of the voltage stored in the storage capacitor Cst. The OLED can emit light with a certain brightness according to the driving current. The opposite electrode (e.g., the cathode) of the OLED can receive a second power supply voltage ELVSS.

[0061] Figure 2 The pixel circuit PC shown may include two thin-film transistors T1 and T2 and a storage capacitor Cst. However, in another embodiment, the number of thin-film transistors and the number of storage capacitors can be varied depending on the design of the pixel circuit PC.

[0062] Figure 3This is a schematic plan view of the display panel 100 and the cover film 40 of the display device 1 according to one embodiment.

[0063] refer to Figure 3 The display device 1 may include a display panel 100 and a cover film 40. The display panel 100 may include a display area DA and a non-display area NDA on a substrate 101. Here, the substrate 101 can be understood as including the display area DA and the non-display area NDA. Pixel P may be disposed in the display area DA, and the first voltage line 10, the second voltage line 20, and the terminal component 30 may be disposed in the non-display area NDA.

[0064] The substrate 101 may include one or more of glass and polymer resin, such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or combinations thereof.

[0065] In one embodiment, the display area DA may have a polygonal shape. In another embodiment, the display area DA may have a polygonal shape including curvature, as discussed further herein. For example, the display panel 100 may include a first boundary line BL1, a second boundary line BL2, a third boundary line BL3, and a fourth boundary line BL4, each defining a boundary between the display area DA and the non-display area NDA. The first boundary line BL1 and the third boundary line BL3 may extend in a first direction (e.g., the x-direction), and the second boundary line BL2 and the fourth boundary line BL4 may extend in a second direction (e.g., the y-direction) intersecting the first direction. The first boundary line BL1 and the third boundary line BL3 may face each other, with the display area DA between the first boundary line BL1 and the third boundary line BL3, and the second boundary line BL2 and the fourth boundary line BL4 may face each other, with the display area DA between the second boundary line BL2 and the fourth boundary line BL4. The corner portion CN connecting adjacent boundary lines may have curvature. In another embodiment, the display area DA may have a circular or elliptical shape. In this way, the display area DA can have various shapes. For ease of explanation, the display area DA with curvature at the corner CN will be described in detail below.

[0066] Pixel P can be electrically connected to a scan line SL that can extend in a first direction (e.g., the x-direction) and a data line DL that can extend in a second direction (e.g., the y-direction) intersecting the first direction (e.g., the x-direction). Additionally, pixel P can be electrically connected to a drive voltage line PL.

[0067] In one embodiment, the driving voltage line PL may include a first driving voltage line PL1 and a second driving voltage line PL2. The first driving voltage line PL1 may extend in a first direction (e.g., the x-direction), and the second driving voltage line PL2 may extend in a second direction (e.g., the y-direction) intersecting the first direction (e.g., the x-direction). In one embodiment, the first driving voltage line PL1 and the second driving voltage line PL2 may be disposed on different layers. The first driving voltage line PL1 may be electrically connected to the second driving voltage line PL2 via a contact hole in an insulating layer between the first driving voltage line PL1 and the second driving voltage line PL2. Therefore, the driving voltage line PL may be provided as a mesh structure. Pixel P may be electrically connected to either the first driving voltage line PL1 or the second driving voltage line PL2. For example, a first power supply voltage ELVDD (see [link to relevant documentation]) may be supplied to pixel P via the first driving voltage line PL1 extending in the first direction (e.g., the x-direction) or the second driving voltage line PL2 extending in the second direction (e.g., the y-direction). Figure 2 ).

[0068] The non-display area NDA may include a bent area BA. The bent area BA may be located between the terminal component 30 and the display area DA. The substrate 101 may be bent in the bent area BA such that at least a portion of the terminal component 30 may overlap with the display area DA and / or the non-display area NDA. The terminal component 30 may not obscure the display area DA and / or the non-display area NDA, and the bending direction may be configured such that the terminal component 30 can be placed behind the display area DA and / or the non-display area NDA. Therefore, the user can recognize that the display area DA occupies most of the display device 1 relative to the non-display area NDA.

[0069] At least a portion of the first voltage line 10 may overlap with a first virtual straight line ST1 parallel to one side of the display area DA. One side of the display area DA may be defined as one of a first boundary line BL1, a second boundary line BL2, a third boundary line BL3, and a fourth boundary line BL4. When one side of the display area DA is the first boundary line BL1, the first virtual straight line ST1 may be separated from the display area DA and therefore may be arranged in a first direction (e.g., the x-direction). When one side of the display area DA is the second boundary line BL2, the first virtual straight line ST1 may be separated from the display area DA and therefore may be arranged in a second direction (e.g., the y-direction). The case where one side of the display area DA is the first boundary line BL1 will be described below.

[0070] The first voltage line 10 may include a first main voltage line 11 and a first connecting line 12 that may be disposed on one side of the display area DA. The first main voltage line 11 may overlap with the first virtual straight line ST1, and the first connecting line 12 may extend in a direction intersecting the first virtual straight line ST1 (e.g., the y direction or the -y direction) and thus may be electrically connected to the first terminal 31 of the terminal component 30.

[0071] The first main voltage line 11 may extend in a first direction (e.g., the x-direction). In one embodiment, the length of the first main voltage line 11 may be less than the length of one side of the display area DA. For example, the first main voltage line 11 may not surround one or more corner portions CN, but may correspond to the first virtual straight line ST1. Because the driving voltage line PL that can be electrically connected to the first main voltage line 11 may have a mesh structure including the first driving voltage line PL1 and a second driving voltage line PL2 that may intersect the first driving voltage line PL1, the first power supply voltage ELVDD can still be sent to the pixel P disposed in the display area DA even if the first voltage line 10 may not surround one or more corner portions CN and may not extend in a second direction (e.g., the y-direction).

[0072] The second voltage line 20 may surround at least a portion of the display area DA. In one embodiment, the second voltage line 20 may extend along a side other than the side adjacent to the first voltage line 10, excluding the display area DA. For example, the second voltage line 20 may extend to correspond to the second boundary line BL2, the third boundary line BL3, and the fourth boundary line BL4. In another embodiment, the second voltage line 20 may correspond to the second boundary line BL2 and the fourth boundary line BL4.

[0073] The second voltage line 20 may surround the corner portion CN. If the corner portion CN includes curvature, the second voltage line 20 may also include curvature. In another example, even if the corner portion CN includes curvature, the second voltage line 20 may have a curved shape.

[0074] The second voltage line 20 may include a second main voltage line 21 that may surround at least a portion of the display area DA, and a second connecting line 22 that is parallel to the first connecting line 12 in a second direction (e.g., the y-direction). The second connecting line 22 may be electrically connected to a second terminal 32 of the terminal component 30.

[0075] In one embodiment, the width L1 of the first voltage line 10 may be smaller than the width L2 of the second voltage line 20. Each of the width L1 of the first voltage line 10 and the width L2 of the second voltage line 20 may be defined in a direction perpendicular to the direction in which the first voltage line 10 and the second voltage line 20 may extend. For example, the width L1 of the first voltage line 10 may be defined as the length of the first main voltage line 11 in a second direction (e.g., the y direction) perpendicular to a first direction (e.g., the x-direction). The width L2 of the second voltage line 20 may be defined as the length of the portion of the second main voltage line 21 corresponding to the first boundary line BL1 in a second direction (e.g., the y direction) perpendicular to the first direction (e.g., the x-direction). In one embodiment, the width L2 of the second voltage line 20 may be larger than the width L1 of the first voltage line 10, thereby reducing the heat generated by the second voltage line 20.

[0076] To achieve a brighter screen and enhance visibility even in outdoor environments with high ambient light, it may be necessary to increase the amount of current flowing through the display element. Therefore, it may be necessary to increase the amount of current flowing through the first voltage line 10 and the second voltage line 20. Unlike the embodiment described above, in the case where both the first voltage line 10 and the second voltage line 20 extend to and correspond to the corner portion CN, and a large current flows through the first voltage line 10 and the second voltage line 20, the heat generated by the portion corresponding to the corner portion CN of the non-display area NDA may be higher (increased) compared to the heat generated by the portion corresponding to other boundary lines. Organic Light Emitting Diode (OLED) (see...) Figure 2 The display area DA may degrade within the portion corresponding to the corner CN. In one embodiment, the first voltage line 10 may correspond to the first boundary line BL1 and may be electrically connected to the first driving voltage line PL1 and the second driving voltage line PL2, which can be provided as a mesh structure. Additionally, the second voltage line 20 may be disposed at the corner CN, and the width L2 of the second voltage line 20 may be greater than the width L1 of the first voltage line 10, thereby reducing the heat generated by the corner CN. Therefore, in one or more embodiments of this disclosure, even in outdoor environments with high external light levels, the amount of current flowing through the first voltage line 10 and the second voltage line 20 can be increased, thereby enhancing visibility. Degradation of the organic light-emitting diode (OLED) disposed in the portion corresponding to the corner CN of the display area DA can be prevented.

[0077] Terminal component 30 may be disposed at one end of substrate 101 and may include terminals, namely, first terminal 31, second terminal 32 and third terminal 33. Terminal component 30 may not be covered by an insulating layer but may be exposed, and thus may be electrically connected to a controller (not shown), such as a flexible printed circuit board or a driver integrated circuit (IC) chip.

[0078] The controller can convert externally transmitted image signals into image data signals and send the image data signals to the display area DA via the third terminal 33. Furthermore, the controller can receive vertical synchronization signals, horizontal synchronization signals, and clock signals to generate control signals for controlling the drive of each of the first and second gate drive circuits (not shown), and send these control signals to each of the first and second gate drive circuits (not shown) via terminals (not shown).

[0079] The controller can send different voltages to the first voltage line 10 and the second voltage line 20 respectively via the first terminal 31 and the second terminal 32. The first voltage line 10 can provide a first power supply voltage ELVDD to each pixel P (see...). Figure 2 Furthermore, the second voltage line 20 can provide a second power supply voltage ELVSS to each pixel P (see...). Figure 2 For example, a first power supply voltage ELVDD can be provided to each pixel P via a drive voltage line PL electrically connected to the first voltage line 10. A second power supply voltage ELVSS can be electrically connected to the organic light-emitting diode OLED provided in each pixel P in the non-display area NDA (see...). Figure 2 The cathode of ).

[0080] Although not shown, it is used to scan the signal Sn (see Figure 2 The scan driver for the scan line SL provided to each pixel P is used to transmit the data signal Dm (see scan driver). Figure 2 The data driver provided to the data line DL and the dam portion adjacent to or surrounding the display area DA can be located in the non-display area NDA.

[0081] In one embodiment, the metal pattern MP can be located between the first voltage line 10 and the second voltage line 20. The metal pattern MP can be positioned along the extension of the first voltage line 10. For example, the metal pattern MP can be positioned along a first virtual straight line ST1. Alternatively, in one embodiment, the metal pattern MP can be located between the display area DA and the cover film 40. The metal pattern MP can be located between the first voltage line 10 and the second voltage line 20 in a first direction (e.g., the x-direction) and between the display area DA and the cover film 40 in a second direction (e.g., the y-direction). Reference will be made below. Figure 4Provide a detailed description of the metal pattern MP.

[0082] The cover film 40 can be disposed in the non-display area NDA. The cover film 40 can be separated from the display area DA in a second direction (e.g., the y-direction). The cover film 40 can be disposed on the first voltage line 10 and the second voltage line 20. That is, the first voltage line 10 and the second voltage line 20 can be between the substrate 101 and the cover film 40. Therefore, the cover film 40 can cover a portion of the first voltage line 10 or a portion of the second voltage line 20.

[0083] The cover film 40 may overlap with the first voltage line 10 or the second voltage line 20. For example, the cover film 40 may partially overlap with the first main voltage line 11 and may overlap with the first connecting line 12. In addition, the cover film 40 may partially overlap with the second main voltage line 21 and may overlap with the second connecting line 22.

[0084] The cover film 40 can have various structures that can shield light. In some embodiments, the cover film 40 may be a film covered with a material for absorbing light or preventing light transmission. The cover film 40 may include a flexible film.

[0085] Figure 4 yes Figure 3 An enlarged schematic diagram of region IV. Figure 4 In the middle, in the appendix Figure 3 Similar reference numerals in the figures represent similar elements. Therefore, redundant descriptions of them will be omitted.

[0086] refer to Figure 4 as well as Figure 3 The display device 1 may include a display area DA and a non-display area NDA surrounding the display area DA. A first voltage line 10 may be disposed in the non-display area NDA and may supply a first power supply voltage ELVDD to a pixel P disposed in the display area DA. The first voltage line 10 may include a first main voltage line 11 and a first connecting line 12. A second voltage line 20 may be disposed in the non-display area NDA, separated from the first voltage line 10, and may supply a second power supply voltage ELVSS to a pixel P disposed in the display area DA. The second voltage line 20 may include a second main voltage line 21 and a second connecting line 22. A metallic pattern MP may be disposed between the first voltage line 10 and the second voltage line 20. A cover film 40 may be disposed in the non-display area NDA.

[0087] In one embodiment, the first voltage line 10 may include a first lower voltage line and a first upper voltage line on the first lower voltage line. For example, as... Figure 4As shown, the first main voltage line 11 may include a first lower main voltage line 11a and a first upper main voltage line 11b on the first lower main voltage line 11a. The width of the first lower main voltage line 11a may be greater than the width of the first upper main voltage line 11b. Furthermore, the first lower main voltage line 11a and the first upper main voltage line 11b may be electrically connected to each other via a first contact hole CNT1 in the insulating layer between the first lower main voltage line 11a and the first upper main voltage line 11b.

[0088] In one embodiment, the second voltage line 20 may include a second lower voltage line and a second upper voltage line on the second lower voltage line. For example, as... Figure 4 As shown, the second main voltage line 21 may include a second lower main voltage line 21a and a second upper main voltage line 21b on the second lower main voltage line 21a. The width of the second lower main voltage line 21a may be greater than the width of the second upper main voltage line 21b. Furthermore, the second lower main voltage line 21a and the second upper main voltage line 21b may be electrically connected to each other via a second contact hole CNT2 in the insulating layer between the second lower main voltage line 21a and the second upper main voltage line 21b.

[0089] In this embodiment, the width L1 of the first voltage line 10 may be smaller than the width L2 of the second voltage line 20. The width L1 of the first voltage line 10 may be defined as the width of the first lower main voltage line 11a. The width L2 of the second voltage line 20 may be defined as the width of the second lower main voltage line 21a.

[0090] In one embodiment, the shortest distance d between the first voltage line 10 and the second voltage line 20 can be greater than the width MPW of the metal pattern MP. The shortest distance d between the first voltage line 10 and the second voltage line 20 can be defined as the minimum value of the spacing between adjacent first voltage lines 10 and second voltage lines 20. For example, refer to... Figure 4 The shortest distance d between the first voltage line 10 and the second voltage line 20 can be the spacing distance between the first main voltage line 11 and the second main voltage line 21 in a first direction (e.g., the x direction). Because the width MPW of the metal pattern MP can be smaller than the spacing distance between the first main voltage line 11 and the second main voltage line 21, the metal pattern MP can be between the first main voltage line 11 and the second main voltage line 21.

[0091] In one embodiment, the first voltage line 10 and the metal pattern MP can be separated from each other. For example, the first main voltage line 11 and the metal pattern MP can be separated from each other in a first direction (e.g., the x-direction). The distance W1 between the first main voltage line 11 and the metal pattern MP can be equal to or less than about 50 μm. More specifically, the distance W1 between the first main voltage line 11 and the metal pattern MP can be from about 1 μm to about 50 μm. When the distance W1 between the metal pattern MP and the first voltage line 10 is equal to or less than about 1 μm, the metal pattern MP and the first voltage line 10 may extend into each other due to process errors during their formation.

[0092] In one embodiment, the second voltage line 20 and the metal pattern MP can be separated from each other. For example, the second main voltage line 21 and the metal pattern MP can be separated from each other in a first direction (e.g., the x-direction). The distance W2 between the second main voltage line 21 and the metal pattern MP can be equal to or less than about 50 μm. More specifically, the distance W2 between the metal pattern MP and the second voltage line 20 can be from about 1 μm to about 50 μm. When the distance W2 between the metal pattern MP and the second voltage line 20 is equal to or less than about 1 μm, the metal pattern MP and the second voltage line 20 may extend into each other due to process errors during the formation of the metal pattern MP and the second voltage line 20.

[0093] In one embodiment, the metal pattern MP can be positioned between the first voltage line 10 and the second voltage line 20, minimizing flicker that may be caused by external light reflection in the non-display area NDA due to the distance between the first voltage line 10 and the second voltage line 20. Unlike the embodiment described above, where the metal pattern MP may not be positioned between the first voltage line 10 and the second voltage line 20, the distance between the first voltage line 10 and the second voltage line 20 can be approximately 50 μm or more. Furthermore, due to process errors in the process of attaching the cover film 40 to the non-display area NDA, a transmissive region TA that allows external light to pass through may be formed between the display area DA and the cover film 40.

[0094] Therefore, a user may perceive external light or external light reflection through the transmissive region TA defined between the first voltage line 10 and the second voltage line 20 and between the display area DA and the cover film 40. For example, a user may perceive flicker caused by external light or external light reflection in the transmissive region TA adjacent to the display area DA. In particular, if both the width of the transmissive region TA in the first direction (e.g., the x-direction) and the width of the transmissive region TA in the second direction (e.g., the y-direction) exceed approximately 50 μm, the user may perceive external light or external light reflection. In one embodiment, the metal pattern MP may be located between the first voltage line 10 and the second voltage line 20, such that flicker that may be caused by external light or external light reflection in the transmissive region TA can be minimized. In particular, if the distance W1 between the first voltage line 10 and the metal pattern MP and / or the distance W2 between the second voltage line 20 and the metal pattern MP is equal to or less than approximately 50 μm, the user may not perceive external light or external light reflection. Therefore, flicker caused by external light or external light reflection in the non-display area NDA can be minimized.

[0095] In the following text, reference will be made to Figures 5 to 7 The stacking structure of display device 1 is described in detail.

[0096] Figures 5 to 7 The display device 1 according to one embodiment is along Figure 3 The line A-A' and Figure 4 A schematic cross-sectional view taken from line B-B'. Figures 5 to 7 In Figure 3 and Figure 4 Similar reference numerals in the figures represent similar elements, and therefore redundant descriptions of them will be omitted.

[0097] refer to Figures 5 to 7 A pixel circuit PC and an organic light-emitting diode (OLED) that can be electrically connected to the pixel circuit PC as a display element can be disposed on the substrate 101. The pixel circuit PC may include a thin-film transistor (TFT) and a storage capacitor Cst, as shown in the reference. Figure 2 As described above.

[0098] The buffer layer 201 can be located between the substrate 101 and the thin-film transistor (TFT) and can prevent impurities from penetrating into the TFT. The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof, and may have a single-layer structure or a multi-layer structure including the inorganic insulating material as described above.

[0099] A thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figures 5 to 7The diagram illustrates a top-gate type, where the gate electrode GE can be disposed on the semiconductor layer Act, and the gate insulating layer 203 is located between the gate electrode GE and the semiconductor layer Act. However, according to another embodiment, the thin-film transistor (TFT) can be a bottom-gate type.

[0100] The semiconductor layer Act may include polycrystalline silicon. As another example, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, organic semiconductor, or a combination thereof. The gate electrode GE may include a low-resistance metallic material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or a combination thereof, and may have a single-layer structure or a multilayer structure including the materials described above.

[0101] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or combinations thereof. The gate insulating layer 203 may have a single-layer structure or a multi-layer structure including the materials described above.

[0102] The source electrode SE and drain electrode DE can be disposed on the same layer, for example, on the second interlayer insulating layer 207, and can comprise the same material. The source electrode SE and drain electrode DE can comprise materials with good conductivity. The source electrode SE and drain electrode DE can comprise conductive materials including Mo, Al, Cu, Ti, or combinations thereof, and can have a single-layer structure or a multilayer structure comprising the materials described above. In one embodiment, the source electrode SE and drain electrode DE can have a multilayer structure of Ti layer, Al layer, and Ti layer (Ti / Al / Ti).

[0103] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 that overlap each other, with a first interlayer insulating layer 205 between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap with a thin-film transistor (TFT). In this regard, Figures 5 to 7 The gate electrode GE of the thin-film transistor TFT is shown to be the lower electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not overlap with the thin-film transistor TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material comprising Mo, Al, Cu, Ti, or combinations thereof, and may have a single-layer structure or a multilayer structure comprising the materials described above.

[0104] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may comprise inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may have a single-layer structure or a multi-layer structure comprising the materials described above.

[0105] The thin-film transistor (TFT) and the storage capacitor Cst can be covered by the first organic insulating layer 209.

[0106] The second organic insulating layer 211 may be disposed on the first organic insulating layer 209. Both the first organic insulating layer 209 and the second organic insulating layer 211 may comprise organic insulating materials. These organic insulating materials may include general polymers such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0107] Pixel electrode 221 may be disposed on second organic insulating layer 211. In some embodiments, inorganic insulating layer (not shown) may be disposed on second organic insulating layer 211, and pixel electrode 221 may be disposed on inorganic insulating layer.

[0108] Pixel electrode 221 can be electrically connected to the thin-film transistor (TFT) of the pixel circuit PC. In this regard, Figures 5 to 7 The thin-film transistor (TFT) and pixel electrode 221 are shown to be electrically connected to each other via a contact conductive pattern CM on a first organic insulating layer 209. The contact conductive pattern CM may include a conductive material comprising Mo, Al, Cu, Ti, or combinations thereof, and may have a single-layer or multi-layer structure comprising the materials described above. In one embodiment, the contact conductive pattern CM may have a multi-layer structure comprising a Ti layer, an Al layer, and a Ti layer (Ti / Al / Ti).

[0109] Pixel electrode 221 may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), zinc aluminum oxide (AZO), or combinations thereof. In another embodiment, pixel electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In another embodiment, pixel electrode 221 may also include a layer formed of ITO, IZO, ZnO, or In2O3 on or below the reflective layer as described above. For example, pixel electrode 221 may have a three-layer structure in which the ITO layer, Ag layer, and ITO layer can be stacked on top of each other.

[0110] The pixel defining layer 213 may cover the edge of the pixel electrode 221 and may include an opening that overlaps with the central portion of the pixel electrode 221. The opening of the pixel electrode 221 may define a light-emitting area.

[0111] The pixel defining layer 213 may include an organic insulating material, such as polyimide. As another example, the pixel defining layer 213 may include an inorganic insulating material. As yet another example, the pixel defining layer 213 may include both organic and inorganic insulating materials.

[0112] Intermediate layer 222 may be disposed on pixel defining layer 213. Intermediate layer 222 may include light-emitting layer 222b. Light-emitting layer 222b may include organic light-emitting material, such as a polymer or low molecular weight organic material that emits light of a certain color. As another example, light-emitting layer 222b may include inorganic light-emitting material or quantum dots.

[0113] The first functional layer 222a and the second functional layer 222c can be respectively disposed below and above the light-emitting layer 222b.

[0114] The first functional layer 222a may have a single-layer structure or a multi-layer structure. For example, the first functional layer 222a may be a hole transport layer (HTL) with a single-layer structure and may be formed of poly(3,4)-ethylene-dihydroxythiophene (PEDOT) or polyaniline (PANI). As another example, the first functional layer 222a may include a hole injection layer (HIL) and an HTL.

[0115] The second functional layer 222c can have a single-layer structure or a multi-layer structure. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0116] Figures 5 to 7 The intermediate layer 222 is shown to include a first functional layer 222a and a second functional layer 222c. However, in another embodiment, the intermediate layer 222 may optionally include the first functional layer 222a and the second functional layer 222c. For example, the intermediate layer 222 may not include the second functional layer 222c.

[0117] The light-emitting layer 222b of the intermediate layer 222 can be disposed in each pixel P, while the first functional layer 222a and the second functional layer 222c can be formed as a single body to cover the pixel P.

[0118] The counter electrode 223 may include a conductive material with a small work function. For example, the counter electrode 223 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or alloys thereof. As another example, the counter electrode 223 may also include a layer such as ITO, IZO, ZnO, or In2O3 on a (semi-)transparent layer comprising the material described above. The counter electrode 223 may be formed as a single body to cover the pixel P. For example, the counter electrode 223 may completely cover the substrate 101. The area of ​​the counter electrode 223 may differ from the area of ​​the first functional layer 222a and the area of ​​the second functional layer 222c as described above.

[0119] The upper portion of the relative electrode 223 may be covered by an encapsulation layer (not shown). The encapsulation layer may include at least one inorganic encapsulation layer and / or at least one organic encapsulation layer. In one embodiment, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0120] Each of the first and second inorganic encapsulation layers may include one or more inorganic insulating materials. The inorganic insulating materials may include alumina, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride. The organic encapsulation layer may include a polymer-based material. The polymer-based material may include acrylic resins, epoxy resins, polyimide, polyethylene, or combinations thereof. The acrylic resin may include polymethyl methacrylate or polyacrylic acid, or combinations thereof.

[0121] In another embodiment, the encapsulation layer may have a structure in which a substrate 101 and an upper substrate, as a transparent member, are combined with each other using a sealing member, and thus the internal space between the substrate 101 and the upper substrate can be sealed. A moisture absorbent or filler material may be disposed in the internal space. The sealing member may be a sealant. In another embodiment, the sealing member may include a material cured by laser. For example, the sealing member may include a glass frit. Specifically, the sealing member may include polyurethane-based resins, epoxy-based resins, acrylic-based resins as organic sealants; silicone resins as inorganic sealants; or combinations thereof. Polyurethane-based resins may include, for example, polyurethane acrylates. Acrylic-based resins may include, for example, butyl acrylate or ethylhexyl acrylate, or combinations thereof. The sealing member may include a material cured by thermosetting.

[0122] A touch electrode layer (not shown), including touch electrodes, may be disposed on an encapsulation layer, and an optical functional layer (not shown) may be disposed on the touch electrode layer. The touch electrode layer can obtain coordinate information based on external input, such as a touch event. The optical functional layer can reduce the reflectivity of light incident on the display device 1 from the outside (external light) and / or can enhance the color purity of light emitted from the display device 1. In one embodiment, the optical functional layer may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include an elongated synthetic resin film, and the liquid crystal coating type may include liquid crystal positioned in a certain arrangement. The phase retarder and polarizer may also include a protective film.

[0123] In another embodiment, the optical functional layer may include a black matrix and color filters. The color filters can be configured based on the color of light emitted from each pixel P. Each color filter may include a red, green, or blue pigment or dye. As another example, in addition to the pigments or dyes described above, each color filter may also include quantum dots. As yet another example, some color filters may not include the pigments or dyes described above and may include scattering particles such as titanium dioxide.

[0124] In another embodiment, the optical functional layer may include a destructive offset structure. The destructive offset structure may include a first reflective layer and a second reflective layer, which may be disposed on different layers. First and second reflected light reflected from each of the first and second reflective layers can destructively interfere. Therefore, the reflectivity of external light can be reduced.

[0125] The first lower main voltage line 11a and the second lower main voltage line 21a can be disposed on the second interlayer insulating layer 207. Specifically, the first lower main voltage line 11a and the second lower main voltage line 21a can be located between the second interlayer insulating layer 207 and the first organic insulating layer 209. The first lower main voltage line 11a and the second lower main voltage line 21a can comprise the same material used to form the source electrode SE or the drain electrode DE. When the source electrode SE or the drain electrode DE can be formed, the first lower main voltage line 11a and the second lower main voltage line 21a can be formed simultaneously.

[0126] The first upper main voltage line 11b and the second upper main voltage line 21b can be disposed on the first organic insulating layer 209. Specifically, the first upper main voltage line 11b and the second upper main voltage line 21b can be located between the first organic insulating layer 209 and the second organic insulating layer 211. The first upper main voltage line 11b and the second upper main voltage line 21b can comprise the same material as the material used to form the contact conductive pattern CM. When the contact conductive pattern CM can be formed, the first upper main voltage line 11b and the second upper main voltage line 21b can be formed simultaneously.

[0127] In one embodiment, reference Figure 5 The metal pattern MP can be disposed on the same layer as the first upper main voltage line 11b or the second upper main voltage line 21b. The metal pattern MP can include the same material used to form the first upper main voltage line 11b or the second upper main voltage line 21b. When the first upper main voltage line 11b or the second upper main voltage line 21b can be formed, the metal pattern MP can be formed simultaneously. For example, after shielding between the first upper main voltage line 11b and the metal pattern MP, and between the second upper main voltage line 21b and the metal pattern MP, can be performed using a mask, the metal pattern MP, the first upper main voltage line 11b, and the second upper main voltage line 21b can be formed.

[0128] The metallic pattern MP can be separated from the first upper main voltage line 11b or the second upper main voltage line 21b. The distance between the metallic pattern MP and the first upper main voltage line 11b, or between the metallic pattern MP and the second upper main voltage line 21b, can be from approximately 1 μm to approximately 50 μm.

[0129] In one embodiment, reference Figure 6 The metal pattern MP can be disposed on the same layer as the first lower main voltage line 11a or the second lower main voltage line 21a. The metal pattern MP can include the same material used to form the first lower main voltage line 11a or the second lower main voltage line 21a. When the first lower main voltage line 11a or the second lower main voltage line 21a can be formed, the metal pattern MP can be formed simultaneously. For example, after shielding between the first lower main voltage line 11a and the metal pattern MP, and between the second lower main voltage line 21a and the metal pattern MP using a mask, the metal pattern MP, the first lower main voltage line 11a, and the second lower main voltage line 21a can be formed.

[0130] The metallic pattern MP can be separated from the first lower main voltage line 11a or the second lower main voltage line 21a. The distance between the metallic pattern MP and the first lower main voltage line 11a or between the metallic pattern MP and the second lower main voltage line 21a can be approximately 1 μm to approximately 50 μm.

[0131] In one embodiment, reference Figure 7 The metal pattern MP may include a lower metal pattern MPa and an upper metal pattern MPb on the lower metal pattern MPa. Figure 7 The lower metal pattern MPa and the upper metal pattern MPb are shown to be separated from each other. However, in some embodiments, the lower metal pattern MPa and the upper metal pattern MPb can be connected to each other via contact holes (not shown) provided in the first organic insulating layer 209.

[0132] The lower metal pattern MPa can be disposed on the same layer as the first lower main voltage line 11a or the second lower main voltage line 21a. The lower metal pattern MPa can include the same material used to form the first lower main voltage line 11a or the second lower main voltage line 21a. When the first lower main voltage line 11a or the second lower main voltage line 21a can be formed, the lower metal pattern MPa can be formed simultaneously. For example, after shielding between the first lower main voltage line 11a and the lower metal pattern MPa, and between the second lower main voltage line 21a and the lower metal pattern MPa using a mask, the lower metal pattern MPa, the first lower main voltage line 11a, and the second lower main voltage line 21a can be formed.

[0133] The lower metal pattern MPa can be separated from the first lower main voltage line 11a or the second lower main voltage line 21a. The distance between the lower metal pattern MPa and the first lower main voltage line 11a, or between the lower metal pattern MPa and the second lower main voltage line 21a, can be approximately 1 μm to approximately 50 μm.

[0134] The upper metal pattern MPb can be disposed on the same layer as the first upper main voltage line 11b or the second upper main voltage line 21b. The upper metal pattern MPb can include the same material used to form the first upper main voltage line 11b or the second upper main voltage line 21b. When the first upper main voltage line 11b or the second upper main voltage line 21b can be formed, the upper metal pattern MPb can be formed simultaneously. For example, after shielding between the first upper main voltage line 11b and the upper metal pattern MPb, and between the second upper main voltage line 21b and the upper metal pattern MPb using a mask, the upper metal pattern MPb, the first upper main voltage line 11b, and the second upper main voltage line 21b can be formed.

[0135] The upper metal pattern MPb can be separated from the first upper main voltage line 11b or the second upper main voltage line 21b. The distance between the upper metal pattern MPb and the first upper main voltage line 11b, or between the upper metal pattern MPb and the second upper main voltage line 21b, can be from about 1 μm to about 50 μm.

[0136] Figure 8 This is a schematic plan view of the display panel 100 and the cover film 40 of the display device 1 according to another embodiment. Figure 9 yes Figure 8 A magnified view of region IX. Figure 8 and Figure 9 In Figure 3 and Figure 4 Similar reference numerals in the figures represent similar elements, and therefore redundant descriptions of them will be omitted.

[0137] refer to Figure 8 and Figure 9 The display device 1 may include a display area DA and a non-display area NDA that may surround the display area DA. A first voltage line 10 may be disposed in the non-display area NDA and may supply a first power supply voltage ELVDD to each pixel P disposed in the display area DA. At least a portion of the first voltage line 10 may overlap with a first virtual straight line ST1 parallel to one side of the display area DA. The first voltage line 10 may include a first main voltage line 11 and a first connecting line 12. A second voltage line 20 may be disposed in the non-display area NDA, separated from the first voltage line 10, and may supply a second power supply voltage ELVSS to each pixel P disposed in the display area DA. The second voltage line 20 may include a second main voltage line 21 and a second connecting line 22. A metallic pattern MP may be disposed between the first voltage line 10 and the second voltage line 20, and the metallic pattern MP may be disposed along the first virtual straight line ST1. In addition, a cover film 40 may be disposed in the non-display area NDA.

[0138] In one embodiment, the first voltage line 10 or the second voltage line 20 may include a hole. For example, the first voltage line 10 may include a first hole H1, and the second voltage line 20 may include a second hole H2. In another example, the first voltage line 10 may include a first hole H1, and the second voltage line 20 may not include a hole. In yet another example, the first voltage line 10 may not include a hole, and the second voltage line 20 may include a second hole H2. However, for ease of explanation, the case where the first voltage line 10 includes a first hole H1 and the second voltage line 20 includes a second hole H2 will be described in detail.

[0139] A first aperture H1 can be provided to reduce the heat generated by the first voltage line 10. A second aperture H2 can be provided to reduce the heat generated by the second voltage line 20. Each of the first aperture H1 and the second aperture H2 can increase the heat dissipation area of ​​the first voltage line 10 and the second voltage line 20. Therefore, degradation of the organic light-emitting diode (OLED) disposed in the display area DA adjacent to the first voltage line 10 and the second voltage line 20 can be prevented.

[0140] In one embodiment, the first holes H1 can be arranged at a fixed interval. In another embodiment, any one of the adjacent first holes H1 can be arranged at a different distance from another adjacent first hole H1. The distance between the first holes H1 can vary depending on the degree of heating of the first voltage line 10.

[0141] exist Figure 9 In this embodiment, the first aperture H1 may be separated from the cover film 40. In one embodiment, the width of the first aperture H1 may be equal to or less than approximately 50 μm. Therefore, a user may not be able to perceive external light or external light reflection caused by the first aperture H1. In another embodiment, the first aperture H1 may overlap with the cover film 40. In one embodiment, the width of the first aperture H1 may be equal to or greater than approximately 50 μm. Because the first aperture H1 may overlap with the cover film 40, a user may not be able to perceive external light or external light reflection.

[0142] In one embodiment, the first holes H1 may have the same size. In another embodiment, any one of the first holes H1 may be provided with a different size than the other of the first holes H1. The size of the first holes H1 may vary depending on the degree of heating of the first voltage line 10.

[0143] In one embodiment, the second holes H2 can be arranged at a fixed interval. In another embodiment, any one of the adjacent second holes H2 can be arranged at a different distance from another adjacent second hole H2. The distance between the second holes H2 can vary depending on the degree of heating of the second voltage line 20.

[0144] In one embodiment, the second holes H2 may have the same size. In another embodiment, either of the second holes H2 may be provided with a different size than the other. For example, the width of the second hole H2 separated from the cover film 40 may be equal to or less than approximately 50 μm. The user may not be able to perceive external light or external light reflection caused by the second hole H2. The width of the second hole H2 that may overlap with the cover film 40 may be equal to or greater than 50 μm. Because the second hole H2 may overlap with the cover film 40, the user may not be able to perceive external light or external light reflection. In addition, the size of the second hole H2 may vary depending on the degree of heating of the second voltage line 20.

[0145] As described above, in one or more embodiments of this disclosure, a brighter screen can be achieved, and a metallic pattern can be provided between the first voltage line and the second voltage line, so that flicker that may be caused by external light or external light reflection in the non-display area can be minimized.

[0146] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made in one or more embodiments without departing from the spirit and scope of this disclosure.

Claims

1. A display device, wherein, The display device includes: A substrate, comprising a display area and a non-display area adjacent to the display area; Pixels are set in the display area; A first voltage line is disposed in the non-display area and supplies a first power supply voltage to the pixel; A second voltage line is disposed in the non-display area and supplies a second power supply voltage to the pixel. The second voltage line is separated from the first voltage line, and the second voltage line surrounds the corner portion of an adjacent boundary line among a plurality of boundary lines connecting the boundary between the display area and the non-display area; and A metallic pattern is disposed between the first voltage line and the second voltage line. Wherein, the shortest distance between the first voltage line and the second voltage line is greater than the width of the metal pattern, and The width of the second voltage line is greater than the width of the first voltage line.

2. The display device according to claim 1, wherein, The distance between the first voltage line and the metal pattern is 1 μm to 50 μm, and The distance between the second voltage line and the metal pattern is 1 μm to 50 μm.

3. The display device according to claim 1, wherein... At least a portion of the first voltage line overlaps with a first virtual line parallel to one side of the display area, and The second voltage line surrounds at least a portion of the display area.

4. The display device according to claim 1, wherein, The first voltage line includes a first lower voltage line and a first upper voltage line on the first lower voltage line, and The metal pattern and the first lower voltage line or the first upper voltage line are disposed on the same layer.

5. The display device according to claim 1, wherein, The display device further includes a cover film in the non-display area.

6. The display device according to claim 5, wherein, The cover film is separated from the metal pattern in the direction in which the cover film is separated from the display area.

7. The display device according to claim 5, wherein, The metallic pattern is disposed between the cover film and the display area.

8. The display device according to claim 1, wherein, The first voltage line or the second voltage line includes a hole.

9. A display device, wherein, The display device includes: A substrate, comprising a display area and a non-display area adjacent to the display area; Covering film, in the non-display area; Pixels are set in the display area; A first voltage line is disposed between the substrate and the cover film and electrically connected to the pixel, wherein at least a portion of the first voltage line overlaps with a first virtual line parallel to one side of the display area; A second voltage line is disposed between the substrate and the cover film and electrically connected to the pixel. The second voltage line is separated from the first voltage line and surrounds the corner portion of an adjacent boundary line among a plurality of boundary lines defining the display area and the non-display area. A metallic pattern is disposed between the first voltage line and the second voltage line. The metal pattern is arranged along the first virtual line, and The width of the second voltage line is greater than the width of the first voltage line.

10. The display device according to claim 9, wherein, The metallic pattern is disposed between the display area and the cover film.

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