Display device

Abstract

A display device with a bankless structure, the display device may include: a substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer, which is arranged on the substrate and includes a lower electrode of a storage capacitor; an active layer, which is formed on the first conductive layer; a second conductive layer, which is formed on the active layer and includes an electrode of at least one transistor and an upper electrode of a storage capacitor, wherein the upper electrode of the storage capacitor and at least one of the electrodes of the at least one transistor are formed in a single pattern; an overcoat, which covers the second conductive layer; and a light-emitting element, which may be arranged on the overcoat and connected to the upper electrode of the storage capacitor through a through hole, wherein the through hole does not overlap with the at least one transistor when viewed from above.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method for manufacturing the same. Background Art

[0002] The organic light emitting element (hereinafter referred to as the light emitting element) constituting the organic light emitting diode display is self-luminous and does not require a separate light source, thereby reducing the thickness and weight of the display device. In addition, the organic light emitting diode display has high quality characteristics such as low power consumption, high brightness and high response rate.

[0003] Generally, a light-emitting element has a structure in which an anode electrode, a bank surrounding an edge region of the anode electrode, a light-emitting layer formed on the anode electrode at the inside of the bank, and a cathode electrode covering the light-emitting layer and the bank are stacked. The amount of current flowing to the light-emitting element is controlled by a driving transistor so that the light-emitting element emits light at a desired brightness.

[0004] The foregoing content is only intended to help understand the background of the present disclosure, but is not intended to indicate that the present disclosure falls within the scope of the relevant technologies known to those skilled in the art. Summary of the invention

[0005] Embodiments are directed to providing a display device having a bank-less structure in which banks of an organic light emitting element are omitted, thereby reducing process steps and manufacturing costs.

[0006] Embodiments are directed to providing a display device having a bankless structure, which prevents a light emitting element in a non-light emitting area from emitting light and prevents a short circuit between an anode electrode and a cathode electrode of the light emitting element.

[0007] Embodiments are directed to providing a display device having a bankless structure including a repair pattern in order to repair a pixel without damaging a light emitting element.

[0008] According to one embodiment, a display device with a bankless structure may include: a substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer, which is arranged on the substrate and includes a lower electrode of a storage capacitor; an active layer, which is formed on the first conductive layer; a second conductive layer, which is formed on the active layer and includes an electrode of at least one transistor, and an upper electrode of the storage capacitor, and the upper electrode of the storage capacitor and at least one of the electrodes of the at least one transistor are formed in a single pattern; an overcoat, which covers the second conductive layer; and a light-emitting element, which may be arranged on the overcoat and connected to the upper electrode of the storage capacitor through a through hole, wherein the through hole does not overlap with the at least one transistor when viewed from above.

[0009] The light emitting element may include: an anode electrode, which is disposed on the overcoat layer and connected to the upper electrode of the storage capacitor through a through hole; a light emitting layer, which covers the entire surface of the anode electrode; and a cathode electrode, which covers the cathode electrode of the light emitting layer.

[0010] The display device may further include a light absorbing layer disposed below the overcoat layer in the non-light emitting region and composed of a colorant.

[0011] The light absorbing layer may include at least one of a first absorbing layer including a colorant of a first color and a second absorbing layer including a colorant of a second color.

[0012] The display device may further include: a color filter formed over the second conductive layer in the light emitting region.

[0013] The display device may further include: a buffer layer covering the first conductive layer; a gate insulating layer covering the active layer; and a passivation layer covering the second conductive layer.

[0014] According to one embodiment, a display device with a bankless structure may include: a substrate on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer, which is arranged on the substrate and includes a lower electrode of a storage capacitor; an active layer, which is formed on the first conductive layer; a second conductive layer, which is formed on the active layer and includes an electrode of at least one transistor, and an upper electrode of the storage capacitor, the upper electrode of the storage capacitor and at least one of the electrodes of the at least one transistor being formed in a single pattern; an overcoat, which covers the second conductive layer; and a light-emitting element, which is arranged on the overcoat and connected to the upper electrode of the storage capacitor through a through hole, wherein the at least one transistor includes a driving transistor, which controls an amount of current flowing to the light-emitting element in response to a voltage stored in the storage capacitor, and the driving transistor includes: a first electrode, which is included in the second conductive layer and is connected to a power line; a second electrode, which is included in the second conductive layer and is connected to the lower electrode of the storage capacitor; and a third electrode, which is included in the second conductive layer, which is formed in a single pattern with the upper electrode of the storage capacitor and is connected to the light-emitting element via the upper electrode of the storage capacitor.

[0015] The through hole may be disposed closer to the light emitting region than the driving transistor.

[0016] The first conductive layer may further include a light shielding layer, and the light shielding layer is arranged in such a manner that at least one region thereof overlaps with the driving transistor.

[0017] According to one embodiment, a display device with a bankless structure may include: a substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer, which is arranged on the substrate and includes a lower electrode of a storage capacitor; an active layer, which is formed on the first conductive layer; a second conductive layer, which is formed on the active layer and includes an electrode of at least one transistor, and an upper electrode of the storage capacitor, and the upper electrode of the storage capacitor and at least one of the electrodes of the at least one transistor are formed in a single pattern; an overcoat, which covers the second conductive layer; and a light-emitting element, which is arranged on the overcoat and connected to the upper electrode of the storage capacitor through a through hole, wherein the upper electrode is constructed as a plurality of layers, and a first electrode pattern arranged at the second conductive layer and a second electrode pattern arranged at the active layer overlap in the plurality of layers.

[0018] According to one embodiment, a display device with a bankless structure may include: a substrate on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer, which is arranged on the substrate and includes a lower electrode of a storage capacitor; an active layer, which is formed on the first conductive layer; a second conductive layer, which is formed on the active layer and includes an electrode of at least one transistor, and an upper electrode of the storage capacitor, and the upper electrode of the storage capacitor and at least one of the electrodes of the at least one transistor are formed in a single pattern; an overcoat, which covers the second conductive layer; and a light-emitting element, which is arranged on the overcoat and connected to the upper electrode of the storage capacitor through a through hole, wherein, among the pixels, the areas of the upper electrode and the lower electrode of the pixel displaying white are set to be smaller than the areas of the upper electrode and the lower electrode of the pixel displaying red, blue or green.

[0019] According to one embodiment, a display device with a bankless structure may include: a substrate on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer, which is arranged on the substrate and includes a lower electrode of a storage capacitor; an active layer, which is formed on the first conductive layer; a second conductive layer, which is formed on the active layer and includes an electrode of at least one transistor, and an upper electrode of the storage capacitor, wherein the upper electrode of the storage capacitor and at least one of the electrodes of the at least one transistor are formed in a single pattern; an overcoat, which covers the second conductive layer; and a light-emitting element, which is arranged on the overcoat and connected to the upper electrode of the storage capacitor through a through hole, wherein the overcoat is formed in an area other than the light-emitting area of ​​a pixel displaying white among the pixels.

[0020] According to one embodiment, a display device with a bankless structure may include: a substrate on which pixels are arranged, the pixels including a light-emitting region and a circuit region in which circuit elements are arranged, and emitting white light; a first conductive layer, the first conductive layer is arranged on the substrate and includes a lower electrode of a storage capacitor; an active layer, the active layer is formed above the first conductive layer; a second conductive layer, the second conductive layer is formed on the active layer and includes an electrode of at least one transistor; an overcoat, the overcoat covers the second conductive layer; and an anode electrode, the anode electrode is arranged on the overcoat, wherein the anode electrode includes an extension portion extending from the light-emitting region to the circuit region and constituting an upper electrode of the storage capacitor.

[0021] The anode electrode may be configured to emit light in the circuit region through the extension portion.

[0022] The first conductive layer may further include a light shielding layer, and the upper electrode and the lower electrode of the storage capacitor are disposed not to overlap the light shielding layer.

[0023] The overcoat layer may be omitted between the upper electrode and the lower electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 is a block diagram showing a configuration of a display device according to an embodiment;

[0026] Figure 2 It is shown Figure 1 A circuit diagram of an embodiment of the pixel shown;

[0027] Figure 3A and Figure 3B is a diagram showing a planar layout of a pixel according to an embodiment;

[0028] Figure 4A It is shown along Figure 3B A diagram of an embodiment of a cross-sectional view taken along line II';

[0029] Figure 4B It is shown along Figure 3B A diagram of another embodiment of a cross-sectional view taken along line II';

[0030] Figure 4C It is along Figure 3B A cross-sectional view taken along line I"-I"';

[0031] Figure 5 is a cross-sectional view of a storage capacitor according to another embodiment;

[0032] FIG. 6A to FIG. 6Dis a diagram showing a short circuit problem in a light emitting element that may occur in a display device having a bankless structure;

[0033] Figure 7 is a diagram showing a method of forming a first through hole according to an embodiment;

[0034] Figure 8 and Fig. 9 is a diagram showing a method of repairing a display device according to an embodiment;

[0035] Fig.10 and Fig.11 is a diagram showing a short circuit problem in a light emitting element that may occur during a repair process;

[0036] Fig.12 It shows the repair FIG. 4A to FIG. 5 A diagram of the pixel method shown;

[0037] Fig.13 is a diagram showing a method of repairing a display device according to another embodiment;

[0038] Fig.14 It shows the repair FIG. 4A to FIG. 5 A diagram of the pixel method shown;

[0039] Fig.15 It is along Figure 3A A cross-sectional view taken along line II-II';

[0040] Fig.16 is a diagram showing a planar layout of white pixels according to another embodiment;

[0041] Fig.17 It is along Fig.16 A cross-sectional view taken along line III-III'; and

[0042] Fig.18 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this specification, when an element (region, layer, component, etc.) is referred to as being "on another element", "connected to another element" or "combined with another element", it may be directly on another element / connected to another element / combined with another element, or there may be intermediate elements therebetween.

[0044] The same reference numerals represent the same elements. In the drawings, the thickness, proportion and size of the elements are exaggerated to effectively describe the technical details. The term "and / or" includes one or more combinations that the related elements can define.

[0045] The terms "first", "second", etc. may be used to describe various elements, but the elements should not be construed as being limited to these terms. These terms are only used to distinguish an element from other elements. For example, without departing from the scope of the embodiments, the "first" element may be named as the "second" element, and the "second" element may also be named as the "first" element similarly. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include plural forms.

[0046] The terms "lower", "below", "upper", "above", etc. are used herein to describe the relationship between one or more elements shown in the drawings. These terms are relative concepts and are described based on directions in the drawings.

[0047] It should be understood that terms such as "including", "having", etc. are intended to indicate the presence of features, numbers, steps, actions, elements, components, or a combination thereof disclosed in the specification, but are not intended to exclude the possibility that one or more other features, numbers, steps, actions, elements, components, or a combination thereof may exist or may be added.

[0048] Figure 1 is a block diagram showing a configuration of a display device according to an embodiment.

[0049] Reference Figure 1 , the display device 1 includes a timing controller 10 , a gate driver 20 , a data driver 30 , a power supply 40 and a display panel 50 .

[0050] The timing controller 10 may receive an image signal RGB and a control signal CS from the outside. The image signal RGB may include grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0051] The timing controller 10 may process the image signal RGB and the control signal CS to adapt the signals to the operating conditions of the display panel 50 , so that the timing controller 10 may generate and output the image data DATA, the gate driving control signal CONT1 , the data driving control signal CONT2 , and the power control signal CONT3 .

[0052] The gate driver 20 may be connected to the pixels (or sub-pixels) PX of the display panel 50 through a plurality of first gate lines GL11 to GL1n. The gate driver 20 may generate a gate signal based on a gate driving control signal CONT1 output from the timing controller 10. The gate driver 20 may provide the generated gate signal to the pixels PX through the plurality of first gate lines GL11 to GL1n.

[0053] In various embodiments, the gate driver 20 may also be connected to the pixels PX of the display panel 50 through a plurality of second gate lines GL21 to GL2n. The gate driver 20 may provide a sensing signal to the pixels PX through the plurality of second gate lines GL21 to GL2n. The sensing signal may be provided to measure the characteristics of the driving transistor and / or the light emitting element disposed inside the pixel PX.

[0054] The data driver 30 may be connected to the pixels PX of the display panel 50 through the plurality of data lines DL1 to DLm. The data driver 30 may generate data signals based on the image data DATA and the data driving control signal CONT2 output from the timing controller 10. The data driver 30 may provide the generated data signals to the pixels PX through the plurality of data lines DL1 to DLm.

[0055] In various embodiments, the data driver 30 may also be connected to the pixels PX of the display panel 50 through a plurality of sensing lines (or reference lines) SL1 to SLm. The data driver 30 may provide a reference voltage (sensing voltage or initialization voltage) to the pixels PX through the plurality of sensing lines SL1 to SLm, or may sense the state of the pixels PX based on an electrical signal fed back from the pixels PX.

[0056] The power supply 40 may be connected to the pixels PX of the display panel 50 through a plurality of power supply lines PL1 and PL2. The power supply 40 may generate a driving voltage to be provided to the display panel 50 based on a power supply control signal CONT3. The driving voltage may include, for example, a high potential driving voltage ELVDD and a low potential driving voltage ELVSS. The power supply 40 may provide the generated driving voltages ELVDD and ELVSS to the pixels PX through the corresponding power supply lines PL1 and PL2.

[0057] In the display panel 50, a plurality of pixels PX (or referred to as sub-pixels) are arranged. The pixels PX may be arranged on the display panel 50, for example, in a matrix form.

[0058] Each pixel PX may be electrically connected to a corresponding gate line and a corresponding data line. Such a pixel PX may emit light having brightness corresponding to a gate signal and a data signal provided through the first gate lines GL11 to GL1n and the data lines DL1 to DLm, respectively.

[0059] Each pixel PX can display any one of the first color to the third color. In one embodiment, each pixel PX can display any one of red, green and blue. In another embodiment, each pixel PX can display any one of cyan, magenta and yellow. In various embodiments, the pixel PX can be configured to display any one of four or more colors. For example, each pixel PX can display any one of red, green, blue and white.

[0060] The timing controller 10, the gate driver 20, the data driver 30 and the power supply 40 may be configured as separate integrated circuits (ICs) or at least some of them may be integrated ICs. For example, at least one of the data driver 30 and the power supply 40 may be configured as an integrated circuit integrated with the timing controller 10.

[0061] In addition, Figure 1 , the gate driver 20 and the data driver 30 are shown as elements separated from the display panel 50, but at least one of the gate driver 20 and the data driver 30 may be configured in an in-panel manner formed to be integrated with the display panel 50. For example, the gate driver 20 may be formed to be integrated with the display panel 50 according to a gate-in-panel (GIP) manner.

[0062] Figure 2 It is shown Figure 1 Circuit diagram of an embodiment of a pixel is shown. Figure 2 A pixel PXij connected to an i-th first gate line GL1i and a j-th data line DLj is shown as an example.

[0063] Reference Figure 2 , the pixel PX includes a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst and a light emitting element LD.

[0064] A first electrode (e.g., source) of the switching transistor ST is electrically connected to the j-th data line DLj, and a second electrode (e.g., drain) of the switching transistor ST is electrically connected to the first node N1. A gate of the switching transistor ST is electrically connected to the i-th first gate line GL1i. When a gate signal at a gate-on level is applied through the i-th first gate line GL1i, the switching transistor ST is turned on and transmits a data signal applied through the j-th data line DLj to the first node N1.

[0065] A first electrode of the storage capacitor Cst is electrically connected to the first node N1, and a second electrode of the storage capacitor Cst receives the high potential driving voltage ELVDD. The storage capacitor Cst may be charged with a voltage corresponding to a difference between a voltage applied to the first node N1 and the high potential driving voltage ELVDD.

[0066] A first electrode (e.g., source) of the driving transistor DT receives a high potential driving voltage ELVDD, and a second electrode (e.g., drain) of the driving transistor DT is electrically connected to a first electrode (e.g., anode electrode) of the light emitting element LD. A gate of the driving transistor DT is electrically connected to a first node N1. When a voltage at a gate-on level is applied through the first node N1, the driving transistor DT is turned on, and the amount of driving current flowing to the light emitting element LD can be controlled according to a voltage supplied to the gate (i.e., a voltage stored in the storage capacitor Cst).

[0067] A first electrode (e.g., source) of the sensing transistor SST is electrically connected to the j-th sensing line SLj, and a second electrode (e.g., drain) of the sensing transistor SST is electrically connected to a first electrode (e.g., anode electrode) of the light emitting element LD. A gate of the sensing transistor SST is electrically connected to the i-th second gate line GL2i. When a sensing signal at a gate-on level is applied through the i-th second gate line GL2i, the sensing transistor SST is turned on and transmits a reference voltage applied through the j-th sensing line SLj to the anode electrode of the light emitting element LD.

[0068] The light emitting element LD outputs light corresponding to the driving current. The light emitting element LD may output light corresponding to any one of red, green, and blue. The light emitting element LD may be an organic light emitting diode (OLED) or an ultra-small inorganic light emitting diode having a size ranging from micrometers to nanometers, but the present disclosure is not limited thereto. Hereinafter, an embodiment in which the light emitting element LD is configured as an organic light emitting diode will be described.

[0069] In the present disclosure, the structure of the pixel PX is not limited to Figure 2 According to one embodiment, the pixel PX may further include at least one element for compensating for the threshold voltage of the driving transistor DT or initializing the voltage of the gate of the driving transistor DT and / or the voltage of the anode electrode of the light emitting element LD.

[0070] Figure 2 An example in which the switch transistor ST, the drive transistor, and the sense transistor SST are NMOS transistors is shown, but the present disclosure is not limited thereto. For example, at least some or all of the transistors constituting each pixel PX may be configured as PMOS transistors. In various embodiments, each of the switch transistor ST, the drive transistor DT, and the sense transistor SST may be implemented as a low temperature polycrystalline silicon (LTPS) thin film transistor, an oxide thin film transistor, or a low temperature polycrystalline oxide (LTPO) thin film transistor.

[0071] Figure 3A and Figure 3B is a diagram showing a planar layout of a pixel according to an embodiment.

[0072] Refer to Figure 2 , Figure 3A and Figure 3B The display panel 50 includes pixel areas PXA defined at intersections of data lines DL extending in a first direction (e.g., pixel column direction (DR1)) and first and second gate lines GL1 and GL2 extending in a second direction (e.g., pixel row direction (DR2). Pixels PX are arranged in each pixel area PXA.

[0073] Each pixel region PXA may include a light emitting region EA and a non-light emitting region NEA. In the light emitting region EA, a light emitting element LD of the pixel PX is disposed. In the non-light emitting region NEA, circuit elements (e.g., a switching transistor ST, a driving transistor DT, a sensing transistor SST, and a storage capacitor Cst) for driving the light emitting element LD are disposed. The light emitting element LD is driven by the circuit elements disposed in the non-light emitting region NEA and emits light of a specific color.

[0074] The wiring area WA may be defined between the pixel columns. In each wiring area WA, a data line DL and a sensing line SL extending in the first direction DR1 are disposed. The data line DL may receive a data signal from the data driver 30. The sensing line SL may receive a reference voltage from the data driver 30, or may transmit an electrical signal output from a corresponding pixel PX to the data driver 30.

[0075] In one embodiment, in some wiring areas WA, first power lines PL1 for applying a high potential driving voltage ELVDD to the pixels PX may be further formed The first power lines PL1 may extend in a first direction DR1 substantially parallel to the data lines DL and the sensing lines SL.

[0076] The first gate line GL1 and the second gate line GL2 extend in the second direction DR2 to pass through the non-emission area NEA. Herein, the first gate line GL1 and the second gate line GL2 may be arranged at regular intervals along the first direction DR1.

[0077] The data line DL, the sensing line SL, the first power line PL1, the first gate line GL1, and the second gate line GL2 are electrically connected to the circuit elements through the contact holes. Specifically, the data line DL can be electrically connected to the electrode (e.g., source) of the switching transistor ST, and the sensing line SL can be electrically connected to the electrode (e.g., source) of the sensing transistor SST. The first gate line GL1 is electrically connected to the gate of the switching transistor ST, and the second gate line GL2 is electrically connected to the gate of the sensing transistor SST.

[0078] As above Figure 2As described above, the pixel PX may include a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, and a light emitting element LD.

[0079] The switch transistor ST may include a first gate GE1 , a first source SE1 , and a first drain DE1 .

[0080] The first gate GE1 may be disposed to overlap with the first channel CH1 formed in the active layer ACT. The first channel CH1 may be a semiconductor pattern without doping impurities in the active layer ACT. The first gate GE1 may be electrically connected to the first gate line GL1. For example, the first gate GE1 may be a region on the first gate line GL1 that overlaps with the first channel CH1.

[0081] The first source electrode SE1 may be connected to the first source area SA1 formed on the first side of the first channel CH1 in the active layer ACT. The first source electrode SE1 may also be connected to the data line DL through the first contact hole CT1.

[0082] The first drain electrode DE1 may be connected to the first drain area DA1 formed on the second side of the first channel CH1 in the active layer ACT. The first drain electrode DE1 may be electrically connected to the lower electrode BE of the storage capacitor Cst through the second contact hole CT2.

[0083] The driving transistor DT may include a second gate electrode GE2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0084] The second gate GE2 may be disposed to overlap the second channel CH2 formed in the active layer ACT. The second gate GE2 may be electrically connected to the lower electrode BE of the storage capacitor Cst through the third contact hole CT3.

[0085] The second source electrode SE2 may be connected to the second source area SA2 formed on the first side of the second channel CH2 in the active layer ACT. The second source electrode SE2 may be electrically connected to the first power line PL1 through which the high potential driving voltage ELVDD is applied through the fourth contact hole CT4. In this embodiment, the second source electrode SE2 may be substantially configured as a conductive pattern provided in the wiring area WA.

[0086] The second drain electrode DE2 may be connected to the second drain area DA2 formed on the second side of the second channel CH2 in the active layer ACT. The second drain electrode DE2 may be electrically connected to the upper electrode UE of the storage capacitor Cst. For example, the second drain electrode DE2 may be formed to be integrated with the upper electrode UE of the storage capacitor Cst, and thus may form one pattern. As described below, the upper electrode UE of the storage capacitor Cst is connected to the anode electrode AE ​​of the light emitting element LD through the first through hole VIA1. Therefore, the second drain electrode DE2 of the driving transistor DT is electrically connected to the anode electrode AE ​​of the light emitting element LD through the upper electrode UE of the storage capacitor Cst.

[0087] In addition, the second drain electrode DE2 can be connected to the light shielding layer LS through the fifth contact hole CT5. Therefore, when a defect in the pixel PX is repaired by using the repair pattern RP to be described later, the repair pattern RP and the light shielding layer LS are connected by laser welding, so the anode electrode AE ​​of the adjacent pixel PX(i+1)j and the second drain electrode DE2 of the driving transistor DT are electrically connected.

[0088] The sensing transistor SST may include a third gate GE3 , a third source SE3 , and a third drain DE3 .

[0089] The third gate GE3 may be disposed to overlap the third channel CH3 formed in the active layer ACT. The third gate GE3 may be electrically connected to the second gate line GL2. For example, the third gate GE3 may be a region on the second gate line GL2 overlapping the third channel CH3.

[0090] The third source electrode SE3 may be connected to the third source area SA3 formed on the first side of the third channel CH3 in the active layer ACT. The third source electrode SE3 may be electrically connected to the bridge pattern BRP through the sixth contact hole CT6. The bridge pattern BRP is electrically connected to the sensing line SL through the eighth contact hole CT8. Therefore, through the bridge pattern BRP, the third source electrode SE3 may be electrically connected to the sensing line SL.

[0091] The third drain electrode DE3 may be connected to the third drain area DA3 formed on the second side of the third channel CH3 in the active layer ACT. In addition, the third drain electrode DE3 may be connected to the light shielding layer LS through the seventh contact hole CT7. In this embodiment, the light shielding layer LS is connected to the second drain electrode DE2 of the driving transistor DT through the fifth contact hole CT5. Therefore, the third drain electrode DE3 is electrically connected to the second drain electrode DE2 of the driving transistor DT through the light shielding layer LS.

[0092] The storage capacitor Cst may include a lower electrode BE and an upper electrode UE.

[0093] The lower electrode BE may be electrically connected to the first drain electrode DE1 of the switching transistor ST through the second contact hole CT2. In addition, the lower electrode BE may be electrically connected to the second gate electrode GE2 of the driving transistor DT through the third contact hole CT3.

[0094] In one embodiment, the lower electrode BE may include an extension portion EXT for connecting to the second gate electrode GE2 of the driving transistor DT. In the region of the extension portion EXT, the lower electrode BE overlaps with the second gate electrode GE2 and is electrically connected to the second gate electrode GE2 through the third contact hole CT3. Other regions of the extension portion EXT are arranged not to overlap with the second conductive layer and the anode electrode AE ​​of the light emitting element LD, which will be described later. Therefore, when the second gate electrode GE2 and the anode electrode AE ​​are electrically separated by cutting the extension portion EXT with a laser beam and a defect in the pixel PX is repaired, an electrical short circuit between the conductive layers and / or between the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD is prevented.

[0095] The upper electrode UE is formed in such a manner that at least one region thereof covers the lower electrode BE. Between the upper electrode UE and the lower electrode BE, charges corresponding to the potential difference between the two electrodes are stored so that the upper electrode UE and the lower electrode BE can function as a storage capacitor Cst.

[0096] An area where the upper electrode UE and the lower electrode BE overlap may determine the capacitance of the storage capacitor Cst. Therefore, the upper electrode UE and the lower electrode BE may have an area (size) satisfying a required capacitance of the storage capacitor Cst.

[0097] In one embodiment, in the case where the pixel PX emits white light, it is important to ensure the opening area of ​​the pixel PX rather than the capacitance of the storage capacitor Cst. In this embodiment, the area of ​​the upper electrode UE and the lower electrode BE of the pixel PX that emits white light can be set to be smaller than the area of ​​the upper electrode UE and the lower electrode BE of the pixel that emits another color light. Therefore, the size of the opening area between the storage capacitor Cst and the driving transistor DT can be increased. In the case where the anode electrode AE ​​of the light emitting element LD extends to the opening area of ​​the non-light emitting area NEA, the light generated by the light emitting element LD is emitted to the outside through the extended opening area.

[0098] The upper electrode UE may be electrically connected to the second drain electrode DE2 of the driving transistor DT through the fifth contact hole CT5. In addition, the upper electrode UE may be electrically connected to the anode electrode AE ​​of the light emitting element LD through the first through hole VIA1.

[0099] The storage capacitor Cst as described above is connected to the second gate GE2 of the driving transistor DT through the lower electrode BE. Above the driving transistor DT, the cathode electrode CE of the light emitting element LD to be described later may be formed. In this article, an electric field may be formed between the second gate GE2 of the driving transistor DT and the cathode electrode CE, which may reduce the charging rate of the storage capacitor Cst electrically connected to the second gate GE2. In other words, a parasitic capacitance having the second gate GE2 as a first electrode and the cathode electrode CE as a second electrode may be formed. Since in the present embodiment, in the case where the second gate GE2 is electrically connected to the lower electrode BE of the storage capacitor Cst instead of the upper electrode UE, the electrical path from the parasitic capacitance to the storage capacitor Cst is relatively long, the influence of the parasitic capacitance can be reduced. In addition, because the lower electrode BE of the storage capacitor Cst is formed on the substrate of the display panel 50, the formation of an electric field between the second gate GE2 and the cathode electrode CE is prevented, thereby removing the parasitic capacitance.

[0100] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and a light emitting layer EML disposed therebetween. In one embodiment, the anode electrode AE, the light emitting layer EML, and the cathode electrode CE may be disposed to overlap each other in the light emitting area EA.

[0101] Typically, the anode electrode AE ​​is formed in the light emitting area EA, and is provided with an area having at least a shape extending to the non-light emitting area NEA. In the extended area, the anode electrode AE ​​can be connected to the upper electrode UE of the storage capacitor Cst through the first through hole VIA1. In order to minimize the undesired light emission from the light emitting element LD in the non-light emitting area NEA, the area and length of the extended area can be designed to be minimum. Therefore, the first through hole VIA1 is provided near the light emitting area EA. More specifically, compared with the driving transistor DT, the first through hole VIA1 is provided near the light emitting area EA. In this article, when viewed from above, the first through hole VIA1 is provided in a manner not to overlap with the transistor. In particular, the first through hole VIA1 is provided in a manner not to overlap with the active layer ACT of the transistor.

[0102] On the anode electrode AE, a light emitting layer EML and a cathode electrode CE may be disposed. Generally, the anode electrode AE ​​is formed in the light emitting area EA. However, in order to contact the upper electrode UE of the storage capacitor Cst, at least one area of ​​the anode electrode AE ​​may extend to the non-light emitting area NEA.

[0103] In one embodiment, when the pixel PX displays white, the anode electrode AE ​​may extend widely to the non-emission area NEA. Herein, light generated from the light emitting element LD implemented as a bottom emission type may be emitted to the outside through an opening area between circuit elements provided in the non-emission area NEA.

[0104] The emission layer EML and the cathode electrode CE are widely formed in the emission area EA and the non-emission area NEA. Herein, the emission layer EML covers the anode electrode AE.

[0105] In one embodiment, the pixel PX may further include a repair pattern RP. The repair pattern RP is disposed in such a manner that its region does not overlap with the anode electrode AE ​​of the adjacent pixel PX(i+1)j but overlaps with the light shielding layer LS.

[0106] Herein, the repair pattern RP is electrically connected to the anode electrode AE ​​of the adjacent pixel PX(i+1)j in an area other than the above-mentioned area through the second through hole VIA2. In order to be electrically connected to the anode electrode AE ​​of the adjacent pixel PX(i+1)j, the repair pattern RP may be disposed close to the anode electrode AE ​​of the adjacent pixel PX(i+1)j in the non-luminous area NEA.

[0107] Since the repair pattern RP is disposed in the non-emission area NEA near the anode electrode AE ​​of the adjacent pixel PX(i+1)j, the light shielding layer LS disposed overlapping the area of ​​the repair pattern RP may have an area widely extending from a portion overlapping the driving transistor DT to the area.

[0108] Generally, the repair pattern RP as described above may be an island electrode having a stripe shape extending along the second direction DR2. However, the shape of the repair pattern RP is not limited thereto and may be variously modified according to relative arrangement states of other elements including the light shielding layer LS and the anode electrode AE.

[0109] Figure 3A and Figure 3B As an example, a display device 1 having a WRGB structure including a white pixel W is shown. However, the above embodiment is not only applied to the display device 1 having a WRGB structure. That is, in the above embodiment, various features unrelated to the white pixel W can be applied to a display device having an RGB structure or an RGBG structure that does not include the white pixel W. In addition, in the above embodiment, various features related to the white pixel W can be applied to the display device 1 having a WRGB structure and display devices having various structures including the white pixel W.

[0110] Hereinafter, a stacked structure (cross-sectional structure) of a pixel PX according to an embodiment will be described in more detail with reference to the accompanying drawings.

[0111] Figure 4A It is shown along Figure 3B FIG. 1 is a diagram of an embodiment of a cross-sectional view taken along line II'. Figure 4B It is shown along Figure 3B FIG. 1 is a diagram of another embodiment of a cross-sectional view taken along line II'. Figure 4C It is along Figure 3B A cross-sectional view taken along line I"-I"'.

[0112] Refer to Figure 3A and Figure 3B as well as FIG. 4A to FIG. 4C , the display panel 50 may include a substrate SUB, a circuit element layer, and a light emitting element layer.

[0113] The substrate SUB is a base member of the display panel 50 and may be a light-transmitting substrate. The substrate SUB may be a rigid substrate including glass or tempered glass, or may be a flexible substrate made of a plastic material. For example, the substrate SUB may be made of a plastic material such as polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), etc. However, the material of the substrate SUB is not limited thereto.

[0114] On the substrate SUB, a pixel area PXA is defined. The pixel area PXA may be defined as an area including at least one circuit element disposed at the circuit element layer and a light emitting element LD disposed at the light emitting element layer. At least one circuit element and the light emitting element LD may constitute one pixel PX.

[0115] The circuit element layer is formed on the substrate SUB and may include circuit elements (eg, a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, etc.) and wirings constituting the pixel PX.

[0116] First, a first conductive layer may be disposed on the substrate SUB The first conductive layer may include a light shielding layer LS and a lower electrode BE of the storage capacitor Cst.

[0117] When viewed from above, the light shielding layer LS is arranged in a manner overlapping with the semiconductor pattern (particularly, the second channel CH2) of the driving transistor DT, and thus the oxide semiconductor device can be protected from external light. In one embodiment, the light shielding layer LS can also be connected to the second drain electrode DE2 of the driving transistor DT through the fifth contact hole CT5. Therefore, when a defect in the pixel PX is repaired by using the repair pattern RP to be described later, the repair pattern RP and the light shielding layer LS are connected by laser welding, so that the anode electrode AE ​​of the adjacent pixel PX(i+1)j and the second drain electrode DE2 of the driving transistor DT are electrically connected.

[0118] The lower electrode BE may be electrically connected to the first drain electrode DE1 of the switching transistor ST through the second contact hole CT2. In addition, the lower electrode BE may be electrically connected to the second gate electrode GE2 of the driving transistor DT through the third contact hole CT3.

[0119] In one embodiment, the lower electrode BE may include an extension portion EXT for connecting to the second gate electrode GE2 of the driving transistor DT. In the region of the extension portion EXT, the lower electrode BE overlaps with the second gate electrode GE2 and is electrically connected to the second gate electrode GE2 through the third contact hole CT3. Another region of the extension portion EXT is set not to overlap with other electrodes of the circuit element and the anode electrode AE ​​of the light emitting element LD. Therefore, when the second gate electrode GE2 and the anode electrode AE ​​are electrically separated by cutting the extension portion EXT with a laser and a defect in the pixel PX is repaired, an electrical short circuit between other electrodes and / or between the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD is prevented.

[0120] In the wiring area WA, the first conductive layer may further include a data line DL, a sensing line SL, and a first power line PL1. The data line DLj is connected to the first source SE1 of the switching transistor ST through the first contact hole CT1. The sensing line SL is connected to the third source SE3 of the sensing transistor SST through the bridge pattern BRP. The first power line PL1 is connected to the second source SE2 of the driving transistor DT through the fourth contact hole CT4.

[0121] In various embodiments, wirings and / or electrodes not shown may be further provided on the substrate SUB, for example, a second power line PL2 through which the low potential driving power ELVSS is applied, an auxiliary electrode, etc.

[0122] The buffer layer BUF is disposed on the substrate SUB so as to cover the light shielding layer LS, the lower electrode BE of the storage capacitor Cst, and the wiring. The buffer layer BUF can prevent ions or impurities from diffusing from the substrate SUB and can block moisture penetration. In addition, the buffer layer BUF can enhance the flatness of the surface of the substrate SUB. The buffer layer BUF may include inorganic materials, organic materials, or organic-inorganic compounds such as oxides, nitrides, etc. The buffer layer BUF may be formed in a single-layer or multi-layer structure. For example, the buffer layer BUF may have a structure of three or more layers in the order of silicon oxide, silicon nitride, and silicon oxide. In another embodiment, the buffer layer BUF may be omitted.

[0123] An active layer ACT may be formed on the buffer layer BUF. The active layer ACT may be made of a silicon-based semiconductor material or an oxide-based semiconductor material. As a silicon-based semiconductor material, amorphous silicon or polycrystalline silicon may be used. As an oxide-based semiconductor material, a quaternary metal oxide such as indium tin gallium zinc oxide (InSnGaZnO) may be used; a ternary metal oxide such as indium gallium zinc oxide (InGaZnO), indium tin zinc oxide (InSnZnO), indium aluminum zinc oxide (InAlZnO), tin gallium zinc oxide (SnGaZnO), aluminum gallium zinc oxide (AlGaZnO) or tin aluminum zinc oxide (SnAlZnO) may be used; or a binary metal oxide such as indium zinc oxide (InZnO), tin zinc oxide (SnZnO), aluminum zinc oxide (AlZnO), zinc magnesium oxide (ZnMgO), tin magnesium oxide (SnMgO), indium magnesium oxide (InMgO), indium gallium oxide (InGaO), indium oxide (InO), tin oxide (SnO) or zinc oxide (ZnO).

[0124] The active layer ACT may include: first to third source areas SA1 to SA3 and first to third drain areas DA1 to DA3 including p-type impurities or n-type impurities; and first to third channels CH1 to CH3 formed between the first to third source areas SA1 to SA3 and the first to third drain areas DA1 to DA3, respectively.

[0125] The second conductive layer is disposed on the active layer ACT. Between the active layer ACT and the second conductive layer, a gate insulating layer GI may be interposed. The gate insulating layer GI may be silicon oxide (SiOx), silicon nitride (SiNx), or a plurality of layers of silicon oxide (SiOx) and silicon nitride (SiNx).

[0126] The second conductive layer may include gates GE1, GE2, and GE3, source electrodes SE1, SE2, and SE3, and drain electrodes DE1, DE2, and DE3. The gates GE1, GE2, and GE3 may be disposed to overlap with corresponding channels CH1, CH2, and CH3 in the active layer ACT, respectively. At least some (GE1 and GE3) of the gates GE1, GE2, and GE3 are integrally formed with wirings GL1 and GL2 electrically connected to the gates GE1 and GE3, thereby forming a pattern.

[0127] The second conductive layer may further include an upper electrode UE of a storage capacitor Cst. The upper electrode UE is formed in such a way that at least one region thereof covers the lower electrode BE. Between the upper electrode UE and the lower electrode BE, charges corresponding to the potential difference between the two electrodes are stored, so that the upper electrode UE and the lower electrode BE can function as a storage capacitor Cst.

[0128] The upper electrode UE may be electrically connected to the second drain electrode DE2 of the driving transistor DT through the fifth contact hole CT5. In addition, the upper electrode UE may be electrically connected to the anode electrode AE ​​of the light emitting element LD through the first through hole VIA1.

[0129] The storage capacitor Cst as described above is connected to the second gate GE2 of the driving transistor DT through the lower electrode BE. Above the driving transistor DT, the cathode electrode CE of the light emitting element LD to be described later may be formed. In this article, an electric field may be formed between the second gate GE2 of the driving transistor DT and the cathode electrode CE, which may reduce the charging rate of the storage capacitor Cst electrically connected to the second gate GE2. In other words, a parasitic capacitance having the second gate GE2 as a first electrode and the cathode electrode CE as a second electrode may be formed. Since in the present embodiment, in the case where the second gate GE2 is electrically connected to the lower electrode BE of the storage capacitor Cst instead of the upper electrode UE, the electrical path from the parasitic capacitance to the storage capacitor Cst is relatively long, the influence of the parasitic capacitance can be reduced. In addition, because the lower electrode BE of the storage capacitor Cst is formed on the substrate of the display panel 50, the formation of an electric field between the second gate GE2 and the cathode electrode CE is prevented, thereby removing the parasitic capacitance.

[0130] Meanwhile, in the present embodiment, the upper electrode UE of the storage capacitor Cst is configured as a single-layer electrode formed at the second conductive layer. However, the present disclosure is not limited thereto. In another embodiment, the upper electrode UE of the storage capacitor Cst may be configured as a multi-layer electrode in which a conductive pattern disposed at the second conductive layer and a conductive pattern disposed at another layer (e.g., an active layer ACT) overlap. Figure 5 This embodiment is described in detail.

[0131] The second conductive layer may further include a bridge pattern BRP. The bridge pattern BRP may electrically connect the third source electrode SE3 of the sensing transistor SST and the sensing line SL.

[0132] The second conductive layer may further include a repair pattern RP. The repair pattern RP is arranged in such a manner that its area does not overlap with the anode electrode AE ​​of the adjacent pixel PX(i+1)j, but overlaps with the light shielding layer LS. In this article, an area of ​​the repair pattern RP other than the above-mentioned area is electrically connected to the anode electrode AE ​​of the adjacent pixel PX(i+1)j through the second through hole VIA2.

[0133] The first conductive layer and the second conductive layer may be made of any one or an alloy of two or more selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). In addition, the first conductive layer and the second conductive layer may be a multilayer consisting of any one or an alloy of two or more selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu). For example, the first conductive layer and the second conductive layer may be two layers of molybdenum and aluminum-neodymium or molybdenum and aluminum.

[0134] The circuit element layer may be covered by a passivation layer PAS. The passivation layer PAS may cover the second conductive layer and the exposed areas of the buffer layer BUF and the active layer ACT that are not covered by the second conductive layer. The passivation layer PAS may be an insulating film for protecting the lower element, and may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer of a silicon oxide film (SiOx) and a silicon nitride film (SiNx). In various embodiments, the passivation layer PAS may be omitted.

[0135] On the passivation layer PAS, an overcoat layer OC may be formed The overcoat layer OC may be a planarization film for reducing a height difference of a lower structure, and may be composed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or the like.

[0136] In one embodiment, a color filter CF may be formed between the passivation layer PAS and the overcoat OC. The color filter CF may be formed in the light emitting area EA. The color filter CF is a wavelength selective filter that selectively transmits only a partial wavelength band of incident light by transmitting light in a specific wavelength band and blocking light in other specific wavelength bands. The color filter CF may be made of a photosensitive resin containing a colorant such as a pigment, a dye, etc. In the light emitting area EA, the light passing through the color filter CF may have any one of red, green, and blue. In the case where the pixel PX displays white, the color filter CF may be omitted for the pixel PX.

[0137] The color filter CF is formed between the passivation layer PAS and the overcoat layer OC, but the present embodiment is not limited thereto. That is, when the light emitting element LD is a top emission type, the color filter CF may be formed on an upper layer of a light emitting element layer to be described later.

[0138] The light emitting element layer is formed on the overcoat layer OC and includes a light emitting element LD. The light emitting element LD may include an anode electrode AE, a light emitting layer EML, and a cathode electrode CE.

[0139] At least one of the anode electrode AE ​​and the cathode electrode CE may be a transmissive electrode, and at least the other may be a reflective electrode. For example, in the case where the light emitting element LD is a bottom emission type, the anode electrode AE ​​may be a transmissive electrode, and the cathode electrode CE may be a reflective electrode. Conversely, in the case where the light emitting element LD is a top emission type, the anode electrode AE ​​may be a reflective electrode, and the cathode electrode CE may be a transmissive electrode. In another example, in the case where the light emitting element LD is a double-sided emission type, both the anode electrode AE ​​and the cathode electrode CE may be transmissive electrodes. Below, taking the case where the light emitting element LD is a bottom emission type as an example, the detailed structure of the light emitting element LD will be described.

[0140] The anode electrode AE ​​is formed on the overcoat layer OC. The anode electrode AE ​​is electrically connected to the upper electrode UE of the storage capacitor Cst through the first through hole VIA1 that passes through the overcoat layer OC and the passivation layer PAS. The anode electrode AE ​​may be electrically connected to the second drain electrode DE2 of the driving transistor DT through the storage capacitor Cst. As described above, when the first through hole VIA1 is formed to contact the upper electrode UE of the storage capacitor Cst having a larger area than the other electrodes, the influence of the height difference near the first through hole VIA1 is reduced.

[0141] The anode electrode AE ​​may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In the case where the anode electrode AE ​​is a reflective electrode, the anode electrode AE ​​may include a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof. In one embodiment, the reflective layer may be composed of an alloy of silver, palladium, and copper (APC).

[0142] The light emitting layer EML is formed on the anode electrode AE. In the present embodiment, the display device 1 has a bankless form. In the present embodiment, the light emitting layer EML is formed in a manner of covering the anode electrode AE. The light emitting layer EML may be widely formed in the light emitting area EA and the non-light emitting area NEA.

[0143] The light emitting layer EML may have a multi-layer thin film structure including a light generating layer. Herein, the color of light generated by the light generating layer may be white, red, blue, green, etc., but is not limited thereto.

[0144] The light generating layer may include, for example, a hole transport layer (HTL), an organic light emitting layer, and an electron transport layer (ETL). The hole transport layer smoothly transports the holes injected from the anode electrode AE ​​to the organic light emitting layer. The organic light emitting layer may be made of an organic material including a phosphorescent or fluorescent material. The electron transport layer smoothly transports the electrons injected from the cathode electrode CE to the organic light emitting layer. In addition to the hole transport layer, the organic light emitting layer, and the electron transport layer, the light emitting layer (EML) may also include a hole injection layer (HIL), a hole blocking layer (HBL), an electron injection layer (EIL), and an electron blocking layer (EBL).

[0145] The light-emitting layer EML may be formed as a series structure of two or more stacks. In this case, each stack may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. In the case where the light-emitting layer EML is formed as a series structure of two or more stacks, a charge generation layer is formed between the stacks. The charge generation layer may include an n-type charge generation layer and a p-type charge generation layer. The n-type charge generation layer is located near the lower stack. The p-type charge generation layer is formed on the n-type charge generation layer and is therefore located near the upper stack. The n-type charge generation layer injects electrons into the lower stack, and the p-type charge generation layer injects holes into the upper stack. The n-type charge generation layer may be an organic layer obtained by doping an alkali metal such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra) into an organic matrix material having electron transport capability. The p-type charge generation layer may be an organic layer obtained by doping a dopant into an organic matrix material having hole transport capability.

[0146] The cathode electrode CE is formed on the emission layer EML. The cathode electrode CE may be widely formed in the emission area EA and the non-emission area NEA.

[0147] The cathode electrode CE may be made of a transparent conductive material (TCO) capable of transmitting light or a semi-transmissive conductive material such as molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and alloys thereof. In the case where the cathode electrode CE is made of a semi-transmissive conductive material, the light emitting efficiency may be increased due to the microcavity.

[0148] Refer to Figures 3A to 4CIn the present embodiment, at least one region of the anode electrode AE ​​extends to the non-light emitting area NEA so as to contact the circuit element. Since the light emitting layer EML and the cathode electrode CE are stacked on the entire area of ​​the anode electrode AE, undesired light emission (light leakage phenomenon) may occur in the non-light emitting area NEA. In the non-light emitting area NEA, in order to prevent the light generated by the light emitting element LD from being emitted to the outside, in the present embodiment, a light absorbing layer LA is further included between the passivation layer PAS and the overcoat layer OC and formed in the non-light emitting area NEA.

[0149] The light absorbing layer LA may contain a colorant such as a pigment, a dye, etc. that selectively transmits only a partial wavelength band of incident light by transmitting light in a specific wavelength band and blocking light in other specific wavelength bands. The light absorbing layer LA may have a structure in which one or more pigment layers are stacked so as to absorb light generated by the light emitting element LD.

[0150] In one embodiment, if Figure 4A As shown, the light absorbing layer LA may include: a first absorbing layer LA1 including a first color pigment; and a second absorbing layer LA2 including a second color pigment different from the first color. In one embodiment, the first color may be red and the second color may be blue, but is not limited thereto.

[0151] In another embodiment, Figure 4B As shown, the light absorbing layer LA may be constructed as a single absorbing layer. In this embodiment, the light absorbing layer LA may be constructed using red or blue pigment. Figure 4B An example is shown in which the light absorbing layer LA is configured as a single absorbing layer of red.

[0152] In the case where the light absorption layer LA is configured as a single absorption layer of red, the height of the light absorption layer LA is low. Therefore, the taper angle of the overcoat OC can be reduced, and light can be prevented from being discharged in an undesired direction at the upper boundary surface of the overcoat OC.

[0153] For example, in the case where the light absorption layer LA is configured as a single absorption layer of red, the light reflectivity of a polarization layer or the like attached to the display panel 50 is improved, and thus a sense of discomfort can be prevented.

[0154] Generally, blue pigments are thinner than red pigments. Therefore, in the case where the light absorbing layer LA is constructed as a single absorption layer of blue, the taper angle of the overcoat layer OC can be greatly reduced. In addition, in the case of red pigments, an inverted taper may appear at the end of the light absorbing layer LA, and there is a problem of a gap appearing. The formation of such a red pigment near the driving transistor DT may affect the performance of the driving transistor DT. However, in the case where the light absorbing layer LA is constructed as a single absorption layer of blue, this problem can be prevented.

[0155] In the case where the light absorbing layer LA has a form in which absorbing layers including pigments of different colors are overlapped, the light leakage phenomenon is effectively blocked by a reflective luminescence effect (eg, a black luminescence effect).

[0156] The above-mentioned light absorption layer LA is composed of the same material as the color filter CF and can be formed by the same process as the color filter CF. That is, the color filter CF and the light absorption layer LA containing the pigment of the same color can be formed together through a single mask process. For example, when the color filter CF containing the pigment of the first color is formed, the first absorption layer LA1 of the light absorption layer LA is formed together. When the color filter CF containing the pigment of the second color is formed, the second absorption layer LA2 of the light absorption layer LA is formed together. Therefore, the present embodiment makes it possible to prevent the light leakage phenomenon in the bankless structure without requiring a separate additional process for producing the light absorption layer LA.

[0157] The light absorbing layer LA may be formed in the entire area of ​​the non-luminous area NEA. However, the present embodiment is not limited thereto. According to an embodiment, the light absorbing layer LA may be formed on the anode electrode AE ​​in the non-luminous area NEA. In one embodiment, when the pixel PX displays white, the light absorbing layer LA may not be formed in the pixel PX.

[0158] When the light absorbing layer LA is formed in the entire non-emission area NEA, the first and second through holes VIA1 and VIA2 are formed to penetrate the light absorbing layer LA. Alternatively, the light absorbing layer LA may be configured not to be formed around the first and second through holes VIA1 and VIA2.

[0159] Figure 5 is a cross-sectional view of a storage capacitor according to another embodiment.

[0160] As mentioned above FIG. 3A to FIG. 4C As described above, in one embodiment, the storage capacitor Cst may be composed of a lower electrode BE formed at the first conductive layer and an upper electrode UE formed at the second conductive layer. Between the lower electrode BE and the upper electrode UE, a buffer layer BUF and a gate insulating layer GI are interposed.

[0161] In the case where two insulating layers are interposed between the lower electrode BE and the upper electrode UE, the distance between the electrodes BE and UE is relatively long, resulting in a decrease in the capacitance of the storage capacitor Cst. In order to ensure the desired capacitance, it is necessary to increase the area of ​​the lower electrode BE and the upper electrode UE. However, when the area of ​​the storage capacitor Cst increases, the size of the pixel PX increases, making it difficult to implement a high-resolution display device. In addition, in the case where the pixel PX displays white, it is difficult to ensure the aperture ratio.

[0162] To solve this problem, in one embodiment, the upper electrode UE of the storage capacitor Cst may have a multi-layer structure in which the active layer ACT and the second conductive layer TGA overlap. Here, the buffer layer BUF is interposed between the lower electrode BE and the upper electrode UE.

[0163] and FIG. 4A to FIG. 4C Compared with the implementation method of Figure 5 In the illustrated embodiment, only one insulating layer is interposed between the lower electrode BE and the upper electrode UE of the storage capacitor Cst. Therefore, the distance between the electrodes is relatively reduced, so that the capacitance of the storage capacitor Cst can be increased. Therefore, the increase in the area of ​​the storage capacitor Cst is prevented, and as a result, the size of the pixel PX is reduced and the aperture ratio of the white pixel is guaranteed.

[0164] FIG. 6A to FIG. 6D is a diagram illustrating a short-circuit problem that may occur in a light-emitting element in a display device having a bankless structure. Figure 7 is a diagram illustrating a method of forming a first through hole according to an embodiment.

[0165] As described above, the anode electrode AE ​​of the light emitting element LD may be connected to the upper electrode UE of the storage capacitor Cst through the first via hole VIA1 penetrating the overcoat layer OC and the passivation layer PAS. The first via hole VIA1 may be formed by a photoresist (PR) process and a wet etching process.

[0166] Specifically, Fig. 6A As shown, on the passivation layer PAS, the overcoat layer OC may be exposed and developed by using a mask (photolithography). In this article, the mask may be patterned in such a way that the overcoat layer OC is not formed in the area corresponding to the first through hole VIA1. On the exposed passivation layer PAS where the overcoat layer OC is not formed, the residual film of the overcoat layer OC may be removed.

[0167] Then, a passivation hole may be formed on the exposed passivation layer PAS. Figure 6B As shown, with a mask having openings corresponding to the first through holes VIA1 applied, a selective etchant capable of selectively etching the passivation layer PAS is applied, thereby forming a passivation hole.

[0168] Then, if Figure 6C As shown, the overcoat layer OC is etched to remove the overcoat layer OC around the passivation hole. With the removal of the overcoat layer OC, the passivation hole is completely exposed to the outside, and a first through hole VIA1 penetrating the overcoat layer OC and the passivation layer PAS is formed.

[0169] In the display device 1 having a bankless structure, the overcoat OC is formed in a thicker manner than the overcoat of the structure having a bank. For example, the overcoat OC may have a thickness of about 4.5 μm. As the overcoat OC becomes thicker, the rate of removing the overcoat OC by etching decreases, so the overcoat OC remains in the area adjacent to the edge of the passivation hole. In addition, when etching the overcoat OC, the side is over-etched, resulting in the formation of undercuts. Due to the remaining portion of the overcoat OC and the undercut around the passivation hole, a gap GAP between the overcoat OC and the passivation layer PAS may be formed at the sidewall of the first through hole VIA1.

[0170] After forming the first through hole VIA1, the anode electrode AE, the light emitting layer EML, and the cathode electrode CE may be sequentially stacked on the overcoat layer OC. Herein, the anode electrode AE, the light emitting layer EML, and the cathode electrode CE may be stacked inside the first through hole VIA1 and may fill the inside of the gap formed at the sidewall of the first through hole VIA1.

[0171] The anode electrode AE ​​and the cathode electrode CE having relatively good step coverage characteristics can be continuously formed near the gap without being separated due to the undercut of the overcoat layer OC. However, the light emitting layer EML having relatively poor step coverage characteristics may be separated near the gap due to the undercut. As the light emitting layer EM is separated, inside the gap, the anode electrode AE ​​and the cathode electrode CE may have a Fig.6D Electrical short circuit shown.

[0172] In order to prevent such a short circuit failure in the light emitting element LD, in one embodiment, the first through hole VIA1 may be formed in a manner of penetrating the light absorbing layer LA. That is, the light absorbing layer LA may be formed along the edge of the first through hole VIA1.

[0173] Due to the material properties, the light absorbing layer LA is not over-etched during etching, so no undercut is formed. The etching section has a positive tapered shape. Therefore, no gap is formed between the passivation layer PAS, the light absorbing layer LA, and the overcoat layer OC, and the light emitting layer EML and the cathode electrode CE can be continuously formed in the etching section.

[0174] In one embodiment, if Figure 7 As shown, in the region around the edge of the first through hole VIA1, the light absorbing layer LA can be constructed as a single absorbing layer containing a blue pigment. The blue pigment has a relatively good ability to form a positive tapered cross section by etching. Therefore, by forming a single absorbing layer containing a blue pigment around the first through hole VIA1, a short circuit problem between the anode electrode AE ​​and the cathode electrode CE of the light emitting element LD can be prevented.

[0175] Reference FIG. 4A to FIG. 4CIn the embodiment, in the region around the edge of the first through hole VIA1, the light absorbing layer LA may be configured as a single absorbing layer including a blue pigment. In the remaining region, the light absorbing layer LA may be configured as a plurality of layers including a first absorbing layer LA1 including a red pigment and a second absorbing layer LA2 including a blue pigment.

[0176] Figure 8 and Fig. 9 is a diagram illustrating a method of repairing a display device according to an embodiment. Fig.10 and Fig.11 is a diagram illustrating a short circuit problem in a light emitting element that may occur during a repair process. Fig.12 It shows the repair FIG. 4A to FIG. 5 FIG. 5 shows a method of pixels.

[0177] Figure 8 and Fig. 9 Two pixels PXij and PX(i+1)j are shown, which are arranged adjacent to each other in the first direction DR1. The pixels PXij and PX(i+1)j are arranged in the j-th pixel column and are commonly connected to the j-th data line DLj. In addition, among the pixels PXij and PX(i+1)j, the first pixel PXij is arranged in the i-th pixel row and is connected to the i-th gate lines GL1i and GL2i. The second pixel PX(i+1)j is arranged in the i+1-th pixel row and is connected to the i+1-th gate lines GL1(i+1) and GL2(i+1).

[0178] Reference Figure 8 and Fig. 9 The display panel 50 includes a plurality of pixel areas PXA defined in intersections of data lines (DLj) extending in a first direction DR1 and gate lines (GL1i, GL1(i+1), GL2i, and GL2(i+1)) extending in a second direction DR2. In the pixel area PXA, pixels PXij and PX(i+1)j are provided.

[0179] The pixel area PXA may include a light emitting area EA and a non-light emitting area NEA. In the light emitting area EA, light emitting elements LD of pixels PXij and PX(i+1)j are arranged. The non-light emitting area NEA includes circuit elements (e.g., a switching transistor ST, a driving transistor DT, a sensing transistor SST, and a storage capacitor Cst) for driving the light emitting element LD. The light emitting element LD is driven by the circuit elements arranged in the non-light emitting area NEA and emits light of a specific color.

[0180] A wiring area WA may be defined between adjacent pixel areas PXA in the second direction DR2. In the wiring area WA, data lines (DLj) and sensing lines (SLj) extending in the first direction DR1 are disposed. First gate lines (GL1i and GL1(i+1)) and second gate lines (GL2i and GL2(i+1)) extend through the non-emission area NEA in the second direction DR2.

[0181] The data line (DLj), the sensing line (SLj), the first selection line (GL1i and GL1(i+1)), and the second selection line (GL2i, GL2(i+1)) are electrically connected to the circuit elements through the contact holes. Specifically, the data line (DLj) can be electrically connected to the electrode (e.g., source) of the switching transistor ST. The sensing line (SLj) can be electrically connected to the electrode (e.g., source) of the sensing transistor SST. The first selection line (GL1i and GL1(i+1)) is electrically connected to the gate of the switching transistor ST, and the second selection line (GL2i and GL2(i+1)) is electrically connected to the gate of the sensing transistor SST.

[0182] In various embodiments, when at least one or some of the driving lines are cut off, defects such as dark spots may appear in the corresponding pixels PXij and PX(i+1)j. Fig. 9 As shown, the line between the switching transistor ST of the first pixel PXij and the j-th data line DLj, the line between the sensing transistor SST of the first pixel PXij and the j-th sensing line SLj, and / or the line between the driving transistor DT of the first pixel PXij and the first power line PL1 through which the high potential driving voltage ELVDD is supplied may be cut off. Then, the correct driving current is not applied to the first pixel PXij, and the light emitting element LD of the first pixel PXij does not emit light, so a dark spot may be observed.

[0183] To repair the defective pixel PXij, the anode electrode AE ​​of the light emitting element LD of the first pixel PXij may be electrically connected to the anode electrode AE ​​of the light emitting element LD of the second pixel PX(i+1)j adjacent to the first pixel PXij, such as Fig. 9 Then, the driving current of the second pixel PX(i+1)j is applied to the light emitting element LD of the first pixel PXij. Therefore, the first pixel PXij can emit light in response to the same data signal as the second pixel PX(i+1)j, thereby repairing the dark spot defect.

[0184] The repair process may be performed by laser welding. Specifically, the repair process may be performed by irradiating any repair pattern disposed in the non-luminous area NEA of the first pixel PXij with a laser beam to remove an insulating film interposed between the repair pattern RP and the anode electrode AE ​​of the second pixel PX(i+1)j, and by forming an electrical connection between the repair pattern and the anode electrode AE ​​of the second pixel PX(i+1)j.

[0185] As above Figure 5 As described above, the pixels PXij and PX(i+1)j include a substrate SUB, a buffer layer BUF and a gate insulating layer GI stacked in sequence on the substrate SUB, a second conductive layer TGA, and a passivation layer PA. On the passivation layer PAS, an anode electrode AE, a light-emitting layer EML, and a cathode electrode CE of the light-emitting element LD are stacked. In the case where the display device 1 is provided with a bank, in the non-light-emitting area NEA of the pixels PXij and PX(i+1)j, a bank layer BNK for defining the light-emitting area EA may be formed between the anode electrode AE ​​and the light-emitting layer EML.

[0186] like Fig.10 As shown in FIG. 1 , in the case where the bank layer BNK is formed in the non-light emitting area NEA, the laser beam irradiating the non-light emitting area NEA is blocked by the bank layer BNK, and thus the light emitting element LD disposed in the upper layer is not damaged. Fig.11 In the bankless structure in which the bank layer BNK is not formed as shown, one or some layers of the light emitting element LD may be damaged by the laser beam, resulting in an electrical short circuit between the anode electrode AE ​​and the cathode electrode CE.

[0187] To solve this problem, Figure 5 In the illustrated embodiment, the repair pattern RP is arranged in such a manner that its region does not overlap with the anode electrode AE ​​of the adjacent pixel PX(i+1)j, but overlaps with the light shielding layer LS. Electrode layers other than the light shielding layer LS may not be arranged on or under the region. The region other than the above region of the repair pattern RP is electrically connected to the anode electrode AE ​​of the adjacent pixel PX(i+1)j through the second through hole VIA2.

[0188] Reference Fig.12 Laser welding is performed on the area where the light shielding layer LS overlaps the repair pattern RP. Since the area not overlapping the anode electrode AE ​​of the second pixel PX(i+1)j is irradiated with the laser beam, the anode electrode AE ​​and the cathode electrode CE can be prevented from being short-circuited by the laser beam.

[0189] The insulating layer between the light shielding layer LS and the repair pattern RP can be removed by laser welding, and an electrical connection between the light shielding layer LS and the repair pattern RP can be formed. The light shielding layer LS is connected to the anode electrode AE ​​of the light emitting element LD through the second drain electrode DE2 of the driving transistor DT of the first pixel PXij and the upper electrode UE of the storage capacitor Cst. The repair pattern RP is connected to the anode electrode AE ​​of the light emitting element LD of the second pixel PX(i+1)j through the second through hole VIA2. Therefore, when the light shielding layer LS is electrically connected to the repair pattern RP by laser welding, the anode electrode AE ​​of the light emitting element LD of the first pixel PXij is connected to the anode electrode AE ​​of the light emitting element LD of the second pixel PX(i+1)j. Then, when a driving current is applied to the anode electrode AE ​​of the light emitting element LD of the second pixel PX(i+1)j, the same driving current is applied to the anode electrode AE ​​of the light emitting element LD of the first pixel PXij, and the first pixel PXij can emit light with the same brightness as the second pixel PX(i+1)j.

[0190] Fig.13 is a diagram illustrating a method of repairing a display device according to another embodiment. Fig.14 It shows the repair FIG. 4A to FIG. 5 FIG. 5 shows a method of pixels.

[0191] Fig.13 Two pixels PX(i-1)j and PXij are shown arranged close to each other in the first direction DR1. The pixels PX(i-1)j and PXij are arranged in the j-th pixel column and are commonly connected to the j-th data line DLj. In addition, among the pixels PX(i-1)j and PXij, the first pixel PX(i-1)j is arranged in the i-1-th pixel row and is connected to the i-1-th first gate line GL1(i-1). The second pixel PXij is arranged in the i-th pixel row and is connected to the i-th first gate line GL1i.

[0192] In one embodiment, a defect may occur in a driving circuit for driving the light emitting element LD of the second pixel PXij, and thus the light emitting element LD may not emit light correctly. In order to repair a defective pixel (eg, the second pixel PXij), as shown in FIG. Fig.13 As shown, the light emitting element LD of the second pixel PXij can be separated from the driving circuit. Afterwards, the anode electrode AE ​​of the light emitting element LD of the second pixel PXij can be electrically connected to the anode electrode AE ​​of the light emitting element LD of the adjacent pixel (e.g., the first pixel PX(i-1)j). Then, the driving current of the first pixel PX(i-1)j is applied to the light emitting element LD of the second pixel PXij. Therefore, the second pixel PXij can emit light in response to the same data signal as the first pixel PX(i-1)j, thereby repairing the defect in the pixel.

[0193] The repair process may be performed by laser cutting and laser welding. Specifically, in the non-luminous area NEA of the second pixel PXij, when the anode electrode AE ​​of the light emitting element LD is irradiated with a laser beam, a disconnection occurs between the anode electrode AE ​​and the driving circuit. Thereafter, the anode electrode AE ​​of the light emitting element LD of the first pixel PX(i-1)j may be electrically connected to the anode electrode AE ​​of the light emitting element LD of the second pixel PXij by laser welding.

[0194] As above Fig.10 and Fig.11 As mentioned above, laser cutting in a bankless structure may result in an electrical short circuit between the anode electrode AE ​​and the cathode electrode CE. Figure 5 In the illustrated embodiment, the lower electrode BE of the storage capacitor Cst may include an extension portion EXT for connecting to the second gate electrode GE2 of the driving transistor DT. On the extension portion EXT, the lower electrode BE overlaps the second gate electrode GE2 and is electrically connected to the second gate electrode GE2 through the third contact hole CT3. At least one region of the extension portion EXT is arranged not to overlap with other electrodes of the circuit element and the anode electrode AE ​​of the light emitting element LD.

[0195] Reference Fig.14 , laser cutting is performed on the extension portion EXT. Since the area not overlapping with the anode electrode AE ​​of the second pixel PXij is irradiated with the laser beam, the anode electrode AE ​​and the cathode electrode CE can be prevented from being short-circuited by the laser beam.

[0196] When the extension portion EXT is cut by laser cutting, the second drain electrode DE2 of the driving transistor DT and the lower electrode BE of the storage capacitor Cst are electrically separated. The second drain electrode DE2 is connected to the anode electrode AE ​​of the light emitting element LD through the extension portion EXT of the lower electrode BE. Therefore, the driving transistor DT and the light emitting element LD can be electrically separated by cutting the extension portion EXT.

[0197] After laser cutting, the anode electrode AE ​​of the light emitting element LD of the second pixel PXij can be electrically connected to the anode electrode AE ​​of the light emitting element LD of the first pixel PX(i-1)j by laser welding. Fig.12 The descriptions are the same, so their detailed descriptions are omitted.

[0198] Fig.15 It is along Figure 3A A cross-sectional view taken along line II-II'.

[0199] Reference FIG. 3A to FIG. 4C, in order for the pixel to display the desired color, the light generated by the light emitting element LD needs to be emitted to the outside of the display panel 50 via the color filter CF. In the case where the pixel is configured to have a bankless structure, light shielding is not performed around the light emitting area EA. Therefore, the light emitted from the light emitting element LD is discharged to the periphery of the light emitting area EA, and thus is emitted to the outside of the display panel 50 without passing through the color filter CF. Therefore, light leakage and fading phenomena may occur.

[0200] In the case where the white pixel displays white, the color filter CF is not provided, and the light generated by the light emitting element LD does not pass through the color filter CF but is emitted to the outside of the display panel 50. Therefore, in the case of the white pixel, light leakage and fading phenomena may not be a problem.

[0201] In order to solve the light leakage and fading phenomenon in the pixels displaying red, blue and green, in one embodiment, the pixels may have Fig.15 The structure shown.

[0202] Specifically, refer to Fig.15 ,and FIG. 4A to FIG. 4C In contrast, the light emitting area EA of the white pixel W may have a form in which the overcoat layer OC is removed. For example, the overcoat layer OC may be formed in an area other than the light emitting area EA of the white pixel W by a photolithography process using a halftone mask. Therefore, at the edge of the light emitting area EA of the white pixel W, the overcoat layer OC has a height difference.

[0203] After forming the overcoat OC, the anode electrode AE ​​of each pixel in the light emitting area EA may be patterned. In the red pixel R, the anode electrode AE ​​is formed on the overcoat OC. Since the overcoat OC is not formed in the white pixel W, the anode electrode AE ​​may be formed on the buffer layer BUF as the lower layer. In the illustrated embodiment, in the case of the white pixel W, the anode electrode AE ​​is formed on the buffer layer BUF, but the present embodiment is not limited thereto. That is, in various embodiments, the passivation layer PAS may be formed in the light emitting area EA of the white pixel W. In this article, the anode electrode AE ​​may be formed on the passivation layer PAS. That is, in addition to the overcoat OC, the anode electrode AE ​​may be formed on the exposed lower layer of the light emitting area EA.

[0204] Then, the light emitting layer EML and the cathode electrode CE may be formed. Along the overcoat layer OC provided with the height difference, the light emitting layer EML and the cathode electrode CE also have a height difference at the edge of the light emitting area EA of the white pixel W. In the area with the height difference, the light emitting layer EML and the cathode electrode CE cover the exposed side of the overcoat layer OC, and thus have a curved portion around the step. In this article, the curved portion may include at least one angular shape or at least one curved surface shape.

[0205] When light is emitted from the light emitting element LD of the red pixel R, light discharged to the non-light emitting area NEA in which the color filter CF is not formed travels in a direction adjacent to the white pixel W. The light is reflected from the bent portion of the cathode electrode CE, and the traveling direction of the light can be controlled to be toward a lower position of the display panel 50. By providing the data line DL along the edge of the light emitting area EA of the white pixel W, the reflected light can be prevented from being emitted outside the display panel 50.

[0206] As described above, in the display panel 50 according to the embodiment, a height difference of the cathode electrode CE is formed at the periphery of another adjacent pixel by removing the overcoat layer OC of the white pixel W. Then, light released from the light emitting element LD to the non-light emitting area NEA in which the color filter CF is not formed is reflected from the cathode electrode CE and blocked by the conductive layer such as the data line DL of the lower layer, thereby solving the light leakage and fading phenomenon.

[0207] Fig.16 is a diagram showing a planar layout of white pixels according to another embodiment. Fig.17 It is along Fig.16 A cross-sectional view taken along line III-III'.

[0208] Refer to Figure 2 and Fig.16 , the pixel PX may include a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, and a light emitting element LD.

[0209] The switch transistor ST may include a first gate GE1 , a first source SE1 , and a first drain DE1 .

[0210] The first gate GE1 may be disposed to overlap with a first channel formed in the active layer ACT. The first channel may be a semiconductor pattern without doping impurities in the active layer ACT. The first gate GE1 may be electrically connected to the first gate line GL1. For example, the first gate GE1 may be a region on the first gate line GL1 that overlaps with the first channel.

[0211] The first source electrode SE1 may be connected to a source region formed on a first side of the first channel in the active layer ACT The first source electrode SE1 may also be connected to the data line DL through a contact hole.

[0212] The first drain electrode DE1 may be a drain region formed on the second side of the first channel in the active layer ACT. The first drain electrode DE1 may be formed to be integrated with the lower electrode BE of the storage capacitor Cst.

[0213] The driving transistor DT may include a second gate electrode GE2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0214] The second gate GE2 may be disposed to overlap the second channel formed in the active layer ACT. The second gate GE2 may be electrically connected to the lower electrode BE of the storage capacitor Cst through a contact hole.

[0215] The second source electrode SE2 may be a second source region formed on a first side of the second channel in the active layer ACT The second source electrode SE2 may be electrically connected to the first power line PL1 through which the high potential driving voltage ELVDD is applied.

[0216] The second drain electrode DE2 may be connected to a second drain region formed on a second side of the second channel in the active layer ACT. The second drain electrode DE2 may be connected to the anode electrode AE ​​of the light emitting element LD through the via VIA.

[0217] In addition, the second drain electrode DE2 may be connected to the light shielding layer LS through the contact hole. The light shielding layer LS is connected to the third drain electrode DE3 of the sensing transistor SST. Therefore, the second drain electrode DE2 may be connected to the third drain electrode DE3 of the sensing transistor SST through the light shielding layer LS.

[0218] The sensing transistor SST may include a third gate GE3 , a third source SE3 , and a third drain DE3 .

[0219] The third gate GE3 may be disposed to overlap the third channel formed in the active layer ACT. The third gate GE3 may be electrically connected to the second gate line GL2. For example, the third gate GE3 may be a region on the second gate line GL2 that overlaps the third channel.

[0220] The third source electrode SE3 may be connected to the third source region formed on the first side of the third channel in the active layer ACT. The third source electrode SE3 may be electrically connected to the sensing line SL through the contact hole.

[0221] The third drain electrode DE3 may be connected to the third drain region formed on the second side of the third channel in the active layer ACT. In addition, the third drain electrode DE3 may be connected to the light shielding layer LS through a contact hole. Through the light shielding layer LS, the third drain electrode DE3 is electrically connected to the second drain electrode DE2 of the driving transistor DT and the anode electrode AE.

[0222] The storage capacitor Cst may include a lower electrode BE and an upper electrode UE.

[0223] The lower electrode BE constitutes the active layer ACT. The lower electrode BE may be electrically connected to the first drain electrode DE1 of the switching transistor ST through a contact hole. In addition, the lower electrode BE may be electrically connected to the second gate electrode GE2 of the driving transistor DT through a contact hole.

[0224] The upper electrode UE is formed in such a manner that at least one region thereof covers the lower electrode BE. Between the upper electrode UE and the lower electrode BE, charges corresponding to the potential difference between the two electrodes are stored so that the upper electrode UE and the lower electrode BE can function as a storage capacitor Cst.

[0225] The upper electrode UE is configured as a region of the anode electrode AE. That is, the upper electrode UE may be an extended portion of the non-emission region NEA of the anode electrode AE ​​formed in the emission region EA.

[0226] The upper electrode UE may be electrically connected to the second drain electrode DE2 of the driving transistor DT through the via VIA.

[0227] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and a light emitting layer EML disposed between the anode electrode AE ​​and the cathode electrode CE.

[0228] In general, the anode electrode AE ​​is formed in the light emitting area EA and is provided with an area extending to the non-light emitting area NEA. The extension area may be provided in a manner overlapping with the lower electrode BE of the storage capacitor Cst and may constitute the upper electrode UE of the storage capacitor Cst. In the present embodiment, the extension area may have a sufficient area to ensure the storage capacitance of the storage capacitor Cst.

[0229] On the anode electrode AE, a light emitting layer EML and a cathode electrode CE are formed. The light emitting layer EML and the cathode electrode CE may be widely formed in the light emitting area EA and the non-light emitting area NEA. In this article, since the light emitting layer EML and the cathode electrode CE are stacked on the area of ​​the non-light emitting area NEA extending to the anode electrode AE, light may be emitted from the non-light emitting area NEA. This has the effect of significantly expanding the light emitting area EA of the white pixel W.

[0230] Reference Fig.17 The storage capacitor Cst includes a lower electrode BE formed in the active layer ACT, and an upper electrode UE configured as an extended region of the anode electrode AE. Since the upper electrode UE is configured as the anode electrode AE, the upper electrode UE of the storage capacitor Cst can emit light.

[0231] Reference Fig.15 The described embodiments can be applied to Fig.16 and Fig.17 That is, the overcoat layer OC may not be formed in the light emitting area EA of the white pixel W. Fig.16 and Fig.17 In the embodiment, since the upper electrode UE of the storage capacitor Cst is configured as the anode electrode AE ​​and substantially extends the emission area EA, the overcoat layer OC may not be formed in the region where the upper electrode UE is disposed.

[0232] In this embodiment, between the lower electrode BE and the upper electrode UE of the storage capacitor Cst, in addition to the overcoat layer OC, at least one insulating layer interposed between the active layer ACT and the anode electrode AE ​​may be interposed. For example, between the lower electrode BE and the upper electrode UE, a passivation layer PAS may be interposed.

[0233] Fig.18 is a flowchart showing a method for manufacturing a display device according to an embodiment. Specifically, Fig.18 Shown is the manufacture with the above reference FIG. 4A to FIG. 5 A method of describing a pixel (PXij) of a display panel 50 .

[0234] Reference Fig.18 and FIG. 3A to FIG. 4C , first, a circuit element layer may be formed on a substrate SUB. Specifically, at step 1501, a first conductive layer may be formed on the substrate SUB. A conductive film may be formed on the substrate SUB via a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer deposition process, etc.; and the first conductive layer may be generated by performing patterning through an etching process using a mask. In this article, a first mask may be used.

[0235] Then, at step 1502, a buffer layer BUF may be formed on the first conductive layer. The buffer layer BUF may be formed by chemical vapor deposition, spin coating, plasma enhanced chemical vapor deposition, sputtering, vacuum deposition, high density plasma chemical vapor deposition, printing, etc.

[0236] At step 1503, an active layer ACT may be formed on the buffer layer BUF. For example, an amorphous silicon layer may be formed on the buffer layer BUF, and the amorphous silicon layer may be crystallized to form a polysilicon layer. Then, the polysilicon layer is patterned by photolithography or the like to form an active layer ACT. In this article, a second mask may be used for a photolithography process. Impurities are implanted into the polysilicon layer constituting the active layer ACT to form source regions SA1, SA2, and SA3, drain regions DA1, DA2, and DA3, and channels CH1, CH2, and CH3. In the buffer layer BUF, contact holes may also be formed to enable the first conductive layer and the upper layer to contact each other.

[0237] At step 1504, a gate insulating layer GI may be formed on the active layer ACT. The gate insulating layer GI may be selectively formed in a region to be described later where a second conductive layer is to be formed. Specifically, the gate insulating layer GI may be formed by photolithography or the like, in which the gate insulating layer GI is exposed and developed by using a mask. In this context, a third mask may be used.

[0238] At step 1505, a second conductive layer may be formed on the gate insulating layer GI. The second conductive layer may be produced by forming a conductive film on the gate insulating layer GI through a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer deposition process, etc.; and performing patterning through an etching process using a mask. In this article, a fourth mask may be used.

[0239] Then, at step 1506, a passivation layer PAS may be formed to cover the second conductive layer. At step 1507, a color filter may be formed on the passivation layer PAS. For the color filter, for example, a color filter of a first color may be formed into a pattern by using a first mask, a color filter of a second color may be formed into a pattern by using a second mask, and a color filter of a third color may be formed into a pattern by using a third mask. While forming the color filter, a light absorbing layer LA is formed together. In order to form the color filter and the light absorbing layer LA, three masks corresponding to the respective colors (i.e., the fifth mask to the seventh mask) may be used.

[0240] Then, at step 1508, an overcoat layer OC is formed to cover the color filter and the light absorbing layer LA. The overcoat layer OC may be exposed and developed on the passivation layer PAS by using a mask. The mask may include openings corresponding to the through holes VIA1 and VIA2. Herein, an eighth mask may be used.

[0241] The light emitting element may be formed on the overcoat layer OC. Specifically, at step 1509, on the overcoat layer OC, an anode electrode AE ​​is formed in a pattern by using a ninth mask having an opening corresponding to the light emitting area EA, and then, at step 1510, a light emitting layer EML and a cathode electrode CE are widely formed on the overcoat layer OC to cover the entire area of ​​the anode electrode AE.

[0242] In order to manufacture the display panel 50 having the above-mentioned bankless structure, nine masks can be used in total. In order to manufacture the display panel 50 provided with a bank, an additional mask is required to form the bank, so 10 mask processes using a total of 10 masks can be performed. However, in the case of a bankless structure such as the present embodiment, nine masks and nine mask processes are required to manufacture the display panel 50, thereby simplifying the process and reducing the manufacturing cost.

[0243] Those skilled in the art will understand that the present disclosure can be implemented in other specific forms without changing the technical ideas or basic features of the present disclosure. Therefore, it should be understood that the above-mentioned embodiments are illustrative rather than restrictive in all aspects. The scope of the present disclosure is characterized by the attached claims rather than the above detailed description, and it should be understood that all changes or modifications derived from the meaning and scope of the attached claims and their equivalents fall within the scope of the present disclosure.

[0244] CROSS-REFERENCE TO RELATED APPLICATIONS

[0245] This application claims priority to Korean Patent Application No. 10-2019-0179722, filed on Dec. 31, 2019, and Korean Patent Application No. 10-2020-0061098, filed on May 21, 2020, which are hereby incorporated by reference in their entirety for all purposes.

Claims

1. A display device having a bankless structure, the display device comprising: A substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer disposed on the substrate and comprising a lower electrode of a storage capacitor; an active layer, the active layer being formed on the first conductive layer; a second conductive layer formed on the active layer and including a plurality of electrodes of at least one transistor and an upper electrode of the storage capacitor, the upper electrode of the storage capacitor and at least one electrode of the plurality of electrodes of the at least one transistor being formed in a single pattern; an outer covering layer, the outer covering layer covering the second conductive layer; as well as a light emitting element disposed on the overcoat layer and connected to the upper electrode of the storage capacitor through a through hole, wherein the through hole does not overlap with the at least one transistor when viewed from above, and The display device further comprises: A light absorbing layer is provided below the overcoat layer in the non-light emitting region and is composed of a colorant.

2. The display device according to claim 1, wherein: The light emitting element comprises: an anode electrode disposed on the overcoat layer and connected to the upper electrode of the storage capacitor through the through hole; a light-emitting layer covering the entire surface of the anode electrode; and A cathode electrode covers the light emitting layer.

3. The display device according to claim 1, wherein: The light absorbing layer includes at least one of a first absorbing layer including a colorant of a first color and a second absorbing layer including a colorant of a second color.

4. The display device according to claim 1, further comprising: A color filter is formed over the second conductive layer in the light emitting region.

5. The display device according to claim 1, further comprising: a buffer layer covering the first conductive layer; a gate insulating layer covering the active layer; as well as A passivation layer covers the second conductive layer.

6. A display device having a bankless structure, the display device comprising: A substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer disposed on the substrate and comprising a lower electrode of a storage capacitor; an active layer, the active layer being formed on the first conductive layer; a second conductive layer formed on the active layer and including a plurality of electrodes of at least one transistor and an upper electrode of the storage capacitor, the upper electrode of the storage capacitor and at least one electrode of the plurality of electrodes of the at least one transistor being formed in a single pattern; an outer covering layer, the outer covering layer covering the second conductive layer; as well as a light emitting element disposed on the overcoat layer and connected to the upper electrode of the storage capacitor through a through hole, wherein the at least one transistor includes a driving transistor that controls an amount of current flowing to the light emitting element in response to a voltage stored in the storage capacitor, and The driving transistor comprises: a first electrode included in the second conductive layer and connected to a power line; a second electrode included in the second conductive layer and connected to the lower electrode of the storage capacitor; and a third electrode included in the second conductive layer, the third electrode being formed in a single pattern with the upper electrode of the storage capacitor and connected to the light emitting element via the upper electrode of the storage capacitor, and The display device further comprises: A light absorbing layer is provided below the overcoat layer in the non-light emitting region and is composed of a colorant.

7. The display device according to claim 6, wherein: The through hole is disposed closer to the light emitting region than the driving transistor.

8. The display device according to claim 7, wherein: The first conductive layer further includes a light shielding layer, and the light shielding layer is arranged in a manner that at least a region of the light shielding layer overlaps with the driving transistor.

9. A display device having a bankless structure, the display device comprising: A substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer disposed on the substrate and comprising a lower electrode of a storage capacitor; an active layer, the active layer being formed on the first conductive layer; a second conductive layer formed on the active layer and including a plurality of electrodes of at least one transistor and an upper electrode of the storage capacitor, the upper electrode of the storage capacitor and at least one electrode of the plurality of electrodes of the at least one transistor being formed in a single pattern; an outer covering layer, the outer covering layer covering the second conductive layer; as well as a light emitting element disposed on the overcoat layer and connected to the upper electrode of the storage capacitor through a through hole, wherein the upper electrode is constructed as a plurality of layers, in which a first electrode pattern disposed at the second conductive layer overlaps with a second electrode pattern disposed at the active layer, and The display device further comprises: A light absorbing layer is provided below the overcoat layer in the non-light emitting region and is composed of a colorant.

10. A display device having a bankless structure, the display device comprising: A substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer disposed on the substrate and comprising a lower electrode of a storage capacitor; an active layer, the active layer being formed on the first conductive layer; a second conductive layer formed on the active layer and including a plurality of electrodes of at least one transistor and an upper electrode of the storage capacitor, the upper electrode of the storage capacitor and at least one electrode of the plurality of electrodes of the at least one transistor being formed in a single pattern; an outer covering layer, the outer covering layer covering the second conductive layer; as well as a light emitting element disposed on the overcoat layer and connected to the upper electrode of the storage capacitor through a through hole, Among the plurality of pixels, the areas of the upper electrode and the lower electrode in the pixel displaying white are set to be smaller than the areas of the upper electrode and the lower electrode in the pixel displaying red, blue or green, and The display device further comprises: A light absorbing layer is provided below the overcoat layer in the non-light emitting region and is composed of a colorant.

11. A display device having a bankless structure, the display device comprising: A substrate, on which pixels including a light-emitting area and a non-light-emitting area are arranged; a first conductive layer disposed on the substrate and comprising a lower electrode of a storage capacitor; an active layer, the active layer being formed on the first conductive layer; a second conductive layer formed on the active layer and including a plurality of electrodes of at least one transistor and an upper electrode of the storage capacitor, the upper electrode of the storage capacitor and at least one electrode of the plurality of electrodes of the at least one transistor being formed in a single pattern; an outer covering layer, the outer covering layer covering the second conductive layer; as well as a light emitting element provided on the overcoat layer and connected to the upper electrode of the storage capacitor through a through hole, wherein the overcoat layer is formed in a region other than the light emitting region of a pixel displaying white among the plurality of pixels, and The display device further comprises: A light absorbing layer is provided below the overcoat layer in the non-light emitting region and is composed of a colorant.

12. A display device having a bankless structure, the display device comprising: A substrate, on which pixels are arranged, the pixels including a light-emitting area and a circuit area and emitting white light, and circuit elements are arranged in the circuit area; a first conductive layer disposed on the substrate and comprising a lower electrode of a storage capacitor; an active layer formed on the first conductive layer; a second conductive layer formed on the active layer and including a plurality of electrodes of at least one transistor; an outer covering layer, the outer covering layer covering the second conductive layer; as well as an anode electrode, the anode electrode being disposed on the outer covering layer, wherein the anode electrode includes an extension portion extending from the light emitting region to the circuit region and constituting an upper electrode of the storage capacitor, and The display device further comprises: A light absorbing layer is disposed below the cover layer in the circuit region and is composed of a colorant.

13. The display device according to claim 12, wherein: The anode electrode is configured to emit light in the circuit region through the extending portion.

14. The display device according to claim 12, wherein: The first conductive layer further includes a light shielding layer, and The upper electrode and the lower electrode of the storage capacitor are disposed not to overlap the light shielding layer.

15. The display device according to claim 12, wherein: The overcoat layer is omitted between the upper electrode and the lower electrode.

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